1;; Mips.md Machine Description for MIPS based processors 2;; Copyright (C) 1989-2015 Free Software Foundation, Inc. 3;; Contributed by A. Lichnewsky, lich@inria.inria.fr 4;; Changes by Michael Meissner, meissner@osf.org 5;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and 6;; Brendan Eich, brendan@microunity.com. 7 8;; This file is part of GCC. 9 10;; GCC is free software; you can redistribute it and/or modify 11;; it under the terms of the GNU General Public License as published by 12;; the Free Software Foundation; either version 3, or (at your option) 13;; any later version. 14 15;; GCC is distributed in the hope that it will be useful, 16;; but WITHOUT ANY WARRANTY; without even the implied warranty of 17;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18;; GNU General Public License for more details. 19 20;; You should have received a copy of the GNU General Public License 21;; along with GCC; see the file COPYING3. If not see 22;; <http://www.gnu.org/licenses/>. 23 24(define_enum "processor" [ 25 r3000 26 4kc 27 4kp 28 5kc 29 5kf 30 20kc 31 24kc 32 24kf2_1 33 24kf1_1 34 74kc 35 74kf2_1 36 74kf1_1 37 74kf3_2 38 loongson_2e 39 loongson_2f 40 loongson_3a 41 m4k 42 octeon 43 octeon2 44 octeon3 45 r3900 46 r6000 47 r4000 48 r4100 49 r4111 50 r4120 51 r4130 52 r4300 53 r4600 54 r4650 55 r4700 56 r5000 57 r5400 58 r5500 59 r5900 60 r7000 61 r8000 62 r9000 63 r10000 64 sb1 65 sb1a 66 sr71000 67 xlr 68 xlp 69 p5600 70 w32 71 w64 72]) 73 74(define_c_enum "unspec" [ 75 ;; Unaligned accesses. 76 UNSPEC_LOAD_LEFT 77 UNSPEC_LOAD_RIGHT 78 UNSPEC_STORE_LEFT 79 UNSPEC_STORE_RIGHT 80 81 ;; Integer operations that are too cumbersome to describe directly. 82 UNSPEC_WSBH 83 UNSPEC_DSBH 84 UNSPEC_DSHD 85 86 ;; Floating-point moves. 87 UNSPEC_LOAD_LOW 88 UNSPEC_LOAD_HIGH 89 UNSPEC_STORE_WORD 90 UNSPEC_MFHC1 91 UNSPEC_MTHC1 92 93 ;; Floating-point environment. 94 UNSPEC_GET_FCSR 95 UNSPEC_SET_FCSR 96 97 ;; HI/LO moves. 98 UNSPEC_MFHI 99 UNSPEC_MTHI 100 UNSPEC_SET_HILO 101 102 ;; GP manipulation. 103 UNSPEC_LOADGP 104 UNSPEC_COPYGP 105 UNSPEC_MOVE_GP 106 UNSPEC_POTENTIAL_CPRESTORE 107 UNSPEC_CPRESTORE 108 UNSPEC_RESTORE_GP 109 UNSPEC_EH_RETURN 110 UNSPEC_GP 111 UNSPEC_SET_GOT_VERSION 112 UNSPEC_UPDATE_GOT_VERSION 113 114 ;; Symbolic accesses. 115 UNSPEC_LOAD_CALL 116 UNSPEC_LOAD_GOT 117 UNSPEC_TLS_LDM 118 UNSPEC_TLS_GET_TP 119 UNSPEC_UNSHIFTED_HIGH 120 121 ;; MIPS16 constant pools. 122 UNSPEC_ALIGN 123 UNSPEC_CONSTTABLE_INT 124 UNSPEC_CONSTTABLE_FLOAT 125 126 ;; Blockage and synchronisation. 127 UNSPEC_BLOCKAGE 128 UNSPEC_CLEAR_HAZARD 129 UNSPEC_RDHWR 130 UNSPEC_SYNCI 131 UNSPEC_SYNC 132 133 ;; Cache manipulation. 134 UNSPEC_MIPS_CACHE 135 UNSPEC_R10K_CACHE_BARRIER 136 137 ;; Interrupt handling. 138 UNSPEC_ERET 139 UNSPEC_DERET 140 UNSPEC_DI 141 UNSPEC_EHB 142 UNSPEC_RDPGPR 143 UNSPEC_COP0 144 145 ;; Used in a call expression in place of args_size. It's present for PIC 146 ;; indirect calls where it contains args_size and the function symbol. 147 UNSPEC_CALL_ATTR 148 149 ;; MIPS16 casesi jump table dispatch. 150 UNSPEC_CASESI_DISPATCH 151 152 ;; Stack checking. 153 UNSPEC_PROBE_STACK_RANGE 154]) 155 156(define_constants 157 [(TLS_GET_TP_REGNUM 3) 158 (GET_FCSR_REGNUM 2) 159 (SET_FCSR_REGNUM 4) 160 (MIPS16_T_REGNUM 24) 161 (PIC_FUNCTION_ADDR_REGNUM 25) 162 (RETURN_ADDR_REGNUM 31) 163 (CPRESTORE_SLOT_REGNUM 76) 164 (GOT_VERSION_REGNUM 79) 165 166 ;; PIC long branch sequences are never longer than 100 bytes. 167 (MAX_PIC_BRANCH_LENGTH 100) 168 ] 169) 170 171(include "predicates.md") 172(include "constraints.md") 173 174;; .................... 175;; 176;; Attributes 177;; 178;; .................... 179 180(define_attr "got" "unset,xgot_high,load" 181 (const_string "unset")) 182 183;; For jal instructions, this attribute is DIRECT when the target address 184;; is symbolic and INDIRECT when it is a register. 185(define_attr "jal" "unset,direct,indirect" 186 (const_string "unset")) 187 188;; This attribute is YES if the instruction is a jal macro (not a 189;; real jal instruction). 190;; 191;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes 192;; an instruction to restore $gp. Direct jals are also macros for 193;; !TARGET_ABSOLUTE_JUMPS because they first load the target address 194;; into a register. 195(define_attr "jal_macro" "no,yes" 196 (cond [(eq_attr "jal" "direct") 197 (symbol_ref "(TARGET_CALL_CLOBBERED_GP || !TARGET_ABSOLUTE_JUMPS 198 ? JAL_MACRO_YES : JAL_MACRO_NO)") 199 (eq_attr "jal" "indirect") 200 (symbol_ref "(TARGET_CALL_CLOBBERED_GP 201 ? JAL_MACRO_YES : JAL_MACRO_NO)")] 202 (const_string "no"))) 203 204;; Classification of moves, extensions and truncations. Most values 205;; are as for "type" (see below) but there are also the following 206;; move-specific values: 207;; 208;; constN move an N-constraint integer into a MIPS16 register 209;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed 210;; to produce a sign-extended DEST, even if SRC is not 211;; properly sign-extended 212;; ext_ins EXT, DEXT, INS or DINS instruction 213;; andi a single ANDI instruction 214;; loadpool move a constant into a MIPS16 register by loading it 215;; from the pool 216;; shift_shift a shift left followed by a shift right 217;; 218;; This attribute is used to determine the instruction's length and 219;; scheduling type. For doubleword moves, the attribute always describes 220;; the split instructions; in some cases, it is more appropriate for the 221;; scheduling type to be "multi" instead. 222(define_attr "move_type" 223 "unknown,load,fpload,store,fpstore,mtc,mfc,mtlo,mflo,imul,move,fmove, 224 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool, 225 shift_shift" 226 (const_string "unknown")) 227 228(define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor" 229 (const_string "unknown")) 230 231;; Main data type used by the insn 232(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW" 233 (const_string "unknown")) 234 235;; True if the main data type is twice the size of a word. 236(define_attr "dword_mode" "no,yes" 237 (cond [(and (eq_attr "mode" "DI,DF") 238 (not (match_test "TARGET_64BIT"))) 239 (const_string "yes") 240 241 (and (eq_attr "mode" "TI,TF") 242 (match_test "TARGET_64BIT")) 243 (const_string "yes")] 244 (const_string "no"))) 245 246;; Attributes describing a sync loop. These loops have the form: 247;; 248;; if (RELEASE_BARRIER == YES) sync 249;; 1: OLDVAL = *MEM 250;; if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2 251;; CMP = 0 [delay slot] 252;; $TMP1 = OLDVAL & EXCLUSIVE_MASK 253;; $TMP2 = INSN1 (OLDVAL, INSN1_OP2) 254;; $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK) 255;; $AT |= $TMP1 | $TMP3 256;; if (!commit (*MEM = $AT)) goto 1. 257;; if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot] 258;; CMP = 1 259;; if (ACQUIRE_BARRIER == YES) sync 260;; 2: 261;; 262;; where "$" values are temporaries and where the other values are 263;; specified by the attributes below. Values are specified as operand 264;; numbers and insns are specified as enums. If no operand number is 265;; specified, the following values are used instead: 266;; 267;; - OLDVAL: $AT 268;; - CMP: NONE 269;; - NEWVAL: $AT 270;; - INCLUSIVE_MASK: -1 271;; - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK 272;; - EXCLUSIVE_MASK: 0 273;; 274;; MEM and INSN1_OP2 are required. 275;; 276;; Ideally, the operand attributes would be integers, with -1 meaning "none", 277;; but the gen* programs don't yet support that. 278(define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none")) 279(define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none")) 280(define_attr "sync_cmp" "none,0,1,2,3,4,5" (const_string "none")) 281(define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none")) 282(define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none")) 283(define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none")) 284(define_attr "sync_required_oldval" "none,0,1,2,3,4,5" (const_string "none")) 285(define_attr "sync_insn1_op2" "none,0,1,2,3,4,5" (const_string "none")) 286(define_attr "sync_insn1" "move,li,addu,addiu,subu,and,andi,or,ori,xor,xori" 287 (const_string "move")) 288(define_attr "sync_insn2" "nop,and,xor,not" 289 (const_string "nop")) 290;; Memory model specifier. 291;; "0"-"9" values specify the operand that stores the memory model value. 292;; "10" specifies MEMMODEL_ACQ_REL, 293;; "11" specifies MEMMODEL_ACQUIRE. 294(define_attr "sync_memmodel" "" (const_int 10)) 295 296;; Accumulator operand for madd patterns. 297(define_attr "accum_in" "none,0,1,2,3,4,5" (const_string "none")) 298 299;; Classification of each insn. 300;; branch conditional branch 301;; jump unconditional jump 302;; call unconditional call 303;; load load instruction(s) 304;; fpload floating point load 305;; fpidxload floating point indexed load 306;; store store instruction(s) 307;; fpstore floating point store 308;; fpidxstore floating point indexed store 309;; prefetch memory prefetch (register + offset) 310;; prefetchx memory indexed prefetch (register + register) 311;; condmove conditional moves 312;; mtc transfer to coprocessor 313;; mfc transfer from coprocessor 314;; mthi transfer to a hi register 315;; mtlo transfer to a lo register 316;; mfhi transfer from a hi register 317;; mflo transfer from a lo register 318;; const load constant 319;; arith integer arithmetic instructions 320;; logical integer logical instructions 321;; shift integer shift instructions 322;; slt set less than instructions 323;; signext sign extend instructions 324;; clz the clz and clo instructions 325;; pop the pop instruction 326;; trap trap if instructions 327;; imul integer multiply 2 operands 328;; imul3 integer multiply 3 operands 329;; imul3nc integer multiply 3 operands without clobbering HI/LO 330;; imadd integer multiply-add 331;; idiv integer divide 2 operands 332;; idiv3 integer divide 3 operands 333;; move integer register move ({,D}ADD{,U} with rt = 0) 334;; fmove floating point register move 335;; fadd floating point add/subtract 336;; fmul floating point multiply 337;; fmadd floating point multiply-add 338;; fdiv floating point divide 339;; frdiv floating point reciprocal divide 340;; frdiv1 floating point reciprocal divide step 1 341;; frdiv2 floating point reciprocal divide step 2 342;; fabs floating point absolute value 343;; fneg floating point negation 344;; fcmp floating point compare 345;; fcvt floating point convert 346;; fsqrt floating point square root 347;; frsqrt floating point reciprocal square root 348;; frsqrt1 floating point reciprocal square root step1 349;; frsqrt2 floating point reciprocal square root step2 350;; dspmac DSP MAC instructions not saturating the accumulator 351;; dspmacsat DSP MAC instructions that saturate the accumulator 352;; accext DSP accumulator extract instructions 353;; accmod DSP accumulator modify instructions 354;; dspalu DSP ALU instructions not saturating the result 355;; dspalusat DSP ALU instructions that saturate the result 356;; multi multiword sequence (or user asm statements) 357;; atomic atomic memory update instruction 358;; syncloop memory atomic operation implemented as a sync loop 359;; nop no operation 360;; ghost an instruction that produces no real code 361;; multimem microMIPS multiword load and store 362(define_attr "type" 363 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore, 364 prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical, 365 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move, 366 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt, 367 frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat, 368 multi,atomic,syncloop,nop,ghost,multimem" 369 (cond [(eq_attr "jal" "!unset") (const_string "call") 370 (eq_attr "got" "load") (const_string "load") 371 372 (eq_attr "alu_type" "add,sub") (const_string "arith") 373 374 (eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical") 375 376 ;; If a doubleword move uses these expensive instructions, 377 ;; it is usually better to schedule them in the same way 378 ;; as the singleword form, rather than as "multi". 379 (eq_attr "move_type" "load") (const_string "load") 380 (eq_attr "move_type" "fpload") (const_string "fpload") 381 (eq_attr "move_type" "store") (const_string "store") 382 (eq_attr "move_type" "fpstore") (const_string "fpstore") 383 (eq_attr "move_type" "mtc") (const_string "mtc") 384 (eq_attr "move_type" "mfc") (const_string "mfc") 385 (eq_attr "move_type" "mtlo") (const_string "mtlo") 386 (eq_attr "move_type" "mflo") (const_string "mflo") 387 388 ;; These types of move are always single insns. 389 (eq_attr "move_type" "imul") (const_string "imul") 390 (eq_attr "move_type" "fmove") (const_string "fmove") 391 (eq_attr "move_type" "loadpool") (const_string "load") 392 (eq_attr "move_type" "signext") (const_string "signext") 393 (eq_attr "move_type" "ext_ins") (const_string "arith") 394 (eq_attr "move_type" "arith") (const_string "arith") 395 (eq_attr "move_type" "logical") (const_string "logical") 396 (eq_attr "move_type" "sll0") (const_string "shift") 397 (eq_attr "move_type" "andi") (const_string "logical") 398 399 ;; These types of move are always split. 400 (eq_attr "move_type" "constN,shift_shift") 401 (const_string "multi") 402 403 ;; These types of move are split for doubleword modes only. 404 (and (eq_attr "move_type" "move,const") 405 (eq_attr "dword_mode" "yes")) 406 (const_string "multi") 407 (eq_attr "move_type" "move") (const_string "move") 408 (eq_attr "move_type" "const") (const_string "const") 409 (eq_attr "sync_mem" "!none") (const_string "syncloop")] 410 (const_string "unknown"))) 411 412;; Mode for conversion types (fcvt) 413;; I2S integer to float single (SI/DI to SF) 414;; I2D integer to float double (SI/DI to DF) 415;; S2I float to integer (SF to SI/DI) 416;; D2I float to integer (DF to SI/DI) 417;; D2S double to float single 418;; S2D float single to double 419 420(define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D" 421 (const_string "unknown")) 422 423;; Is this an extended instruction in mips16 mode? 424(define_attr "extended_mips16" "no,yes" 425 (if_then_else (ior ;; In general, constant-pool loads are extended 426 ;; instructions. We don't yet optimize for 16-bit 427 ;; PC-relative references. 428 (eq_attr "move_type" "sll0,loadpool") 429 (eq_attr "jal" "direct") 430 (eq_attr "got" "load")) 431 (const_string "yes") 432 (const_string "no"))) 433 434(define_attr "compression" "none,all,micromips32,micromips" 435 (const_string "none")) 436 437(define_attr "enabled" "no,yes" 438 (cond [;; The o32 FPXX and FP64A ABI extensions prohibit direct moves between 439 ;; GR_REG and FR_REG for 64-bit values. 440 (and (eq_attr "move_type" "mtc,mfc") 441 (match_test "(TARGET_FLOATXX && !ISA_HAS_MXHC1) 442 || TARGET_O32_FP64A_ABI") 443 (eq_attr "dword_mode" "yes")) 444 (const_string "no") 445 (and (eq_attr "compression" "micromips32,micromips") 446 (match_test "!TARGET_MICROMIPS")) 447 (const_string "no")] 448 (const_string "yes"))) 449 450;; The number of individual instructions that a non-branch pattern generates, 451;; using units of BASE_INSN_LENGTH. 452(define_attr "insn_count" "" 453 (cond [;; "Ghost" instructions occupy no space. 454 (eq_attr "type" "ghost") 455 (const_int 0) 456 457 ;; Extended instructions count as 2. 458 (and (eq_attr "extended_mips16" "yes") 459 (match_test "TARGET_MIPS16")) 460 (const_int 2) 461 462 ;; A GOT load followed by an add of $gp. This is not used for MIPS16. 463 (eq_attr "got" "xgot_high") 464 (const_int 2) 465 466 ;; SHIFT_SHIFTs are decomposed into two separate instructions. 467 ;; They are extended instructions on MIPS16 targets. 468 (eq_attr "move_type" "shift_shift") 469 (if_then_else (match_test "TARGET_MIPS16") 470 (const_int 4) 471 (const_int 2)) 472 473 ;; Check for doubleword moves that are decomposed into two 474 ;; instructions. The individual instructions are unextended 475 ;; MIPS16 ones. 476 (and (eq_attr "move_type" "mtc,mfc,mtlo,mflo,move") 477 (eq_attr "dword_mode" "yes")) 478 (const_int 2) 479 480 ;; Constants, loads and stores are handled by external routines. 481 (and (eq_attr "move_type" "const,constN") 482 (eq_attr "dword_mode" "yes")) 483 (symbol_ref "mips_split_const_insns (operands[1])") 484 (eq_attr "move_type" "const,constN") 485 (symbol_ref "mips_const_insns (operands[1])") 486 (eq_attr "move_type" "load,fpload") 487 (symbol_ref "mips_load_store_insns (operands[1], insn)") 488 (eq_attr "move_type" "store,fpstore") 489 (symbol_ref "mips_load_store_insns (operands[0], insn) 490 + (TARGET_FIX_24K ? 1 : 0)") 491 492 ;; In the worst case, a call macro will take 8 instructions: 493 ;; 494 ;; lui $25,%call_hi(FOO) 495 ;; addu $25,$25,$28 496 ;; lw $25,%call_lo(FOO)($25) 497 ;; nop 498 ;; jalr $25 499 ;; nop 500 ;; lw $gp,X($sp) 501 ;; nop 502 (eq_attr "jal_macro" "yes") 503 (const_int 8) 504 505 ;; Various VR4120 errata require a nop to be inserted after a macc 506 ;; instruction. The assembler does this for us, so account for 507 ;; the worst-case length here. 508 (and (eq_attr "type" "imadd") 509 (match_test "TARGET_FIX_VR4120")) 510 (const_int 2) 511 512 ;; VR4120 errata MD(4): if there are consecutive dmult instructions, 513 ;; the result of the second one is missed. The assembler should work 514 ;; around this by inserting a nop after the first dmult. 515 (and (eq_attr "type" "imul,imul3") 516 (eq_attr "mode" "DI") 517 (match_test "TARGET_FIX_VR4120")) 518 (const_int 2) 519 520 (eq_attr "type" "idiv,idiv3") 521 (symbol_ref "mips_idiv_insns ()") 522 523 (not (eq_attr "sync_mem" "none")) 524 (symbol_ref "mips_sync_loop_insns (insn, operands)")] 525 (const_int 1))) 526 527;; Length of instruction in bytes. The default is derived from "insn_count", 528;; but there are special cases for branches (which must be handled here) 529;; and for compressed single instructions. 530(define_attr "length" "" 531 (cond [(and (ior (eq_attr "compression" "micromips,all") 532 (and (eq_attr "compression" "micromips32") 533 (eq_attr "mode" "SI,SF"))) 534 (eq_attr "dword_mode" "no") 535 (match_test "TARGET_MICROMIPS")) 536 (const_int 2) 537 538 ;; Direct microMIPS branch instructions have a range of 539 ;; [-0x10000,0xfffe], otherwise the range is [-0x20000,0x1fffc]. 540 ;; If a branch is outside this range, we have a choice of two 541 ;; sequences. 542 ;; 543 ;; For PIC, an out-of-range branch like: 544 ;; 545 ;; bne r1,r2,target 546 ;; dslot 547 ;; 548 ;; becomes the equivalent of: 549 ;; 550 ;; beq r1,r2,1f 551 ;; dslot 552 ;; la $at,target 553 ;; jr $at 554 ;; nop 555 ;; 1: 556 ;; 557 ;; The non-PIC case is similar except that we use a direct 558 ;; jump instead of an la/jr pair. Since the target of this 559 ;; jump is an absolute 28-bit bit address (the other bits 560 ;; coming from the address of the delay slot) this form cannot 561 ;; cross a 256MB boundary. We could provide the option of 562 ;; using la/jr in this case too, but we do not do so at 563 ;; present. 564 ;; 565 ;; The value we specify here does not account for the delay slot 566 ;; instruction, whose length is added separately. If the RTL 567 ;; pattern has no explicit delay slot, mips_adjust_insn_length 568 ;; will add the length of the implicit nop. The range of 569 ;; [-0x20000, 0x1fffc] from the address of the delay slot 570 ;; therefore translates to a range of: 571 ;; 572 ;; [-(0x20000 - sizeof (branch)), 0x1fffc - sizeof (slot)] 573 ;; == [-0x1fffc, 0x1fff8] 574 ;; 575 ;; from the shorten_branches reference address. 576 (and (eq_attr "type" "branch") 577 (not (match_test "TARGET_MIPS16"))) 578 (cond [;; Any variant can handle the 17-bit range. 579 (and (le (minus (match_dup 0) (pc)) (const_int 65532)) 580 (le (minus (pc) (match_dup 0)) (const_int 65534))) 581 (const_int 4) 582 583 ;; The 18-bit range is OK other than for microMIPS. 584 (and (not (match_test "TARGET_MICROMIPS")) 585 (and (le (minus (match_dup 0) (pc)) (const_int 131064)) 586 (le (minus (pc) (match_dup 0)) (const_int 131068)))) 587 (const_int 4) 588 589 ;; The non-PIC case: branch, first delay slot, and J. 590 (match_test "TARGET_ABSOLUTE_JUMPS") 591 (const_int 12)] 592 593 ;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate. 594 ;; mips_adjust_insn_length substitutes the correct length. 595 ;; 596 ;; Note that we can't simply use (symbol_ref ...) here 597 ;; because genattrtab needs to know the maximum length 598 ;; of an insn. 599 (const_int MAX_PIC_BRANCH_LENGTH)) 600 601 ;; An unextended MIPS16 branch has a range of [-0x100, 0xfe] 602 ;; from the address of the following instruction, which leads 603 ;; to a range of: 604 ;; 605 ;; [-(0x100 - sizeof (branch)), 0xfe] 606 ;; == [-0xfe, 0xfe] 607 ;; 608 ;; from the shorten_branches reference address. Extended branches 609 ;; likewise have a range of [-0x10000, 0xfffe] from the address 610 ;; of the following instruction, which leads to a range of: 611 ;; 612 ;; [-(0x10000 - sizeof (branch)), 0xfffe] 613 ;; == [-0xfffc, 0xfffe] 614 ;; 615 ;; from the reference address. 616 ;; 617 ;; When a branch is out of range, mips_reorg splits it into a form 618 ;; that uses in-range branches. There are four basic sequences: 619 ;; 620 ;; (1) Absolute addressing with a readable text segment 621 ;; (32-bit addresses): 622 ;; 623 ;; b... foo 2 bytes 624 ;; move $1,$2 2 bytes 625 ;; lw $2,label 2 bytes 626 ;; jr $2 2 bytes 627 ;; move $2,$1 2 bytes 628 ;; .align 2 0 or 2 bytes 629 ;; label: 630 ;; .word target 4 bytes 631 ;; foo: 632 ;; (16 bytes in the worst case) 633 ;; 634 ;; (2) Absolute addressing with a readable text segment 635 ;; (64-bit addresses): 636 ;; 637 ;; b... foo 2 bytes 638 ;; move $1,$2 2 bytes 639 ;; ld $2,label 2 bytes 640 ;; jr $2 2 bytes 641 ;; move $2,$1 2 bytes 642 ;; .align 3 0 to 6 bytes 643 ;; label: 644 ;; .dword target 8 bytes 645 ;; foo: 646 ;; (24 bytes in the worst case) 647 ;; 648 ;; (3) Absolute addressing without a readable text segment 649 ;; (which requires 32-bit addresses at present): 650 ;; 651 ;; b... foo 2 bytes 652 ;; move $1,$2 2 bytes 653 ;; lui $2,%hi(target) 4 bytes 654 ;; sll $2,8 2 bytes 655 ;; sll $2,8 2 bytes 656 ;; addiu $2,%lo(target) 4 bytes 657 ;; jr $2 2 bytes 658 ;; move $2,$1 2 bytes 659 ;; foo: 660 ;; (20 bytes) 661 ;; 662 ;; (4) PIC addressing (which requires 32-bit addresses at present): 663 ;; 664 ;; b... foo 2 bytes 665 ;; move $1,$2 2 bytes 666 ;; lw $2,cprestore 0, 2 or 4 bytes 667 ;; lw $2,%got(target)($2) 4 bytes 668 ;; addiu $2,%lo(target) 4 bytes 669 ;; jr $2 2 bytes 670 ;; move $2,$1 2 bytes 671 ;; foo: 672 ;; (20 bytes in the worst case) 673 (and (eq_attr "type" "branch") 674 (match_test "TARGET_MIPS16")) 675 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254)) 676 (le (minus (pc) (match_dup 0)) (const_int 254))) 677 (const_int 2) 678 (and (le (minus (match_dup 0) (pc)) (const_int 65534)) 679 (le (minus (pc) (match_dup 0)) (const_int 65532))) 680 (const_int 4) 681 (and (match_test "TARGET_ABICALLS") 682 (not (match_test "TARGET_ABSOLUTE_ABICALLS"))) 683 (const_int 20) 684 (match_test "Pmode == SImode") 685 (const_int 16) 686 ] (const_int 24))] 687 (symbol_ref "get_attr_insn_count (insn) * BASE_INSN_LENGTH"))) 688 689;; Attribute describing the processor. 690(define_enum_attr "cpu" "processor" 691 (const (symbol_ref "mips_tune"))) 692 693;; The type of hardware hazard associated with this instruction. 694;; DELAY means that the next instruction cannot read the result 695;; of this one. HILO means that the next two instructions cannot 696;; write to HI or LO. 697(define_attr "hazard" "none,delay,hilo" 698 (cond [(and (eq_attr "type" "load,fpload,fpidxload") 699 (match_test "ISA_HAS_LOAD_DELAY")) 700 (const_string "delay") 701 702 (and (eq_attr "type" "mfc,mtc") 703 (match_test "ISA_HAS_XFER_DELAY")) 704 (const_string "delay") 705 706 (and (eq_attr "type" "fcmp") 707 (match_test "ISA_HAS_FCMP_DELAY")) 708 (const_string "delay") 709 710 ;; The r4000 multiplication patterns include an mflo instruction. 711 (and (eq_attr "type" "imul") 712 (match_test "TARGET_FIX_R4000")) 713 (const_string "hilo") 714 715 (and (eq_attr "type" "mfhi,mflo") 716 (not (match_test "ISA_HAS_HILO_INTERLOCKS"))) 717 (const_string "hilo")] 718 (const_string "none"))) 719 720;; Can the instruction be put into a delay slot? 721(define_attr "can_delay" "no,yes" 722 (if_then_else (and (eq_attr "type" "!branch,call,jump") 723 (eq_attr "hazard" "none") 724 (match_test "get_attr_insn_count (insn) == 1")) 725 (const_string "yes") 726 (const_string "no"))) 727 728;; Attribute defining whether or not we can use the branch-likely 729;; instructions. 730(define_attr "branch_likely" "no,yes" 731 (if_then_else (match_test "GENERATE_BRANCHLIKELY") 732 (const_string "yes") 733 (const_string "no"))) 734 735;; True if an instruction might assign to hi or lo when reloaded. 736;; This is used by the TUNE_MACC_CHAINS code. 737(define_attr "may_clobber_hilo" "no,yes" 738 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthi,mtlo") 739 (const_string "yes") 740 (const_string "no"))) 741 742;; Describe a user's asm statement. 743(define_asm_attributes 744 [(set_attr "type" "multi") 745 (set_attr "can_delay" "no")]) 746 747;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated 748;; from the same template. 749(define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) 750 751;; A copy of GPR that can be used when a pattern has two independent 752;; modes. 753(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")]) 754 755(define_mode_iterator MOVEP1 [SI SF]) 756(define_mode_iterator MOVEP2 [SI SF]) 757 758;; This mode iterator allows :HILO to be used as the mode of the 759;; concatenated HI and LO registers. 760(define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")]) 761 762;; This mode iterator allows :P to be used for patterns that operate on 763;; pointer-sized quantities. Exactly one of the two alternatives will match. 764(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) 765 766;; This mode iterator allows :MOVECC to be used anywhere that a 767;; conditional-move-type condition is needed. 768(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") 769 (CC "TARGET_HARD_FLOAT 770 && !TARGET_LOONGSON_2EF 771 && !TARGET_MIPS5900")]) 772 773;; This mode iterator allows :FPCC to be used anywhere that an FP condition 774;; is needed. 775(define_mode_iterator FPCC [(CC "!ISA_HAS_CCF") 776 (CCF "ISA_HAS_CCF")]) 777 778;; 32-bit integer moves for which we provide move patterns. 779(define_mode_iterator IMOVE32 780 [SI 781 (V2HI "TARGET_DSP") 782 (V4QI "TARGET_DSP") 783 (V2HQ "TARGET_DSP") 784 (V2UHQ "TARGET_DSP") 785 (V2HA "TARGET_DSP") 786 (V2UHA "TARGET_DSP") 787 (V4QQ "TARGET_DSP") 788 (V4UQQ "TARGET_DSP")]) 789 790;; 64-bit modes for which we provide move patterns. 791(define_mode_iterator MOVE64 792 [DI DF 793 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT") 794 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS") 795 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS") 796 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")]) 797 798;; 128-bit modes for which we provide move patterns on 64-bit targets. 799(define_mode_iterator MOVE128 [TI TF]) 800 801;; This mode iterator allows the QI and HI extension patterns to be 802;; defined from the same template. 803(define_mode_iterator SHORT [QI HI]) 804 805;; Likewise the 64-bit truncate-and-shift patterns. 806(define_mode_iterator SUBDI [QI HI SI]) 807 808;; This mode iterator allows :ANYF to be used wherever a scalar or vector 809;; floating-point mode is allowed. 810(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT") 811 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT") 812 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")]) 813 814;; Like ANYF, but only applies to scalar modes. 815(define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT") 816 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")]) 817 818;; A floating-point mode for which moves involving FPRs may need to be split. 819(define_mode_iterator SPLITF 820 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") 821 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") 822 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT") 823 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS") 824 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS") 825 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS") 826 (TF "TARGET_64BIT && TARGET_FLOAT64")]) 827 828;; In GPR templates, a string like "<d>subu" will expand to "subu" in the 829;; 32-bit version and "dsubu" in the 64-bit version. 830(define_mode_attr d [(SI "") (DI "d") 831 (QQ "") (HQ "") (SQ "") (DQ "d") 832 (UQQ "") (UHQ "") (USQ "") (UDQ "d") 833 (HA "") (SA "") (DA "d") 834 (UHA "") (USA "") (UDA "d")]) 835 836;; Same as d but upper-case. 837(define_mode_attr D [(SI "") (DI "D") 838 (QQ "") (HQ "") (SQ "") (DQ "D") 839 (UQQ "") (UHQ "") (USQ "") (UDQ "D") 840 (HA "") (SA "") (DA "D") 841 (UHA "") (USA "") (UDA "D")]) 842 843;; This attribute gives the length suffix for a load or store instruction. 844;; The same suffixes work for zero and sign extensions. 845(define_mode_attr size [(QI "b") (HI "h") (SI "w") (DI "d")]) 846(define_mode_attr SIZE [(QI "B") (HI "H") (SI "W") (DI "D")]) 847 848;; This attributes gives the mode mask of a SHORT. 849(define_mode_attr mask [(QI "0x00ff") (HI "0xffff")]) 850 851;; Mode attributes for GPR loads. 852(define_mode_attr load [(SI "lw") (DI "ld")]) 853;; Instruction names for stores. 854(define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")]) 855 856;; Similarly for MIPS IV indexed FPR loads and stores. 857(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")]) 858(define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")]) 859 860;; The unextended ranges of the MIPS16 addiu and daddiu instructions 861;; are different. Some forms of unextended addiu have an 8-bit immediate 862;; field but the equivalent daddiu has only a 5-bit field. 863(define_mode_attr si8_di5 [(SI "8") (DI "5")]) 864 865;; This attribute gives the best constraint to use for registers of 866;; a given mode. 867(define_mode_attr reg [(SI "d") (DI "d") (CC "z") (CCF "f")]) 868 869;; This attribute gives the format suffix for floating-point operations. 870(define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")]) 871 872;; This attribute gives the upper-case mode name for one unit of a 873;; floating-point mode. 874(define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")]) 875 876;; This attribute gives the integer mode that has the same size as a 877;; fixed-point mode. 878(define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI") 879 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI") 880 (HA "HI") (SA "SI") (DA "DI") 881 (UHA "HI") (USA "SI") (UDA "DI") 882 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI") 883 (V2HQ "SI") (V2HA "SI")]) 884 885;; This attribute gives the integer mode that has half the size of 886;; the controlling mode. 887(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI") 888 (V2SI "SI") (V4HI "SI") (V8QI "SI") 889 (TF "DI")]) 890 891;; This attribute works around the early SB-1 rev2 core "F2" erratum: 892;; 893;; In certain cases, div.s and div.ps may have a rounding error 894;; and/or wrong inexact flag. 895;; 896;; Therefore, we only allow div.s if not working around SB-1 rev2 897;; errata or if a slight loss of precision is OK. 898(define_mode_attr divide_condition 899 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations") 900 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")]) 901 902;; This attribute gives the conditions under which SQRT.fmt instructions 903;; can be used. 904(define_mode_attr sqrt_condition 905 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")]) 906 907;; This attribute provides the correct mnemonic for each FP condition mode. 908(define_mode_attr fpcmp [(CC "c") (CCF "cmp")]) 909 910;; This code iterator allows signed and unsigned widening multiplications 911;; to use the same template. 912(define_code_iterator any_extend [sign_extend zero_extend]) 913 914;; This code iterator allows the two right shift instructions to be 915;; generated from the same template. 916(define_code_iterator any_shiftrt [ashiftrt lshiftrt]) 917 918;; This code iterator allows the three shift instructions to be generated 919;; from the same template. 920(define_code_iterator any_shift [ashift ashiftrt lshiftrt]) 921 922;; This code iterator allows unsigned and signed division to be generated 923;; from the same template. 924(define_code_iterator any_div [div udiv]) 925 926;; This code iterator allows unsigned and signed modulus to be generated 927;; from the same template. 928(define_code_iterator any_mod [mod umod]) 929 930;; This code iterator allows all native floating-point comparisons to be 931;; generated from the same template. 932(define_code_iterator fcond [unordered uneq unlt unle eq lt le 933 (ordered "ISA_HAS_CCF") 934 (ltgt "ISA_HAS_CCF") 935 (ne "ISA_HAS_CCF")]) 936 937;; This code iterator is used for comparisons that can be implemented 938;; by swapping the operands. 939(define_code_iterator swapped_fcond [ge gt unge ungt]) 940 941;; Equality operators. 942(define_code_iterator equality_op [eq ne]) 943 944;; These code iterators allow the signed and unsigned scc operations to use 945;; the same template. 946(define_code_iterator any_gt [gt gtu]) 947(define_code_iterator any_ge [ge geu]) 948(define_code_iterator any_lt [lt ltu]) 949(define_code_iterator any_le [le leu]) 950 951(define_code_iterator any_return [return simple_return]) 952 953;; <u> expands to an empty string when doing a signed operation and 954;; "u" when doing an unsigned operation. 955(define_code_attr u [(sign_extend "") (zero_extend "u") 956 (div "") (udiv "u") 957 (mod "") (umod "u") 958 (gt "") (gtu "u") 959 (ge "") (geu "u") 960 (lt "") (ltu "u") 961 (le "") (leu "u")]) 962 963;; <U> is like <u> except uppercase. 964(define_code_attr U [(sign_extend "") (zero_extend "U")]) 965 966;; <su> is like <u>, but the signed form expands to "s" rather than "". 967(define_code_attr su [(sign_extend "s") (zero_extend "u")]) 968 969;; <optab> expands to the name of the optab for a particular code. 970(define_code_attr optab [(ashift "ashl") 971 (ashiftrt "ashr") 972 (lshiftrt "lshr") 973 (ior "ior") 974 (xor "xor") 975 (and "and") 976 (plus "add") 977 (minus "sub") 978 (return "return") 979 (simple_return "simple_return")]) 980 981;; <insn> expands to the name of the insn that implements a particular code. 982(define_code_attr insn [(ashift "sll") 983 (ashiftrt "sra") 984 (lshiftrt "srl") 985 (ior "or") 986 (xor "xor") 987 (and "and") 988 (plus "addu") 989 (minus "subu")]) 990 991;; <immediate_insn> expands to the name of the insn that implements 992;; a particular code to operate on immediate values. 993(define_code_attr immediate_insn [(ior "ori") 994 (xor "xori") 995 (and "andi")]) 996 997(define_code_attr shift_compression [(ashift "micromips32") 998 (lshiftrt "micromips32") 999 (ashiftrt "none")]) 1000 1001;; <fcond> is the c.cond.fmt condition associated with a particular code. 1002(define_code_attr fcond [(unordered "un") 1003 (uneq "ueq") 1004 (unlt "ult") 1005 (unle "ule") 1006 (eq "eq") 1007 (lt "lt") 1008 (le "le") 1009 (ordered "or") 1010 (ltgt "ne") 1011 (ne "une")]) 1012 1013;; Similar, but for swapped conditions. 1014(define_code_attr swapped_fcond [(ge "le") 1015 (gt "lt") 1016 (unge "ule") 1017 (ungt "ult")]) 1018 1019;; The value of the bit when the branch is taken for branch_bit patterns. 1020;; Comparison is always against zero so this depends on the operator. 1021(define_code_attr bbv [(eq "0") (ne "1")]) 1022 1023;; This is the inverse value of bbv. 1024(define_code_attr bbinv [(eq "1") (ne "0")]) 1025 1026;; The sel mnemonic to use depending on the condition test. 1027(define_code_attr sel [(eq "seleqz") (ne "selnez")]) 1028(define_code_attr selinv [(eq "selnez") (ne "seleqz")]) 1029 1030;; ......................... 1031;; 1032;; Branch, call and jump delay slots 1033;; 1034;; ......................... 1035 1036(define_delay (and (eq_attr "type" "branch") 1037 (not (match_test "TARGET_MIPS16")) 1038 (eq_attr "branch_likely" "yes")) 1039 [(eq_attr "can_delay" "yes") 1040 (nil) 1041 (eq_attr "can_delay" "yes")]) 1042 1043;; Branches that don't have likely variants do not annul on false. 1044(define_delay (and (eq_attr "type" "branch") 1045 (not (match_test "TARGET_MIPS16")) 1046 (eq_attr "branch_likely" "no")) 1047 [(eq_attr "can_delay" "yes") 1048 (nil) 1049 (nil)]) 1050 1051(define_delay (eq_attr "type" "jump") 1052 [(eq_attr "can_delay" "yes") 1053 (nil) 1054 (nil)]) 1055 1056(define_delay (and (eq_attr "type" "call") 1057 (eq_attr "jal_macro" "no")) 1058 [(eq_attr "can_delay" "yes") 1059 (nil) 1060 (nil)]) 1061 1062;; Pipeline descriptions. 1063;; 1064;; generic.md provides a fallback for processors without a specific 1065;; pipeline description. It is derived from the old define_function_unit 1066;; version and uses the "alu" and "imuldiv" units declared below. 1067;; 1068;; Some of the processor-specific files are also derived from old 1069;; define_function_unit descriptions and simply override the parts of 1070;; generic.md that don't apply. The other processor-specific files 1071;; are self-contained. 1072(define_automaton "alu,imuldiv") 1073 1074(define_cpu_unit "alu" "alu") 1075(define_cpu_unit "imuldiv" "imuldiv") 1076 1077;; Ghost instructions produce no real code and introduce no hazards. 1078;; They exist purely to express an effect on dataflow. 1079(define_insn_reservation "ghost" 0 1080 (eq_attr "type" "ghost") 1081 "nothing") 1082 1083(include "p5600.md") 1084(include "4k.md") 1085(include "5k.md") 1086(include "20kc.md") 1087(include "24k.md") 1088(include "74k.md") 1089(include "3000.md") 1090(include "4000.md") 1091(include "4100.md") 1092(include "4130.md") 1093(include "4300.md") 1094(include "4600.md") 1095(include "5000.md") 1096(include "5400.md") 1097(include "5500.md") 1098(include "6000.md") 1099(include "7000.md") 1100(include "9000.md") 1101(include "10000.md") 1102(include "loongson2ef.md") 1103(include "loongson3a.md") 1104(include "octeon.md") 1105(include "sb1.md") 1106(include "sr71k.md") 1107(include "xlr.md") 1108(include "xlp.md") 1109(include "generic.md") 1110 1111;; 1112;; .................... 1113;; 1114;; CONDITIONAL TRAPS 1115;; 1116;; .................... 1117;; 1118 1119(define_insn "trap" 1120 [(trap_if (const_int 1) (const_int 0))] 1121 "" 1122{ 1123 if (ISA_HAS_COND_TRAP) 1124 return "teq\t$0,$0"; 1125 else if (TARGET_MIPS16) 1126 return "break 0"; 1127 else 1128 return "break"; 1129} 1130 [(set_attr "type" "trap")]) 1131 1132(define_expand "ctrap<mode>4" 1133 [(trap_if (match_operator 0 "comparison_operator" 1134 [(match_operand:GPR 1 "reg_or_0_operand") 1135 (match_operand:GPR 2 "arith_operand")]) 1136 (match_operand 3 "const_0_operand"))] 1137 "ISA_HAS_COND_TRAPI || ISA_HAS_COND_TRAP" 1138{ 1139 mips_expand_conditional_trap (operands[0]); 1140 DONE; 1141}) 1142 1143(define_insn "*conditional_trap_reg<mode>" 1144 [(trap_if (match_operator:GPR 0 "trap_comparison_operator" 1145 [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 1146 (match_operand:GPR 2 "reg_or_0_operand" "dJ")]) 1147 (const_int 0))] 1148 "ISA_HAS_COND_TRAP && !ISA_HAS_COND_TRAPI" 1149 "t%C0\t%z1,%2" 1150 [(set_attr "type" "trap")]) 1151 1152(define_insn "*conditional_trap<mode>" 1153 [(trap_if (match_operator:GPR 0 "trap_comparison_operator" 1154 [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 1155 (match_operand:GPR 2 "arith_operand" "dI")]) 1156 (const_int 0))] 1157 "ISA_HAS_COND_TRAPI" 1158 "t%C0\t%z1,%2" 1159 [(set_attr "type" "trap")]) 1160 1161;; 1162;; .................... 1163;; 1164;; ADDITION 1165;; 1166;; .................... 1167;; 1168 1169(define_insn "add<mode>3" 1170 [(set (match_operand:ANYF 0 "register_operand" "=f") 1171 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f") 1172 (match_operand:ANYF 2 "register_operand" "f")))] 1173 "" 1174 "add.<fmt>\t%0,%1,%2" 1175 [(set_attr "type" "fadd") 1176 (set_attr "mode" "<UNITMODE>")]) 1177 1178(define_expand "add<mode>3" 1179 [(set (match_operand:GPR 0 "register_operand") 1180 (plus:GPR (match_operand:GPR 1 "register_operand") 1181 (match_operand:GPR 2 "arith_operand")))] 1182 "") 1183 1184(define_insn "*add<mode>3" 1185 [(set (match_operand:GPR 0 "register_operand" "=!u,d,!u,!u,!ks,!d,d") 1186 (plus:GPR (match_operand:GPR 1 "register_operand" "!u,d,!u,!ks,!ks,0,d") 1187 (match_operand:GPR 2 "arith_operand" "!u,d,Uead,Uuw6,Uesp,Usb4,Q")))] 1188 "!TARGET_MIPS16" 1189{ 1190 if (which_alternative == 0 1191 || which_alternative == 1) 1192 return "<d>addu\t%0,%1,%2"; 1193 else 1194 return "<d>addiu\t%0,%1,%2"; 1195} 1196 [(set_attr "alu_type" "add") 1197 (set_attr "compression" "micromips32,*,micromips32,micromips32,micromips32,micromips32,*") 1198 (set_attr "mode" "<MODE>")]) 1199 1200(define_insn "*add<mode>3_mips16" 1201 [(set (match_operand:GPR 0 "register_operand" "=ks,ks,d,d,d,d,d,d,d") 1202 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,ks,ks,0,0,d,d,d") 1203 (match_operand:GPR 2 "arith_operand" "Usd8,Q,Uuw<si8_di5>,Q,Usb<si8_di5>,Q,Usb4,O,d")))] 1204 "TARGET_MIPS16" 1205 "@ 1206 <d>addiu\t%0,%2 1207 <d>addiu\t%0,%2 1208 <d>addiu\t%0,%1,%2 1209 <d>addiu\t%0,%1,%2 1210 <d>addiu\t%0,%2 1211 <d>addiu\t%0,%2 1212 <d>addiu\t%0,%1,%2 1213 <d>addiu\t%0,%1,%2 1214 <d>addu\t%0,%1,%2" 1215 [(set_attr "alu_type" "add") 1216 (set_attr "mode" "<MODE>") 1217 (set_attr "extended_mips16" "no,yes,no,yes,no,yes,no,yes,no")]) 1218 1219;; On the mips16, we can sometimes split an add of a constant which is 1220;; a 4 byte instruction into two adds which are both 2 byte 1221;; instructions. There are two cases: one where we are adding a 1222;; constant plus a register to another register, and one where we are 1223;; simply adding a constant to a register. 1224 1225(define_split 1226 [(set (match_operand:SI 0 "d_operand") 1227 (plus:SI (match_dup 0) 1228 (match_operand:SI 1 "const_int_operand")))] 1229 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 1230 && ((INTVAL (operands[1]) > 0x7f 1231 && INTVAL (operands[1]) <= 0x7f + 0x7f) 1232 || (INTVAL (operands[1]) < - 0x80 1233 && INTVAL (operands[1]) >= - 0x80 - 0x80))" 1234 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 1235 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] 1236{ 1237 HOST_WIDE_INT val = INTVAL (operands[1]); 1238 1239 if (val >= 0) 1240 { 1241 operands[1] = GEN_INT (0x7f); 1242 operands[2] = GEN_INT (val - 0x7f); 1243 } 1244 else 1245 { 1246 operands[1] = GEN_INT (- 0x80); 1247 operands[2] = GEN_INT (val + 0x80); 1248 } 1249}) 1250 1251(define_split 1252 [(set (match_operand:SI 0 "d_operand") 1253 (plus:SI (match_operand:SI 1 "d_operand") 1254 (match_operand:SI 2 "const_int_operand")))] 1255 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 1256 && REGNO (operands[0]) != REGNO (operands[1]) 1257 && ((INTVAL (operands[2]) > 0x7 1258 && INTVAL (operands[2]) <= 0x7 + 0x7f) 1259 || (INTVAL (operands[2]) < - 0x8 1260 && INTVAL (operands[2]) >= - 0x8 - 0x80))" 1261 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2))) 1262 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))] 1263{ 1264 HOST_WIDE_INT val = INTVAL (operands[2]); 1265 1266 if (val >= 0) 1267 { 1268 operands[2] = GEN_INT (0x7); 1269 operands[3] = GEN_INT (val - 0x7); 1270 } 1271 else 1272 { 1273 operands[2] = GEN_INT (- 0x8); 1274 operands[3] = GEN_INT (val + 0x8); 1275 } 1276}) 1277 1278(define_split 1279 [(set (match_operand:DI 0 "d_operand") 1280 (plus:DI (match_dup 0) 1281 (match_operand:DI 1 "const_int_operand")))] 1282 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE 1283 && ((INTVAL (operands[1]) > 0xf 1284 && INTVAL (operands[1]) <= 0xf + 0xf) 1285 || (INTVAL (operands[1]) < - 0x10 1286 && INTVAL (operands[1]) >= - 0x10 - 0x10))" 1287 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1))) 1288 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))] 1289{ 1290 HOST_WIDE_INT val = INTVAL (operands[1]); 1291 1292 if (val >= 0) 1293 { 1294 operands[1] = GEN_INT (0xf); 1295 operands[2] = GEN_INT (val - 0xf); 1296 } 1297 else 1298 { 1299 operands[1] = GEN_INT (- 0x10); 1300 operands[2] = GEN_INT (val + 0x10); 1301 } 1302}) 1303 1304(define_split 1305 [(set (match_operand:DI 0 "d_operand") 1306 (plus:DI (match_operand:DI 1 "d_operand") 1307 (match_operand:DI 2 "const_int_operand")))] 1308 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE 1309 && REGNO (operands[0]) != REGNO (operands[1]) 1310 && ((INTVAL (operands[2]) > 0x7 1311 && INTVAL (operands[2]) <= 0x7 + 0xf) 1312 || (INTVAL (operands[2]) < - 0x8 1313 && INTVAL (operands[2]) >= - 0x8 - 0x10))" 1314 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) 1315 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] 1316{ 1317 HOST_WIDE_INT val = INTVAL (operands[2]); 1318 1319 if (val >= 0) 1320 { 1321 operands[2] = GEN_INT (0x7); 1322 operands[3] = GEN_INT (val - 0x7); 1323 } 1324 else 1325 { 1326 operands[2] = GEN_INT (- 0x8); 1327 operands[3] = GEN_INT (val + 0x8); 1328 } 1329}) 1330 1331(define_insn "*addsi3_extended" 1332 [(set (match_operand:DI 0 "register_operand" "=d,d") 1333 (sign_extend:DI 1334 (plus:SI (match_operand:SI 1 "register_operand" "d,d") 1335 (match_operand:SI 2 "arith_operand" "d,Q"))))] 1336 "TARGET_64BIT && !TARGET_MIPS16" 1337 "@ 1338 addu\t%0,%1,%2 1339 addiu\t%0,%1,%2" 1340 [(set_attr "alu_type" "add") 1341 (set_attr "mode" "SI")]) 1342 1343;; Split this insn so that the addiu splitters can have a crack at it. 1344;; Use a conservative length estimate until the split. 1345(define_insn_and_split "*addsi3_extended_mips16" 1346 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 1347 (sign_extend:DI 1348 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d") 1349 (match_operand:SI 2 "arith_operand" "Q,O,d"))))] 1350 "TARGET_64BIT && TARGET_MIPS16" 1351 "#" 1352 "&& reload_completed" 1353 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))] 1354 { operands[3] = gen_lowpart (SImode, operands[0]); } 1355 [(set_attr "alu_type" "add") 1356 (set_attr "mode" "SI") 1357 (set_attr "extended_mips16" "yes")]) 1358 1359;; Combiner patterns for unsigned byte-add. 1360 1361(define_insn "*baddu_si_eb" 1362 [(set (match_operand:SI 0 "register_operand" "=d") 1363 (zero_extend:SI 1364 (subreg:QI 1365 (plus:SI (match_operand:SI 1 "register_operand" "d") 1366 (match_operand:SI 2 "register_operand" "d")) 3)))] 1367 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN" 1368 "baddu\\t%0,%1,%2" 1369 [(set_attr "alu_type" "add")]) 1370 1371(define_insn "*baddu_si_el" 1372 [(set (match_operand:SI 0 "register_operand" "=d") 1373 (zero_extend:SI 1374 (subreg:QI 1375 (plus:SI (match_operand:SI 1 "register_operand" "d") 1376 (match_operand:SI 2 "register_operand" "d")) 0)))] 1377 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN" 1378 "baddu\\t%0,%1,%2" 1379 [(set_attr "alu_type" "add")]) 1380 1381(define_insn "*baddu_di<mode>" 1382 [(set (match_operand:GPR 0 "register_operand" "=d") 1383 (zero_extend:GPR 1384 (truncate:QI 1385 (plus:DI (match_operand:DI 1 "register_operand" "d") 1386 (match_operand:DI 2 "register_operand" "d")))))] 1387 "ISA_HAS_BADDU && TARGET_64BIT" 1388 "baddu\\t%0,%1,%2" 1389 [(set_attr "alu_type" "add")]) 1390 1391;; 1392;; .................... 1393;; 1394;; SUBTRACTION 1395;; 1396;; .................... 1397;; 1398 1399(define_insn "sub<mode>3" 1400 [(set (match_operand:ANYF 0 "register_operand" "=f") 1401 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f") 1402 (match_operand:ANYF 2 "register_operand" "f")))] 1403 "" 1404 "sub.<fmt>\t%0,%1,%2" 1405 [(set_attr "type" "fadd") 1406 (set_attr "mode" "<UNITMODE>")]) 1407 1408(define_insn "sub<mode>3" 1409 [(set (match_operand:GPR 0 "register_operand" "=!u,d") 1410 (minus:GPR (match_operand:GPR 1 "register_operand" "!u,d") 1411 (match_operand:GPR 2 "register_operand" "!u,d")))] 1412 "" 1413 "<d>subu\t%0,%1,%2" 1414 [(set_attr "alu_type" "sub") 1415 (set_attr "compression" "micromips32,*") 1416 (set_attr "mode" "<MODE>")]) 1417 1418(define_insn "*subsi3_extended" 1419 [(set (match_operand:DI 0 "register_operand" "=d") 1420 (sign_extend:DI 1421 (minus:SI (match_operand:SI 1 "register_operand" "d") 1422 (match_operand:SI 2 "register_operand" "d"))))] 1423 "TARGET_64BIT" 1424 "subu\t%0,%1,%2" 1425 [(set_attr "alu_type" "sub") 1426 (set_attr "mode" "DI")]) 1427 1428;; 1429;; .................... 1430;; 1431;; MULTIPLICATION 1432;; 1433;; .................... 1434;; 1435 1436(define_expand "mul<mode>3" 1437 [(set (match_operand:SCALARF 0 "register_operand") 1438 (mult:SCALARF (match_operand:SCALARF 1 "register_operand") 1439 (match_operand:SCALARF 2 "register_operand")))] 1440 "" 1441 "") 1442 1443(define_insn "*mul<mode>3" 1444 [(set (match_operand:SCALARF 0 "register_operand" "=f") 1445 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f") 1446 (match_operand:SCALARF 2 "register_operand" "f")))] 1447 "!TARGET_4300_MUL_FIX" 1448 "mul.<fmt>\t%0,%1,%2" 1449 [(set_attr "type" "fmul") 1450 (set_attr "mode" "<MODE>")]) 1451 1452;; Early VR4300 silicon has a CPU bug where multiplies with certain 1453;; operands may corrupt immediately following multiplies. This is a 1454;; simple fix to insert NOPs. 1455 1456(define_insn "*mul<mode>3_r4300" 1457 [(set (match_operand:SCALARF 0 "register_operand" "=f") 1458 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f") 1459 (match_operand:SCALARF 2 "register_operand" "f")))] 1460 "TARGET_4300_MUL_FIX" 1461 "mul.<fmt>\t%0,%1,%2\;nop" 1462 [(set_attr "type" "fmul") 1463 (set_attr "mode" "<MODE>") 1464 (set_attr "insn_count" "2")]) 1465 1466(define_insn "mulv2sf3" 1467 [(set (match_operand:V2SF 0 "register_operand" "=f") 1468 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f") 1469 (match_operand:V2SF 2 "register_operand" "f")))] 1470 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" 1471 "mul.ps\t%0,%1,%2" 1472 [(set_attr "type" "fmul") 1473 (set_attr "mode" "SF")]) 1474 1475;; The original R4000 has a cpu bug. If a double-word or a variable 1476;; shift executes while an integer multiplication is in progress, the 1477;; shift may give an incorrect result. Avoid this by keeping the mflo 1478;; with the mult on the R4000. 1479;; 1480;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" 1481;; (also valid for MIPS R4000MC processors): 1482;; 1483;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to 1484;; this errata description. 1485;; The following code sequence causes the R4000 to incorrectly 1486;; execute the Double Shift Right Arithmetic 32 (dsra32) 1487;; instruction. If the dsra32 instruction is executed during an 1488;; integer multiply, the dsra32 will only shift by the amount in 1489;; specified in the instruction rather than the amount plus 32 1490;; bits. 1491;; instruction 1: mult rs,rt integer multiply 1492;; instruction 2-12: dsra32 rd,rt,rs doubleword shift 1493;; right arithmetic + 32 1494;; Workaround: A dsra32 instruction placed after an integer 1495;; multiply should not be one of the 11 instructions after the 1496;; multiply instruction." 1497;; 1498;; and: 1499;; 1500;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by 1501;; the following description. 1502;; All extended shifts (shift by n+32) and variable shifts (32 and 1503;; 64-bit versions) may produce incorrect results under the 1504;; following conditions: 1505;; 1) An integer multiply is currently executing 1506;; 2) These types of shift instructions are executed immediately 1507;; following an integer divide instruction. 1508;; Workaround: 1509;; 1) Make sure no integer multiply is running wihen these 1510;; instruction are executed. If this cannot be predicted at 1511;; compile time, then insert a "mfhi" to R0 instruction 1512;; immediately after the integer multiply instruction. This 1513;; will cause the integer multiply to complete before the shift 1514;; is executed. 1515;; 2) Separate integer divide and these two classes of shift 1516;; instructions by another instruction or a noop." 1517;; 1518;; These processors have PRId values of 0x00004220 and 0x00004300, 1519;; respectively. 1520 1521(define_expand "mul<mode>3" 1522 [(set (match_operand:GPR 0 "register_operand") 1523 (mult:GPR (match_operand:GPR 1 "register_operand") 1524 (match_operand:GPR 2 "register_operand")))] 1525 "ISA_HAS_<D>MULT || ISA_HAS_R6<D>MUL" 1526{ 1527 rtx lo; 1528 1529 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>MUL) 1530 emit_insn (gen_mul<mode>3_mul3_nohilo (operands[0], operands[1], 1531 operands[2])); 1532 else if (ISA_HAS_<D>MUL3) 1533 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2])); 1534 else if (TARGET_MIPS16) 1535 { 1536 lo = gen_rtx_REG (<MODE>mode, LO_REGNUM); 1537 emit_insn (gen_mul<mode>3_internal (lo, operands[1], operands[2])); 1538 emit_move_insn (operands[0], lo); 1539 } 1540 else if (TARGET_FIX_R4000) 1541 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2])); 1542 else 1543 emit_insn 1544 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2])); 1545 DONE; 1546}) 1547 1548(define_insn "mul<mode>3_mul3_nohilo" 1549 [(set (match_operand:GPR 0 "register_operand" "=d") 1550 (mult:GPR (match_operand:GPR 1 "register_operand" "d") 1551 (match_operand:GPR 2 "register_operand" "d")))] 1552 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>MUL" 1553{ 1554 if (TARGET_LOONGSON_2EF) 1555 return "<d>multu.g\t%0,%1,%2"; 1556 else if (TARGET_LOONGSON_3A) 1557 return "gs<d>multu\t%0,%1,%2"; 1558 else 1559 return "<d>mul\t%0,%1,%2"; 1560} 1561 [(set_attr "type" "imul3nc") 1562 (set_attr "mode" "<MODE>")]) 1563 1564(define_insn "mul<mode>3_mul3" 1565 [(set (match_operand:GPR 0 "register_operand" "=d,l") 1566 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d") 1567 (match_operand:GPR 2 "register_operand" "d,d"))) 1568 (clobber (match_scratch:GPR 3 "=l,X"))] 1569 "ISA_HAS_<D>MUL3" 1570{ 1571 if (which_alternative == 1) 1572 return "<d>mult\t%1,%2"; 1573 if (<MODE>mode == SImode && (TARGET_MIPS3900 || TARGET_MIPS5900)) 1574 return "mult\t%0,%1,%2"; 1575 return "<d>mul\t%0,%1,%2"; 1576} 1577 [(set_attr "type" "imul3,imul") 1578 (set_attr "mode" "<MODE>")]) 1579 1580;; If a register gets allocated to LO, and we spill to memory, the reload 1581;; will include a move from LO to a GPR. Merge it into the multiplication 1582;; if it can set the GPR directly. 1583;; 1584;; Operand 0: LO 1585;; Operand 1: GPR (1st multiplication operand) 1586;; Operand 2: GPR (2nd multiplication operand) 1587;; Operand 3: GPR (destination) 1588(define_peephole2 1589 [(parallel 1590 [(set (match_operand:SI 0 "lo_operand") 1591 (mult:SI (match_operand:SI 1 "d_operand") 1592 (match_operand:SI 2 "d_operand"))) 1593 (clobber (scratch:SI))]) 1594 (set (match_operand:SI 3 "d_operand") 1595 (match_dup 0))] 1596 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])" 1597 [(parallel 1598 [(set (match_dup 3) 1599 (mult:SI (match_dup 1) 1600 (match_dup 2))) 1601 (clobber (match_dup 0))])]) 1602 1603(define_insn "mul<mode>3_internal" 1604 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l") 1605 (mult:GPR (match_operand:GPR 1 "register_operand" "d") 1606 (match_operand:GPR 2 "register_operand" "d")))] 1607 "ISA_HAS_<D>MULT && !TARGET_FIX_R4000" 1608 "<d>mult\t%1,%2" 1609 [(set_attr "type" "imul") 1610 (set_attr "mode" "<MODE>")]) 1611 1612(define_insn "mul<mode>3_r4000" 1613 [(set (match_operand:GPR 0 "register_operand" "=d") 1614 (mult:GPR (match_operand:GPR 1 "register_operand" "d") 1615 (match_operand:GPR 2 "register_operand" "d"))) 1616 (clobber (match_scratch:GPR 3 "=l"))] 1617 "ISA_HAS_<D>MULT && TARGET_FIX_R4000" 1618 "<d>mult\t%1,%2\;mflo\t%0" 1619 [(set_attr "type" "imul") 1620 (set_attr "mode" "<MODE>") 1621 (set_attr "insn_count" "2")]) 1622 1623;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead 1624;; of "mult; mflo". They have the same latency, but the first form gives 1625;; us an extra cycle to compute the operands. 1626 1627;; Operand 0: LO 1628;; Operand 1: GPR (1st multiplication operand) 1629;; Operand 2: GPR (2nd multiplication operand) 1630;; Operand 3: GPR (destination) 1631(define_peephole2 1632 [(set (match_operand:SI 0 "lo_operand") 1633 (mult:SI (match_operand:SI 1 "d_operand") 1634 (match_operand:SI 2 "d_operand"))) 1635 (set (match_operand:SI 3 "d_operand") 1636 (match_dup 0))] 1637 "ISA_HAS_MACC && !ISA_HAS_MUL3" 1638 [(set (match_dup 0) 1639 (const_int 0)) 1640 (parallel 1641 [(set (match_dup 0) 1642 (plus:SI (mult:SI (match_dup 1) 1643 (match_dup 2)) 1644 (match_dup 0))) 1645 (set (match_dup 3) 1646 (plus:SI (mult:SI (match_dup 1) 1647 (match_dup 2)) 1648 (match_dup 0)))])]) 1649 1650;; Multiply-accumulate patterns 1651 1652;; This pattern is first matched by combine, which tries to use the 1653;; pattern wherever it can. We don't know until later whether it 1654;; is actually profitable to use MADD over a "MUL; ADDIU" sequence, 1655;; so we need to keep both options open. 1656;; 1657;; The second alternative has a "?" marker because it is generally 1658;; one instruction more costly than the first alternative. This "?" 1659;; marker is enough to convey the relative costs to the register 1660;; allocator. 1661;; 1662;; However, reload counts reloads of operands 4 and 5 in the same way as 1663;; reloads of the other operands, even though operands 4 and 5 need no 1664;; copy instructions. Reload therefore thinks that the second alternative 1665;; is two reloads more costly than the first. We add "*?*?" to the first 1666;; alternative as a counterweight. 1667;; 1668;; LRA simulates reload but the cost of reloading scratches is lower 1669;; than of the classic reload. For the time being, removing the counterweight 1670;; for LRA is more profitable. 1671(define_insn "*mul_acc_si" 1672 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d?") 1673 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d") 1674 (match_operand:SI 2 "register_operand" "d,d,d")) 1675 (match_operand:SI 3 "register_operand" "0,0,d"))) 1676 (clobber (match_scratch:SI 4 "=X,X,l")) 1677 (clobber (match_scratch:SI 5 "=X,X,&d"))] 1678 "GENERATE_MADD_MSUB && !TARGET_MIPS16" 1679 "@ 1680 madd\t%1,%2 1681 madd\t%1,%2 1682 #" 1683 [(set_attr "type" "imadd") 1684 (set_attr "accum_in" "3") 1685 (set_attr "mode" "SI") 1686 (set_attr "insn_count" "1,1,2") 1687 (set (attr "enabled") 1688 (cond [(and (eq_attr "alternative" "0") 1689 (match_test "!mips_lra_flag")) 1690 (const_string "yes") 1691 (and (eq_attr "alternative" "1") 1692 (match_test "mips_lra_flag")) 1693 (const_string "yes") 1694 (eq_attr "alternative" "2") 1695 (const_string "yes")] 1696 (const_string "no")))]) 1697 1698;; The same idea applies here. The middle alternative needs one less 1699;; clobber than the final alternative, so we add "*?" as a counterweight. 1700(define_insn "*mul_acc_si_r3900" 1701 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d*?,d?") 1702 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d,d") 1703 (match_operand:SI 2 "register_operand" "d,d,d,d")) 1704 (match_operand:SI 3 "register_operand" "0,0,l,d"))) 1705 (clobber (match_scratch:SI 4 "=X,X,3,l")) 1706 (clobber (match_scratch:SI 5 "=X,X,X,&d"))] 1707 "TARGET_MIPS3900 && !TARGET_MIPS16" 1708 "@ 1709 madd\t%1,%2 1710 madd\t%1,%2 1711 madd\t%0,%1,%2 1712 #" 1713 [(set_attr "type" "imadd") 1714 (set_attr "accum_in" "3") 1715 (set_attr "mode" "SI") 1716 (set_attr "insn_count" "1,1,1,2") 1717 (set (attr "enabled") 1718 (cond [(and (eq_attr "alternative" "0") 1719 (match_test "!mips_lra_flag")) 1720 (const_string "yes") 1721 (and (eq_attr "alternative" "1") 1722 (match_test "mips_lra_flag")) 1723 (const_string "yes") 1724 (eq_attr "alternative" "2,3") 1725 (const_string "yes")] 1726 (const_string "no")))]) 1727 1728;; Split *mul_acc_si if both the source and destination accumulator 1729;; values are GPRs. 1730(define_split 1731 [(set (match_operand:SI 0 "d_operand") 1732 (plus:SI (mult:SI (match_operand:SI 1 "d_operand") 1733 (match_operand:SI 2 "d_operand")) 1734 (match_operand:SI 3 "d_operand"))) 1735 (clobber (match_operand:SI 4 "lo_operand")) 1736 (clobber (match_operand:SI 5 "d_operand"))] 1737 "reload_completed" 1738 [(parallel [(set (match_dup 5) 1739 (mult:SI (match_dup 1) (match_dup 2))) 1740 (clobber (match_dup 4))]) 1741 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))] 1742 "") 1743 1744(define_insn "*macc" 1745 [(set (match_operand:SI 0 "register_operand" "=l,d") 1746 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") 1747 (match_operand:SI 2 "register_operand" "d,d")) 1748 (match_operand:SI 3 "register_operand" "0,l"))) 1749 (clobber (match_scratch:SI 4 "=X,3"))] 1750 "ISA_HAS_MACC" 1751{ 1752 if (which_alternative == 1) 1753 return "macc\t%0,%1,%2"; 1754 else if (TARGET_MIPS5500) 1755 return "madd\t%1,%2"; 1756 else 1757 /* The VR4130 assumes that there is a two-cycle latency between a macc 1758 that "writes" to $0 and an instruction that reads from it. We avoid 1759 this by assigning to $1 instead. */ 1760 return "%[macc\t%@,%1,%2%]"; 1761} 1762 [(set_attr "type" "imadd") 1763 (set_attr "accum_in" "3") 1764 (set_attr "mode" "SI")]) 1765 1766(define_insn "*msac" 1767 [(set (match_operand:SI 0 "register_operand" "=l,d") 1768 (minus:SI (match_operand:SI 1 "register_operand" "0,l") 1769 (mult:SI (match_operand:SI 2 "register_operand" "d,d") 1770 (match_operand:SI 3 "register_operand" "d,d")))) 1771 (clobber (match_scratch:SI 4 "=X,1"))] 1772 "ISA_HAS_MSAC" 1773{ 1774 if (which_alternative == 1) 1775 return "msac\t%0,%2,%3"; 1776 else if (TARGET_MIPS5500) 1777 return "msub\t%2,%3"; 1778 else 1779 return "msac\t$0,%2,%3"; 1780} 1781 [(set_attr "type" "imadd") 1782 (set_attr "accum_in" "1") 1783 (set_attr "mode" "SI")]) 1784 1785;; An msac-like instruction implemented using negation and a macc. 1786(define_insn_and_split "*msac_using_macc" 1787 [(set (match_operand:SI 0 "register_operand" "=l,d") 1788 (minus:SI (match_operand:SI 1 "register_operand" "0,l") 1789 (mult:SI (match_operand:SI 2 "register_operand" "d,d") 1790 (match_operand:SI 3 "register_operand" "d,d")))) 1791 (clobber (match_scratch:SI 4 "=X,1")) 1792 (clobber (match_scratch:SI 5 "=d,d"))] 1793 "ISA_HAS_MACC && !ISA_HAS_MSAC" 1794 "#" 1795 "&& reload_completed" 1796 [(set (match_dup 5) 1797 (neg:SI (match_dup 3))) 1798 (parallel 1799 [(set (match_dup 0) 1800 (plus:SI (mult:SI (match_dup 2) 1801 (match_dup 5)) 1802 (match_dup 1))) 1803 (clobber (match_dup 4))])] 1804 "" 1805 [(set_attr "type" "imadd") 1806 (set_attr "accum_in" "1") 1807 (set_attr "insn_count" "2")]) 1808 1809;; Patterns generated by the define_peephole2 below. 1810 1811(define_insn "*macc2" 1812 [(set (match_operand:SI 0 "muldiv_target_operand" "=l") 1813 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") 1814 (match_operand:SI 2 "register_operand" "d")) 1815 (match_dup 0))) 1816 (set (match_operand:SI 3 "register_operand" "=d") 1817 (plus:SI (mult:SI (match_dup 1) 1818 (match_dup 2)) 1819 (match_dup 0)))] 1820 "ISA_HAS_MACC && reload_completed" 1821 "macc\t%3,%1,%2" 1822 [(set_attr "type" "imadd") 1823 (set_attr "accum_in" "0") 1824 (set_attr "mode" "SI")]) 1825 1826(define_insn "*msac2" 1827 [(set (match_operand:SI 0 "muldiv_target_operand" "=l") 1828 (minus:SI (match_dup 0) 1829 (mult:SI (match_operand:SI 1 "register_operand" "d") 1830 (match_operand:SI 2 "register_operand" "d")))) 1831 (set (match_operand:SI 3 "register_operand" "=d") 1832 (minus:SI (match_dup 0) 1833 (mult:SI (match_dup 1) 1834 (match_dup 2))))] 1835 "ISA_HAS_MSAC && reload_completed" 1836 "msac\t%3,%1,%2" 1837 [(set_attr "type" "imadd") 1838 (set_attr "accum_in" "0") 1839 (set_attr "mode" "SI")]) 1840 1841;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2> 1842;; Similarly msac. 1843;; 1844;; Operand 0: LO 1845;; Operand 1: macc/msac 1846;; Operand 2: GPR (destination) 1847(define_peephole2 1848 [(parallel 1849 [(set (match_operand:SI 0 "lo_operand") 1850 (match_operand:SI 1 "macc_msac_operand")) 1851 (clobber (scratch:SI))]) 1852 (set (match_operand:SI 2 "d_operand") 1853 (match_dup 0))] 1854 "" 1855 [(parallel [(set (match_dup 0) 1856 (match_dup 1)) 1857 (set (match_dup 2) 1858 (match_dup 1))])]) 1859 1860;; When we have a three-address multiplication instruction, it should 1861;; be faster to do a separate multiply and add, rather than moving 1862;; something into LO in order to use a macc instruction. 1863;; 1864;; This peephole needs a scratch register to cater for the case when one 1865;; of the multiplication operands is the same as the destination. 1866;; 1867;; Operand 0: GPR (scratch) 1868;; Operand 1: LO 1869;; Operand 2: GPR (addend) 1870;; Operand 3: GPR (destination) 1871;; Operand 4: macc/msac 1872;; Operand 5: new multiplication 1873;; Operand 6: new addition/subtraction 1874(define_peephole2 1875 [(match_scratch:SI 0 "d") 1876 (set (match_operand:SI 1 "lo_operand") 1877 (match_operand:SI 2 "d_operand")) 1878 (match_dup 0) 1879 (parallel 1880 [(set (match_operand:SI 3 "d_operand") 1881 (match_operand:SI 4 "macc_msac_operand")) 1882 (clobber (match_dup 1))])] 1883 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])" 1884 [(parallel [(set (match_dup 0) 1885 (match_dup 5)) 1886 (clobber (match_dup 1))]) 1887 (set (match_dup 3) 1888 (match_dup 6))] 1889{ 1890 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1); 1891 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, 1892 operands[2], operands[0]); 1893}) 1894 1895;; Same as above, except LO is the initial target of the macc. 1896;; 1897;; Operand 0: GPR (scratch) 1898;; Operand 1: LO 1899;; Operand 2: GPR (addend) 1900;; Operand 3: macc/msac 1901;; Operand 4: GPR (destination) 1902;; Operand 5: new multiplication 1903;; Operand 6: new addition/subtraction 1904(define_peephole2 1905 [(match_scratch:SI 0 "d") 1906 (set (match_operand:SI 1 "lo_operand") 1907 (match_operand:SI 2 "d_operand")) 1908 (match_dup 0) 1909 (parallel 1910 [(set (match_dup 1) 1911 (match_operand:SI 3 "macc_msac_operand")) 1912 (clobber (scratch:SI))]) 1913 (match_dup 0) 1914 (set (match_operand:SI 4 "d_operand") 1915 (match_dup 1))] 1916 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])" 1917 [(parallel [(set (match_dup 0) 1918 (match_dup 5)) 1919 (clobber (match_dup 1))]) 1920 (set (match_dup 4) 1921 (match_dup 6))] 1922{ 1923 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1); 1924 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, 1925 operands[2], operands[0]); 1926}) 1927 1928;; See the comment above *mul_add_si for details. 1929(define_insn "*mul_sub_si" 1930 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d?") 1931 (minus:SI (match_operand:SI 1 "register_operand" "0,0,d") 1932 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d") 1933 (match_operand:SI 3 "register_operand" "d,d,d")))) 1934 (clobber (match_scratch:SI 4 "=X,X,l")) 1935 (clobber (match_scratch:SI 5 "=X,X,&d"))] 1936 "GENERATE_MADD_MSUB" 1937 "@ 1938 msub\t%2,%3 1939 msub\t%2,%3 1940 #" 1941 [(set_attr "type" "imadd") 1942 (set_attr "accum_in" "1") 1943 (set_attr "mode" "SI") 1944 (set_attr "insn_count" "1,1,2") 1945 (set (attr "enabled") 1946 (cond [(and (eq_attr "alternative" "0") 1947 (match_test "!mips_lra_flag")) 1948 (const_string "yes") 1949 (and (eq_attr "alternative" "1") 1950 (match_test "mips_lra_flag")) 1951 (const_string "yes") 1952 (eq_attr "alternative" "2") 1953 (const_string "yes")] 1954 (const_string "no")))]) 1955 1956;; Split *mul_sub_si if both the source and destination accumulator 1957;; values are GPRs. 1958(define_split 1959 [(set (match_operand:SI 0 "d_operand") 1960 (minus:SI (match_operand:SI 1 "d_operand") 1961 (mult:SI (match_operand:SI 2 "d_operand") 1962 (match_operand:SI 3 "d_operand")))) 1963 (clobber (match_operand:SI 4 "lo_operand")) 1964 (clobber (match_operand:SI 5 "d_operand"))] 1965 "reload_completed" 1966 [(parallel [(set (match_dup 5) 1967 (mult:SI (match_dup 2) (match_dup 3))) 1968 (clobber (match_dup 4))]) 1969 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))] 1970 "") 1971 1972(define_insn "*muls" 1973 [(set (match_operand:SI 0 "register_operand" "=l,d") 1974 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d") 1975 (match_operand:SI 2 "register_operand" "d,d")))) 1976 (clobber (match_scratch:SI 3 "=X,l"))] 1977 "ISA_HAS_MULS" 1978 "@ 1979 muls\t$0,%1,%2 1980 muls\t%0,%1,%2" 1981 [(set_attr "type" "imul,imul3") 1982 (set_attr "mode" "SI")]) 1983 1984(define_expand "<u>mulsidi3" 1985 [(set (match_operand:DI 0 "register_operand") 1986 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 1987 (any_extend:DI (match_operand:SI 2 "register_operand"))))] 1988 "mips_mulsidi3_gen_fn (<CODE>) != NULL" 1989{ 1990 mulsidi3_gen_fn fn = mips_mulsidi3_gen_fn (<CODE>); 1991 emit_insn (fn (operands[0], operands[1], operands[2])); 1992 DONE; 1993}) 1994 1995(define_expand "<u>mulsidi3_32bit_r6" 1996 [(set (match_operand:DI 0 "register_operand") 1997 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 1998 (any_extend:DI (match_operand:SI 2 "register_operand"))))] 1999 "!TARGET_64BIT && ISA_HAS_R6MUL" 2000{ 2001 rtx dest = gen_reg_rtx (DImode); 2002 rtx low = mips_subword (dest, 0); 2003 rtx high = mips_subword (dest, 1); 2004 2005 emit_insn (gen_mulsi3_mul3_nohilo (low, operands[1], operands[2])); 2006 emit_insn (gen_<su>mulsi3_highpart_r6 (high, operands[1], operands[2])); 2007 2008 emit_move_insn (mips_subword (operands[0], 0), low); 2009 emit_move_insn (mips_subword (operands[0], 1), high); 2010 DONE; 2011}) 2012 2013(define_expand "<u>mulsidi3_32bit_mips16" 2014 [(set (match_operand:DI 0 "register_operand") 2015 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2016 (any_extend:DI (match_operand:SI 2 "register_operand"))))] 2017 "!TARGET_64BIT && TARGET_MIPS16" 2018{ 2019 rtx hilo; 2020 2021 hilo = gen_rtx_REG (DImode, MD_REG_FIRST); 2022 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2])); 2023 emit_move_insn (operands[0], hilo); 2024 DONE; 2025}) 2026 2027;; As well as being named patterns, these instructions are used by the 2028;; __builtin_mips_mult<u>() functions. We must always make those functions 2029;; available if !TARGET_64BIT && ISA_HAS_DSP. 2030(define_insn "<u>mulsidi3_32bit" 2031 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka") 2032 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2033 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))] 2034 "!TARGET_64BIT && (!TARGET_FIX_R4000 || ISA_HAS_DSP) && ISA_HAS_MULT" 2035{ 2036 if (ISA_HAS_DSP_MULT) 2037 return "mult<u>\t%q0,%1,%2"; 2038 else 2039 return "mult<u>\t%1,%2"; 2040} 2041 [(set_attr "type" "imul") 2042 (set_attr "mode" "SI")]) 2043 2044(define_insn "<u>mulsidi3_32bit_r4000" 2045 [(set (match_operand:DI 0 "register_operand" "=d") 2046 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2047 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) 2048 (clobber (match_scratch:DI 3 "=x"))] 2049 "!TARGET_64BIT && TARGET_FIX_R4000 && !ISA_HAS_DSP && ISA_HAS_MULT" 2050 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0" 2051 [(set_attr "type" "imul") 2052 (set_attr "mode" "SI") 2053 (set_attr "insn_count" "3")]) 2054 2055(define_insn_and_split "<u>mulsidi3_64bit" 2056 [(set (match_operand:DI 0 "register_operand" "=d") 2057 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2058 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) 2059 (clobber (match_scratch:TI 3 "=x")) 2060 (clobber (match_scratch:DI 4 "=d"))] 2061 "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DMUL3 2062 && !TARGET_MIPS16 && ISA_HAS_MULT" 2063 "#" 2064 "&& reload_completed" 2065 [(const_int 0)] 2066{ 2067 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1], 2068 operands[2], operands[4])); 2069 DONE; 2070} 2071 [(set_attr "type" "imul") 2072 (set_attr "mode" "SI") 2073 (set (attr "insn_count") 2074 (if_then_else (match_test "ISA_HAS_EXT_INS") 2075 (const_int 4) 2076 (const_int 7)))]) 2077 2078(define_expand "<u>mulsidi3_64bit_mips16" 2079 [(set (match_operand:DI 0 "register_operand") 2080 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2081 (any_extend:DI (match_operand:SI 2 "register_operand"))))] 2082 "TARGET_64BIT && TARGET_MIPS16" 2083{ 2084 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1], 2085 operands[2], gen_reg_rtx (DImode))); 2086 DONE; 2087}) 2088 2089(define_expand "<u>mulsidi3_64bit_split" 2090 [(set (match_operand:DI 0 "register_operand") 2091 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2092 (any_extend:DI (match_operand:SI 2 "register_operand")))) 2093 (clobber (match_operand:DI 3 "register_operand"))] 2094 "" 2095{ 2096 rtx hilo; 2097 2098 hilo = gen_rtx_REG (TImode, MD_REG_FIRST); 2099 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2])); 2100 2101 emit_move_insn (operands[0], gen_rtx_REG (DImode, LO_REGNUM)); 2102 emit_insn (gen_mfhidi_ti (operands[3], hilo)); 2103 2104 if (ISA_HAS_EXT_INS) 2105 emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32), 2106 operands[3])); 2107 else 2108 { 2109 /* Zero-extend the low part. */ 2110 mips_emit_binary (ASHIFT, operands[0], operands[0], GEN_INT (32)); 2111 mips_emit_binary (LSHIFTRT, operands[0], operands[0], GEN_INT (32)); 2112 2113 /* Shift the high part into place. */ 2114 mips_emit_binary (ASHIFT, operands[3], operands[3], GEN_INT (32)); 2115 2116 /* OR the two halves together. */ 2117 mips_emit_binary (IOR, operands[0], operands[0], operands[3]); 2118 } 2119 DONE; 2120}) 2121 2122(define_insn "<u>mulsidi3_64bit_hilo" 2123 [(set (match_operand:TI 0 "muldiv_target_operand" "=x") 2124 (unspec:TI 2125 [(mult:DI 2126 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2127 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))] 2128 UNSPEC_SET_HILO))] 2129 "TARGET_64BIT && !TARGET_FIX_R4000" 2130 "mult<u>\t%1,%2" 2131 [(set_attr "type" "imul") 2132 (set_attr "mode" "SI")]) 2133 2134;; See comment before the ISA_HAS_DMUL3 case in mips_mulsidi3_gen_fn. 2135(define_insn "mulsidi3_64bit_dmul" 2136 [(set (match_operand:DI 0 "register_operand" "=d") 2137 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) 2138 (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))) 2139 (clobber (match_scratch:DI 3 "=l"))] 2140 "ISA_HAS_DMUL3" 2141 "dmul\t%0,%1,%2" 2142 [(set_attr "type" "imul3") 2143 (set_attr "mode" "DI")]) 2144 2145(define_insn "mulsidi3_64bit_r6dmul" 2146 [(set (match_operand:DI 0 "register_operand" "=d") 2147 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) 2148 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] 2149 "ISA_HAS_R6DMUL" 2150 "dmul\t%0,%1,%2" 2151 [(set_attr "type" "imul3nc") 2152 (set_attr "mode" "DI")]) 2153 2154;; Widening multiply with negation. 2155(define_insn "*muls<u>_di" 2156 [(set (match_operand:DI 0 "muldiv_target_operand" "=x") 2157 (neg:DI 2158 (mult:DI 2159 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2160 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))] 2161 "!TARGET_64BIT && ISA_HAS_MULS" 2162 "muls<u>\t$0,%1,%2" 2163 [(set_attr "type" "imul") 2164 (set_attr "mode" "SI")]) 2165 2166;; As well as being named patterns, these instructions are used by the 2167;; __builtin_mips_msub<u>() functions. We must always make those functions 2168;; available if !TARGET_64BIT && ISA_HAS_DSP. 2169;; 2170;; This leads to a slight inconsistency. We honor any tuning overrides 2171;; in GENERATE_MADD_MSUB for -mno-dsp, but always ignore them for -mdsp, 2172;; even if !ISA_HAS_DSP_MULT. 2173(define_insn "<u>msubsidi4" 2174 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka") 2175 (minus:DI 2176 (match_operand:DI 3 "muldiv_target_operand" "0") 2177 (mult:DI 2178 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2179 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))] 2180 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)" 2181{ 2182 if (ISA_HAS_DSP_MULT) 2183 return "msub<u>\t%q0,%1,%2"; 2184 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB) 2185 return "msub<u>\t%1,%2"; 2186 else 2187 return "msac<u>\t$0,%1,%2"; 2188} 2189 [(set_attr "type" "imadd") 2190 (set_attr "accum_in" "3") 2191 (set_attr "mode" "SI")]) 2192 2193;; _highpart patterns 2194 2195(define_expand "<su>mulsi3_highpart" 2196 [(set (match_operand:SI 0 "register_operand") 2197 (truncate:SI 2198 (lshiftrt:DI 2199 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2200 (any_extend:DI (match_operand:SI 2 "register_operand"))) 2201 (const_int 32))))] 2202 "" 2203{ 2204 if (ISA_HAS_MULHI) 2205 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0], 2206 operands[1], 2207 operands[2])); 2208 else if (TARGET_MIPS16) 2209 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1], 2210 operands[2])); 2211 else if (ISA_HAS_R6MUL) 2212 emit_insn (gen_<su>mulsi3_highpart_r6 (operands[0], operands[1], 2213 operands[2])); 2214 else 2215 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1], 2216 operands[2])); 2217 DONE; 2218}) 2219 2220(define_insn "<su>mulsi3_highpart_r6" 2221 [(set (match_operand:SI 0 "register_operand" "=d") 2222 (truncate:SI 2223 (lshiftrt:DI 2224 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2225 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) 2226 (const_int 32))))] 2227 "ISA_HAS_R6MUL" 2228 "muh<u>\t%0,%1,%2" 2229 [(set_attr "type" "imul3nc") 2230 (set_attr "mode" "SI")]) 2231 2232(define_insn_and_split "<su>mulsi3_highpart_internal" 2233 [(set (match_operand:SI 0 "register_operand" "=d") 2234 (truncate:SI 2235 (lshiftrt:DI 2236 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2237 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) 2238 (const_int 32)))) 2239 (clobber (match_scratch:SI 3 "=l"))] 2240 "ISA_HAS_MULT && !ISA_HAS_MULHI && !TARGET_MIPS16" 2241 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; } 2242 "&& reload_completed && !TARGET_FIX_R4000" 2243 [(const_int 0)] 2244{ 2245 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1], 2246 operands[2])); 2247 DONE; 2248} 2249 [(set_attr "type" "imul") 2250 (set_attr "mode" "SI") 2251 (set_attr "insn_count" "2")]) 2252 2253(define_expand "<su>mulsi3_highpart_split" 2254 [(set (match_operand:SI 0 "register_operand") 2255 (truncate:SI 2256 (lshiftrt:DI 2257 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) 2258 (any_extend:DI (match_operand:SI 2 "register_operand"))) 2259 (const_int 32))))] 2260 "" 2261{ 2262 rtx hilo; 2263 2264 if (TARGET_64BIT) 2265 { 2266 hilo = gen_rtx_REG (TImode, MD_REG_FIRST); 2267 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2])); 2268 emit_insn (gen_mfhisi_ti (operands[0], hilo)); 2269 } 2270 else 2271 { 2272 hilo = gen_rtx_REG (DImode, MD_REG_FIRST); 2273 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2])); 2274 emit_insn (gen_mfhisi_di (operands[0], hilo)); 2275 } 2276 DONE; 2277}) 2278 2279(define_insn "<su>mulsi3_highpart_mulhi_internal" 2280 [(set (match_operand:SI 0 "register_operand" "=d") 2281 (truncate:SI 2282 (lshiftrt:DI 2283 (mult:DI 2284 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2285 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) 2286 (const_int 32)))) 2287 (clobber (match_scratch:SI 3 "=l"))] 2288 "ISA_HAS_MULHI" 2289 "mulhi<u>\t%0,%1,%2" 2290 [(set_attr "type" "imul3") 2291 (set_attr "mode" "SI")]) 2292 2293(define_insn "*<su>mulsi3_highpart_neg_mulhi_internal" 2294 [(set (match_operand:SI 0 "register_operand" "=d") 2295 (truncate:SI 2296 (lshiftrt:DI 2297 (neg:DI 2298 (mult:DI 2299 (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2300 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))) 2301 (const_int 32)))) 2302 (clobber (match_scratch:SI 3 "=l"))] 2303 "ISA_HAS_MULHI" 2304 "mulshi<u>\t%0,%1,%2" 2305 [(set_attr "type" "imul3") 2306 (set_attr "mode" "SI")]) 2307 2308;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120 2309;; errata MD(0), which says that dmultu does not always produce the 2310;; correct result. 2311(define_expand "<su>muldi3_highpart" 2312 [(set (match_operand:DI 0 "register_operand") 2313 (truncate:DI 2314 (lshiftrt:TI 2315 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) 2316 (any_extend:TI (match_operand:DI 2 "register_operand"))) 2317 (const_int 64))))] 2318 "ISA_HAS_R6DMUL 2319 || (ISA_HAS_DMULT 2320 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120))" 2321{ 2322 if (TARGET_MIPS16) 2323 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1], 2324 operands[2])); 2325 else if (ISA_HAS_R6DMUL) 2326 emit_insn (gen_<su>muldi3_highpart_r6 (operands[0], operands[1], 2327 operands[2])); 2328 else 2329 emit_insn (gen_<su>muldi3_highpart_internal (operands[0], operands[1], 2330 operands[2])); 2331 DONE; 2332}) 2333 2334(define_insn "<su>muldi3_highpart_r6" 2335 [(set (match_operand:DI 0 "register_operand" "=d") 2336 (truncate:DI 2337 (lshiftrt:TI 2338 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) 2339 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))) 2340 (const_int 64))))] 2341 "ISA_HAS_R6DMUL" 2342 "dmuh<u>\t%0,%1,%2" 2343 [(set_attr "type" "imul3nc") 2344 (set_attr "mode" "DI")]) 2345 2346(define_insn_and_split "<su>muldi3_highpart_internal" 2347 [(set (match_operand:DI 0 "register_operand" "=d") 2348 (truncate:DI 2349 (lshiftrt:TI 2350 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) 2351 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))) 2352 (const_int 64)))) 2353 (clobber (match_scratch:DI 3 "=l"))] 2354 "ISA_HAS_DMULT 2355 && !TARGET_MIPS16 2356 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)" 2357 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; } 2358 "&& reload_completed && !TARGET_FIX_R4000" 2359 [(const_int 0)] 2360{ 2361 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1], 2362 operands[2])); 2363 DONE; 2364} 2365 [(set_attr "type" "imul") 2366 (set_attr "mode" "DI") 2367 (set_attr "insn_count" "2")]) 2368 2369(define_expand "<su>muldi3_highpart_split" 2370 [(set (match_operand:DI 0 "register_operand") 2371 (truncate:DI 2372 (lshiftrt:TI 2373 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) 2374 (any_extend:TI (match_operand:DI 2 "register_operand"))) 2375 (const_int 64))))] 2376 "" 2377{ 2378 rtx hilo; 2379 2380 hilo = gen_rtx_REG (TImode, MD_REG_FIRST); 2381 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2])); 2382 emit_insn (gen_mfhidi_ti (operands[0], hilo)); 2383 DONE; 2384}) 2385 2386(define_expand "<u>mulditi3" 2387 [(set (match_operand:TI 0 "register_operand") 2388 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) 2389 (any_extend:TI (match_operand:DI 2 "register_operand"))))] 2390 "ISA_HAS_DMULT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)" 2391{ 2392 rtx hilo; 2393 2394 if (TARGET_MIPS16) 2395 { 2396 hilo = gen_rtx_REG (TImode, MD_REG_FIRST); 2397 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2])); 2398 emit_move_insn (operands[0], hilo); 2399 } 2400 else if (TARGET_FIX_R4000) 2401 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2])); 2402 else 2403 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1], 2404 operands[2])); 2405 DONE; 2406}) 2407 2408(define_insn "<u>mulditi3_internal" 2409 [(set (match_operand:TI 0 "muldiv_target_operand" "=x") 2410 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) 2411 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))] 2412 "ISA_HAS_DMULT 2413 && !TARGET_FIX_R4000 2414 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)" 2415 "dmult<u>\t%1,%2" 2416 [(set_attr "type" "imul") 2417 (set_attr "mode" "DI")]) 2418 2419(define_insn "<u>mulditi3_r4000" 2420 [(set (match_operand:TI 0 "register_operand" "=d") 2421 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d")) 2422 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))) 2423 (clobber (match_scratch:TI 3 "=x"))] 2424 "ISA_HAS_DMULT 2425 && TARGET_FIX_R4000 2426 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)" 2427 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0" 2428 [(set_attr "type" "imul") 2429 (set_attr "mode" "DI") 2430 (set_attr "insn_count" "3")]) 2431 2432;; The R4650 supports a 32-bit multiply/ 64-bit accumulate 2433;; instruction. The HI/LO registers are used as a 64-bit accumulator. 2434 2435(define_insn "madsi" 2436 [(set (match_operand:SI 0 "register_operand" "+l") 2437 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") 2438 (match_operand:SI 2 "register_operand" "d")) 2439 (match_dup 0)))] 2440 "TARGET_MAD" 2441 "mad\t%1,%2" 2442 [(set_attr "type" "imadd") 2443 (set_attr "accum_in" "0") 2444 (set_attr "mode" "SI")]) 2445 2446;; See the comment above <u>msubsidi4 for the relationship between 2447;; ISA_HAS_DSP and ISA_HAS_DSP_MULT. 2448(define_insn "<u>maddsidi4" 2449 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka") 2450 (plus:DI 2451 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) 2452 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) 2453 (match_operand:DI 3 "muldiv_target_operand" "0")))] 2454 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP) 2455 && !TARGET_64BIT" 2456{ 2457 if (TARGET_MAD) 2458 return "mad<u>\t%1,%2"; 2459 else if (ISA_HAS_DSP_MULT) 2460 return "madd<u>\t%q0,%1,%2"; 2461 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500) 2462 return "madd<u>\t%1,%2"; 2463 else 2464 /* See comment in *macc. */ 2465 return "%[macc<u>\t%@,%1,%2%]"; 2466} 2467 [(set_attr "type" "imadd") 2468 (set_attr "accum_in" "3") 2469 (set_attr "mode" "SI")]) 2470 2471;; Floating point multiply accumulate instructions. 2472 2473(define_insn "*madd4<mode>" 2474 [(set (match_operand:ANYF 0 "register_operand" "=f") 2475 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 2476 (match_operand:ANYF 2 "register_operand" "f")) 2477 (match_operand:ANYF 3 "register_operand" "f")))] 2478 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD" 2479 "madd.<fmt>\t%0,%3,%1,%2" 2480 [(set_attr "type" "fmadd") 2481 (set_attr "accum_in" "3") 2482 (set_attr "mode" "<UNITMODE>")]) 2483 2484(define_insn "fma<mode>4" 2485 [(set (match_operand:ANYF 0 "register_operand" "=f") 2486 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f") 2487 (match_operand:ANYF 2 "register_operand" "f") 2488 (match_operand:ANYF 3 "register_operand" "0")))] 2489 "ISA_HAS_FP_MADDF_MSUBF" 2490 "maddf.<fmt>\t%0,%1,%2" 2491 [(set_attr "type" "fmadd") 2492 (set_attr "mode" "<UNITMODE>")]) 2493 2494(define_insn "*madd3<mode>" 2495 [(set (match_operand:ANYF 0 "register_operand" "=f") 2496 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 2497 (match_operand:ANYF 2 "register_operand" "f")) 2498 (match_operand:ANYF 3 "register_operand" "0")))] 2499 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD" 2500 "madd.<fmt>\t%0,%1,%2" 2501 [(set_attr "type" "fmadd") 2502 (set_attr "accum_in" "3") 2503 (set_attr "mode" "<UNITMODE>")]) 2504 2505(define_insn "*msub4<mode>" 2506 [(set (match_operand:ANYF 0 "register_operand" "=f") 2507 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 2508 (match_operand:ANYF 2 "register_operand" "f")) 2509 (match_operand:ANYF 3 "register_operand" "f")))] 2510 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD" 2511 "msub.<fmt>\t%0,%3,%1,%2" 2512 [(set_attr "type" "fmadd") 2513 (set_attr "accum_in" "3") 2514 (set_attr "mode" "<UNITMODE>")]) 2515 2516(define_insn "*msub3<mode>" 2517 [(set (match_operand:ANYF 0 "register_operand" "=f") 2518 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 2519 (match_operand:ANYF 2 "register_operand" "f")) 2520 (match_operand:ANYF 3 "register_operand" "0")))] 2521 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD" 2522 "msub.<fmt>\t%0,%1,%2" 2523 [(set_attr "type" "fmadd") 2524 (set_attr "accum_in" "3") 2525 (set_attr "mode" "<UNITMODE>")]) 2526 2527(define_insn "*nmadd4<mode>" 2528 [(set (match_operand:ANYF 0 "register_operand" "=f") 2529 (neg:ANYF (plus:ANYF 2530 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 2531 (match_operand:ANYF 2 "register_operand" "f")) 2532 (match_operand:ANYF 3 "register_operand" "f"))))] 2533 "ISA_HAS_NMADD4_NMSUB4 2534 && TARGET_FUSED_MADD 2535 && HONOR_SIGNED_ZEROS (<MODE>mode) 2536 && !HONOR_NANS (<MODE>mode)" 2537 "nmadd.<fmt>\t%0,%3,%1,%2" 2538 [(set_attr "type" "fmadd") 2539 (set_attr "accum_in" "3") 2540 (set_attr "mode" "<UNITMODE>")]) 2541 2542(define_insn "*nmadd3<mode>" 2543 [(set (match_operand:ANYF 0 "register_operand" "=f") 2544 (neg:ANYF (plus:ANYF 2545 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") 2546 (match_operand:ANYF 2 "register_operand" "f")) 2547 (match_operand:ANYF 3 "register_operand" "0"))))] 2548 "ISA_HAS_NMADD3_NMSUB3 2549 && TARGET_FUSED_MADD 2550 && HONOR_SIGNED_ZEROS (<MODE>mode) 2551 && !HONOR_NANS (<MODE>mode)" 2552 "nmadd.<fmt>\t%0,%1,%2" 2553 [(set_attr "type" "fmadd") 2554 (set_attr "accum_in" "3") 2555 (set_attr "mode" "<UNITMODE>")]) 2556 2557(define_insn "*nmadd4<mode>_fastmath" 2558 [(set (match_operand:ANYF 0 "register_operand" "=f") 2559 (minus:ANYF 2560 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) 2561 (match_operand:ANYF 2 "register_operand" "f")) 2562 (match_operand:ANYF 3 "register_operand" "f")))] 2563 "ISA_HAS_NMADD4_NMSUB4 2564 && TARGET_FUSED_MADD 2565 && !HONOR_SIGNED_ZEROS (<MODE>mode) 2566 && !HONOR_NANS (<MODE>mode)" 2567 "nmadd.<fmt>\t%0,%3,%1,%2" 2568 [(set_attr "type" "fmadd") 2569 (set_attr "accum_in" "3") 2570 (set_attr "mode" "<UNITMODE>")]) 2571 2572(define_insn "*nmadd3<mode>_fastmath" 2573 [(set (match_operand:ANYF 0 "register_operand" "=f") 2574 (minus:ANYF 2575 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) 2576 (match_operand:ANYF 2 "register_operand" "f")) 2577 (match_operand:ANYF 3 "register_operand" "0")))] 2578 "ISA_HAS_NMADD3_NMSUB3 2579 && TARGET_FUSED_MADD 2580 && !HONOR_SIGNED_ZEROS (<MODE>mode) 2581 && !HONOR_NANS (<MODE>mode)" 2582 "nmadd.<fmt>\t%0,%1,%2" 2583 [(set_attr "type" "fmadd") 2584 (set_attr "accum_in" "3") 2585 (set_attr "mode" "<UNITMODE>")]) 2586 2587(define_insn "*nmsub4<mode>" 2588 [(set (match_operand:ANYF 0 "register_operand" "=f") 2589 (neg:ANYF (minus:ANYF 2590 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f") 2591 (match_operand:ANYF 3 "register_operand" "f")) 2592 (match_operand:ANYF 1 "register_operand" "f"))))] 2593 "ISA_HAS_NMADD4_NMSUB4 2594 && TARGET_FUSED_MADD 2595 && HONOR_SIGNED_ZEROS (<MODE>mode) 2596 && !HONOR_NANS (<MODE>mode)" 2597 "nmsub.<fmt>\t%0,%1,%2,%3" 2598 [(set_attr "type" "fmadd") 2599 (set_attr "accum_in" "1") 2600 (set_attr "mode" "<UNITMODE>")]) 2601 2602(define_insn "*nmsub3<mode>" 2603 [(set (match_operand:ANYF 0 "register_operand" "=f") 2604 (neg:ANYF (minus:ANYF 2605 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f") 2606 (match_operand:ANYF 3 "register_operand" "f")) 2607 (match_operand:ANYF 1 "register_operand" "0"))))] 2608 "ISA_HAS_NMADD3_NMSUB3 2609 && TARGET_FUSED_MADD 2610 && HONOR_SIGNED_ZEROS (<MODE>mode) 2611 && !HONOR_NANS (<MODE>mode)" 2612 "nmsub.<fmt>\t%0,%1,%2" 2613 [(set_attr "type" "fmadd") 2614 (set_attr "accum_in" "1") 2615 (set_attr "mode" "<UNITMODE>")]) 2616 2617(define_insn "*nmsub4<mode>_fastmath" 2618 [(set (match_operand:ANYF 0 "register_operand" "=f") 2619 (minus:ANYF 2620 (match_operand:ANYF 1 "register_operand" "f") 2621 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f") 2622 (match_operand:ANYF 3 "register_operand" "f"))))] 2623 "ISA_HAS_NMADD4_NMSUB4 2624 && TARGET_FUSED_MADD 2625 && !HONOR_SIGNED_ZEROS (<MODE>mode) 2626 && !HONOR_NANS (<MODE>mode)" 2627 "nmsub.<fmt>\t%0,%1,%2,%3" 2628 [(set_attr "type" "fmadd") 2629 (set_attr "accum_in" "1") 2630 (set_attr "mode" "<UNITMODE>")]) 2631 2632(define_insn "*nmsub3<mode>_fastmath" 2633 [(set (match_operand:ANYF 0 "register_operand" "=f") 2634 (minus:ANYF 2635 (match_operand:ANYF 1 "register_operand" "f") 2636 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f") 2637 (match_operand:ANYF 3 "register_operand" "0"))))] 2638 "ISA_HAS_NMADD3_NMSUB3 2639 && TARGET_FUSED_MADD 2640 && !HONOR_SIGNED_ZEROS (<MODE>mode) 2641 && !HONOR_NANS (<MODE>mode)" 2642 "nmsub.<fmt>\t%0,%1,%2" 2643 [(set_attr "type" "fmadd") 2644 (set_attr "accum_in" "1") 2645 (set_attr "mode" "<UNITMODE>")]) 2646 2647;; 2648;; .................... 2649;; 2650;; DIVISION and REMAINDER 2651;; 2652;; .................... 2653;; 2654 2655(define_expand "div<mode>3" 2656 [(set (match_operand:ANYF 0 "register_operand") 2657 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand") 2658 (match_operand:ANYF 2 "register_operand")))] 2659 "<divide_condition>" 2660{ 2661 if (const_1_operand (operands[1], <MODE>mode)) 2662 if (!(ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) 2663 && flag_unsafe_math_optimizations)) 2664 operands[1] = force_reg (<MODE>mode, operands[1]); 2665}) 2666 2667;; These patterns work around the early SB-1 rev2 core "F1" erratum: 2668;; 2669;; If an mfc1 or dmfc1 happens to access the floating point register 2670;; file at the same time a long latency operation (div, sqrt, recip, 2671;; sqrt) iterates an intermediate result back through the floating 2672;; point register file bypass, then instead returning the correct 2673;; register value the mfc1 or dmfc1 operation returns the intermediate 2674;; result of the long latency operation. 2675;; 2676;; The workaround is to insert an unconditional 'mov' from/to the 2677;; long latency op destination register. 2678 2679(define_insn "*div<mode>3" 2680 [(set (match_operand:ANYF 0 "register_operand" "=f") 2681 (div:ANYF (match_operand:ANYF 1 "register_operand" "f") 2682 (match_operand:ANYF 2 "register_operand" "f")))] 2683 "<divide_condition>" 2684{ 2685 if (TARGET_FIX_SB1) 2686 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0"; 2687 else 2688 return "div.<fmt>\t%0,%1,%2"; 2689} 2690 [(set_attr "type" "fdiv") 2691 (set_attr "mode" "<UNITMODE>") 2692 (set (attr "insn_count") 2693 (if_then_else (match_test "TARGET_FIX_SB1") 2694 (const_int 2) 2695 (const_int 1)))]) 2696 2697(define_insn "*recip<mode>3" 2698 [(set (match_operand:ANYF 0 "register_operand" "=f") 2699 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") 2700 (match_operand:ANYF 2 "register_operand" "f")))] 2701 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations" 2702{ 2703 if (TARGET_FIX_SB1) 2704 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0"; 2705 else 2706 return "recip.<fmt>\t%0,%2"; 2707} 2708 [(set_attr "type" "frdiv") 2709 (set_attr "mode" "<UNITMODE>") 2710 (set (attr "insn_count") 2711 (if_then_else (match_test "TARGET_FIX_SB1") 2712 (const_int 2) 2713 (const_int 1)))]) 2714 2715;; VR4120 errata MD(A1): signed division instructions do not work correctly 2716;; with negative operands. We use special libgcc functions instead. 2717(define_expand "divmod<mode>4" 2718 [(parallel 2719 [(set (match_operand:GPR 0 "register_operand") 2720 (div:GPR (match_operand:GPR 1 "register_operand") 2721 (match_operand:GPR 2 "register_operand"))) 2722 (set (match_operand:GPR 3 "register_operand") 2723 (mod:GPR (match_dup 1) 2724 (match_dup 2)))])] 2725 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120" 2726{ 2727 if (TARGET_MIPS16) 2728 { 2729 rtx lo = gen_rtx_REG (<MODE>mode, LO_REGNUM); 2730 emit_insn (gen_divmod<mode>4_mips16 (operands[0], operands[1], 2731 operands[2], operands[3], lo)); 2732 DONE; 2733 } 2734}) 2735 2736(define_insn_and_split "*divmod<mode>4" 2737 [(set (match_operand:GPR 0 "register_operand" "=l") 2738 (div:GPR (match_operand:GPR 1 "register_operand" "d") 2739 (match_operand:GPR 2 "register_operand" "d"))) 2740 (set (match_operand:GPR 3 "register_operand" "=d") 2741 (mod:GPR (match_dup 1) 2742 (match_dup 2)))] 2743 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120 && !TARGET_MIPS16" 2744 "#" 2745 "&& reload_completed" 2746 [(const_int 0)] 2747{ 2748 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2])); 2749 DONE; 2750} 2751 [(set_attr "type" "idiv") 2752 (set_attr "mode" "<MODE>") 2753 (set_attr "insn_count" "2")]) 2754 2755;; Expand generates divmod instructions for individual division and modulus 2756;; operations. We then rely on CSE to reuse earlier divmods where possible. 2757;; This means that, when generating MIPS16 code, it is better not to expose 2758;; the fixed LO register until after CSE has finished. However, it's still 2759;; better to split before register allocation, so that we don't allocate 2760;; one of the scarce MIPS16 registers to an unused result. 2761(define_insn_and_split "divmod<mode>4_mips16" 2762 [(set (match_operand:GPR 0 "register_operand" "=d") 2763 (div:GPR (match_operand:GPR 1 "register_operand" "d") 2764 (match_operand:GPR 2 "register_operand" "d"))) 2765 (set (match_operand:GPR 3 "register_operand" "=d") 2766 (mod:GPR (match_dup 1) 2767 (match_dup 2))) 2768 (clobber (match_operand:GPR 4 "lo_operand" "=l"))] 2769 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120 && TARGET_MIPS16" 2770 "#" 2771 "&& cse_not_expected" 2772 [(const_int 0)] 2773{ 2774 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2])); 2775 emit_move_insn (operands[0], operands[4]); 2776 DONE; 2777} 2778 [(set_attr "type" "idiv") 2779 (set_attr "mode" "<MODE>") 2780 (set_attr "insn_count" "3")]) 2781 2782(define_expand "udivmod<mode>4" 2783 [(parallel 2784 [(set (match_operand:GPR 0 "register_operand") 2785 (udiv:GPR (match_operand:GPR 1 "register_operand") 2786 (match_operand:GPR 2 "register_operand"))) 2787 (set (match_operand:GPR 3 "register_operand") 2788 (umod:GPR (match_dup 1) 2789 (match_dup 2)))])] 2790 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120" 2791{ 2792 if (TARGET_MIPS16) 2793 { 2794 rtx lo = gen_rtx_REG (<MODE>mode, LO_REGNUM); 2795 emit_insn (gen_udivmod<mode>4_mips16 (operands[0], operands[1], 2796 operands[2], operands[3], lo)); 2797 DONE; 2798 } 2799}) 2800 2801(define_insn_and_split "*udivmod<mode>4" 2802 [(set (match_operand:GPR 0 "register_operand" "=l") 2803 (udiv:GPR (match_operand:GPR 1 "register_operand" "d") 2804 (match_operand:GPR 2 "register_operand" "d"))) 2805 (set (match_operand:GPR 3 "register_operand" "=d") 2806 (umod:GPR (match_dup 1) 2807 (match_dup 2)))] 2808 "ISA_HAS_<D>DIV && !TARGET_MIPS16" 2809 "#" 2810 "reload_completed" 2811 [(const_int 0)] 2812{ 2813 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2])); 2814 DONE; 2815} 2816 [(set_attr "type" "idiv") 2817 (set_attr "mode" "<MODE>") 2818 (set_attr "insn_count" "2")]) 2819 2820;; See the comment above "divmod<mode>4_mips16" for the split timing. 2821(define_insn_and_split "udivmod<mode>4_mips16" 2822 [(set (match_operand:GPR 0 "register_operand" "=d") 2823 (udiv:GPR (match_operand:GPR 1 "register_operand" "d") 2824 (match_operand:GPR 2 "register_operand" "d"))) 2825 (set (match_operand:GPR 3 "register_operand" "=d") 2826 (umod:GPR (match_dup 1) 2827 (match_dup 2))) 2828 (clobber (match_operand:GPR 4 "lo_operand" "=l"))] 2829 "ISA_HAS_<D>DIV && TARGET_MIPS16" 2830 "#" 2831 "cse_not_expected" 2832 [(const_int 0)] 2833{ 2834 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2])); 2835 emit_move_insn (operands[0], operands[4]); 2836 DONE; 2837} 2838 [(set_attr "type" "idiv") 2839 (set_attr "mode" "<MODE>") 2840 (set_attr "insn_count" "3")]) 2841 2842(define_expand "<u>divmod<mode>4_split" 2843 [(set (match_operand:GPR 0 "register_operand") 2844 (any_mod:GPR (match_operand:GPR 1 "register_operand") 2845 (match_operand:GPR 2 "register_operand")))] 2846 "" 2847{ 2848 rtx hilo; 2849 2850 if (TARGET_64BIT) 2851 { 2852 hilo = gen_rtx_REG (TImode, MD_REG_FIRST); 2853 emit_insn (gen_<u>divmod<mode>4_hilo_ti (hilo, operands[1], 2854 operands[2])); 2855 emit_insn (gen_mfhi<mode>_ti (operands[0], hilo)); 2856 } 2857 else 2858 { 2859 hilo = gen_rtx_REG (DImode, MD_REG_FIRST); 2860 emit_insn (gen_<u>divmod<mode>4_hilo_di (hilo, operands[1], 2861 operands[2])); 2862 emit_insn (gen_mfhi<mode>_di (operands[0], hilo)); 2863 } 2864 DONE; 2865}) 2866 2867(define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>" 2868 [(set (match_operand:HILO 0 "muldiv_target_operand" "=x") 2869 (unspec:HILO 2870 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d") 2871 (match_operand:GPR 2 "register_operand" "d"))] 2872 UNSPEC_SET_HILO))] 2873 "ISA_HAS_<GPR:D>DIV" 2874 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); } 2875 [(set_attr "type" "idiv") 2876 (set_attr "mode" "<GPR:MODE>")]) 2877 2878;; Integer division and modulus. 2879 2880(define_insn "<u>div<mode>3" 2881 [(set (match_operand:GPR 0 "register_operand" "=&d") 2882 (any_div:GPR (match_operand:GPR 1 "register_operand" "d") 2883 (match_operand:GPR 2 "register_operand" "d")))] 2884 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>DIV" 2885 { 2886 if (TARGET_LOONGSON_2EF) 2887 return mips_output_division ("<d>div<u>.g\t%0,%1,%2", operands); 2888 else if (TARGET_LOONGSON_3A) 2889 return mips_output_division ("gs<d>div<u>\t%0,%1,%2", operands); 2890 else 2891 return mips_output_division ("<d>div<u>\t%0,%1,%2", operands); 2892 } 2893 [(set_attr "type" "idiv3") 2894 (set_attr "mode" "<MODE>")]) 2895 2896(define_insn "<u>mod<mode>3" 2897 [(set (match_operand:GPR 0 "register_operand" "=&d") 2898 (any_mod:GPR (match_operand:GPR 1 "register_operand" "d") 2899 (match_operand:GPR 2 "register_operand" "d")))] 2900 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>DIV" 2901 { 2902 if (TARGET_LOONGSON_2EF) 2903 return mips_output_division ("<d>mod<u>.g\t%0,%1,%2", operands); 2904 else if (TARGET_LOONGSON_3A) 2905 return mips_output_division ("gs<d>mod<u>\t%0,%1,%2", operands); 2906 else 2907 return mips_output_division ("<d>mod<u>\t%0,%1,%2", operands); 2908 } 2909 [(set_attr "type" "idiv3") 2910 (set_attr "mode" "<MODE>")]) 2911 2912;; 2913;; .................... 2914;; 2915;; SQUARE ROOT 2916;; 2917;; .................... 2918 2919;; These patterns work around the early SB-1 rev2 core "F1" erratum (see 2920;; "*div[sd]f3" comment for details). 2921 2922(define_insn "sqrt<mode>2" 2923 [(set (match_operand:ANYF 0 "register_operand" "=f") 2924 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))] 2925 "<sqrt_condition>" 2926{ 2927 if (TARGET_FIX_SB1) 2928 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0"; 2929 else 2930 return "sqrt.<fmt>\t%0,%1"; 2931} 2932 [(set_attr "type" "fsqrt") 2933 (set_attr "mode" "<UNITMODE>") 2934 (set (attr "insn_count") 2935 (if_then_else (match_test "TARGET_FIX_SB1") 2936 (const_int 2) 2937 (const_int 1)))]) 2938 2939(define_insn "*rsqrt<mode>a" 2940 [(set (match_operand:ANYF 0 "register_operand" "=f") 2941 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") 2942 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))] 2943 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations" 2944{ 2945 if (TARGET_FIX_SB1) 2946 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0"; 2947 else 2948 return "rsqrt.<fmt>\t%0,%2"; 2949} 2950 [(set_attr "type" "frsqrt") 2951 (set_attr "mode" "<UNITMODE>") 2952 (set (attr "insn_count") 2953 (if_then_else (match_test "TARGET_FIX_SB1") 2954 (const_int 2) 2955 (const_int 1)))]) 2956 2957(define_insn "*rsqrt<mode>b" 2958 [(set (match_operand:ANYF 0 "register_operand" "=f") 2959 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") 2960 (match_operand:ANYF 2 "register_operand" "f"))))] 2961 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations" 2962{ 2963 if (TARGET_FIX_SB1) 2964 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0"; 2965 else 2966 return "rsqrt.<fmt>\t%0,%2"; 2967} 2968 [(set_attr "type" "frsqrt") 2969 (set_attr "mode" "<UNITMODE>") 2970 (set (attr "insn_count") 2971 (if_then_else (match_test "TARGET_FIX_SB1") 2972 (const_int 2) 2973 (const_int 1)))]) 2974 2975;; 2976;; .................... 2977;; 2978;; ABSOLUTE VALUE 2979;; 2980;; .................... 2981 2982;; Do not use the integer abs macro instruction, since that signals an 2983;; exception on -2147483648 (sigh). 2984 2985;; The "legacy" (as opposed to "2008") form of ABS.fmt is an arithmetic 2986;; instruction that treats all NaN inputs as invalid; it does not clear 2987;; their sign bit. We therefore can't use that form if the signs of 2988;; NaNs matter. 2989 2990(define_insn "abs<mode>2" 2991 [(set (match_operand:ANYF 0 "register_operand" "=f") 2992 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))] 2993 "mips_abs == MIPS_IEEE_754_2008 || !HONOR_NANS (<MODE>mode)" 2994 "abs.<fmt>\t%0,%1" 2995 [(set_attr "type" "fabs") 2996 (set_attr "mode" "<UNITMODE>")]) 2997 2998;; 2999;; ................... 3000;; 3001;; Count leading zeroes. 3002;; 3003;; ................... 3004;; 3005 3006(define_insn "clz<mode>2" 3007 [(set (match_operand:GPR 0 "register_operand" "=d") 3008 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))] 3009 "ISA_HAS_CLZ_CLO" 3010 "<d>clz\t%0,%1" 3011 [(set_attr "type" "clz") 3012 (set_attr "mode" "<MODE>")]) 3013 3014;; 3015;; ................... 3016;; 3017;; Count number of set bits. 3018;; 3019;; ................... 3020;; 3021 3022(define_insn "popcount<mode>2" 3023 [(set (match_operand:GPR 0 "register_operand" "=d") 3024 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))] 3025 "ISA_HAS_POP" 3026 "<d>pop\t%0,%1" 3027 [(set_attr "type" "pop") 3028 (set_attr "mode" "<MODE>")]) 3029 3030;; The POP instruction is special as it does not take into account the upper 3031;; 32bits and is documented that way. 3032(define_insn "*popcountdi2_trunc" 3033 [(set (match_operand:SI 0 "register_operand" "=d") 3034 (popcount:SI (truncate:SI (match_operand:DI 1 "register_operand" "d"))))] 3035 "ISA_HAS_POP && TARGET_64BIT" 3036 "pop\t%0,%1" 3037 [(set_attr "type" "pop") 3038 (set_attr "mode" "SI")]) 3039 3040;; 3041;; .................... 3042;; 3043;; NEGATION and ONE'S COMPLEMENT 3044;; 3045;; .................... 3046 3047(define_insn "negsi2" 3048 [(set (match_operand:SI 0 "register_operand" "=d") 3049 (neg:SI (match_operand:SI 1 "register_operand" "d")))] 3050 "" 3051{ 3052 if (TARGET_MIPS16) 3053 return "neg\t%0,%1"; 3054 else 3055 return "subu\t%0,%.,%1"; 3056} 3057 [(set_attr "alu_type" "sub") 3058 (set_attr "mode" "SI")]) 3059 3060(define_insn "negdi2" 3061 [(set (match_operand:DI 0 "register_operand" "=d") 3062 (neg:DI (match_operand:DI 1 "register_operand" "d")))] 3063 "TARGET_64BIT && !TARGET_MIPS16" 3064 "dsubu\t%0,%.,%1" 3065 [(set_attr "alu_type" "sub") 3066 (set_attr "mode" "DI")]) 3067 3068;; The "legacy" (as opposed to "2008") form of NEG.fmt is an arithmetic 3069;; instruction that treats all NaN inputs as invalid; it does not flip 3070;; their sign bit. We therefore can't use that form if the signs of 3071;; NaNs matter. 3072 3073(define_insn "neg<mode>2" 3074 [(set (match_operand:ANYF 0 "register_operand" "=f") 3075 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))] 3076 "mips_abs == MIPS_IEEE_754_2008 || !HONOR_NANS (<MODE>mode)" 3077 "neg.<fmt>\t%0,%1" 3078 [(set_attr "type" "fneg") 3079 (set_attr "mode" "<UNITMODE>")]) 3080 3081(define_insn "one_cmpl<mode>2" 3082 [(set (match_operand:GPR 0 "register_operand" "=!u,d") 3083 (not:GPR (match_operand:GPR 1 "register_operand" "!u,d")))] 3084 "" 3085{ 3086 if (TARGET_MIPS16) 3087 return "not\t%0,%1"; 3088 else 3089 return "nor\t%0,%.,%1"; 3090} 3091 [(set_attr "alu_type" "not") 3092 (set_attr "compression" "micromips,*") 3093 (set_attr "mode" "<MODE>")]) 3094 3095;; 3096;; .................... 3097;; 3098;; LOGICAL 3099;; 3100;; .................... 3101;; 3102 3103;; Many of these instructions use trivial define_expands, because we 3104;; want to use a different set of constraints when TARGET_MIPS16. 3105 3106(define_expand "and<mode>3" 3107 [(set (match_operand:GPR 0 "register_operand") 3108 (and:GPR (match_operand:GPR 1 "register_operand") 3109 (match_operand:GPR 2 "and_reg_operand")))]) 3110 3111;; The middle-end is not allowed to convert ANDing with 0xffff_ffff into a 3112;; zero_extendsidi2 because of TRULY_NOOP_TRUNCATION, so handle these here. 3113;; Note that this variant does not trigger for SI mode because we require 3114;; a 64-bit HOST_WIDE_INT and 0xffff_ffff wouldn't be a canonical 3115;; sign-extended SImode value. 3116;; 3117;; These are possible combinations for operand 1 and 2. The table 3118;; includes both MIPS and MIPS16 cases. (r=register, mem=memory, 3119;; 16=MIPS16, x=match, S=split): 3120;; 3121;; \ op1 r/EXT r/!EXT mem r/16 mem/16 3122;; op2 3123;; 3124;; andi x x 3125;; 0xff x x x x 3126;; 0xffff x x x x 3127;; 0xffff_ffff x S x S x 3128;; low-bitmask x 3129;; register x x 3130;; register =op1 x 3131 3132(define_insn "*and<mode>3" 3133 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,!u,d,d,d,!u,d") 3134 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,!u,d,d,d,0,d") 3135 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Uean,K,Yx,Yw,!u,d")))] 3136 "!TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])" 3137{ 3138 int len; 3139 3140 switch (which_alternative) 3141 { 3142 case 0: 3143 operands[1] = gen_lowpart (QImode, operands[1]); 3144 return "lbu\t%0,%1"; 3145 case 1: 3146 operands[1] = gen_lowpart (HImode, operands[1]); 3147 return "lhu\t%0,%1"; 3148 case 2: 3149 operands[1] = gen_lowpart (SImode, operands[1]); 3150 return "lwu\t%0,%1"; 3151 case 3: 3152 case 4: 3153 return "andi\t%0,%1,%x2"; 3154 case 5: 3155 len = low_bitmask_len (<MODE>mode, INTVAL (operands[2])); 3156 operands[2] = GEN_INT (len); 3157 return "<d>ext\t%0,%1,0,%2"; 3158 case 6: 3159 return "#"; 3160 case 7: 3161 case 8: 3162 return "and\t%0,%1,%2"; 3163 default: 3164 gcc_unreachable (); 3165 } 3166} 3167 [(set_attr "move_type" "load,load,load,andi,andi,ext_ins,shift_shift,logical,logical") 3168 (set_attr "compression" "*,*,*,micromips,*,*,*,micromips,*") 3169 (set_attr "mode" "<MODE>")]) 3170 3171(define_insn "*and<mode>3_mips16" 3172 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d") 3173 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%W,W,W,d,0") 3174 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))] 3175 "TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])" 3176{ 3177 switch (which_alternative) 3178 { 3179 case 0: 3180 operands[1] = gen_lowpart (QImode, operands[1]); 3181 return "lbu\t%0,%1"; 3182 case 1: 3183 operands[1] = gen_lowpart (HImode, operands[1]); 3184 return "lhu\t%0,%1"; 3185 case 2: 3186 operands[1] = gen_lowpart (SImode, operands[1]); 3187 return "lwu\t%0,%1"; 3188 case 3: 3189 return "#"; 3190 case 4: 3191 return "and\t%0,%2"; 3192 default: 3193 gcc_unreachable (); 3194 } 3195} 3196 [(set_attr "move_type" "load,load,load,shift_shift,logical") 3197 (set_attr "mode" "<MODE>")]) 3198 3199(define_expand "ior<mode>3" 3200 [(set (match_operand:GPR 0 "register_operand") 3201 (ior:GPR (match_operand:GPR 1 "register_operand") 3202 (match_operand:GPR 2 "uns_arith_operand")))] 3203 "" 3204{ 3205 if (TARGET_MIPS16) 3206 operands[2] = force_reg (<MODE>mode, operands[2]); 3207}) 3208 3209(define_insn "*ior<mode>3" 3210 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d") 3211 (ior:GPR (match_operand:GPR 1 "register_operand" "%0,d,d") 3212 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))] 3213 "!TARGET_MIPS16" 3214 "@ 3215 or\t%0,%1,%2 3216 or\t%0,%1,%2 3217 ori\t%0,%1,%x2" 3218 [(set_attr "alu_type" "or") 3219 (set_attr "compression" "micromips,*,*") 3220 (set_attr "mode" "<MODE>")]) 3221 3222(define_insn "*ior<mode>3_mips16" 3223 [(set (match_operand:GPR 0 "register_operand" "=d") 3224 (ior:GPR (match_operand:GPR 1 "register_operand" "%0") 3225 (match_operand:GPR 2 "register_operand" "d")))] 3226 "TARGET_MIPS16" 3227 "or\t%0,%2" 3228 [(set_attr "alu_type" "or") 3229 (set_attr "mode" "<MODE>")]) 3230 3231(define_expand "xor<mode>3" 3232 [(set (match_operand:GPR 0 "register_operand") 3233 (xor:GPR (match_operand:GPR 1 "register_operand") 3234 (match_operand:GPR 2 "uns_arith_operand")))] 3235 "" 3236 "") 3237 3238(define_insn "*xor<mode>3" 3239 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d") 3240 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d") 3241 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))] 3242 "!TARGET_MIPS16" 3243 "@ 3244 xor\t%0,%1,%2 3245 xor\t%0,%1,%2 3246 xori\t%0,%1,%x2" 3247 [(set_attr "alu_type" "xor") 3248 (set_attr "compression" "micromips,*,*") 3249 (set_attr "mode" "<MODE>")]) 3250 3251(define_insn "*xor<mode>3_mips16" 3252 [(set (match_operand:GPR 0 "register_operand" "=d,t,t,t") 3253 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d,d") 3254 (match_operand:GPR 2 "uns_arith_operand" "d,Uub8,K,d")))] 3255 "TARGET_MIPS16" 3256 "@ 3257 xor\t%0,%2 3258 cmpi\t%1,%2 3259 cmpi\t%1,%2 3260 cmp\t%1,%2" 3261 [(set_attr "alu_type" "xor") 3262 (set_attr "mode" "<MODE>") 3263 (set_attr "extended_mips16" "no,no,yes,no")]) 3264 3265(define_insn "*nor<mode>3" 3266 [(set (match_operand:GPR 0 "register_operand" "=d") 3267 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) 3268 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))] 3269 "!TARGET_MIPS16" 3270 "nor\t%0,%1,%2" 3271 [(set_attr "alu_type" "nor") 3272 (set_attr "mode" "<MODE>")]) 3273 3274;; 3275;; .................... 3276;; 3277;; TRUNCATION 3278;; 3279;; .................... 3280 3281 3282 3283(define_insn "truncdfsf2" 3284 [(set (match_operand:SF 0 "register_operand" "=f") 3285 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] 3286 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 3287 "cvt.s.d\t%0,%1" 3288 [(set_attr "type" "fcvt") 3289 (set_attr "cnv_mode" "D2S") 3290 (set_attr "mode" "SF")]) 3291 3292;; Integer truncation patterns. Truncating SImode values to smaller 3293;; modes is a no-op, as it is for most other GCC ports. Truncating 3294;; DImode values to SImode is not a no-op for TARGET_64BIT since we 3295;; need to make sure that the lower 32 bits are properly sign-extended 3296;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes 3297;; smaller than SImode is equivalent to two separate truncations: 3298;; 3299;; A B 3300;; DI ---> HI == DI ---> SI ---> HI 3301;; DI ---> QI == DI ---> SI ---> QI 3302;; 3303;; Step A needs a real instruction but step B does not. 3304 3305(define_insn "truncdi<mode>2" 3306 [(set (match_operand:SUBDI 0 "nonimmediate_operand" "=d,m") 3307 (truncate:SUBDI (match_operand:DI 1 "register_operand" "d,d")))] 3308 "TARGET_64BIT" 3309 "@ 3310 sll\t%0,%1,0 3311 <store>\t%1,%0" 3312 [(set_attr "move_type" "sll0,store") 3313 (set_attr "mode" "SI")]) 3314 3315;; Combiner patterns to optimize shift/truncate combinations. 3316 3317(define_insn "*ashr_trunc<mode>" 3318 [(set (match_operand:SUBDI 0 "register_operand" "=d") 3319 (truncate:SUBDI 3320 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") 3321 (match_operand:DI 2 "const_arith_operand" ""))))] 3322 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)" 3323 "dsra\t%0,%1,%2" 3324 [(set_attr "type" "shift") 3325 (set_attr "mode" "<MODE>")]) 3326 3327(define_insn "*lshr32_trunc<mode>" 3328 [(set (match_operand:SUBDI 0 "register_operand" "=d") 3329 (truncate:SUBDI 3330 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") 3331 (const_int 32))))] 3332 "TARGET_64BIT && !TARGET_MIPS16" 3333 "dsra\t%0,%1,32" 3334 [(set_attr "type" "shift") 3335 (set_attr "mode" "<MODE>")]) 3336 3337;; Logical shift by more than 32 results in proper SI values so truncation is 3338;; removed by the middle end. Note that a logical shift by 32 is handled by 3339;; the previous pattern. 3340(define_insn "*<optab>_trunc<mode>_exts" 3341 [(set (match_operand:SUBDI 0 "register_operand" "=d") 3342 (truncate:SUBDI 3343 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d") 3344 (match_operand:DI 2 "const_arith_operand" ""))))] 3345 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32" 3346 "exts\t%0,%1,%2,31" 3347 [(set_attr "type" "arith") 3348 (set_attr "mode" "<MODE>")]) 3349 3350;; 3351;; .................... 3352;; 3353;; ZERO EXTENSION 3354;; 3355;; .................... 3356 3357;; Extension insns. 3358 3359(define_expand "zero_extendsidi2" 3360 [(set (match_operand:DI 0 "register_operand") 3361 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))] 3362 "TARGET_64BIT") 3363 3364(define_insn_and_split "*zero_extendsidi2" 3365 [(set (match_operand:DI 0 "register_operand" "=d,d") 3366 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))] 3367 "TARGET_64BIT && !ISA_HAS_EXT_INS" 3368 "@ 3369 # 3370 lwu\t%0,%1" 3371 "&& reload_completed && REG_P (operands[1])" 3372 [(set (match_dup 0) 3373 (ashift:DI (match_dup 1) (const_int 32))) 3374 (set (match_dup 0) 3375 (lshiftrt:DI (match_dup 0) (const_int 32)))] 3376 { operands[1] = gen_lowpart (DImode, operands[1]); } 3377 [(set_attr "move_type" "shift_shift,load") 3378 (set_attr "mode" "DI")]) 3379 3380(define_insn "*zero_extendsidi2_dext" 3381 [(set (match_operand:DI 0 "register_operand" "=d,d") 3382 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))] 3383 "TARGET_64BIT && ISA_HAS_EXT_INS" 3384 "@ 3385 dext\t%0,%1,0,32 3386 lwu\t%0,%1" 3387 [(set_attr "move_type" "arith,load") 3388 (set_attr "mode" "DI")]) 3389 3390;; See the comment before the *and<mode>3 pattern why this is generated by 3391;; combine. 3392 3393(define_split 3394 [(set (match_operand:DI 0 "register_operand") 3395 (and:DI (match_operand:DI 1 "register_operand") 3396 (const_int 4294967295)))] 3397 "TARGET_64BIT && !ISA_HAS_EXT_INS && reload_completed" 3398 [(set (match_dup 0) 3399 (ashift:DI (match_dup 1) (const_int 32))) 3400 (set (match_dup 0) 3401 (lshiftrt:DI (match_dup 0) (const_int 32)))]) 3402 3403(define_expand "zero_extend<SHORT:mode><GPR:mode>2" 3404 [(set (match_operand:GPR 0 "register_operand") 3405 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))] 3406 "" 3407{ 3408 if (TARGET_MIPS16 && !GENERATE_MIPS16E 3409 && !memory_operand (operands[1], <SHORT:MODE>mode)) 3410 { 3411 emit_insn (gen_and<GPR:mode>3 (operands[0], 3412 gen_lowpart (<GPR:MODE>mode, operands[1]), 3413 force_reg (<GPR:MODE>mode, 3414 GEN_INT (<SHORT:mask>)))); 3415 DONE; 3416 } 3417}) 3418 3419(define_insn "*zero_extend<SHORT:mode><GPR:mode>2" 3420 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d") 3421 (zero_extend:GPR 3422 (match_operand:SHORT 1 "nonimmediate_operand" "!u,d,m")))] 3423 "!TARGET_MIPS16" 3424 "@ 3425 andi\t%0,%1,<SHORT:mask> 3426 andi\t%0,%1,<SHORT:mask> 3427 l<SHORT:size>u\t%0,%1" 3428 [(set_attr "move_type" "andi,andi,load") 3429 (set_attr "compression" "micromips,*,*") 3430 (set_attr "mode" "<GPR:MODE>")]) 3431 3432(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e" 3433 [(set (match_operand:GPR 0 "register_operand" "=d") 3434 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))] 3435 "GENERATE_MIPS16E" 3436 "ze<SHORT:size>\t%0" 3437 ;; This instruction is effectively a special encoding of ANDI. 3438 [(set_attr "move_type" "andi") 3439 (set_attr "mode" "<GPR:MODE>")]) 3440 3441(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16" 3442 [(set (match_operand:GPR 0 "register_operand" "=d") 3443 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))] 3444 "TARGET_MIPS16" 3445 "l<SHORT:size>u\t%0,%1" 3446 [(set_attr "move_type" "load") 3447 (set_attr "mode" "<GPR:MODE>")]) 3448 3449(define_expand "zero_extendqihi2" 3450 [(set (match_operand:HI 0 "register_operand") 3451 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))] 3452 "" 3453{ 3454 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode)) 3455 { 3456 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]), 3457 operands[1])); 3458 DONE; 3459 } 3460}) 3461 3462(define_insn "*zero_extendqihi2" 3463 [(set (match_operand:HI 0 "register_operand" "=d,d") 3464 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 3465 "!TARGET_MIPS16" 3466 "@ 3467 andi\t%0,%1,0x00ff 3468 lbu\t%0,%1" 3469 [(set_attr "move_type" "andi,load") 3470 (set_attr "mode" "HI")]) 3471 3472(define_insn "*zero_extendqihi2_mips16" 3473 [(set (match_operand:HI 0 "register_operand" "=d") 3474 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] 3475 "TARGET_MIPS16" 3476 "lbu\t%0,%1" 3477 [(set_attr "move_type" "load") 3478 (set_attr "mode" "HI")]) 3479 3480;; Combiner patterns to optimize truncate/zero_extend combinations. 3481 3482(define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>" 3483 [(set (match_operand:GPR 0 "register_operand" "=d") 3484 (zero_extend:GPR 3485 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))] 3486 "TARGET_64BIT && !TARGET_MIPS16" 3487{ 3488 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode)); 3489 return "andi\t%0,%1,%x2"; 3490} 3491 [(set_attr "alu_type" "and") 3492 (set_attr "mode" "<GPR:MODE>")]) 3493 3494(define_insn "*zero_extendhi_truncqi" 3495 [(set (match_operand:HI 0 "register_operand" "=d") 3496 (zero_extend:HI 3497 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))] 3498 "TARGET_64BIT && !TARGET_MIPS16" 3499 "andi\t%0,%1,0xff" 3500 [(set_attr "alu_type" "and") 3501 (set_attr "mode" "HI")]) 3502 3503;; 3504;; .................... 3505;; 3506;; SIGN EXTENSION 3507;; 3508;; .................... 3509 3510;; Extension insns. 3511;; Those for integer source operand are ordered widest source type first. 3512 3513;; When TARGET_64BIT, all SImode integer and accumulator registers 3514;; should already be in sign-extended form (see TRULY_NOOP_TRUNCATION 3515;; and truncdisi2). We can therefore get rid of register->register 3516;; instructions if we constrain the source to be in the same register as 3517;; the destination. 3518;; 3519;; Only the pre-reload scheduler sees the type of the register alternatives; 3520;; we split them into nothing before the post-reload scheduler runs. 3521;; These alternatives therefore have type "move" in order to reflect 3522;; what happens if the two pre-reload operands cannot be tied, and are 3523;; instead allocated two separate GPRs. We don't distinguish between 3524;; the GPR and LO cases because we don't usually know during pre-reload 3525;; scheduling whether an operand will be LO or not. 3526(define_insn_and_split "extendsidi2" 3527 [(set (match_operand:DI 0 "register_operand" "=d,l,d") 3528 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,0,m")))] 3529 "TARGET_64BIT" 3530 "@ 3531 # 3532 # 3533 lw\t%0,%1" 3534 "&& reload_completed && register_operand (operands[1], VOIDmode)" 3535 [(const_int 0)] 3536{ 3537 emit_note (NOTE_INSN_DELETED); 3538 DONE; 3539} 3540 [(set_attr "move_type" "move,move,load") 3541 (set_attr "mode" "DI")]) 3542 3543(define_expand "extend<SHORT:mode><GPR:mode>2" 3544 [(set (match_operand:GPR 0 "register_operand") 3545 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))] 3546 "") 3547 3548(define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e" 3549 [(set (match_operand:GPR 0 "register_operand" "=d,d") 3550 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))] 3551 "GENERATE_MIPS16E" 3552 "@ 3553 se<SHORT:size>\t%0 3554 l<SHORT:size>\t%0,%1" 3555 [(set_attr "move_type" "signext,load") 3556 (set_attr "mode" "<GPR:MODE>")]) 3557 3558(define_insn_and_split "*extend<SHORT:mode><GPR:mode>2" 3559 [(set (match_operand:GPR 0 "register_operand" "=d,d") 3560 (sign_extend:GPR 3561 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))] 3562 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E" 3563 "@ 3564 # 3565 l<SHORT:size>\t%0,%1" 3566 "&& reload_completed && REG_P (operands[1])" 3567 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2))) 3568 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))] 3569{ 3570 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]); 3571 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode) 3572 - GET_MODE_BITSIZE (<SHORT:MODE>mode)); 3573} 3574 [(set_attr "move_type" "shift_shift,load") 3575 (set_attr "mode" "<GPR:MODE>")]) 3576 3577(define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>" 3578 [(set (match_operand:GPR 0 "register_operand" "=d,d") 3579 (sign_extend:GPR 3580 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))] 3581 "ISA_HAS_SEB_SEH" 3582 "@ 3583 se<SHORT:size>\t%0,%1 3584 l<SHORT:size>\t%0,%1" 3585 [(set_attr "move_type" "signext,load") 3586 (set_attr "mode" "<GPR:MODE>")]) 3587 3588(define_expand "extendqihi2" 3589 [(set (match_operand:HI 0 "register_operand") 3590 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))] 3591 "") 3592 3593(define_insn "*extendqihi2_mips16e" 3594 [(set (match_operand:HI 0 "register_operand" "=d,d") 3595 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))] 3596 "GENERATE_MIPS16E" 3597 "@ 3598 seb\t%0 3599 lb\t%0,%1" 3600 [(set_attr "move_type" "signext,load") 3601 (set_attr "mode" "SI")]) 3602 3603(define_insn_and_split "*extendqihi2" 3604 [(set (match_operand:HI 0 "register_operand" "=d,d") 3605 (sign_extend:HI 3606 (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 3607 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E" 3608 "@ 3609 # 3610 lb\t%0,%1" 3611 "&& reload_completed && REG_P (operands[1])" 3612 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2))) 3613 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))] 3614{ 3615 operands[0] = gen_lowpart (SImode, operands[0]); 3616 operands[1] = gen_lowpart (SImode, operands[1]); 3617 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode) 3618 - GET_MODE_BITSIZE (QImode)); 3619} 3620 [(set_attr "move_type" "shift_shift,load") 3621 (set_attr "mode" "SI")]) 3622 3623(define_insn "*extendqihi2_seb" 3624 [(set (match_operand:HI 0 "register_operand" "=d,d") 3625 (sign_extend:HI 3626 (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 3627 "ISA_HAS_SEB_SEH" 3628 "@ 3629 seb\t%0,%1 3630 lb\t%0,%1" 3631 [(set_attr "move_type" "signext,load") 3632 (set_attr "mode" "SI")]) 3633 3634;; Combiner patterns for truncate/sign_extend combinations. The SI versions 3635;; use the shift/truncate patterns. 3636 3637(define_insn_and_split "*extenddi_truncate<mode>" 3638 [(set (match_operand:DI 0 "register_operand" "=d") 3639 (sign_extend:DI 3640 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))] 3641 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS" 3642 "#" 3643 "&& reload_completed" 3644 [(set (match_dup 2) 3645 (ashift:DI (match_dup 1) 3646 (match_dup 3))) 3647 (set (match_dup 0) 3648 (ashiftrt:DI (match_dup 2) 3649 (match_dup 3)))] 3650{ 3651 operands[2] = gen_lowpart (DImode, operands[0]); 3652 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode)); 3653} 3654 [(set_attr "move_type" "shift_shift") 3655 (set_attr "mode" "DI")]) 3656 3657(define_insn_and_split "*extendsi_truncate<mode>" 3658 [(set (match_operand:SI 0 "register_operand" "=d") 3659 (sign_extend:SI 3660 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))] 3661 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS" 3662 "#" 3663 "&& reload_completed" 3664 [(set (match_dup 2) 3665 (ashift:DI (match_dup 1) 3666 (match_dup 3))) 3667 (set (match_dup 0) 3668 (truncate:SI (ashiftrt:DI (match_dup 2) 3669 (match_dup 3))))] 3670{ 3671 operands[2] = gen_lowpart (DImode, operands[0]); 3672 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode)); 3673} 3674 [(set_attr "move_type" "shift_shift") 3675 (set_attr "mode" "SI")]) 3676 3677(define_insn_and_split "*extendhi_truncateqi" 3678 [(set (match_operand:HI 0 "register_operand" "=d") 3679 (sign_extend:HI 3680 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))] 3681 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS" 3682 "#" 3683 "&& reload_completed" 3684 [(set (match_dup 2) 3685 (ashift:DI (match_dup 1) 3686 (const_int 56))) 3687 (set (match_dup 0) 3688 (truncate:HI (ashiftrt:DI (match_dup 2) 3689 (const_int 56))))] 3690{ 3691 operands[2] = gen_lowpart (DImode, operands[0]); 3692} 3693 [(set_attr "move_type" "shift_shift") 3694 (set_attr "mode" "SI")]) 3695 3696(define_insn "*extend<GPR:mode>_truncate<SHORT:mode>_exts" 3697 [(set (match_operand:GPR 0 "register_operand" "=d") 3698 (sign_extend:GPR 3699 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))] 3700 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS" 3701{ 3702 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode)); 3703 return "exts\t%0,%1,0,%m2"; 3704} 3705 [(set_attr "type" "arith") 3706 (set_attr "mode" "<GPR:MODE>")]) 3707 3708(define_insn "*extendhi_truncateqi_exts" 3709 [(set (match_operand:HI 0 "register_operand" "=d") 3710 (sign_extend:HI 3711 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))] 3712 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS" 3713 "exts\t%0,%1,0,7" 3714 [(set_attr "type" "arith") 3715 (set_attr "mode" "SI")]) 3716 3717(define_insn "extendsfdf2" 3718 [(set (match_operand:DF 0 "register_operand" "=f") 3719 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] 3720 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 3721 "cvt.d.s\t%0,%1" 3722 [(set_attr "type" "fcvt") 3723 (set_attr "cnv_mode" "S2D") 3724 (set_attr "mode" "DF")]) 3725 3726;; 3727;; .................... 3728;; 3729;; CONVERSIONS 3730;; 3731;; .................... 3732 3733(define_expand "fix_truncdfsi2" 3734 [(set (match_operand:SI 0 "register_operand") 3735 (fix:SI (match_operand:DF 1 "register_operand")))] 3736 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 3737{ 3738 if (!ISA_HAS_TRUNC_W) 3739 { 3740 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1])); 3741 DONE; 3742 } 3743}) 3744 3745(define_insn "fix_truncdfsi2_insn" 3746 [(set (match_operand:SI 0 "register_operand" "=f") 3747 (fix:SI (match_operand:DF 1 "register_operand" "f")))] 3748 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W" 3749 "trunc.w.d %0,%1" 3750 [(set_attr "type" "fcvt") 3751 (set_attr "mode" "DF") 3752 (set_attr "cnv_mode" "D2I")]) 3753 3754(define_insn "fix_truncdfsi2_macro" 3755 [(set (match_operand:SI 0 "register_operand" "=f") 3756 (fix:SI (match_operand:DF 1 "register_operand" "f"))) 3757 (clobber (match_scratch:DF 2 "=d"))] 3758 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W" 3759{ 3760 if (mips_nomacro.nesting_level > 0) 3761 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro"; 3762 else 3763 return "trunc.w.d %0,%1,%2"; 3764} 3765 [(set_attr "type" "fcvt") 3766 (set_attr "mode" "DF") 3767 (set_attr "cnv_mode" "D2I") 3768 (set_attr "insn_count" "9")]) 3769 3770(define_expand "fix_truncsfsi2" 3771 [(set (match_operand:SI 0 "register_operand") 3772 (fix:SI (match_operand:SF 1 "register_operand")))] 3773 "TARGET_HARD_FLOAT" 3774{ 3775 if (!ISA_HAS_TRUNC_W) 3776 { 3777 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1])); 3778 DONE; 3779 } 3780}) 3781 3782(define_insn "fix_truncsfsi2_insn" 3783 [(set (match_operand:SI 0 "register_operand" "=f") 3784 (fix:SI (match_operand:SF 1 "register_operand" "f")))] 3785 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W" 3786 "trunc.w.s %0,%1" 3787 [(set_attr "type" "fcvt") 3788 (set_attr "mode" "SF") 3789 (set_attr "cnv_mode" "S2I")]) 3790 3791(define_insn "fix_truncsfsi2_macro" 3792 [(set (match_operand:SI 0 "register_operand" "=f") 3793 (fix:SI (match_operand:SF 1 "register_operand" "f"))) 3794 (clobber (match_scratch:SF 2 "=d"))] 3795 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W" 3796{ 3797 if (mips_nomacro.nesting_level > 0) 3798 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro"; 3799 else 3800 return "trunc.w.s %0,%1,%2"; 3801} 3802 [(set_attr "type" "fcvt") 3803 (set_attr "mode" "SF") 3804 (set_attr "cnv_mode" "S2I") 3805 (set_attr "insn_count" "9")]) 3806 3807 3808(define_insn "fix_truncdfdi2" 3809 [(set (match_operand:DI 0 "register_operand" "=f") 3810 (fix:DI (match_operand:DF 1 "register_operand" "f")))] 3811 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 3812 "trunc.l.d %0,%1" 3813 [(set_attr "type" "fcvt") 3814 (set_attr "mode" "DF") 3815 (set_attr "cnv_mode" "D2I")]) 3816 3817 3818(define_insn "fix_truncsfdi2" 3819 [(set (match_operand:DI 0 "register_operand" "=f") 3820 (fix:DI (match_operand:SF 1 "register_operand" "f")))] 3821 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 3822 "trunc.l.s %0,%1" 3823 [(set_attr "type" "fcvt") 3824 (set_attr "mode" "SF") 3825 (set_attr "cnv_mode" "S2I")]) 3826 3827 3828(define_insn "floatsidf2" 3829 [(set (match_operand:DF 0 "register_operand" "=f") 3830 (float:DF (match_operand:SI 1 "register_operand" "f")))] 3831 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 3832 "cvt.d.w\t%0,%1" 3833 [(set_attr "type" "fcvt") 3834 (set_attr "mode" "DF") 3835 (set_attr "cnv_mode" "I2D")]) 3836 3837 3838(define_insn "floatdidf2" 3839 [(set (match_operand:DF 0 "register_operand" "=f") 3840 (float:DF (match_operand:DI 1 "register_operand" "f")))] 3841 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 3842 "cvt.d.l\t%0,%1" 3843 [(set_attr "type" "fcvt") 3844 (set_attr "mode" "DF") 3845 (set_attr "cnv_mode" "I2D")]) 3846 3847 3848(define_insn "floatsisf2" 3849 [(set (match_operand:SF 0 "register_operand" "=f") 3850 (float:SF (match_operand:SI 1 "register_operand" "f")))] 3851 "TARGET_HARD_FLOAT" 3852 "cvt.s.w\t%0,%1" 3853 [(set_attr "type" "fcvt") 3854 (set_attr "mode" "SF") 3855 (set_attr "cnv_mode" "I2S")]) 3856 3857 3858(define_insn "floatdisf2" 3859 [(set (match_operand:SF 0 "register_operand" "=f") 3860 (float:SF (match_operand:DI 1 "register_operand" "f")))] 3861 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT" 3862 "cvt.s.l\t%0,%1" 3863 [(set_attr "type" "fcvt") 3864 (set_attr "mode" "SF") 3865 (set_attr "cnv_mode" "I2S")]) 3866 3867 3868(define_expand "fixuns_truncdfsi2" 3869 [(set (match_operand:SI 0 "register_operand") 3870 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))] 3871 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 3872{ 3873 rtx reg1 = gen_reg_rtx (DFmode); 3874 rtx reg2 = gen_reg_rtx (DFmode); 3875 rtx reg3 = gen_reg_rtx (SImode); 3876 rtx_code_label *label1 = gen_label_rtx (); 3877 rtx_code_label *label2 = gen_label_rtx (); 3878 rtx test; 3879 REAL_VALUE_TYPE offset; 3880 3881 real_2expN (&offset, 31, DFmode); 3882 3883 if (reg1) /* Turn off complaints about unreached code. */ 3884 { 3885 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode)); 3886 do_pending_stack_adjust (); 3887 3888 test = gen_rtx_GE (VOIDmode, operands[1], reg1); 3889 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1)); 3890 3891 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1])); 3892 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, 3893 gen_rtx_LABEL_REF (VOIDmode, label2))); 3894 emit_barrier (); 3895 3896 emit_label (label1); 3897 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1)); 3898 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode 3899 (BITMASK_HIGH, SImode))); 3900 3901 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2)); 3902 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3)); 3903 3904 emit_label (label2); 3905 3906 /* Allow REG_NOTES to be set on last insn (labels don't have enough 3907 fields, and can't be used for REG_NOTES anyway). */ 3908 emit_use (stack_pointer_rtx); 3909 DONE; 3910 } 3911}) 3912 3913 3914(define_expand "fixuns_truncdfdi2" 3915 [(set (match_operand:DI 0 "register_operand") 3916 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))] 3917 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" 3918{ 3919 rtx reg1 = gen_reg_rtx (DFmode); 3920 rtx reg2 = gen_reg_rtx (DFmode); 3921 rtx reg3 = gen_reg_rtx (DImode); 3922 rtx_code_label *label1 = gen_label_rtx (); 3923 rtx_code_label *label2 = gen_label_rtx (); 3924 rtx test; 3925 REAL_VALUE_TYPE offset; 3926 3927 real_2expN (&offset, 63, DFmode); 3928 3929 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode)); 3930 do_pending_stack_adjust (); 3931 3932 test = gen_rtx_GE (VOIDmode, operands[1], reg1); 3933 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1)); 3934 3935 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1])); 3936 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, 3937 gen_rtx_LABEL_REF (VOIDmode, label2))); 3938 emit_barrier (); 3939 3940 emit_label (label1); 3941 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1)); 3942 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH)); 3943 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32))); 3944 3945 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2)); 3946 emit_insn (gen_iordi3 (operands[0], operands[0], reg3)); 3947 3948 emit_label (label2); 3949 3950 /* Allow REG_NOTES to be set on last insn (labels don't have enough 3951 fields, and can't be used for REG_NOTES anyway). */ 3952 emit_use (stack_pointer_rtx); 3953 DONE; 3954}) 3955 3956 3957(define_expand "fixuns_truncsfsi2" 3958 [(set (match_operand:SI 0 "register_operand") 3959 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))] 3960 "TARGET_HARD_FLOAT" 3961{ 3962 rtx reg1 = gen_reg_rtx (SFmode); 3963 rtx reg2 = gen_reg_rtx (SFmode); 3964 rtx reg3 = gen_reg_rtx (SImode); 3965 rtx_code_label *label1 = gen_label_rtx (); 3966 rtx_code_label *label2 = gen_label_rtx (); 3967 rtx test; 3968 REAL_VALUE_TYPE offset; 3969 3970 real_2expN (&offset, 31, SFmode); 3971 3972 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode)); 3973 do_pending_stack_adjust (); 3974 3975 test = gen_rtx_GE (VOIDmode, operands[1], reg1); 3976 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1)); 3977 3978 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1])); 3979 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, 3980 gen_rtx_LABEL_REF (VOIDmode, label2))); 3981 emit_barrier (); 3982 3983 emit_label (label1); 3984 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1)); 3985 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode 3986 (BITMASK_HIGH, SImode))); 3987 3988 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2)); 3989 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3)); 3990 3991 emit_label (label2); 3992 3993 /* Allow REG_NOTES to be set on last insn (labels don't have enough 3994 fields, and can't be used for REG_NOTES anyway). */ 3995 emit_use (stack_pointer_rtx); 3996 DONE; 3997}) 3998 3999 4000(define_expand "fixuns_truncsfdi2" 4001 [(set (match_operand:DI 0 "register_operand") 4002 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))] 4003 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT" 4004{ 4005 rtx reg1 = gen_reg_rtx (SFmode); 4006 rtx reg2 = gen_reg_rtx (SFmode); 4007 rtx reg3 = gen_reg_rtx (DImode); 4008 rtx_code_label *label1 = gen_label_rtx (); 4009 rtx_code_label *label2 = gen_label_rtx (); 4010 rtx test; 4011 REAL_VALUE_TYPE offset; 4012 4013 real_2expN (&offset, 63, SFmode); 4014 4015 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode)); 4016 do_pending_stack_adjust (); 4017 4018 test = gen_rtx_GE (VOIDmode, operands[1], reg1); 4019 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1)); 4020 4021 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1])); 4022 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, 4023 gen_rtx_LABEL_REF (VOIDmode, label2))); 4024 emit_barrier (); 4025 4026 emit_label (label1); 4027 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1)); 4028 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH)); 4029 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32))); 4030 4031 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2)); 4032 emit_insn (gen_iordi3 (operands[0], operands[0], reg3)); 4033 4034 emit_label (label2); 4035 4036 /* Allow REG_NOTES to be set on last insn (labels don't have enough 4037 fields, and can't be used for REG_NOTES anyway). */ 4038 emit_use (stack_pointer_rtx); 4039 DONE; 4040}) 4041 4042;; 4043;; .................... 4044;; 4045;; DATA MOVEMENT 4046;; 4047;; .................... 4048 4049;; Bit field extract patterns which use lwl/lwr or ldl/ldr. 4050 4051(define_expand "extvmisalign<mode>" 4052 [(set (match_operand:GPR 0 "register_operand") 4053 (sign_extract:GPR (match_operand:BLK 1 "memory_operand") 4054 (match_operand 2 "const_int_operand") 4055 (match_operand 3 "const_int_operand")))] 4056 "ISA_HAS_LWL_LWR" 4057{ 4058 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1], 4059 INTVAL (operands[2]), 4060 INTVAL (operands[3]), 4061 /*unsigned=*/ false)) 4062 DONE; 4063 else 4064 FAIL; 4065}) 4066 4067(define_expand "extv<mode>" 4068 [(set (match_operand:GPR 0 "register_operand") 4069 (sign_extract:GPR (match_operand:GPR 1 "register_operand") 4070 (match_operand 2 "const_int_operand") 4071 (match_operand 3 "const_int_operand")))] 4072 "ISA_HAS_EXTS" 4073{ 4074 if (UINTVAL (operands[2]) > 32) 4075 FAIL; 4076}) 4077 4078(define_insn "*extv<mode>" 4079 [(set (match_operand:GPR 0 "register_operand" "=d") 4080 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d") 4081 (match_operand 2 "const_int_operand" "") 4082 (match_operand 3 "const_int_operand" "")))] 4083 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32" 4084 "exts\t%0,%1,%3,%m2" 4085 [(set_attr "type" "arith") 4086 (set_attr "mode" "<MODE>")]) 4087 4088(define_expand "extzvmisalign<mode>" 4089 [(set (match_operand:GPR 0 "register_operand") 4090 (zero_extract:GPR (match_operand:BLK 1 "memory_operand") 4091 (match_operand 2 "const_int_operand") 4092 (match_operand 3 "const_int_operand")))] 4093 "ISA_HAS_LWL_LWR" 4094{ 4095 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1], 4096 INTVAL (operands[2]), 4097 INTVAL (operands[3]), 4098 /*unsigned=*/ true)) 4099 DONE; 4100 else 4101 FAIL; 4102}) 4103 4104(define_expand "extzv<mode>" 4105 [(set (match_operand:GPR 0 "register_operand") 4106 (zero_extract:GPR (match_operand:GPR 1 "register_operand") 4107 (match_operand 2 "const_int_operand") 4108 (match_operand 3 "const_int_operand")))] 4109 "" 4110{ 4111 if (!mips_use_ins_ext_p (operands[1], INTVAL (operands[2]), 4112 INTVAL (operands[3]))) 4113 FAIL; 4114}) 4115 4116(define_insn "*extzv<mode>" 4117 [(set (match_operand:GPR 0 "register_operand" "=d") 4118 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d") 4119 (match_operand 2 "const_int_operand" "") 4120 (match_operand 3 "const_int_operand" "")))] 4121 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]), 4122 INTVAL (operands[3]))" 4123 "<d>ext\t%0,%1,%3,%2" 4124 [(set_attr "type" "arith") 4125 (set_attr "mode" "<MODE>")]) 4126 4127(define_insn "*extzv_truncsi_exts" 4128 [(set (match_operand:SI 0 "register_operand" "=d") 4129 (truncate:SI 4130 (zero_extract:DI (match_operand:DI 1 "register_operand" "d") 4131 (match_operand 2 "const_int_operand" "") 4132 (match_operand 3 "const_int_operand" ""))))] 4133 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)" 4134 "exts\t%0,%1,%3,31" 4135 [(set_attr "type" "arith") 4136 (set_attr "mode" "SI")]) 4137 4138 4139(define_expand "insvmisalign<mode>" 4140 [(set (zero_extract:GPR (match_operand:BLK 0 "memory_operand") 4141 (match_operand 1 "const_int_operand") 4142 (match_operand 2 "const_int_operand")) 4143 (match_operand:GPR 3 "reg_or_0_operand"))] 4144 "ISA_HAS_LWL_LWR" 4145{ 4146 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3], 4147 INTVAL (operands[1]), 4148 INTVAL (operands[2]))) 4149 DONE; 4150 else 4151 FAIL; 4152}) 4153 4154(define_expand "insv<mode>" 4155 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand") 4156 (match_operand 1 "const_int_operand") 4157 (match_operand 2 "const_int_operand")) 4158 (match_operand:GPR 3 "reg_or_0_operand"))] 4159 "" 4160{ 4161 if (!mips_use_ins_ext_p (operands[0], INTVAL (operands[1]), 4162 INTVAL (operands[2]))) 4163 FAIL; 4164}) 4165 4166(define_insn "*insv<mode>" 4167 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d") 4168 (match_operand:SI 1 "const_int_operand" "") 4169 (match_operand:SI 2 "const_int_operand" "")) 4170 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))] 4171 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]), 4172 INTVAL (operands[2]))" 4173 "<d>ins\t%0,%z3,%2,%1" 4174 [(set_attr "type" "arith") 4175 (set_attr "mode" "<MODE>")]) 4176 4177;; Combiner pattern for cins (clear and insert bit field). We can 4178;; implement mask-and-shift-left operation with this. Note that if 4179;; the upper bit of the mask is set in an SImode operation, the mask 4180;; itself will be sign-extended. mask_low_and_shift_len will 4181;; therefore be greater than our threshold of 32. 4182 4183(define_insn "*cins<mode>" 4184 [(set (match_operand:GPR 0 "register_operand" "=d") 4185 (and:GPR 4186 (ashift:GPR (match_operand:GPR 1 "register_operand" "d") 4187 (match_operand:GPR 2 "const_int_operand" "")) 4188 (match_operand:GPR 3 "const_int_operand" "")))] 4189 "ISA_HAS_CINS 4190 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)" 4191{ 4192 operands[3] = 4193 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2])); 4194 return "cins\t%0,%1,%2,%m3"; 4195} 4196 [(set_attr "type" "shift") 4197 (set_attr "mode" "<MODE>")]) 4198 4199;; Unaligned word moves generated by the bit field patterns. 4200;; 4201;; As far as the rtl is concerned, both the left-part and right-part 4202;; instructions can access the whole field. However, the real operand 4203;; refers to just the first or the last byte (depending on endianness). 4204;; We therefore use two memory operands to each instruction, one to 4205;; describe the rtl effect and one to use in the assembly output. 4206;; 4207;; Operands 0 and 1 are the rtl-level target and source respectively. 4208;; This allows us to use the standard length calculations for the "load" 4209;; and "store" type attributes. 4210 4211(define_insn "mov_<load>l" 4212 [(set (match_operand:GPR 0 "register_operand" "=d") 4213 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m") 4214 (match_operand:QI 2 "memory_operand" "ZC")] 4215 UNSPEC_LOAD_LEFT))] 4216 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])" 4217 "<load>l\t%0,%2" 4218 [(set_attr "move_type" "load") 4219 (set_attr "mode" "<MODE>")]) 4220 4221(define_insn "mov_<load>r" 4222 [(set (match_operand:GPR 0 "register_operand" "=d") 4223 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m") 4224 (match_operand:QI 2 "memory_operand" "ZC") 4225 (match_operand:GPR 3 "register_operand" "0")] 4226 UNSPEC_LOAD_RIGHT))] 4227 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])" 4228 "<load>r\t%0,%2" 4229 [(set_attr "move_type" "load") 4230 (set_attr "mode" "<MODE>")]) 4231 4232(define_insn "mov_<store>l" 4233 [(set (match_operand:BLK 0 "memory_operand" "=m") 4234 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 4235 (match_operand:QI 2 "memory_operand" "ZC")] 4236 UNSPEC_STORE_LEFT))] 4237 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])" 4238 "<store>l\t%z1,%2" 4239 [(set_attr "move_type" "store") 4240 (set_attr "mode" "<MODE>")]) 4241 4242(define_insn "mov_<store>r" 4243 [(set (match_operand:BLK 0 "memory_operand" "+m") 4244 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 4245 (match_operand:QI 2 "memory_operand" "ZC") 4246 (match_dup 0)] 4247 UNSPEC_STORE_RIGHT))] 4248 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])" 4249 "<store>r\t%z1,%2" 4250 [(set_attr "move_type" "store") 4251 (set_attr "mode" "<MODE>")]) 4252 4253;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE. 4254;; The required value is: 4255;; 4256;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16) 4257;; 4258;; which translates to: 4259;; 4260;; lui op0,%highest(op1) 4261;; daddiu op0,op0,%higher(op1) 4262;; dsll op0,op0,16 4263;; daddiu op0,op0,%hi(op1) 4264;; dsll op0,op0,16 4265;; 4266;; The split is deferred until after flow2 to allow the peephole2 below 4267;; to take effect. 4268(define_insn_and_split "*lea_high64" 4269 [(set (match_operand:DI 0 "register_operand" "=d") 4270 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))] 4271 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS" 4272 "#" 4273 "&& epilogue_completed" 4274 [(set (match_dup 0) (high:DI (match_dup 2))) 4275 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2))) 4276 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16))) 4277 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3))) 4278 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))] 4279{ 4280 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH); 4281 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID); 4282} 4283 [(set_attr "insn_count" "5")]) 4284 4285;; Use a scratch register to reduce the latency of the above pattern 4286;; on superscalar machines. The optimized sequence is: 4287;; 4288;; lui op1,%highest(op2) 4289;; lui op0,%hi(op2) 4290;; daddiu op1,op1,%higher(op2) 4291;; dsll32 op1,op1,0 4292;; daddu op1,op1,op0 4293(define_peephole2 4294 [(set (match_operand:DI 1 "d_operand") 4295 (high:DI (match_operand:DI 2 "absolute_symbolic_operand"))) 4296 (match_scratch:DI 0 "d")] 4297 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS" 4298 [(set (match_dup 1) (high:DI (match_dup 3))) 4299 (set (match_dup 0) (high:DI (match_dup 4))) 4300 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3))) 4301 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32))) 4302 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))] 4303{ 4304 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH); 4305 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW); 4306}) 4307 4308;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit 4309;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine 4310;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only 4311;; used once. We can then use the sequence: 4312;; 4313;; lui op0,%highest(op1) 4314;; lui op2,%hi(op1) 4315;; daddiu op0,op0,%higher(op1) 4316;; daddiu op2,op2,%lo(op1) 4317;; dsll32 op0,op0,0 4318;; daddu op0,op0,op2 4319;; 4320;; which takes 4 cycles on most superscalar targets. 4321(define_insn_and_split "*lea64" 4322 [(set (match_operand:DI 0 "register_operand" "=d") 4323 (match_operand:DI 1 "absolute_symbolic_operand" "")) 4324 (clobber (match_scratch:DI 2 "=&d"))] 4325 "!TARGET_MIPS16 4326 && TARGET_EXPLICIT_RELOCS 4327 && ABI_HAS_64BIT_SYMBOLS 4328 && cse_not_expected" 4329 "#" 4330 "&& reload_completed" 4331 [(set (match_dup 0) (high:DI (match_dup 3))) 4332 (set (match_dup 2) (high:DI (match_dup 4))) 4333 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3))) 4334 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4))) 4335 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) 4336 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))] 4337{ 4338 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH); 4339 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW); 4340} 4341 [(set_attr "insn_count" "6")]) 4342 4343;; Split HIGHs into: 4344;; 4345;; li op0,%hi(sym) 4346;; sll op0,16 4347;; 4348;; on MIPS16 targets. 4349(define_split 4350 [(set (match_operand:P 0 "d_operand") 4351 (high:P (match_operand:P 1 "symbolic_operand_with_high")))] 4352 "TARGET_MIPS16 && reload_completed" 4353 [(set (match_dup 0) (unspec:P [(match_dup 1)] UNSPEC_UNSHIFTED_HIGH)) 4354 (set (match_dup 0) (ashift:P (match_dup 0) (const_int 16)))]) 4355 4356(define_insn "*unshifted_high" 4357 [(set (match_operand:P 0 "d_operand" "=d") 4358 (unspec:P [(match_operand:P 1 "symbolic_operand_with_high")] 4359 UNSPEC_UNSHIFTED_HIGH))] 4360 "" 4361 "li\t%0,%h1" 4362 [(set_attr "extended_mips16" "yes")]) 4363 4364;; Insns to fetch a symbol from a big GOT. 4365 4366(define_insn_and_split "*xgot_hi<mode>" 4367 [(set (match_operand:P 0 "register_operand" "=d") 4368 (high:P (match_operand:P 1 "got_disp_operand" "")))] 4369 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT" 4370 "#" 4371 "&& reload_completed" 4372 [(set (match_dup 0) (high:P (match_dup 2))) 4373 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))] 4374{ 4375 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP); 4376 operands[3] = pic_offset_table_rtx; 4377} 4378 [(set_attr "got" "xgot_high") 4379 (set_attr "mode" "<MODE>")]) 4380 4381(define_insn_and_split "*xgot_lo<mode>" 4382 [(set (match_operand:P 0 "register_operand" "=d") 4383 (lo_sum:P (match_operand:P 1 "register_operand" "d") 4384 (match_operand:P 2 "got_disp_operand" "")))] 4385 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT" 4386 "#" 4387 "&& reload_completed" 4388 [(set (match_dup 0) 4389 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))] 4390 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); } 4391 [(set_attr "got" "load") 4392 (set_attr "mode" "<MODE>")]) 4393 4394;; Insns to fetch a symbol from a normal GOT. 4395 4396(define_insn_and_split "*got_disp<mode>" 4397 [(set (match_operand:P 0 "register_operand" "=d") 4398 (match_operand:P 1 "got_disp_operand" ""))] 4399 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]" 4400 "#" 4401 "&& reload_completed" 4402 [(set (match_dup 0) (match_dup 2))] 4403 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); } 4404 [(set_attr "got" "load") 4405 (set_attr "mode" "<MODE>")]) 4406 4407;; Insns for loading the "page" part of a page/ofst address from the GOT. 4408 4409(define_insn_and_split "*got_page<mode>" 4410 [(set (match_operand:P 0 "register_operand" "=d") 4411 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))] 4412 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]" 4413 "#" 4414 "&& reload_completed" 4415 [(set (match_dup 0) (match_dup 2))] 4416 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); } 4417 [(set_attr "got" "load") 4418 (set_attr "mode" "<MODE>")]) 4419 4420;; Convenience expander that generates the rhs of a load_got<mode> insn. 4421(define_expand "unspec_got_<mode>" 4422 [(unspec:P [(match_operand:P 0) 4423 (match_operand:P 1)] UNSPEC_LOAD_GOT)]) 4424 4425;; Lower-level instructions for loading an address from the GOT. 4426;; We could use MEMs, but an unspec gives more optimization 4427;; opportunities. 4428 4429(define_insn "load_got<mode>" 4430 [(set (match_operand:P 0 "register_operand" "=d") 4431 (unspec:P [(match_operand:P 1 "register_operand" "d") 4432 (match_operand:P 2 "immediate_operand" "")] 4433 UNSPEC_LOAD_GOT))] 4434 "" 4435 "<load>\t%0,%R2(%1)" 4436 [(set_attr "got" "load") 4437 (set_attr "mode" "<MODE>")]) 4438 4439;; Instructions for adding the low 16 bits of an address to a register. 4440;; Operand 2 is the address: mips_print_operand works out which relocation 4441;; should be applied. 4442 4443(define_insn "*low<mode>" 4444 [(set (match_operand:P 0 "register_operand" "=d") 4445 (lo_sum:P (match_operand:P 1 "register_operand" "d") 4446 (match_operand:P 2 "immediate_operand" "")))] 4447 "!TARGET_MIPS16" 4448 "<d>addiu\t%0,%1,%R2" 4449 [(set_attr "alu_type" "add") 4450 (set_attr "mode" "<MODE>")]) 4451 4452(define_insn "*low<mode>_mips16" 4453 [(set (match_operand:P 0 "register_operand" "=d") 4454 (lo_sum:P (match_operand:P 1 "register_operand" "0") 4455 (match_operand:P 2 "immediate_operand" "")))] 4456 "TARGET_MIPS16" 4457 "<d>addiu\t%0,%R2" 4458 [(set_attr "alu_type" "add") 4459 (set_attr "mode" "<MODE>") 4460 (set_attr "extended_mips16" "yes")]) 4461 4462;; Expose MIPS16 uses of the global pointer after reload if the function 4463;; is responsible for setting up the register itself. 4464(define_split 4465 [(set (match_operand:GPR 0 "d_operand") 4466 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))] 4467 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed" 4468 [(set (match_dup 0) (match_dup 1))] 4469 { operands[1] = pic_offset_table_rtx; }) 4470 4471;; Allow combine to split complex const_int load sequences, using operand 2 4472;; to store the intermediate results. See move_operand for details. 4473(define_split 4474 [(set (match_operand:GPR 0 "register_operand") 4475 (match_operand:GPR 1 "splittable_const_int_operand")) 4476 (clobber (match_operand:GPR 2 "register_operand"))] 4477 "" 4478 [(const_int 0)] 4479{ 4480 mips_move_integer (operands[2], operands[0], INTVAL (operands[1])); 4481 DONE; 4482}) 4483 4484;; Likewise, for symbolic operands. 4485(define_split 4486 [(set (match_operand:P 0 "register_operand") 4487 (match_operand:P 1)) 4488 (clobber (match_operand:P 2 "register_operand"))] 4489 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)" 4490 [(set (match_dup 0) (match_dup 3))] 4491{ 4492 mips_split_symbol (operands[2], operands[1], 4493 MAX_MACHINE_MODE, &operands[3]); 4494}) 4495 4496;; 64-bit integer moves 4497 4498;; Unlike most other insns, the move insns can't be split with 4499;; different predicates, because register spilling and other parts of 4500;; the compiler, have memoized the insn number already. 4501 4502(define_expand "movdi" 4503 [(set (match_operand:DI 0 "") 4504 (match_operand:DI 1 ""))] 4505 "" 4506{ 4507 if (mips_legitimize_move (DImode, operands[0], operands[1])) 4508 DONE; 4509}) 4510 4511;; For mips16, we need a special case to handle storing $31 into 4512;; memory, since we don't have a constraint to match $31. This 4513;; instruction can be generated by save_restore_insns. 4514 4515(define_insn "*mov<mode>_ra" 4516 [(set (match_operand:GPR 0 "stack_operand" "=m") 4517 (reg:GPR RETURN_ADDR_REGNUM))] 4518 "TARGET_MIPS16" 4519 "<store>\t$31,%0" 4520 [(set_attr "move_type" "store") 4521 (set_attr "mode" "<MODE>")]) 4522 4523(define_insn "*movdi_32bit" 4524 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m") 4525 (match_operand:DI 1 "move_operand" "d,i,m,d,*J,*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))] 4526 "!TARGET_64BIT && !TARGET_MIPS16 4527 && (register_operand (operands[0], DImode) 4528 || reg_or_0_operand (operands[1], DImode))" 4529 { return mips_output_move (operands[0], operands[1]); } 4530 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore") 4531 (set (attr "mode") 4532 (if_then_else (eq_attr "move_type" "imul") 4533 (const_string "SI") 4534 (const_string "DI")))]) 4535 4536(define_insn "*movdi_32bit_mips16" 4537 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") 4538 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))] 4539 "!TARGET_64BIT && TARGET_MIPS16 4540 && (register_operand (operands[0], DImode) 4541 || register_operand (operands[1], DImode))" 4542 { return mips_output_move (operands[0], operands[1]); } 4543 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") 4544 (set_attr "mode" "DI")]) 4545 4546(define_insn "*movdi_64bit" 4547 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m") 4548 (match_operand:DI 1 "move_operand" "d,Yd,Yf,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] 4549 "TARGET_64BIT && !TARGET_MIPS16 4550 && (register_operand (operands[0], DImode) 4551 || reg_or_0_operand (operands[1], DImode))" 4552 { return mips_output_move (operands[0], operands[1]); } 4553 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mtlo,mflo,mtc,fpload,mfc,fpstore") 4554 (set_attr "mode" "DI")]) 4555 4556(define_insn "*movdi_64bit_mips16" 4557 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d") 4558 (match_operand:DI 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))] 4559 "TARGET_64BIT && TARGET_MIPS16 4560 && (register_operand (operands[0], DImode) 4561 || register_operand (operands[1], DImode))" 4562 { return mips_output_move (operands[0], operands[1]); } 4563 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo") 4564 (set_attr "mode" "DI")]) 4565 4566;; On the mips16, we can split ld $r,N($r) into an add and a load, 4567;; when the original load is a 4 byte instruction but the add and the 4568;; load are 2 2 byte instructions. 4569 4570(define_split 4571 [(set (match_operand:DI 0 "d_operand") 4572 (mem:DI (plus:DI (match_dup 0) 4573 (match_operand:DI 1 "const_int_operand"))))] 4574 "TARGET_64BIT && TARGET_MIPS16 && reload_completed 4575 && !TARGET_DEBUG_D_MODE 4576 && ((INTVAL (operands[1]) < 0 4577 && INTVAL (operands[1]) >= -0x10) 4578 || (INTVAL (operands[1]) >= 32 * 8 4579 && INTVAL (operands[1]) <= 31 * 8 + 0x8) 4580 || (INTVAL (operands[1]) >= 0 4581 && INTVAL (operands[1]) < 32 * 8 4582 && (INTVAL (operands[1]) & 7) != 0))" 4583 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1))) 4584 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))] 4585{ 4586 HOST_WIDE_INT val = INTVAL (operands[1]); 4587 4588 if (val < 0) 4589 operands[2] = const0_rtx; 4590 else if (val >= 32 * 8) 4591 { 4592 int off = val & 7; 4593 4594 operands[1] = GEN_INT (0x8 + off); 4595 operands[2] = GEN_INT (val - off - 0x8); 4596 } 4597 else 4598 { 4599 int off = val & 7; 4600 4601 operands[1] = GEN_INT (off); 4602 operands[2] = GEN_INT (val - off); 4603 } 4604}) 4605 4606;; 32-bit Integer moves 4607 4608;; Unlike most other insns, the move insns can't be split with 4609;; different predicates, because register spilling and other parts of 4610;; the compiler, have memoized the insn number already. 4611 4612(define_expand "mov<mode>" 4613 [(set (match_operand:IMOVE32 0 "") 4614 (match_operand:IMOVE32 1 ""))] 4615 "" 4616{ 4617 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1])) 4618 DONE; 4619}) 4620 4621;; The difference between these two is whether or not ints are allowed 4622;; in FP registers (off by default, use -mdebugh to enable). 4623 4624(define_insn "*mov<mode>_internal" 4625 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,!u,!u,d,e,!u,!ks,d,ZS,ZT,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m") 4626 (match_operand:IMOVE32 1 "move_operand" "d,J,Udb7,Yd,Yf,ZT,ZS,m,!ks,!kbJ,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] 4627 "!TARGET_MIPS16 4628 && (register_operand (operands[0], <MODE>mode) 4629 || reg_or_0_operand (operands[1], <MODE>mode))" 4630 { return mips_output_move (operands[0], operands[1]); } 4631 [(set_attr "move_type" "move,move,const,const,const,load,load,load,store,store,store,mtc,fpload,mfc,fpstore,mfc,mtc,mtlo,mflo,mtc,fpload,mfc,fpstore") 4632 (set_attr "compression" "all,micromips,micromips,*,*,micromips,micromips,*,micromips,micromips,*,*,*,*,*,*,*,*,*,*,*,*,*") 4633 (set_attr "mode" "SI")]) 4634 4635(define_insn "*mov<mode>_mips16" 4636 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d") 4637 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))] 4638 "TARGET_MIPS16 4639 && (register_operand (operands[0], <MODE>mode) 4640 || register_operand (operands[1], <MODE>mode))" 4641 { return mips_output_move (operands[0], operands[1]); } 4642 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo") 4643 (set_attr "mode" "SI")]) 4644 4645;; On the mips16, we can split lw $r,N($r) into an add and a load, 4646;; when the original load is a 4 byte instruction but the add and the 4647;; load are 2 2 byte instructions. 4648 4649(define_split 4650 [(set (match_operand:SI 0 "d_operand") 4651 (mem:SI (plus:SI (match_dup 0) 4652 (match_operand:SI 1 "const_int_operand"))))] 4653 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 4654 && ((INTVAL (operands[1]) < 0 4655 && INTVAL (operands[1]) >= -0x80) 4656 || (INTVAL (operands[1]) >= 32 * 4 4657 && INTVAL (operands[1]) <= 31 * 4 + 0x7c) 4658 || (INTVAL (operands[1]) >= 0 4659 && INTVAL (operands[1]) < 32 * 4 4660 && (INTVAL (operands[1]) & 3) != 0))" 4661 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 4662 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))] 4663{ 4664 HOST_WIDE_INT val = INTVAL (operands[1]); 4665 4666 if (val < 0) 4667 operands[2] = const0_rtx; 4668 else if (val >= 32 * 4) 4669 { 4670 int off = val & 3; 4671 4672 operands[1] = GEN_INT (0x7c + off); 4673 operands[2] = GEN_INT (val - off - 0x7c); 4674 } 4675 else 4676 { 4677 int off = val & 3; 4678 4679 operands[1] = GEN_INT (off); 4680 operands[2] = GEN_INT (val - off); 4681 } 4682}) 4683 4684;; On the mips16, we can split a load of certain constants into a load 4685;; and an add. This turns a 4 byte instruction into 2 2 byte 4686;; instructions. 4687 4688(define_split 4689 [(set (match_operand:SI 0 "d_operand") 4690 (match_operand:SI 1 "const_int_operand"))] 4691 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 4692 && INTVAL (operands[1]) >= 0x100 4693 && INTVAL (operands[1]) <= 0xff + 0x7f" 4694 [(set (match_dup 0) (match_dup 1)) 4695 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] 4696{ 4697 int val = INTVAL (operands[1]); 4698 4699 operands[1] = GEN_INT (0xff); 4700 operands[2] = GEN_INT (val - 0xff); 4701}) 4702 4703;; MIPS4 supports loading and storing a floating point register from 4704;; the sum of two general registers. We use two versions for each of 4705;; these four instructions: one where the two general registers are 4706;; SImode, and one where they are DImode. This is because general 4707;; registers will be in SImode when they hold 32-bit values, but, 4708;; since the 32-bit values are always sign extended, the [ls][wd]xc1 4709;; instructions will still work correctly. 4710 4711;; ??? Perhaps it would be better to support these instructions by 4712;; modifying TARGET_LEGITIMATE_ADDRESS_P and friends. However, since 4713;; these instructions can only be used to load and store floating 4714;; point registers, that would probably cause trouble in reload. 4715 4716(define_insn "*<ANYF:loadx>_<P:mode>" 4717 [(set (match_operand:ANYF 0 "register_operand" "=f") 4718 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d") 4719 (match_operand:P 2 "register_operand" "d"))))] 4720 "ISA_HAS_LXC1_SXC1" 4721 "<ANYF:loadx>\t%0,%1(%2)" 4722 [(set_attr "type" "fpidxload") 4723 (set_attr "mode" "<ANYF:UNITMODE>")]) 4724 4725(define_insn "*<ANYF:storex>_<P:mode>" 4726 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d") 4727 (match_operand:P 2 "register_operand" "d"))) 4728 (match_operand:ANYF 0 "register_operand" "f"))] 4729 "ISA_HAS_LXC1_SXC1" 4730 "<ANYF:storex>\t%0,%1(%2)" 4731 [(set_attr "type" "fpidxstore") 4732 (set_attr "mode" "<ANYF:UNITMODE>")]) 4733 4734;; Scaled indexed address load. 4735;; Per md.texi, we only need to look for a pattern with multiply in the 4736;; address expression, not shift. 4737 4738(define_insn "*lwxs" 4739 [(set (match_operand:IMOVE32 0 "register_operand" "=d") 4740 (mem:IMOVE32 4741 (plus:P (mult:P (match_operand:P 1 "register_operand" "d") 4742 (const_int 4)) 4743 (match_operand:P 2 "register_operand" "d"))))] 4744 "ISA_HAS_LWXS" 4745 "lwxs\t%0,%1(%2)" 4746 [(set_attr "type" "load") 4747 (set_attr "mode" "SI")]) 4748 4749;; 16-bit Integer moves 4750 4751;; Unlike most other insns, the move insns can't be split with 4752;; different predicates, because register spilling and other parts of 4753;; the compiler, have memoized the insn number already. 4754;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND. 4755 4756(define_expand "movhi" 4757 [(set (match_operand:HI 0 "") 4758 (match_operand:HI 1 ""))] 4759 "" 4760{ 4761 if (mips_legitimize_move (HImode, operands[0], operands[1])) 4762 DONE; 4763}) 4764 4765(define_insn "*movhi_internal" 4766 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZU,m,*a,*d") 4767 (match_operand:HI 1 "move_operand" "d,J,I,ZU,m,!kbJ,dJ,*d*J,*a"))] 4768 "!TARGET_MIPS16 4769 && (register_operand (operands[0], HImode) 4770 || reg_or_0_operand (operands[1], HImode))" 4771 { return mips_output_move (operands[0], operands[1]); } 4772 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo") 4773 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*") 4774 (set_attr "mode" "HI")]) 4775 4776(define_insn "*movhi_mips16" 4777 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") 4778 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] 4779 "TARGET_MIPS16 4780 && (register_operand (operands[0], HImode) 4781 || register_operand (operands[1], HImode))" 4782 { return mips_output_move (operands[0], operands[1]); } 4783 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") 4784 (set_attr "mode" "HI")]) 4785 4786;; On the mips16, we can split lh $r,N($r) into an add and a load, 4787;; when the original load is a 4 byte instruction but the add and the 4788;; load are 2 2 byte instructions. 4789 4790(define_split 4791 [(set (match_operand:HI 0 "d_operand") 4792 (mem:HI (plus:SI (match_dup 0) 4793 (match_operand:SI 1 "const_int_operand"))))] 4794 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 4795 && ((INTVAL (operands[1]) < 0 4796 && INTVAL (operands[1]) >= -0x80) 4797 || (INTVAL (operands[1]) >= 32 * 2 4798 && INTVAL (operands[1]) <= 31 * 2 + 0x7e) 4799 || (INTVAL (operands[1]) >= 0 4800 && INTVAL (operands[1]) < 32 * 2 4801 && (INTVAL (operands[1]) & 1) != 0))" 4802 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 4803 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))] 4804{ 4805 HOST_WIDE_INT val = INTVAL (operands[1]); 4806 4807 if (val < 0) 4808 operands[2] = const0_rtx; 4809 else if (val >= 32 * 2) 4810 { 4811 int off = val & 1; 4812 4813 operands[1] = GEN_INT (0x7e + off); 4814 operands[2] = GEN_INT (val - off - 0x7e); 4815 } 4816 else 4817 { 4818 int off = val & 1; 4819 4820 operands[1] = GEN_INT (off); 4821 operands[2] = GEN_INT (val - off); 4822 } 4823}) 4824 4825;; 8-bit Integer moves 4826 4827;; Unlike most other insns, the move insns can't be split with 4828;; different predicates, because register spilling and other parts of 4829;; the compiler, have memoized the insn number already. 4830;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND. 4831 4832(define_expand "movqi" 4833 [(set (match_operand:QI 0 "") 4834 (match_operand:QI 1 ""))] 4835 "" 4836{ 4837 if (mips_legitimize_move (QImode, operands[0], operands[1])) 4838 DONE; 4839}) 4840 4841(define_insn "*movqi_internal" 4842 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZV,m,*a,*d") 4843 (match_operand:QI 1 "move_operand" "d,J,I,ZW,m,!kbJ,dJ,*d*J,*a"))] 4844 "!TARGET_MIPS16 4845 && (register_operand (operands[0], QImode) 4846 || reg_or_0_operand (operands[1], QImode))" 4847 { return mips_output_move (operands[0], operands[1]); } 4848 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo") 4849 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*") 4850 (set_attr "mode" "QI")]) 4851 4852(define_insn "*movqi_mips16" 4853 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") 4854 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] 4855 "TARGET_MIPS16 4856 && (register_operand (operands[0], QImode) 4857 || register_operand (operands[1], QImode))" 4858 { return mips_output_move (operands[0], operands[1]); } 4859 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") 4860 (set_attr "mode" "QI")]) 4861 4862;; On the mips16, we can split lb $r,N($r) into an add and a load, 4863;; when the original load is a 4 byte instruction but the add and the 4864;; load are 2 2 byte instructions. 4865 4866(define_split 4867 [(set (match_operand:QI 0 "d_operand") 4868 (mem:QI (plus:SI (match_dup 0) 4869 (match_operand:SI 1 "const_int_operand"))))] 4870 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 4871 && ((INTVAL (operands[1]) < 0 4872 && INTVAL (operands[1]) >= -0x80) 4873 || (INTVAL (operands[1]) >= 32 4874 && INTVAL (operands[1]) <= 31 + 0x7f))" 4875 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) 4876 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))] 4877{ 4878 HOST_WIDE_INT val = INTVAL (operands[1]); 4879 4880 if (val < 0) 4881 operands[2] = const0_rtx; 4882 else 4883 { 4884 operands[1] = GEN_INT (0x7f); 4885 operands[2] = GEN_INT (val - 0x7f); 4886 } 4887}) 4888 4889;; 32-bit floating point moves 4890 4891(define_expand "movsf" 4892 [(set (match_operand:SF 0 "") 4893 (match_operand:SF 1 ""))] 4894 "" 4895{ 4896 if (mips_legitimize_move (SFmode, operands[0], operands[1])) 4897 DONE; 4898}) 4899 4900(define_insn "movccf" 4901 [(set (match_operand:CCF 0 "nonimmediate_operand" "=f,f,m") 4902 (match_operand:CCF 1 "nonimmediate_operand" "f,m,f"))] 4903 "ISA_HAS_CCF" 4904 { return mips_output_move (operands[0], operands[1]); } 4905 [(set_attr "move_type" "fmove,fpload,fpstore")]) 4906 4907(define_insn "*movsf_hardfloat" 4908 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") 4909 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))] 4910 "TARGET_HARD_FLOAT 4911 && (register_operand (operands[0], SFmode) 4912 || reg_or_0_operand (operands[1], SFmode))" 4913 { return mips_output_move (operands[0], operands[1]); } 4914 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") 4915 (set_attr "mode" "SF")]) 4916 4917(define_insn "*movsf_softfloat" 4918 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m") 4919 (match_operand:SF 1 "move_operand" "Gd,m,d"))] 4920 "TARGET_SOFT_FLOAT && !TARGET_MIPS16 4921 && (register_operand (operands[0], SFmode) 4922 || reg_or_0_operand (operands[1], SFmode))" 4923 { return mips_output_move (operands[0], operands[1]); } 4924 [(set_attr "move_type" "move,load,store") 4925 (set_attr "mode" "SF")]) 4926 4927(define_insn "*movsf_mips16" 4928 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m") 4929 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))] 4930 "TARGET_MIPS16 4931 && (register_operand (operands[0], SFmode) 4932 || register_operand (operands[1], SFmode))" 4933 { return mips_output_move (operands[0], operands[1]); } 4934 [(set_attr "move_type" "move,move,move,load,store") 4935 (set_attr "mode" "SF")]) 4936 4937;; 64-bit floating point moves 4938 4939(define_expand "movdf" 4940 [(set (match_operand:DF 0 "") 4941 (match_operand:DF 1 ""))] 4942 "" 4943{ 4944 if (mips_legitimize_move (DFmode, operands[0], operands[1])) 4945 DONE; 4946}) 4947 4948(define_insn "*movdf_hardfloat" 4949 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") 4950 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))] 4951 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT 4952 && (register_operand (operands[0], DFmode) 4953 || reg_or_0_operand (operands[1], DFmode))" 4954 { return mips_output_move (operands[0], operands[1]); } 4955 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") 4956 (set_attr "mode" "DF")]) 4957 4958(define_insn "*movdf_softfloat" 4959 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m") 4960 (match_operand:DF 1 "move_operand" "dG,m,dG"))] 4961 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16 4962 && (register_operand (operands[0], DFmode) 4963 || reg_or_0_operand (operands[1], DFmode))" 4964 { return mips_output_move (operands[0], operands[1]); } 4965 [(set_attr "move_type" "move,load,store") 4966 (set_attr "mode" "DF")]) 4967 4968(define_insn "*movdf_mips16" 4969 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m") 4970 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))] 4971 "TARGET_MIPS16 4972 && (register_operand (operands[0], DFmode) 4973 || register_operand (operands[1], DFmode))" 4974 { return mips_output_move (operands[0], operands[1]); } 4975 [(set_attr "move_type" "move,move,move,load,store") 4976 (set_attr "mode" "DF")]) 4977 4978;; 128-bit integer moves 4979 4980(define_expand "movti" 4981 [(set (match_operand:TI 0) 4982 (match_operand:TI 1))] 4983 "TARGET_64BIT" 4984{ 4985 if (mips_legitimize_move (TImode, operands[0], operands[1])) 4986 DONE; 4987}) 4988 4989(define_insn "*movti" 4990 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d") 4991 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*J,*d,*a"))] 4992 "TARGET_64BIT 4993 && !TARGET_MIPS16 4994 && (register_operand (operands[0], TImode) 4995 || reg_or_0_operand (operands[1], TImode))" 4996 { return mips_output_move (operands[0], operands[1]); } 4997 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo") 4998 (set (attr "mode") 4999 (if_then_else (eq_attr "move_type" "imul") 5000 (const_string "SI") 5001 (const_string "TI")))]) 5002 5003(define_insn "*movti_mips16" 5004 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d") 5005 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))] 5006 "TARGET_64BIT 5007 && TARGET_MIPS16 5008 && (register_operand (operands[0], TImode) 5009 || register_operand (operands[1], TImode))" 5010 "#" 5011 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") 5012 (set_attr "mode" "TI")]) 5013 5014;; 128-bit floating point moves 5015 5016(define_expand "movtf" 5017 [(set (match_operand:TF 0) 5018 (match_operand:TF 1))] 5019 "TARGET_64BIT" 5020{ 5021 if (mips_legitimize_move (TFmode, operands[0], operands[1])) 5022 DONE; 5023}) 5024 5025;; This pattern handles both hard- and soft-float cases. 5026(define_insn "*movtf" 5027 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m") 5028 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))] 5029 "TARGET_64BIT 5030 && !TARGET_MIPS16 5031 && (register_operand (operands[0], TFmode) 5032 || reg_or_0_operand (operands[1], TFmode))" 5033 "#" 5034 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore") 5035 (set_attr "mode" "TF")]) 5036 5037(define_insn "*movtf_mips16" 5038 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m") 5039 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))] 5040 "TARGET_64BIT 5041 && TARGET_MIPS16 5042 && (register_operand (operands[0], TFmode) 5043 || register_operand (operands[1], TFmode))" 5044 "#" 5045 [(set_attr "move_type" "move,move,move,load,store") 5046 (set_attr "mode" "TF")]) 5047 5048(define_split 5049 [(set (match_operand:MOVE64 0 "nonimmediate_operand") 5050 (match_operand:MOVE64 1 "move_operand"))] 5051 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)" 5052 [(const_int 0)] 5053{ 5054 mips_split_move_insn (operands[0], operands[1], curr_insn); 5055 DONE; 5056}) 5057 5058(define_split 5059 [(set (match_operand:MOVE128 0 "nonimmediate_operand") 5060 (match_operand:MOVE128 1 "move_operand"))] 5061 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)" 5062 [(const_int 0)] 5063{ 5064 mips_split_move_insn (operands[0], operands[1], curr_insn); 5065 DONE; 5066}) 5067 5068;; When generating mips16 code, split moves of negative constants into 5069;; a positive "li" followed by a negation. 5070(define_split 5071 [(set (match_operand 0 "d_operand") 5072 (match_operand 1 "const_int_operand"))] 5073 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0" 5074 [(set (match_dup 2) 5075 (match_dup 3)) 5076 (set (match_dup 2) 5077 (neg:SI (match_dup 2)))] 5078{ 5079 operands[2] = gen_lowpart (SImode, operands[0]); 5080 operands[3] = GEN_INT (-INTVAL (operands[1])); 5081}) 5082 5083;; 64-bit paired-single floating point moves 5084 5085(define_expand "movv2sf" 5086 [(set (match_operand:V2SF 0) 5087 (match_operand:V2SF 1))] 5088 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" 5089{ 5090 if (mips_legitimize_move (V2SFmode, operands[0], operands[1])) 5091 DONE; 5092}) 5093 5094(define_insn "*movv2sf" 5095 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m") 5096 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))] 5097 "TARGET_HARD_FLOAT 5098 && TARGET_PAIRED_SINGLE_FLOAT 5099 && (register_operand (operands[0], V2SFmode) 5100 || reg_or_0_operand (operands[1], V2SFmode))" 5101 { return mips_output_move (operands[0], operands[1]); } 5102 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store") 5103 (set_attr "mode" "DF")]) 5104 5105;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p 5106;; for the reason why we can't just use (reg:GPR HI_REGNUM). 5107;; 5108;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI 5109;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards 5110;; and the errata related to -mfix-vr4130. 5111(define_insn "mfhi<GPR:mode>_<HILO:mode>" 5112 [(set (match_operand:GPR 0 "register_operand" "=d") 5113 (unspec:GPR [(match_operand:HILO 1 "hilo_operand" "x")] 5114 UNSPEC_MFHI))] 5115 "" 5116 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; } 5117 [(set_attr "type" "mfhi") 5118 (set_attr "mode" "<GPR:MODE>")]) 5119 5120;; Set the high part of a HI/LO value, given that the low part has 5121;; already been set. See mips_hard_regno_mode_ok_p for the reason 5122;; why we can't just use (reg:GPR HI_REGNUM). 5123(define_insn "mthi<GPR:mode>_<HILO:mode>" 5124 [(set (match_operand:HILO 0 "register_operand" "=x") 5125 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ") 5126 (match_operand:GPR 2 "register_operand" "l")] 5127 UNSPEC_MTHI))] 5128 "" 5129 "mthi\t%z1" 5130 [(set_attr "type" "mthi") 5131 (set_attr "mode" "SI")]) 5132 5133;; Emit a doubleword move in which exactly one of the operands is 5134;; a floating-point register. We can't just emit two normal moves 5135;; because of the constraints imposed by the FPU register model; 5136;; see mips_cannot_change_mode_class for details. Instead, we keep 5137;; the FPR whole and use special patterns to refer to each word of 5138;; the other operand. 5139 5140(define_expand "move_doubleword_fpr<mode>" 5141 [(set (match_operand:SPLITF 0) 5142 (match_operand:SPLITF 1))] 5143 "" 5144{ 5145 if (FP_REG_RTX_P (operands[0])) 5146 { 5147 rtx low = mips_subword (operands[1], 0); 5148 rtx high = mips_subword (operands[1], 1); 5149 emit_insn (gen_load_low<mode> (operands[0], low)); 5150 if (ISA_HAS_MXHC1 && !TARGET_64BIT) 5151 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0])); 5152 else 5153 emit_insn (gen_load_high<mode> (operands[0], high, operands[0])); 5154 } 5155 else 5156 { 5157 rtx low = mips_subword (operands[0], 0); 5158 rtx high = mips_subword (operands[0], 1); 5159 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx)); 5160 if (ISA_HAS_MXHC1 && !TARGET_64BIT) 5161 emit_insn (gen_mfhc1<mode> (high, operands[1])); 5162 else 5163 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx)); 5164 } 5165 DONE; 5166}) 5167 5168;; Load the low word of operand 0 with operand 1. 5169(define_insn "load_low<mode>" 5170 [(set (match_operand:SPLITF 0 "register_operand" "=f,f") 5171 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")] 5172 UNSPEC_LOAD_LOW))] 5173 "TARGET_HARD_FLOAT" 5174{ 5175 operands[0] = mips_subword (operands[0], 0); 5176 return mips_output_move (operands[0], operands[1]); 5177} 5178 [(set_attr "move_type" "mtc,fpload") 5179 (set_attr "mode" "<HALFMODE>")]) 5180 5181;; Load the high word of operand 0 from operand 1, preserving the value 5182;; in the low word. 5183(define_insn "load_high<mode>" 5184 [(set (match_operand:SPLITF 0 "register_operand" "=f,f") 5185 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m") 5186 (match_operand:SPLITF 2 "register_operand" "0,0")] 5187 UNSPEC_LOAD_HIGH))] 5188 "TARGET_HARD_FLOAT" 5189{ 5190 operands[0] = mips_subword (operands[0], 1); 5191 return mips_output_move (operands[0], operands[1]); 5192} 5193 [(set_attr "move_type" "mtc,fpload") 5194 (set_attr "mode" "<HALFMODE>")]) 5195 5196;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the 5197;; high word and 0 to store the low word. 5198(define_insn "store_word<mode>" 5199 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m") 5200 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f") 5201 (match_operand 2 "const_int_operand")] 5202 UNSPEC_STORE_WORD))] 5203 "TARGET_HARD_FLOAT" 5204{ 5205 operands[1] = mips_subword (operands[1], INTVAL (operands[2])); 5206 return mips_output_move (operands[0], operands[1]); 5207} 5208 [(set_attr "move_type" "mfc,fpstore") 5209 (set_attr "mode" "<HALFMODE>")]) 5210 5211;; Move operand 1 to the high word of operand 0 using mthc1, preserving the 5212;; value in the low word. 5213(define_insn "mthc1<mode>" 5214 [(set (match_operand:SPLITF 0 "register_operand" "=f") 5215 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ") 5216 (match_operand:SPLITF 2 "register_operand" "0")] 5217 UNSPEC_MTHC1))] 5218 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1" 5219 "mthc1\t%z1,%0" 5220 [(set_attr "move_type" "mtc") 5221 (set_attr "mode" "<HALFMODE>")]) 5222 5223;; Move high word of operand 1 to operand 0 using mfhc1. 5224(define_insn "mfhc1<mode>" 5225 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d") 5226 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")] 5227 UNSPEC_MFHC1))] 5228 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1" 5229 "mfhc1\t%0,%1" 5230 [(set_attr "move_type" "mfc") 5231 (set_attr "mode" "<HALFMODE>")]) 5232 5233;; Move a constant that satisfies CONST_GP_P into operand 0. 5234(define_expand "load_const_gp_<mode>" 5235 [(set (match_operand:P 0 "register_operand" "=d") 5236 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))]) 5237 5238;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset 5239;; of _gp from the start of this function. Operand 1 is the incoming 5240;; function address. 5241(define_insn_and_split "loadgp_newabi_<mode>" 5242 [(set (match_operand:P 0 "register_operand" "=&d") 5243 (unspec:P [(match_operand:P 1) 5244 (match_operand:P 2 "register_operand" "d")] 5245 UNSPEC_LOADGP))] 5246 "mips_current_loadgp_style () == LOADGP_NEWABI" 5247 { return mips_must_initialize_gp_p () ? "#" : ""; } 5248 "&& mips_must_initialize_gp_p ()" 5249 [(set (match_dup 0) (match_dup 3)) 5250 (set (match_dup 0) (match_dup 4)) 5251 (set (match_dup 0) (match_dup 5))] 5252{ 5253 operands[3] = gen_rtx_HIGH (Pmode, operands[1]); 5254 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]); 5255 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]); 5256} 5257 [(set_attr "type" "ghost")]) 5258 5259;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol. 5260(define_insn_and_split "loadgp_absolute_<mode>" 5261 [(set (match_operand:P 0 "register_operand" "=d") 5262 (unspec:P [(match_operand:P 1)] UNSPEC_LOADGP))] 5263 "mips_current_loadgp_style () == LOADGP_ABSOLUTE" 5264 { return mips_must_initialize_gp_p () ? "#" : ""; } 5265 "&& mips_must_initialize_gp_p ()" 5266 [(const_int 0)] 5267{ 5268 mips_emit_move (operands[0], operands[1]); 5269 DONE; 5270} 5271 [(set_attr "type" "ghost")]) 5272 5273;; This blockage instruction prevents the gp load from being 5274;; scheduled after an implicit use of gp. It also prevents 5275;; the load from being deleted as dead. 5276(define_insn "loadgp_blockage" 5277 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)] 5278 "" 5279 "" 5280 [(set_attr "type" "ghost")]) 5281 5282;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol 5283;; and operand 1 is the __GOTT_INDEX__ symbol. 5284(define_insn_and_split "loadgp_rtp_<mode>" 5285 [(set (match_operand:P 0 "register_operand" "=d") 5286 (unspec:P [(match_operand:P 1 "symbol_ref_operand") 5287 (match_operand:P 2 "symbol_ref_operand")] 5288 UNSPEC_LOADGP))] 5289 "mips_current_loadgp_style () == LOADGP_RTP" 5290 { return mips_must_initialize_gp_p () ? "#" : ""; } 5291 "&& mips_must_initialize_gp_p ()" 5292 [(set (match_dup 0) (high:P (match_dup 3))) 5293 (set (match_dup 0) (unspec:P [(match_dup 0) 5294 (match_dup 3)] UNSPEC_LOAD_GOT)) 5295 (set (match_dup 0) (unspec:P [(match_dup 0) 5296 (match_dup 4)] UNSPEC_LOAD_GOT))] 5297{ 5298 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE); 5299 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF); 5300} 5301 [(set_attr "type" "ghost")]) 5302 5303;; Initialize the global pointer for MIPS16 code. Operand 0 is the 5304;; global pointer and operand 1 is the MIPS16 register that holds 5305;; the required value. 5306(define_insn_and_split "copygp_mips16_<mode>" 5307 [(set (match_operand:P 0 "register_operand" "=y") 5308 (unspec:P [(match_operand:P 1 "register_operand" "d")] 5309 UNSPEC_COPYGP))] 5310 "TARGET_MIPS16" 5311 { return mips_must_initialize_gp_p () ? "#" : ""; } 5312 "&& mips_must_initialize_gp_p ()" 5313 [(set (match_dup 0) (match_dup 1))] 5314 "" 5315 [(set_attr "type" "ghost")]) 5316 5317;; A placeholder for where the cprestore instruction should go, 5318;; if we decide we need one. Operand 0 and operand 1 are as for 5319;; "cprestore". Operand 2 is a register that holds the gp value. 5320;; 5321;; The "cprestore" pattern requires operand 2 to be pic_offset_table_rtx, 5322;; otherwise any register that holds the correct value will do. 5323(define_insn_and_split "potential_cprestore_<mode>" 5324 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X") 5325 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i") 5326 (match_operand:P 2 "register_operand" "d,d")] 5327 UNSPEC_POTENTIAL_CPRESTORE)) 5328 (clobber (match_operand:P 3 "scratch_operand" "=X,&d"))] 5329 "!TARGET_CPRESTORE_DIRECTIVE || operands[2] == pic_offset_table_rtx" 5330 { return mips_must_initialize_gp_p () ? "#" : ""; } 5331 "mips_must_initialize_gp_p ()" 5332 [(const_int 0)] 5333{ 5334 mips_save_gp_to_cprestore_slot (operands[0], operands[1], 5335 operands[2], operands[3]); 5336 DONE; 5337} 5338 [(set_attr "type" "ghost")]) 5339 5340;; Emit a .cprestore directive, which normally expands to a single store 5341;; instruction. Operand 0 is a (possibly illegitimate) sp-based MEM 5342;; for the cprestore slot. Operand 1 is the offset of the slot from 5343;; the stack pointer. (This is redundant with operand 0, but it makes 5344;; things a little simpler.) 5345(define_insn "cprestore_<mode>" 5346 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X") 5347 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i") 5348 (reg:P 28)] 5349 UNSPEC_CPRESTORE))] 5350 "TARGET_CPRESTORE_DIRECTIVE" 5351{ 5352 if (mips_nomacro.nesting_level > 0 && which_alternative == 1) 5353 return ".set\tmacro\;.cprestore\t%1\;.set\tnomacro"; 5354 else 5355 return ".cprestore\t%1"; 5356} 5357 [(set_attr "type" "store") 5358 (set_attr "insn_count" "1,3")]) 5359 5360(define_insn "use_cprestore_<mode>" 5361 [(set (reg:P CPRESTORE_SLOT_REGNUM) 5362 (match_operand:P 0 "cprestore_load_slot_operand"))] 5363 "" 5364 "" 5365 [(set_attr "type" "ghost")]) 5366 5367;; Expand in-line code to clear the instruction cache between operand[0] and 5368;; operand[1]. 5369(define_expand "clear_cache" 5370 [(match_operand 0 "pmode_register_operand") 5371 (match_operand 1 "pmode_register_operand")] 5372 "" 5373 " 5374{ 5375 if (TARGET_SYNCI) 5376 { 5377 mips_expand_synci_loop (operands[0], operands[1]); 5378 emit_insn (gen_sync ()); 5379 emit_insn (PMODE_INSN (gen_clear_hazard, ())); 5380 } 5381 else if (mips_cache_flush_func && mips_cache_flush_func[0]) 5382 { 5383 rtx len = gen_reg_rtx (Pmode); 5384 emit_insn (gen_sub3_insn (len, operands[1], operands[0])); 5385 MIPS_ICACHE_SYNC (operands[0], len); 5386 } 5387 DONE; 5388}") 5389 5390(define_insn "sync" 5391 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)] 5392 "GENERATE_SYNC" 5393 { return mips_output_sync (); }) 5394 5395(define_insn "synci" 5396 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")] 5397 UNSPEC_SYNCI)] 5398 "TARGET_SYNCI" 5399 "synci\t0(%0)") 5400 5401(define_insn "rdhwr_synci_step_<mode>" 5402 [(set (match_operand:P 0 "register_operand" "=d") 5403 (unspec_volatile [(const_int 1)] 5404 UNSPEC_RDHWR))] 5405 "ISA_HAS_SYNCI" 5406 "rdhwr\t%0,$1") 5407 5408(define_insn "clear_hazard_<mode>" 5409 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD) 5410 (clobber (reg:P RETURN_ADDR_REGNUM))] 5411 "ISA_HAS_SYNCI" 5412{ 5413 return "%(%<bal\t1f\n" 5414 "\tnop\n" 5415 "1:\t<d>addiu\t$31,$31,12\n" 5416 "\tjr.hb\t$31\n" 5417 "\tnop%>%)"; 5418} 5419 [(set_attr "insn_count" "5")]) 5420 5421;; Cache operations for R4000-style caches. 5422(define_insn "mips_cache" 5423 [(set (mem:BLK (scratch)) 5424 (unspec:BLK [(match_operand:SI 0 "const_int_operand") 5425 (match_operand:QI 1 "address_operand" "ZD")] 5426 UNSPEC_MIPS_CACHE))] 5427 "ISA_HAS_CACHE" 5428 "cache\t%X0,%a1") 5429 5430;; Similar, but with the operands hard-coded to an R10K cache barrier 5431;; operation. We keep the pattern distinct so that we can identify 5432;; cache operations inserted by -mr10k-cache-barrier=, and so that 5433;; the operation is never inserted into a delay slot. 5434(define_insn "r10k_cache_barrier" 5435 [(set (mem:BLK (scratch)) 5436 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))] 5437 "ISA_HAS_CACHE" 5438 "cache\t0x14,0(%$)" 5439 [(set_attr "can_delay" "no")]) 5440 5441;; Block moves, see mips.c for more details. 5442;; Argument 0 is the destination 5443;; Argument 1 is the source 5444;; Argument 2 is the length 5445;; Argument 3 is the alignment 5446 5447(define_expand "movmemsi" 5448 [(parallel [(set (match_operand:BLK 0 "general_operand") 5449 (match_operand:BLK 1 "general_operand")) 5450 (use (match_operand:SI 2 "")) 5451 (use (match_operand:SI 3 "const_int_operand"))])] 5452 "!TARGET_MIPS16 && !TARGET_MEMCPY" 5453{ 5454 if (mips_expand_block_move (operands[0], operands[1], operands[2])) 5455 DONE; 5456 else 5457 FAIL; 5458}) 5459 5460;; 5461;; .................... 5462;; 5463;; SHIFTS 5464;; 5465;; .................... 5466 5467(define_expand "<optab><mode>3" 5468 [(set (match_operand:GPR 0 "register_operand") 5469 (any_shift:GPR (match_operand:GPR 1 "register_operand") 5470 (match_operand:SI 2 "arith_operand")))] 5471 "" 5472{ 5473 /* On the mips16, a shift of more than 8 is a four byte instruction, 5474 so, for a shift between 8 and 16, it is just as fast to do two 5475 shifts of 8 or less. If there is a lot of shifting going on, we 5476 may win in CSE. Otherwise combine will put the shifts back 5477 together again. This can be called by mips_function_arg, so we must 5478 be careful not to allocate a new register if we've reached the 5479 reload pass. */ 5480 if (TARGET_MIPS16 5481 && optimize 5482 && CONST_INT_P (operands[2]) 5483 && INTVAL (operands[2]) > 8 5484 && INTVAL (operands[2]) <= 16 5485 && !reload_in_progress 5486 && !reload_completed) 5487 { 5488 rtx temp = gen_reg_rtx (<MODE>mode); 5489 5490 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8))); 5491 emit_insn (gen_<optab><mode>3 (operands[0], temp, 5492 GEN_INT (INTVAL (operands[2]) - 8))); 5493 DONE; 5494 } 5495}) 5496 5497(define_insn "*<optab><mode>3" 5498 [(set (match_operand:GPR 0 "register_operand" "=!u,d") 5499 (any_shift:GPR (match_operand:GPR 1 "register_operand" "!u,d") 5500 (match_operand:SI 2 "arith_operand" "Uib3,dI")))] 5501 "!TARGET_MIPS16" 5502{ 5503 if (CONST_INT_P (operands[2])) 5504 operands[2] = GEN_INT (INTVAL (operands[2]) 5505 & (GET_MODE_BITSIZE (<MODE>mode) - 1)); 5506 5507 return "<d><insn>\t%0,%1,%2"; 5508} 5509 [(set_attr "type" "shift") 5510 (set_attr "compression" "<shift_compression>,none") 5511 (set_attr "mode" "<MODE>")]) 5512 5513(define_insn "*<optab>si3_extend" 5514 [(set (match_operand:DI 0 "register_operand" "=d") 5515 (sign_extend:DI 5516 (any_shift:SI (match_operand:SI 1 "register_operand" "d") 5517 (match_operand:SI 2 "arith_operand" "dI"))))] 5518 "TARGET_64BIT && !TARGET_MIPS16" 5519{ 5520 if (CONST_INT_P (operands[2])) 5521 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 5522 5523 return "<insn>\t%0,%1,%2"; 5524} 5525 [(set_attr "type" "shift") 5526 (set_attr "mode" "SI")]) 5527 5528(define_insn "*<optab>si3_mips16" 5529 [(set (match_operand:SI 0 "register_operand" "=d,d,d") 5530 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d,d") 5531 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))] 5532 "TARGET_MIPS16" 5533{ 5534 if (which_alternative == 0) 5535 return "<insn>\t%0,%2"; 5536 5537 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 5538 return "<insn>\t%0,%1,%2"; 5539} 5540 [(set_attr "type" "shift") 5541 (set_attr "mode" "SI") 5542 (set_attr "extended_mips16" "no,no,yes")]) 5543 5544(define_insn "<GPR:d>lsa" 5545 [(set (match_operand:GPR 0 "register_operand" "=d") 5546 (plus:GPR (mult:GPR (match_operand:GPR 1 "register_operand" "d") 5547 (match_operand 2 "const_immlsa_operand" "")) 5548 (match_operand:GPR 3 "register_operand" "d")))] 5549 "ISA_HAS_<GPR:D>LSA" 5550 "<GPR:d>lsa\t%0,%1,%3,%y2" 5551 [(set_attr "type" "arith") 5552 (set_attr "mode" "<GPR:MODE>")]) 5553 5554;; We need separate DImode MIPS16 patterns because of the irregularity 5555;; of right shifts. 5556(define_insn "*ashldi3_mips16" 5557 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 5558 (ashift:DI (match_operand:DI 1 "register_operand" "0,d,d") 5559 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))] 5560 "TARGET_64BIT && TARGET_MIPS16" 5561{ 5562 if (which_alternative == 0) 5563 return "dsll\t%0,%2"; 5564 5565 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 5566 return "dsll\t%0,%1,%2"; 5567} 5568 [(set_attr "type" "shift") 5569 (set_attr "mode" "DI") 5570 (set_attr "extended_mips16" "no,no,yes")]) 5571 5572(define_insn "*ashrdi3_mips16" 5573 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 5574 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0") 5575 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))] 5576 "TARGET_64BIT && TARGET_MIPS16" 5577{ 5578 if (CONST_INT_P (operands[2])) 5579 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 5580 5581 return "dsra\t%0,%2"; 5582} 5583 [(set_attr "type" "shift") 5584 (set_attr "mode" "DI") 5585 (set_attr "extended_mips16" "no,no,yes")]) 5586 5587(define_insn "*lshrdi3_mips16" 5588 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 5589 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0") 5590 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))] 5591 "TARGET_64BIT && TARGET_MIPS16" 5592{ 5593 if (CONST_INT_P (operands[2])) 5594 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 5595 5596 return "dsrl\t%0,%2"; 5597} 5598 [(set_attr "type" "shift") 5599 (set_attr "mode" "DI") 5600 (set_attr "extended_mips16" "no,no,yes")]) 5601 5602;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts. 5603 5604(define_split 5605 [(set (match_operand:GPR 0 "d_operand") 5606 (any_shift:GPR (match_operand:GPR 1 "d_operand") 5607 (match_operand:GPR 2 "const_int_operand")))] 5608 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE 5609 && INTVAL (operands[2]) > 8 5610 && INTVAL (operands[2]) <= 16" 5611 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8))) 5612 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))] 5613 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); }) 5614 5615;; If we load a byte on the mips16 as a bitfield, the resulting 5616;; sequence of instructions is too complicated for combine, because it 5617;; involves four instructions: a load, a shift, a constant load into a 5618;; register, and an and (the key problem here is that the mips16 does 5619;; not have and immediate). We recognize a shift of a load in order 5620;; to make it simple enough for combine to understand. 5621;; 5622;; The instruction count here is the worst case. 5623(define_insn_and_split "" 5624 [(set (match_operand:SI 0 "register_operand" "=d") 5625 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") 5626 (match_operand:SI 2 "immediate_operand" "I")))] 5627 "TARGET_MIPS16" 5628 "#" 5629 "" 5630 [(set (match_dup 0) (match_dup 1)) 5631 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] 5632 "" 5633 [(set_attr "type" "load") 5634 (set_attr "mode" "SI") 5635 (set (attr "insn_count") 5636 (symbol_ref "mips_load_store_insns (operands[1], insn) + 2"))]) 5637 5638(define_insn "rotr<mode>3" 5639 [(set (match_operand:GPR 0 "register_operand" "=d") 5640 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d") 5641 (match_operand:SI 2 "arith_operand" "dI")))] 5642 "ISA_HAS_ROR" 5643{ 5644 if (CONST_INT_P (operands[2])) 5645 gcc_assert (INTVAL (operands[2]) >= 0 5646 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)); 5647 5648 return "<d>ror\t%0,%1,%2"; 5649} 5650 [(set_attr "type" "shift") 5651 (set_attr "mode" "<MODE>")]) 5652 5653(define_insn "bswaphi2" 5654 [(set (match_operand:HI 0 "register_operand" "=d") 5655 (bswap:HI (match_operand:HI 1 "register_operand" "d")))] 5656 "ISA_HAS_WSBH" 5657 "wsbh\t%0,%1" 5658 [(set_attr "type" "shift")]) 5659 5660(define_insn_and_split "bswapsi2" 5661 [(set (match_operand:SI 0 "register_operand" "=d") 5662 (bswap:SI (match_operand:SI 1 "register_operand" "d")))] 5663 "ISA_HAS_WSBH && ISA_HAS_ROR" 5664 "#" 5665 "" 5666 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH)) 5667 (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))] 5668 "" 5669 [(set_attr "insn_count" "2")]) 5670 5671(define_insn_and_split "bswapdi2" 5672 [(set (match_operand:DI 0 "register_operand" "=d") 5673 (bswap:DI (match_operand:DI 1 "register_operand" "d")))] 5674 "TARGET_64BIT && ISA_HAS_WSBH" 5675 "#" 5676 "" 5677 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH)) 5678 (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))] 5679 "" 5680 [(set_attr "insn_count" "2")]) 5681 5682(define_insn "wsbh" 5683 [(set (match_operand:SI 0 "register_operand" "=d") 5684 (unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))] 5685 "ISA_HAS_WSBH" 5686 "wsbh\t%0,%1" 5687 [(set_attr "type" "shift")]) 5688 5689(define_insn "dsbh" 5690 [(set (match_operand:DI 0 "register_operand" "=d") 5691 (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))] 5692 "TARGET_64BIT && ISA_HAS_WSBH" 5693 "dsbh\t%0,%1" 5694 [(set_attr "type" "shift")]) 5695 5696(define_insn "dshd" 5697 [(set (match_operand:DI 0 "register_operand" "=d") 5698 (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))] 5699 "TARGET_64BIT && ISA_HAS_WSBH" 5700 "dshd\t%0,%1" 5701 [(set_attr "type" "shift")]) 5702 5703;; 5704;; .................... 5705;; 5706;; CONDITIONAL BRANCHES 5707;; 5708;; .................... 5709 5710;; Conditional branches on floating-point equality tests. 5711 5712(define_insn "*branch_fp_<mode>" 5713 [(set (pc) 5714 (if_then_else 5715 (match_operator 1 "equality_operator" 5716 [(match_operand:FPCC 2 "register_operand" "<reg>") 5717 (const_int 0)]) 5718 (label_ref (match_operand 0 "" "")) 5719 (pc)))] 5720 "TARGET_HARD_FLOAT" 5721{ 5722 return mips_output_conditional_branch (insn, operands, 5723 MIPS_BRANCH ("b%F1", "%Z2%0"), 5724 MIPS_BRANCH ("b%W1", "%Z2%0")); 5725} 5726 [(set_attr "type" "branch")]) 5727 5728(define_insn "*branch_fp_inverted_<mode>" 5729 [(set (pc) 5730 (if_then_else 5731 (match_operator 1 "equality_operator" 5732 [(match_operand:FPCC 2 "register_operand" "<reg>") 5733 (const_int 0)]) 5734 (pc) 5735 (label_ref (match_operand 0 "" ""))))] 5736 "TARGET_HARD_FLOAT" 5737{ 5738 return mips_output_conditional_branch (insn, operands, 5739 MIPS_BRANCH ("b%W1", "%Z2%0"), 5740 MIPS_BRANCH ("b%F1", "%Z2%0")); 5741} 5742 [(set_attr "type" "branch")]) 5743 5744;; Conditional branches on ordered comparisons with zero. 5745 5746(define_insn "*branch_order<mode>" 5747 [(set (pc) 5748 (if_then_else 5749 (match_operator 1 "order_operator" 5750 [(match_operand:GPR 2 "register_operand" "d") 5751 (const_int 0)]) 5752 (label_ref (match_operand 0 "" "")) 5753 (pc)))] 5754 "!TARGET_MIPS16" 5755 { return mips_output_order_conditional_branch (insn, operands, false); } 5756 [(set_attr "type" "branch")]) 5757 5758(define_insn "*branch_order<mode>_inverted" 5759 [(set (pc) 5760 (if_then_else 5761 (match_operator 1 "order_operator" 5762 [(match_operand:GPR 2 "register_operand" "d") 5763 (const_int 0)]) 5764 (pc) 5765 (label_ref (match_operand 0 "" ""))))] 5766 "!TARGET_MIPS16" 5767 { return mips_output_order_conditional_branch (insn, operands, true); } 5768 [(set_attr "type" "branch")]) 5769 5770;; Conditional branch on equality comparison. 5771 5772(define_insn "*branch_equality<mode>" 5773 [(set (pc) 5774 (if_then_else 5775 (match_operator 1 "equality_operator" 5776 [(match_operand:GPR 2 "register_operand" "d") 5777 (match_operand:GPR 3 "reg_or_0_operand" "dJ")]) 5778 (label_ref (match_operand 0 "" "")) 5779 (pc)))] 5780 "!TARGET_MIPS16" 5781{ 5782 /* For a simple BNEZ or BEQZ microMIPS branch. */ 5783 if (TARGET_MICROMIPS 5784 && operands[3] == const0_rtx 5785 && get_attr_length (insn) <= 8) 5786 return mips_output_conditional_branch (insn, operands, 5787 "%*b%C1z%:\t%2,%0", 5788 "%*b%N1z%:\t%2,%0"); 5789 5790 return mips_output_conditional_branch (insn, operands, 5791 MIPS_BRANCH ("b%C1", "%2,%z3,%0"), 5792 MIPS_BRANCH ("b%N1", "%2,%z3,%0")); 5793} 5794 [(set_attr "type" "branch")]) 5795 5796(define_insn "*branch_equality<mode>_inverted" 5797 [(set (pc) 5798 (if_then_else 5799 (match_operator 1 "equality_operator" 5800 [(match_operand:GPR 2 "register_operand" "d") 5801 (match_operand:GPR 3 "reg_or_0_operand" "dJ")]) 5802 (pc) 5803 (label_ref (match_operand 0 "" ""))))] 5804 "!TARGET_MIPS16" 5805{ 5806 /* For a simple BNEZ or BEQZ microMIPS branch. */ 5807 if (TARGET_MICROMIPS 5808 && operands[3] == const0_rtx 5809 && get_attr_length (insn) <= 8) 5810 return mips_output_conditional_branch (insn, operands, 5811 "%*b%N0z%:\t%2,%1", 5812 "%*b%C0z%:\t%2,%1"); 5813 5814 return mips_output_conditional_branch (insn, operands, 5815 MIPS_BRANCH ("b%N1", "%2,%z3,%0"), 5816 MIPS_BRANCH ("b%C1", "%2,%z3,%0")); 5817} 5818 [(set_attr "type" "branch")]) 5819 5820;; MIPS16 branches 5821 5822(define_insn "*branch_equality<mode>_mips16" 5823 [(set (pc) 5824 (if_then_else 5825 (match_operator 1 "equality_operator" 5826 [(match_operand:GPR 2 "register_operand" "d,t") 5827 (const_int 0)]) 5828 (label_ref (match_operand 0 "" "")) 5829 (pc)))] 5830 "TARGET_MIPS16" 5831 "@ 5832 b%C1z\t%2,%0 5833 bt%C1z\t%0" 5834 [(set_attr "type" "branch")]) 5835 5836(define_insn "*branch_equality<mode>_mips16_inverted" 5837 [(set (pc) 5838 (if_then_else 5839 (match_operator 1 "equality_operator" 5840 [(match_operand:GPR 2 "register_operand" "d,t") 5841 (const_int 0)]) 5842 (pc) 5843 (label_ref (match_operand 0 "" ""))))] 5844 "TARGET_MIPS16" 5845 "@ 5846 b%N1z\t%2,%0 5847 bt%N1z\t%0" 5848 [(set_attr "type" "branch")]) 5849 5850(define_expand "cbranch<mode>4" 5851 [(set (pc) 5852 (if_then_else (match_operator 0 "comparison_operator" 5853 [(match_operand:GPR 1 "register_operand") 5854 (match_operand:GPR 2 "nonmemory_operand")]) 5855 (label_ref (match_operand 3 "")) 5856 (pc)))] 5857 "" 5858{ 5859 mips_expand_conditional_branch (operands); 5860 DONE; 5861}) 5862 5863(define_expand "cbranch<mode>4" 5864 [(set (pc) 5865 (if_then_else (match_operator 0 "comparison_operator" 5866 [(match_operand:SCALARF 1 "register_operand") 5867 (match_operand:SCALARF 2 "register_operand")]) 5868 (label_ref (match_operand 3 "")) 5869 (pc)))] 5870 "" 5871{ 5872 mips_expand_conditional_branch (operands); 5873 DONE; 5874}) 5875 5876;; Used to implement built-in functions. 5877(define_expand "condjump" 5878 [(set (pc) 5879 (if_then_else (match_operand 0) 5880 (label_ref (match_operand 1)) 5881 (pc)))]) 5882 5883;; Branch if bit is set/clear. 5884 5885(define_insn "*branch_bit<bbv><mode>" 5886 [(set (pc) 5887 (if_then_else 5888 (equality_op (zero_extract:GPR 5889 (match_operand:GPR 1 "register_operand" "d") 5890 (const_int 1) 5891 (match_operand 2 "const_int_operand" "")) 5892 (const_int 0)) 5893 (label_ref (match_operand 0 "")) 5894 (pc)))] 5895 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" 5896{ 5897 return 5898 mips_output_conditional_branch (insn, operands, 5899 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"), 5900 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0")); 5901} 5902 [(set_attr "type" "branch") 5903 (set_attr "branch_likely" "no")]) 5904 5905(define_insn "*branch_bit<bbv><mode>_inverted" 5906 [(set (pc) 5907 (if_then_else 5908 (equality_op (zero_extract:GPR 5909 (match_operand:GPR 1 "register_operand" "d") 5910 (const_int 1) 5911 (match_operand 2 "const_int_operand" "")) 5912 (const_int 0)) 5913 (pc) 5914 (label_ref (match_operand 0 ""))))] 5915 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" 5916{ 5917 return 5918 mips_output_conditional_branch (insn, operands, 5919 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"), 5920 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0")); 5921} 5922 [(set_attr "type" "branch") 5923 (set_attr "branch_likely" "no")]) 5924 5925;; 5926;; .................... 5927;; 5928;; SETTING A REGISTER FROM A COMPARISON 5929;; 5930;; .................... 5931 5932;; Destination is always set in SI mode. 5933 5934(define_expand "cstore<mode>4" 5935 [(set (match_operand:SI 0 "register_operand") 5936 (match_operator:SI 1 "mips_cstore_operator" 5937 [(match_operand:GPR 2 "register_operand") 5938 (match_operand:GPR 3 "nonmemory_operand")]))] 5939 "" 5940{ 5941 mips_expand_scc (operands); 5942 DONE; 5943}) 5944 5945(define_insn "*seq_zero_<GPR:mode><GPR2:mode>" 5946 [(set (match_operand:GPR2 0 "register_operand" "=d") 5947 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d") 5948 (const_int 0)))] 5949 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE" 5950 "sltu\t%0,%1,1" 5951 [(set_attr "type" "slt") 5952 (set_attr "mode" "<GPR:MODE>")]) 5953 5954(define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16" 5955 [(set (match_operand:GPR2 0 "register_operand" "=t") 5956 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d") 5957 (const_int 0)))] 5958 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE" 5959 "sltu\t%1,1" 5960 [(set_attr "type" "slt") 5961 (set_attr "mode" "<GPR:MODE>")]) 5962 5963;; Generate sltiu unless using seq results in better code. 5964(define_insn "*seq_<GPR:mode><GPR2:mode>_seq" 5965 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d") 5966 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d") 5967 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))] 5968 "ISA_HAS_SEQ_SNE" 5969 "@ 5970 seq\t%0,%1,%2 5971 sltiu\t%0,%1,1 5972 seqi\t%0,%1,%2" 5973 [(set_attr "type" "slt") 5974 (set_attr "mode" "<GPR:MODE>")]) 5975 5976(define_insn "*sne_zero_<GPR:mode><GPR2:mode>" 5977 [(set (match_operand:GPR2 0 "register_operand" "=d") 5978 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d") 5979 (const_int 0)))] 5980 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE" 5981 "sltu\t%0,%.,%1" 5982 [(set_attr "type" "slt") 5983 (set_attr "mode" "<GPR:MODE>")]) 5984 5985;; Generate sltu unless using sne results in better code. 5986(define_insn "*sne_<GPR:mode><GPR2:mode>_sne" 5987 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d") 5988 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d") 5989 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))] 5990 "ISA_HAS_SEQ_SNE" 5991 "@ 5992 sne\t%0,%1,%2 5993 sltu\t%0,%.,%1 5994 snei\t%0,%1,%2" 5995 [(set_attr "type" "slt") 5996 (set_attr "mode" "<GPR:MODE>")]) 5997 5998(define_insn "*sgt<u>_<GPR:mode><GPR2:mode>" 5999 [(set (match_operand:GPR2 0 "register_operand" "=d") 6000 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d") 6001 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))] 6002 "!TARGET_MIPS16" 6003 "slt<u>\t%0,%z2,%1" 6004 [(set_attr "type" "slt") 6005 (set_attr "mode" "<GPR:MODE>")]) 6006 6007(define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16" 6008 [(set (match_operand:GPR2 0 "register_operand" "=t") 6009 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d") 6010 (match_operand:GPR 2 "register_operand" "d")))] 6011 "TARGET_MIPS16" 6012 "slt<u>\t%2,%1" 6013 [(set_attr "type" "slt") 6014 (set_attr "mode" "<GPR:MODE>")]) 6015 6016(define_insn "*sge<u>_<GPR:mode><GPR2:mode>" 6017 [(set (match_operand:GPR2 0 "register_operand" "=d") 6018 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d") 6019 (const_int 1)))] 6020 "!TARGET_MIPS16" 6021 "slt<u>\t%0,%.,%1" 6022 [(set_attr "type" "slt") 6023 (set_attr "mode" "<GPR:MODE>")]) 6024 6025(define_insn "*slt<u>_<GPR:mode><GPR2:mode>" 6026 [(set (match_operand:GPR2 0 "register_operand" "=d") 6027 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d") 6028 (match_operand:GPR 2 "arith_operand" "dI")))] 6029 "!TARGET_MIPS16" 6030 "slt<u>\t%0,%1,%2" 6031 [(set_attr "type" "slt") 6032 (set_attr "mode" "<GPR:MODE>")]) 6033 6034(define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16" 6035 [(set (match_operand:GPR2 0 "register_operand" "=t,t,t") 6036 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d,d") 6037 (match_operand:GPR 2 "arith_operand" "d,Uub8,I")))] 6038 "TARGET_MIPS16" 6039 "slt<u>\t%1,%2" 6040 [(set_attr "type" "slt") 6041 (set_attr "mode" "<GPR:MODE>") 6042 (set_attr "extended_mips16" "no,no,yes")]) 6043 6044(define_insn "*sle<u>_<GPR:mode><GPR2:mode>" 6045 [(set (match_operand:GPR2 0 "register_operand" "=d") 6046 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d") 6047 (match_operand:GPR 2 "sle_operand" "")))] 6048 "!TARGET_MIPS16" 6049{ 6050 operands[2] = GEN_INT (INTVAL (operands[2]) + 1); 6051 return "slt<u>\t%0,%1,%2"; 6052} 6053 [(set_attr "type" "slt") 6054 (set_attr "mode" "<GPR:MODE>")]) 6055 6056(define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16" 6057 [(set (match_operand:GPR2 0 "register_operand" "=t,t") 6058 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d,d") 6059 (match_operand:GPR 2 "sle_operand" "Udb8,i")))] 6060 "TARGET_MIPS16" 6061{ 6062 operands[2] = GEN_INT (INTVAL (operands[2]) + 1); 6063 return "slt<u>\t%1,%2"; 6064} 6065 [(set_attr "type" "slt") 6066 (set_attr "mode" "<GPR:MODE>") 6067 (set_attr "extended_mips16" "no,yes")]) 6068 6069;; 6070;; .................... 6071;; 6072;; FLOATING POINT COMPARISONS 6073;; 6074;; .................... 6075 6076(define_insn "s<code>_<SCALARF:mode>_using_<FPCC:mode>" 6077 [(set (match_operand:FPCC 0 "register_operand" "=<reg>") 6078 (fcond:FPCC (match_operand:SCALARF 1 "register_operand" "f") 6079 (match_operand:SCALARF 2 "register_operand" "f")))] 6080 "" 6081 "<fpcmp>.<fcond>.<fmt>\t%Z0%1,%2" 6082 [(set_attr "type" "fcmp") 6083 (set_attr "mode" "FPSW")]) 6084 6085(define_insn "s<code>_<SCALARF:mode>_using_<FPCC:mode>" 6086 [(set (match_operand:FPCC 0 "register_operand" "=<reg>") 6087 (swapped_fcond:FPCC (match_operand:SCALARF 1 "register_operand" "f") 6088 (match_operand:SCALARF 2 "register_operand" "f")))] 6089 "" 6090 "<fpcmp>.<swapped_fcond>.<fmt>\t%Z0%2,%1" 6091 [(set_attr "type" "fcmp") 6092 (set_attr "mode" "FPSW")]) 6093 6094;; 6095;; .................... 6096;; 6097;; UNCONDITIONAL BRANCHES 6098;; 6099;; .................... 6100 6101;; Unconditional branches. 6102 6103(define_expand "jump" 6104 [(set (pc) 6105 (label_ref (match_operand 0)))]) 6106 6107(define_insn "*jump_absolute" 6108 [(set (pc) 6109 (label_ref (match_operand 0)))] 6110 "!TARGET_MIPS16 && TARGET_ABSOLUTE_JUMPS" 6111{ 6112 if (get_attr_length (insn) <= 8) 6113 return "%*b\t%l0%/"; 6114 else 6115 return MIPS_ABSOLUTE_JUMP ("%*j\t%l0%/"); 6116} 6117 [(set_attr "type" "branch")]) 6118 6119(define_insn "*jump_pic" 6120 [(set (pc) 6121 (label_ref (match_operand 0)))] 6122 "!TARGET_MIPS16 && !TARGET_ABSOLUTE_JUMPS" 6123{ 6124 if (get_attr_length (insn) <= 8) 6125 return "%*b\t%l0%/"; 6126 else 6127 { 6128 mips_output_load_label (operands[0]); 6129 return "%*jr\t%@%/%]"; 6130 } 6131} 6132 [(set_attr "type" "branch")]) 6133 6134;; We need a different insn for the mips16, because a mips16 branch 6135;; does not have a delay slot. 6136 6137(define_insn "*jump_mips16" 6138 [(set (pc) 6139 (label_ref (match_operand 0 "" "")))] 6140 "TARGET_MIPS16" 6141 "b\t%l0" 6142 [(set_attr "type" "branch") 6143 (set (attr "length") 6144 ;; This calculation is like the normal branch one, but the 6145 ;; range of the unextended instruction is [-0x800, 0x7fe] rather 6146 ;; than [-0x100, 0xfe]. This translates to a range of: 6147 ;; 6148 ;; [-(0x800 - sizeof (branch)), 0x7fe] 6149 ;; == [-0x7fe, 0x7fe] 6150 ;; 6151 ;; from the shorten_branches reference address. Long-branch 6152 ;; sequences will replace this one, so the minimum length 6153 ;; is one instruction shorter than for conditional branches. 6154 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 2046)) 6155 (le (minus (pc) (match_dup 0)) (const_int 2046))) 6156 (const_int 2) 6157 (and (le (minus (match_dup 0) (pc)) (const_int 65534)) 6158 (le (minus (pc) (match_dup 0)) (const_int 65532))) 6159 (const_int 4) 6160 (and (match_test "TARGET_ABICALLS") 6161 (not (match_test "TARGET_ABSOLUTE_ABICALLS"))) 6162 (const_int 18) 6163 (match_test "Pmode == SImode") 6164 (const_int 14) 6165 ] (const_int 22)))]) 6166 6167(define_expand "indirect_jump" 6168 [(set (pc) (match_operand 0 "register_operand"))] 6169 "" 6170{ 6171 operands[0] = force_reg (Pmode, operands[0]); 6172 emit_jump_insn (PMODE_INSN (gen_indirect_jump, (operands[0]))); 6173 DONE; 6174}) 6175 6176(define_insn "indirect_jump_<mode>" 6177 [(set (pc) (match_operand:P 0 "register_operand" "d"))] 6178 "" 6179{ 6180 if (TARGET_MICROMIPS) 6181 return "%*jr%:\t%0"; 6182 else 6183 return "%*j\t%0%/"; 6184} 6185 [(set_attr "type" "jump") 6186 (set_attr "mode" "none")]) 6187 6188;; A combined jump-and-move instruction, used for MIPS16 long-branch 6189;; sequences. Having a dedicated pattern is more convenient than 6190;; creating a SEQUENCE for this special case. 6191(define_insn "indirect_jump_and_restore_<mode>" 6192 [(set (pc) (match_operand:P 1 "register_operand" "d")) 6193 (set (match_operand:P 0 "register_operand" "=d") 6194 (match_operand:P 2 "register_operand" "y"))] 6195 "" 6196 "%(%<jr\t%1\;move\t%0,%2%>%)" 6197 [(set_attr "type" "multi") 6198 (set_attr "extended_mips16" "yes")]) 6199 6200(define_expand "tablejump" 6201 [(set (pc) 6202 (match_operand 0 "register_operand")) 6203 (use (label_ref (match_operand 1 "")))] 6204 "!TARGET_MIPS16_SHORT_JUMP_TABLES" 6205{ 6206 if (TARGET_GPWORD) 6207 operands[0] = expand_binop (Pmode, add_optab, operands[0], 6208 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN); 6209 else if (TARGET_RTP_PIC) 6210 { 6211 /* When generating RTP PIC, we use case table entries that are relative 6212 to the start of the function. Add the function's address to the 6213 value we loaded. */ 6214 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM); 6215 operands[0] = expand_binop (ptr_mode, add_optab, operands[0], 6216 start, 0, 0, OPTAB_WIDEN); 6217 } 6218 6219 emit_jump_insn (PMODE_INSN (gen_tablejump, (operands[0], operands[1]))); 6220 DONE; 6221}) 6222 6223(define_insn "tablejump_<mode>" 6224 [(set (pc) 6225 (match_operand:P 0 "register_operand" "d")) 6226 (use (label_ref (match_operand 1 "" "")))] 6227 "" 6228{ 6229 if (TARGET_MICROMIPS) 6230 return "%*jr%:\t%0"; 6231 else 6232 return "%*j\t%0%/"; 6233} 6234 [(set_attr "type" "jump") 6235 (set_attr "mode" "none")]) 6236 6237;; For MIPS16, we don't know whether a given jump table will use short or 6238;; word-sized offsets until late in compilation, when we are able to determine 6239;; the sizes of the insns which comprise the containing function. This 6240;; necessitates the use of the casesi rather than the tablejump pattern, since 6241;; the latter tries to calculate the index of the offset to jump through early 6242;; in compilation, i.e. at expand time, when nothing is known about the 6243;; eventual function layout. 6244 6245(define_expand "casesi" 6246 [(match_operand:SI 0 "register_operand" "") ; index to jump on 6247 (match_operand:SI 1 "const_int_operand" "") ; lower bound 6248 (match_operand:SI 2 "const_int_operand" "") ; total range 6249 (match_operand 3 "" "") ; table label 6250 (match_operand 4 "" "")] ; out of range label 6251 "TARGET_MIPS16_SHORT_JUMP_TABLES" 6252{ 6253 if (operands[1] != const0_rtx) 6254 { 6255 rtx reg = gen_reg_rtx (SImode); 6256 rtx offset = gen_int_mode (-INTVAL (operands[1]), SImode); 6257 6258 if (!arith_operand (offset, SImode)) 6259 offset = force_reg (SImode, offset); 6260 6261 emit_insn (gen_addsi3 (reg, operands[0], offset)); 6262 operands[0] = reg; 6263 } 6264 6265 if (!arith_operand (operands[0], SImode)) 6266 operands[0] = force_reg (SImode, operands[0]); 6267 6268 operands[2] = GEN_INT (INTVAL (operands[2]) + 1); 6269 6270 emit_jump_insn (PMODE_INSN (gen_casesi_internal_mips16, 6271 (operands[0], operands[2], 6272 operands[3], operands[4]))); 6273 6274 DONE; 6275}) 6276 6277(define_insn "casesi_internal_mips16_<mode>" 6278 [(set (pc) 6279 (if_then_else 6280 (leu (match_operand:SI 0 "register_operand" "d") 6281 (match_operand:SI 1 "arith_operand" "dI")) 6282 (unspec:P 6283 [(match_dup 0) 6284 (label_ref (match_operand 2 "" ""))] 6285 UNSPEC_CASESI_DISPATCH) 6286 (label_ref (match_operand 3 "" "")))) 6287 (clobber (match_scratch:P 4 "=d")) 6288 (clobber (match_scratch:P 5 "=d")) 6289 (clobber (reg:SI MIPS16_T_REGNUM))] 6290 "TARGET_MIPS16_SHORT_JUMP_TABLES" 6291{ 6292 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2]))); 6293 6294 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); 6295 6296 output_asm_insn ("sltu\t%0, %1", operands); 6297 output_asm_insn ("bteqz\t%3", operands); 6298 6299 switch (GET_MODE (diff_vec)) 6300 { 6301 case HImode: 6302 output_asm_insn ("sll\t%5, %0, 1", operands); 6303 output_asm_insn ("la\t%4, %2", operands); 6304 output_asm_insn ("<d>addu\t%5, %4, %5", operands); 6305 output_asm_insn ("lh\t%5, 0(%5)", operands); 6306 break; 6307 6308 case SImode: 6309 output_asm_insn ("sll\t%5, %0, 2", operands); 6310 output_asm_insn ("la\t%4, %2", operands); 6311 output_asm_insn ("<d>addu\t%5, %4, %5", operands); 6312 output_asm_insn ("lw\t%5, 0(%5)", operands); 6313 break; 6314 6315 default: 6316 gcc_unreachable (); 6317 } 6318 6319 output_asm_insn ("addu\t%4, %4, %5", operands); 6320 6321 return "j\t%4"; 6322} 6323 [(set_attr "insn_count" "16")]) 6324 6325;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well. 6326;; While it is possible to either pull it off the stack (in the 6327;; o32 case) or recalculate it given t9 and our target label, 6328;; it takes 3 or 4 insns to do so. 6329 6330(define_expand "builtin_setjmp_setup" 6331 [(use (match_operand 0 "register_operand"))] 6332 "TARGET_USE_GOT" 6333{ 6334 rtx addr; 6335 6336 addr = plus_constant (Pmode, operands[0], GET_MODE_SIZE (Pmode) * 3); 6337 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx); 6338 DONE; 6339}) 6340 6341;; Restore the gp that we saved above. Despite the earlier comment, it seems 6342;; that older code did recalculate the gp from $25. Continue to jump through 6343;; $25 for compatibility (we lose nothing by doing so). 6344 6345(define_expand "builtin_longjmp" 6346 [(use (match_operand 0 "register_operand"))] 6347 "TARGET_USE_GOT" 6348{ 6349 /* The elements of the buffer are, in order: */ 6350 int W = GET_MODE_SIZE (Pmode); 6351 rtx fp = gen_rtx_MEM (Pmode, operands[0]); 6352 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 1*W)); 6353 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 2*W)); 6354 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 3*W)); 6355 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); 6356 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx. 6357 The target is bound to be using $28 as the global pointer 6358 but the current function might not be. */ 6359 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM); 6360 6361 /* This bit is similar to expand_builtin_longjmp except that it 6362 restores $gp as well. */ 6363 mips_emit_move (hard_frame_pointer_rtx, fp); 6364 mips_emit_move (pv, lab); 6365 emit_stack_restore (SAVE_NONLOCAL, stack); 6366 mips_emit_move (gp, gpv); 6367 emit_use (hard_frame_pointer_rtx); 6368 emit_use (stack_pointer_rtx); 6369 emit_use (gp); 6370 emit_indirect_jump (pv); 6371 DONE; 6372}) 6373 6374;; 6375;; .................... 6376;; 6377;; Function prologue/epilogue 6378;; 6379;; .................... 6380;; 6381 6382(define_expand "prologue" 6383 [(const_int 1)] 6384 "" 6385{ 6386 mips_expand_prologue (); 6387 DONE; 6388}) 6389 6390;; Block any insns from being moved before this point, since the 6391;; profiling call to mcount can use various registers that aren't 6392;; saved or used to pass arguments. 6393 6394(define_insn "blockage" 6395 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)] 6396 "" 6397 "" 6398 [(set_attr "type" "ghost") 6399 (set_attr "mode" "none")]) 6400 6401(define_insn "probe_stack_range_<P:mode>" 6402 [(set (match_operand:P 0 "register_operand" "=d") 6403 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0") 6404 (match_operand:P 2 "register_operand" "d")] 6405 UNSPEC_PROBE_STACK_RANGE))] 6406 "" 6407 { return mips_output_probe_stack_range (operands[0], operands[2]); } 6408 [(set_attr "type" "unknown") 6409 (set_attr "can_delay" "no") 6410 (set_attr "mode" "<MODE>")]) 6411 6412(define_expand "epilogue" 6413 [(const_int 2)] 6414 "" 6415{ 6416 mips_expand_epilogue (false); 6417 DONE; 6418}) 6419 6420(define_expand "sibcall_epilogue" 6421 [(const_int 2)] 6422 "" 6423{ 6424 mips_expand_epilogue (true); 6425 DONE; 6426}) 6427 6428;; Trivial return. Make it look like a normal return insn as that 6429;; allows jump optimizations to work better. 6430 6431(define_expand "return" 6432 [(simple_return)] 6433 "mips_can_use_return_insn ()" 6434 { mips_expand_before_return (); }) 6435 6436(define_expand "simple_return" 6437 [(simple_return)] 6438 "" 6439 { mips_expand_before_return (); }) 6440 6441(define_insn "*<optab>" 6442 [(any_return)] 6443 "" 6444 { 6445 if (TARGET_MICROMIPS) 6446 return "%*jr%:\t$31"; 6447 else 6448 return "%*j\t$31%/"; 6449 } 6450 [(set_attr "type" "jump") 6451 (set_attr "mode" "none")]) 6452 6453;; Normal return. 6454 6455(define_insn "<optab>_internal" 6456 [(any_return) 6457 (use (match_operand 0 "pmode_register_operand" ""))] 6458 "" 6459{ 6460 if (TARGET_MICROMIPS) 6461 return "%*jr%:\t%0"; 6462 else 6463 return "%*j\t%0%/"; 6464} 6465 [(set_attr "type" "jump") 6466 (set_attr "mode" "none")]) 6467 6468;; Exception return. 6469(define_insn "mips_eret" 6470 [(return) 6471 (unspec_volatile [(const_int 0)] UNSPEC_ERET)] 6472 "" 6473 "eret" 6474 [(set_attr "type" "trap") 6475 (set_attr "mode" "none")]) 6476 6477;; Debug exception return. 6478(define_insn "mips_deret" 6479 [(return) 6480 (unspec_volatile [(const_int 0)] UNSPEC_DERET)] 6481 "" 6482 "deret" 6483 [(set_attr "type" "trap") 6484 (set_attr "mode" "none")]) 6485 6486;; Disable interrupts. 6487(define_insn "mips_di" 6488 [(unspec_volatile [(const_int 0)] UNSPEC_DI)] 6489 "" 6490 "di" 6491 [(set_attr "type" "trap") 6492 (set_attr "mode" "none")]) 6493 6494;; Execution hazard barrier. 6495(define_insn "mips_ehb" 6496 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)] 6497 "" 6498 "ehb" 6499 [(set_attr "type" "trap") 6500 (set_attr "mode" "none")]) 6501 6502;; Read GPR from previous shadow register set. 6503(define_insn "mips_rdpgpr" 6504 [(set (match_operand:SI 0 "register_operand" "=d") 6505 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")] 6506 UNSPEC_RDPGPR))] 6507 "" 6508 "rdpgpr\t%0,%1" 6509 [(set_attr "type" "move") 6510 (set_attr "mode" "SI")]) 6511 6512;; Move involving COP0 registers. 6513(define_insn "cop0_move" 6514 [(set (match_operand:SI 0 "register_operand" "=B,d") 6515 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")] 6516 UNSPEC_COP0))] 6517 "" 6518{ return mips_output_move (operands[0], operands[1]); } 6519 [(set_attr "type" "mtc,mfc") 6520 (set_attr "mode" "SI")]) 6521 6522;; This is used in compiling the unwind routines. 6523(define_expand "eh_return" 6524 [(use (match_operand 0 "general_operand"))] 6525 "" 6526{ 6527 if (GET_MODE (operands[0]) != word_mode) 6528 operands[0] = convert_to_mode (word_mode, operands[0], 0); 6529 if (TARGET_64BIT) 6530 emit_insn (gen_eh_set_lr_di (operands[0])); 6531 else 6532 emit_insn (gen_eh_set_lr_si (operands[0])); 6533 DONE; 6534}) 6535 6536;; Clobber the return address on the stack. We can't expand this 6537;; until we know where it will be put in the stack frame. 6538 6539(define_insn "eh_set_lr_si" 6540 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN) 6541 (clobber (match_scratch:SI 1 "=&d"))] 6542 "! TARGET_64BIT" 6543 "#") 6544 6545(define_insn "eh_set_lr_di" 6546 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN) 6547 (clobber (match_scratch:DI 1 "=&d"))] 6548 "TARGET_64BIT" 6549 "#") 6550 6551(define_split 6552 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN) 6553 (clobber (match_scratch 1))] 6554 "reload_completed" 6555 [(const_int 0)] 6556{ 6557 mips_set_return_address (operands[0], operands[1]); 6558 DONE; 6559}) 6560 6561(define_expand "exception_receiver" 6562 [(const_int 0)] 6563 "TARGET_USE_GOT" 6564{ 6565 /* See the comment above load_call<mode> for details. */ 6566 emit_insn (gen_set_got_version ()); 6567 6568 /* If we have a call-clobbered $gp, restore it from its save slot. */ 6569 if (HAVE_restore_gp_si) 6570 emit_insn (gen_restore_gp_si ()); 6571 else if (HAVE_restore_gp_di) 6572 emit_insn (gen_restore_gp_di ()); 6573 DONE; 6574}) 6575 6576(define_expand "nonlocal_goto_receiver" 6577 [(const_int 0)] 6578 "TARGET_USE_GOT" 6579{ 6580 /* See the comment above load_call<mode> for details. */ 6581 emit_insn (gen_set_got_version ()); 6582 DONE; 6583}) 6584 6585;; Restore $gp from its .cprestore stack slot. The instruction remains 6586;; volatile until all uses of $28 are exposed. 6587(define_insn_and_split "restore_gp_<mode>" 6588 [(set (reg:P 28) 6589 (unspec_volatile:P [(const_int 0)] UNSPEC_RESTORE_GP)) 6590 (clobber (match_scratch:P 0 "=&d"))] 6591 "TARGET_CALL_CLOBBERED_GP" 6592 "#" 6593 "&& epilogue_completed" 6594 [(const_int 0)] 6595{ 6596 mips_restore_gp_from_cprestore_slot (operands[0]); 6597 DONE; 6598} 6599 [(set_attr "type" "ghost")]) 6600 6601;; Move between $gp and its register save slot. 6602(define_insn_and_split "move_gp<mode>" 6603 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,m") 6604 (unspec:GPR [(match_operand:GPR 1 "move_operand" "m,d")] 6605 UNSPEC_MOVE_GP))] 6606 "" 6607 { return mips_must_initialize_gp_p () ? "#" : ""; } 6608 "mips_must_initialize_gp_p ()" 6609 [(const_int 0)] 6610{ 6611 mips_emit_move (operands[0], operands[1]); 6612 DONE; 6613} 6614 [(set_attr "type" "ghost")]) 6615 6616;; 6617;; .................... 6618;; 6619;; FUNCTION CALLS 6620;; 6621;; .................... 6622 6623;; Instructions to load a call address from the GOT. The address might 6624;; point to a function or to a lazy binding stub. In the latter case, 6625;; the stub will use the dynamic linker to resolve the function, which 6626;; in turn will change the GOT entry to point to the function's real 6627;; address. 6628;; 6629;; This means that every call, even pure and constant ones, can 6630;; potentially modify the GOT entry. And once a stub has been called, 6631;; we must not call it again. 6632;; 6633;; We represent this restriction using an imaginary, fixed, call-saved 6634;; register called GOT_VERSION_REGNUM. The idea is to make the register 6635;; live throughout the function and to change its value after every 6636;; potential call site. This stops any rtx value that uses the register 6637;; from being computed before an earlier call. To do this, we: 6638;; 6639;; - Ensure that the register is live on entry to the function, 6640;; so that it is never thought to be used uninitalized. 6641;; 6642;; - Ensure that the register is live on exit from the function, 6643;; so that it is live throughout. 6644;; 6645;; - Make each call (lazily-bound or not) use the current value 6646;; of GOT_VERSION_REGNUM, so that updates of the register are 6647;; not moved across call boundaries. 6648;; 6649;; - Add "ghost" definitions of the register to the beginning of 6650;; blocks reached by EH and ABNORMAL_CALL edges, because those 6651;; edges may involve calls that normal paths don't. (E.g. the 6652;; unwinding code that handles a non-call exception may change 6653;; lazily-bound GOT entries.) We do this by making the 6654;; exception_receiver and nonlocal_goto_receiver expanders emit 6655;; a set_got_version instruction. 6656;; 6657;; - After each call (lazily-bound or not), use a "ghost" 6658;; update_got_version instruction to change the register's value. 6659;; This instruction mimics the _possible_ effect of the dynamic 6660;; resolver during the call and it remains live even if the call 6661;; itself becomes dead. 6662;; 6663;; - Leave GOT_VERSION_REGNUM out of all register classes. 6664;; The register is therefore not a valid register_operand 6665;; and cannot be moved to or from other registers. 6666 6667(define_insn "load_call<mode>" 6668 [(set (match_operand:P 0 "register_operand" "=d") 6669 (unspec:P [(match_operand:P 1 "register_operand" "d") 6670 (match_operand:P 2 "immediate_operand" "") 6671 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))] 6672 "TARGET_USE_GOT" 6673 "<load>\t%0,%R2(%1)" 6674 [(set_attr "got" "load") 6675 (set_attr "mode" "<MODE>")]) 6676 6677(define_insn "set_got_version" 6678 [(set (reg:SI GOT_VERSION_REGNUM) 6679 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))] 6680 "TARGET_USE_GOT" 6681 "" 6682 [(set_attr "type" "ghost")]) 6683 6684(define_insn "update_got_version" 6685 [(set (reg:SI GOT_VERSION_REGNUM) 6686 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))] 6687 "TARGET_USE_GOT" 6688 "" 6689 [(set_attr "type" "ghost")]) 6690 6691;; Sibling calls. All these patterns use jump instructions. 6692 6693;; If TARGET_SIBCALLS, call_insn_operand will only accept constant 6694;; addresses if a direct jump is acceptable. Since the 'S' constraint 6695;; is defined in terms of call_insn_operand, the same is true of the 6696;; constraints. 6697 6698;; When we use an indirect jump, we need a register that will be 6699;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces 6700;; us to use $25 for this purpose -- and $25 is never clobbered by the 6701;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG 6702;; as well. 6703 6704(define_expand "sibcall" 6705 [(parallel [(call (match_operand 0 "") 6706 (match_operand 1 "")) 6707 (use (match_operand 2 "")) ;; next_arg_reg 6708 (use (match_operand 3 ""))])] ;; struct_value_size_rtx 6709 "TARGET_SIBCALLS" 6710{ 6711 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0), 6712 operands[1], operands[2], false); 6713 DONE; 6714}) 6715 6716(define_insn "sibcall_internal" 6717 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S")) 6718 (match_operand 1 "" ""))] 6719 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)" 6720{ 6721 if (TARGET_MICROMIPS) 6722 return MICROMIPS_J ("j", operands, 0); 6723 else 6724 return MIPS_CALL ("j", operands, 0, 1); 6725} 6726 [(set_attr "jal" "indirect,direct") 6727 (set_attr "jal_macro" "no")]) 6728 6729(define_expand "sibcall_value" 6730 [(parallel [(set (match_operand 0 "") 6731 (call (match_operand 1 "") 6732 (match_operand 2 ""))) 6733 (use (match_operand 3 ""))])] ;; next_arg_reg 6734 "TARGET_SIBCALLS" 6735{ 6736 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0), 6737 operands[2], operands[3], false); 6738 DONE; 6739}) 6740 6741(define_insn "sibcall_value_internal" 6742 [(set (match_operand 0 "register_operand" "") 6743 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S")) 6744 (match_operand 2 "" "")))] 6745 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)" 6746{ 6747 if (TARGET_MICROMIPS) 6748 return MICROMIPS_J ("j", operands, 1); 6749 else 6750 return MIPS_CALL ("j", operands, 1, 2); 6751} 6752 [(set_attr "jal" "indirect,direct") 6753 (set_attr "jal_macro" "no")]) 6754 6755(define_insn "sibcall_value_multiple_internal" 6756 [(set (match_operand 0 "register_operand" "") 6757 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S")) 6758 (match_operand 2 "" ""))) 6759 (set (match_operand 3 "register_operand" "") 6760 (call (mem:SI (match_dup 1)) 6761 (match_dup 2)))] 6762 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)" 6763{ 6764 if (TARGET_MICROMIPS) 6765 return MICROMIPS_J ("j", operands, 1); 6766 else 6767 return MIPS_CALL ("j", operands, 1, 2); 6768} 6769 [(set_attr "jal" "indirect,direct") 6770 (set_attr "jal_macro" "no")]) 6771 6772(define_expand "call" 6773 [(parallel [(call (match_operand 0 "") 6774 (match_operand 1 "")) 6775 (use (match_operand 2 "")) ;; next_arg_reg 6776 (use (match_operand 3 ""))])] ;; struct_value_size_rtx 6777 "" 6778{ 6779 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0), 6780 operands[1], operands[2], false); 6781 DONE; 6782}) 6783 6784;; This instruction directly corresponds to an assembly-language "jal". 6785;; There are four cases: 6786;; 6787;; - -mno-abicalls: 6788;; Both symbolic and register destinations are OK. The pattern 6789;; always expands to a single mips instruction. 6790;; 6791;; - -mabicalls/-mno-explicit-relocs: 6792;; Again, both symbolic and register destinations are OK. 6793;; The call is treated as a multi-instruction black box. 6794;; 6795;; - -mabicalls/-mexplicit-relocs with n32 or n64: 6796;; Only "jal $25" is allowed. This expands to a single "jalr $25" 6797;; instruction. 6798;; 6799;; - -mabicalls/-mexplicit-relocs with o32 or o64: 6800;; Only "jal $25" is allowed. The call is actually two instructions: 6801;; "jalr $25" followed by an insn to reload $gp. 6802;; 6803;; In the last case, we can generate the individual instructions with 6804;; a define_split. There are several things to be wary of: 6805;; 6806;; - We can't expose the load of $gp before reload. If we did, 6807;; it might get removed as dead, but reload can introduce new 6808;; uses of $gp by rematerializing constants. 6809;; 6810;; - We shouldn't restore $gp after calls that never return. 6811;; It isn't valid to insert instructions between a noreturn 6812;; call and the following barrier. 6813;; 6814;; - The splitter deliberately changes the liveness of $gp. The unsplit 6815;; instruction preserves $gp and so have no effect on its liveness. 6816;; But once we generate the separate insns, it becomes obvious that 6817;; $gp is not live on entry to the call. 6818;; 6819(define_insn_and_split "call_internal" 6820 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S")) 6821 (match_operand 1 "" "")) 6822 (clobber (reg:SI RETURN_ADDR_REGNUM))] 6823 "" 6824 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, 1); } 6825 "reload_completed && TARGET_SPLIT_CALLS" 6826 [(const_int 0)] 6827{ 6828 mips_split_call (curr_insn, gen_call_split (operands[0], operands[1])); 6829 DONE; 6830} 6831 [(set_attr "jal" "indirect,direct")]) 6832 6833(define_insn "call_split" 6834 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S")) 6835 (match_operand 1 "" "")) 6836 (clobber (reg:SI RETURN_ADDR_REGNUM)) 6837 (clobber (reg:SI 28))] 6838 "TARGET_SPLIT_CALLS" 6839 { return MIPS_CALL ("jal", operands, 0, 1); } 6840 [(set_attr "jal" "indirect,direct") 6841 (set_attr "jal_macro" "no")]) 6842 6843;; A pattern for calls that must be made directly. It is used for 6844;; MIPS16 calls that the linker may need to redirect to a hard-float 6845;; stub; the linker relies on the call relocation type to detect when 6846;; such redirection is needed. 6847(define_insn_and_split "call_internal_direct" 6848 [(call (mem:SI (match_operand 0 "const_call_insn_operand")) 6849 (match_operand 1)) 6850 (const_int 1) 6851 (clobber (reg:SI RETURN_ADDR_REGNUM))] 6852 "" 6853 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, -1); } 6854 "reload_completed && TARGET_SPLIT_CALLS" 6855 [(const_int 0)] 6856{ 6857 mips_split_call (curr_insn, 6858 gen_call_direct_split (operands[0], operands[1])); 6859 DONE; 6860} 6861 [(set_attr "jal" "direct")]) 6862 6863(define_insn "call_direct_split" 6864 [(call (mem:SI (match_operand 0 "const_call_insn_operand")) 6865 (match_operand 1)) 6866 (const_int 1) 6867 (clobber (reg:SI RETURN_ADDR_REGNUM)) 6868 (clobber (reg:SI 28))] 6869 "TARGET_SPLIT_CALLS" 6870 { return MIPS_CALL ("jal", operands, 0, -1); } 6871 [(set_attr "jal" "direct") 6872 (set_attr "jal_macro" "no")]) 6873 6874(define_expand "call_value" 6875 [(parallel [(set (match_operand 0 "") 6876 (call (match_operand 1 "") 6877 (match_operand 2 ""))) 6878 (use (match_operand 3 ""))])] ;; next_arg_reg 6879 "" 6880{ 6881 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0), 6882 operands[2], operands[3], false); 6883 DONE; 6884}) 6885 6886;; See comment for call_internal. 6887(define_insn_and_split "call_value_internal" 6888 [(set (match_operand 0 "register_operand" "") 6889 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S")) 6890 (match_operand 2 "" ""))) 6891 (clobber (reg:SI RETURN_ADDR_REGNUM))] 6892 "" 6893 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); } 6894 "reload_completed && TARGET_SPLIT_CALLS" 6895 [(const_int 0)] 6896{ 6897 mips_split_call (curr_insn, 6898 gen_call_value_split (operands[0], operands[1], 6899 operands[2])); 6900 DONE; 6901} 6902 [(set_attr "jal" "indirect,direct")]) 6903 6904(define_insn "call_value_split" 6905 [(set (match_operand 0 "register_operand" "") 6906 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S")) 6907 (match_operand 2 "" ""))) 6908 (clobber (reg:SI RETURN_ADDR_REGNUM)) 6909 (clobber (reg:SI 28))] 6910 "TARGET_SPLIT_CALLS" 6911 { return MIPS_CALL ("jal", operands, 1, 2); } 6912 [(set_attr "jal" "indirect,direct") 6913 (set_attr "jal_macro" "no")]) 6914 6915;; See call_internal_direct. 6916(define_insn_and_split "call_value_internal_direct" 6917 [(set (match_operand 0 "register_operand") 6918 (call (mem:SI (match_operand 1 "const_call_insn_operand")) 6919 (match_operand 2))) 6920 (const_int 1) 6921 (clobber (reg:SI RETURN_ADDR_REGNUM))] 6922 "" 6923 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, -1); } 6924 "reload_completed && TARGET_SPLIT_CALLS" 6925 [(const_int 0)] 6926{ 6927 mips_split_call (curr_insn, 6928 gen_call_value_direct_split (operands[0], operands[1], 6929 operands[2])); 6930 DONE; 6931} 6932 [(set_attr "jal" "direct")]) 6933 6934(define_insn "call_value_direct_split" 6935 [(set (match_operand 0 "register_operand") 6936 (call (mem:SI (match_operand 1 "const_call_insn_operand")) 6937 (match_operand 2))) 6938 (const_int 1) 6939 (clobber (reg:SI RETURN_ADDR_REGNUM)) 6940 (clobber (reg:SI 28))] 6941 "TARGET_SPLIT_CALLS" 6942 { return MIPS_CALL ("jal", operands, 1, -1); } 6943 [(set_attr "jal" "direct") 6944 (set_attr "jal_macro" "no")]) 6945 6946;; See comment for call_internal. 6947(define_insn_and_split "call_value_multiple_internal" 6948 [(set (match_operand 0 "register_operand" "") 6949 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S")) 6950 (match_operand 2 "" ""))) 6951 (set (match_operand 3 "register_operand" "") 6952 (call (mem:SI (match_dup 1)) 6953 (match_dup 2))) 6954 (clobber (reg:SI RETURN_ADDR_REGNUM))] 6955 "" 6956 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); } 6957 "reload_completed && TARGET_SPLIT_CALLS" 6958 [(const_int 0)] 6959{ 6960 mips_split_call (curr_insn, 6961 gen_call_value_multiple_split (operands[0], operands[1], 6962 operands[2], operands[3])); 6963 DONE; 6964} 6965 [(set_attr "jal" "indirect,direct")]) 6966 6967(define_insn "call_value_multiple_split" 6968 [(set (match_operand 0 "register_operand" "") 6969 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S")) 6970 (match_operand 2 "" ""))) 6971 (set (match_operand 3 "register_operand" "") 6972 (call (mem:SI (match_dup 1)) 6973 (match_dup 2))) 6974 (clobber (reg:SI RETURN_ADDR_REGNUM)) 6975 (clobber (reg:SI 28))] 6976 "TARGET_SPLIT_CALLS" 6977 { return MIPS_CALL ("jal", operands, 1, 2); } 6978 [(set_attr "jal" "indirect,direct") 6979 (set_attr "jal_macro" "no")]) 6980 6981;; Call subroutine returning any type. 6982 6983(define_expand "untyped_call" 6984 [(parallel [(call (match_operand 0 "") 6985 (const_int 0)) 6986 (match_operand 1 "") 6987 (match_operand 2 "")])] 6988 "" 6989{ 6990 int i; 6991 6992 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx)); 6993 6994 for (i = 0; i < XVECLEN (operands[2], 0); i++) 6995 { 6996 rtx set = XVECEXP (operands[2], 0, i); 6997 mips_emit_move (SET_DEST (set), SET_SRC (set)); 6998 } 6999 7000 emit_insn (gen_blockage ()); 7001 DONE; 7002}) 7003 7004;; 7005;; .................... 7006;; 7007;; MISC. 7008;; 7009;; .................... 7010;; 7011 7012 7013(define_insn "prefetch" 7014 [(prefetch (match_operand:QI 0 "address_operand" "ZD") 7015 (match_operand 1 "const_int_operand" "n") 7016 (match_operand 2 "const_int_operand" "n"))] 7017 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS" 7018{ 7019 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A) 7020 { 7021 /* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching. */ 7022 if (TARGET_64BIT) 7023 return "ld\t$0,%a0"; 7024 else 7025 return "lw\t$0,%a0"; 7026 } 7027 operands[1] = mips_prefetch_cookie (operands[1], operands[2]); 7028 return "pref\t%1,%a0"; 7029} 7030 [(set_attr "type" "prefetch")]) 7031 7032(define_insn "*prefetch_indexed_<mode>" 7033 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d") 7034 (match_operand:P 1 "register_operand" "d")) 7035 (match_operand 2 "const_int_operand" "n") 7036 (match_operand 3 "const_int_operand" "n"))] 7037 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" 7038{ 7039 operands[2] = mips_prefetch_cookie (operands[2], operands[3]); 7040 return "prefx\t%2,%1(%0)"; 7041} 7042 [(set_attr "type" "prefetchx")]) 7043 7044(define_insn "nop" 7045 [(const_int 0)] 7046 "" 7047 "%(nop%)" 7048 [(set_attr "type" "nop") 7049 (set_attr "mode" "none")]) 7050 7051;; Like nop, but commented out when outside a .set noreorder block. 7052(define_insn "hazard_nop" 7053 [(const_int 1)] 7054 "" 7055 { 7056 if (mips_noreorder.nesting_level > 0) 7057 return "nop"; 7058 else 7059 return "#nop"; 7060 } 7061 [(set_attr "type" "nop")]) 7062 7063;; MIPS4 Conditional move instructions. 7064 7065(define_insn "*mov<GPR:mode>_on_<MOVECC:mode>" 7066 [(set (match_operand:GPR 0 "register_operand" "=d,d") 7067 (if_then_else:GPR 7068 (match_operator 4 "equality_operator" 7069 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>") 7070 (const_int 0)]) 7071 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0") 7072 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))] 7073 "ISA_HAS_CONDMOVE" 7074 "@ 7075 mov%T4\t%0,%z2,%1 7076 mov%t4\t%0,%z3,%1" 7077 [(set_attr "type" "condmove") 7078 (set_attr "mode" "<GPR:MODE>")]) 7079 7080(define_insn "*mov<GPR:mode>_on_<GPR2:mode>_ne" 7081 [(set (match_operand:GPR 0 "register_operand" "=d,d") 7082 (if_then_else:GPR 7083 (match_operand:GPR2 1 "register_operand" "<GPR2:reg>,<GPR2:reg>") 7084 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0") 7085 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))] 7086 "ISA_HAS_CONDMOVE" 7087 "@ 7088 movn\t%0,%z2,%1 7089 movz\t%0,%z3,%1" 7090 [(set_attr "type" "condmove") 7091 (set_attr "mode" "<GPR:MODE>")]) 7092 7093(define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>" 7094 [(set (match_operand:SCALARF 0 "register_operand" "=f,f") 7095 (if_then_else:SCALARF 7096 (match_operator 4 "equality_operator" 7097 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>") 7098 (const_int 0)]) 7099 (match_operand:SCALARF 2 "register_operand" "f,0") 7100 (match_operand:SCALARF 3 "register_operand" "0,f")))] 7101 "ISA_HAS_FP_CONDMOVE" 7102 "@ 7103 mov%T4.<fmt>\t%0,%2,%1 7104 mov%t4.<fmt>\t%0,%3,%1" 7105 [(set_attr "type" "condmove") 7106 (set_attr "mode" "<SCALARF:MODE>")]) 7107 7108(define_insn "*sel<code><GPR:mode>_using_<GPR2:mode>" 7109 [(set (match_operand:GPR 0 "register_operand" "=d,d") 7110 (if_then_else:GPR 7111 (equality_op:GPR2 (match_operand:GPR2 1 "register_operand" "d,d") 7112 (const_int 0)) 7113 (match_operand:GPR 2 "reg_or_0_operand" "d,J") 7114 (match_operand:GPR 3 "reg_or_0_operand" "J,d")))] 7115 "ISA_HAS_SEL 7116 && (register_operand (operands[2], <GPR:MODE>mode) 7117 != register_operand (operands[3], <GPR:MODE>mode))" 7118 "@ 7119 <sel>\t%0,%2,%1 7120 <selinv>\t%0,%3,%1" 7121 [(set_attr "type" "condmove") 7122 (set_attr "mode" "<GPR:MODE>")]) 7123 7124;; sel.fmt copies the 3rd argument when the 1st is non-zero and the 2nd 7125;; argument if the 1st is zero. This means operand 2 and 3 are 7126;; inverted in the instruction. 7127 7128(define_insn "*sel<mode>" 7129 [(set (match_operand:SCALARF 0 "register_operand" "=f,f,f") 7130 (if_then_else:SCALARF 7131 (ne:CCF (match_operand:CCF 1 "register_operand" "0,f,f") 7132 (const_int 0)) 7133 (match_operand:SCALARF 2 "reg_or_0_operand" "f,G,f") 7134 (match_operand:SCALARF 3 "reg_or_0_operand" "f,f,G")))] 7135 "ISA_HAS_SEL && ISA_HAS_CCF" 7136 "@ 7137 sel.<fmt>\t%0,%3,%2 7138 seleqz.<fmt>\t%0,%3,%1 7139 selnez.<fmt>\t%0,%2,%1" 7140 [(set_attr "type" "condmove") 7141 (set_attr "mode" "<SCALARF:MODE>")]) 7142 7143;; These are the main define_expand's used to make conditional moves. 7144 7145(define_expand "mov<mode>cc" 7146 [(set (match_dup 4) (match_operand 1 "comparison_operator")) 7147 (set (match_operand:GPR 0 "register_operand") 7148 (if_then_else:GPR (match_dup 5) 7149 (match_operand:GPR 2 "reg_or_0_operand") 7150 (match_operand:GPR 3 "reg_or_0_operand")))] 7151 "ISA_HAS_CONDMOVE || ISA_HAS_SEL" 7152{ 7153 if (!ISA_HAS_FP_CONDMOVE 7154 && !INTEGRAL_MODE_P (GET_MODE (XEXP (operands[1], 0)))) 7155 FAIL; 7156 7157 mips_expand_conditional_move (operands); 7158 DONE; 7159}) 7160 7161(define_expand "mov<mode>cc" 7162 [(set (match_dup 4) (match_operand 1 "comparison_operator")) 7163 (set (match_operand:SCALARF 0 "register_operand") 7164 (if_then_else:SCALARF (match_dup 5) 7165 (match_operand:SCALARF 2 "reg_or_0_operand") 7166 (match_operand:SCALARF 3 "reg_or_0_operand")))] 7167 "ISA_HAS_FP_CONDMOVE 7168 || (ISA_HAS_SEL && ISA_HAS_CCF)" 7169{ 7170 if (ISA_HAS_SEL && !FLOAT_MODE_P (GET_MODE (XEXP (operands[1], 0)))) 7171 FAIL; 7172 7173 /* Workaround an LRA bug which means that tied operands in the sel.fmt 7174 pattern lead to the double precision destination of sel.d getting 7175 reloaded with the full register file usable and the restrictions on 7176 whether the CCFmode input can be used in odd-numbered single-precision 7177 registers are ignored. For consistency reasons the CCF mode values 7178 must be guaranteed to only exist in the even-registers because of 7179 the unusual duality between single and double precision values. */ 7180 if (ISA_HAS_SEL && <MODE>mode == DFmode 7181 && (!TARGET_ODD_SPREG || TARGET_FLOATXX)) 7182 FAIL; 7183 7184 mips_expand_conditional_move (operands); 7185 DONE; 7186}) 7187 7188;; 7189;; .................... 7190;; 7191;; mips16 inline constant tables 7192;; 7193;; .................... 7194;; 7195 7196(define_insn "consttable_tls_reloc" 7197 [(unspec_volatile [(match_operand 0 "tls_reloc_operand" "") 7198 (match_operand 1 "const_int_operand" "")] 7199 UNSPEC_CONSTTABLE_INT)] 7200 "TARGET_MIPS16_PCREL_LOADS" 7201 { return mips_output_tls_reloc_directive (&operands[0]); } 7202 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))]) 7203 7204(define_insn "consttable_int" 7205 [(unspec_volatile [(match_operand 0 "consttable_operand" "") 7206 (match_operand 1 "const_int_operand" "")] 7207 UNSPEC_CONSTTABLE_INT)] 7208 "TARGET_MIPS16" 7209{ 7210 assemble_integer (mips_strip_unspec_address (operands[0]), 7211 INTVAL (operands[1]), 7212 BITS_PER_UNIT * INTVAL (operands[1]), 1); 7213 return ""; 7214} 7215 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))]) 7216 7217(define_insn "consttable_float" 7218 [(unspec_volatile [(match_operand 0 "consttable_operand" "")] 7219 UNSPEC_CONSTTABLE_FLOAT)] 7220 "TARGET_MIPS16" 7221{ 7222 REAL_VALUE_TYPE d; 7223 7224 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE); 7225 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]); 7226 assemble_real (d, GET_MODE (operands[0]), 7227 GET_MODE_BITSIZE (GET_MODE (operands[0]))); 7228 return ""; 7229} 7230 [(set (attr "length") 7231 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))]) 7232 7233(define_insn "align" 7234 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)] 7235 "" 7236 ".align\t%0" 7237 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))]) 7238 7239(define_split 7240 [(match_operand 0 "small_data_pattern")] 7241 "reload_completed" 7242 [(match_dup 0)] 7243 { operands[0] = mips_rewrite_small_data (operands[0]); }) 7244 7245;; 7246;; .................... 7247;; 7248;; MIPS16e Save/Restore 7249;; 7250;; .................... 7251;; 7252 7253(define_insn "*mips16e_save_restore" 7254 [(match_parallel 0 "" 7255 [(set (match_operand:SI 1 "register_operand") 7256 (plus:SI (match_dup 1) 7257 (match_operand:SI 2 "const_int_operand")))])] 7258 "operands[1] == stack_pointer_rtx 7259 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)" 7260 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); } 7261 [(set_attr "type" "arith") 7262 (set_attr "extended_mips16" "yes")]) 7263 7264;; Thread-Local Storage 7265 7266;; The TLS base pointer is accessed via "rdhwr $3, $29". No current 7267;; MIPS architecture defines this register, and no current 7268;; implementation provides it; instead, any OS which supports TLS is 7269;; expected to trap and emulate this instruction. rdhwr is part of the 7270;; MIPS 32r2 specification, but we use it on any architecture because 7271;; we expect it to be emulated. Use .set to force the assembler to 7272;; accept it. 7273;; 7274;; We do not use a constraint to force the destination to be $3 7275;; because $3 can appear explicitly as a function return value. 7276;; If we leave the use of $3 implicit in the constraints until 7277;; reload, we may end up making a $3 return value live across 7278;; the instruction, leading to a spill failure when reloading it. 7279(define_insn_and_split "tls_get_tp_<mode>" 7280 [(set (match_operand:P 0 "register_operand" "=d") 7281 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP)) 7282 (clobber (reg:P TLS_GET_TP_REGNUM))] 7283 "HAVE_AS_TLS && !TARGET_MIPS16" 7284 "#" 7285 "&& reload_completed" 7286 [(set (reg:P TLS_GET_TP_REGNUM) 7287 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP)) 7288 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))] 7289 "" 7290 [(set_attr "type" "unknown") 7291 (set_attr "mode" "<MODE>") 7292 (set_attr "insn_count" "2")]) 7293 7294(define_insn "*tls_get_tp_<mode>_split" 7295 [(set (reg:P TLS_GET_TP_REGNUM) 7296 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))] 7297 "HAVE_AS_TLS && !TARGET_MIPS16" 7298 { 7299 if (mips_isa_rev >= 2) 7300 return "rdhwr\t$3,$29"; 7301 7302 return ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"; 7303 } 7304 [(set_attr "type" "unknown") 7305 ; Since rdhwr always generates a trap for now, putting it in a delay 7306 ; slot would make the kernel's emulation of it much slower. 7307 (set_attr "can_delay" "no") 7308 (set_attr "mode" "<MODE>")]) 7309 7310;; In MIPS16 mode, the TLS base pointer is accessed by a 7311;; libgcc helper function __mips16_rdhwr(), as 'rdhwr' is not 7312;; accessible in MIPS16. 7313;; 7314;; This is not represented as a call insn, to avoid the 7315;; unnecesarry clobbering of caller-save registers by a 7316;; function consisting only of: "rdhwr $3,$29; j $31; nop;" 7317;; 7318;; A $25 clobber is added to cater for a $25 load stub added by the 7319;; linker to __mips16_rdhwr when the call is made from non-PIC code. 7320 7321(define_insn_and_split "tls_get_tp_mips16_<mode>" 7322 [(set (match_operand:P 0 "register_operand" "=d") 7323 (unspec:P [(match_operand:P 1 "call_insn_operand" "dS")] 7324 UNSPEC_TLS_GET_TP)) 7325 (clobber (reg:P TLS_GET_TP_REGNUM)) 7326 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM)) 7327 (clobber (reg:P RETURN_ADDR_REGNUM))] 7328 "HAVE_AS_TLS && TARGET_MIPS16" 7329 "#" 7330 "&& reload_completed" 7331 [(parallel [(set (reg:P TLS_GET_TP_REGNUM) 7332 (unspec:P [(match_dup 1)] UNSPEC_TLS_GET_TP)) 7333 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM)) 7334 (clobber (reg:P RETURN_ADDR_REGNUM))]) 7335 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))] 7336 "" 7337 [(set_attr "type" "multi") 7338 (set_attr "insn_count" "4") 7339 (set_attr "mode" "<MODE>")]) 7340 7341(define_insn "*tls_get_tp_mips16_call_<mode>" 7342 [(set (reg:P TLS_GET_TP_REGNUM) 7343 (unspec:P [(match_operand:P 0 "call_insn_operand" "dS")] 7344 UNSPEC_TLS_GET_TP)) 7345 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM)) 7346 (clobber (reg:P RETURN_ADDR_REGNUM))] 7347 "HAVE_AS_TLS && TARGET_MIPS16" 7348 { return MIPS_CALL ("jal", operands, 0, -1); } 7349 [(set_attr "type" "call") 7350 (set_attr "insn_count" "3") 7351 (set_attr "mode" "<MODE>")]) 7352 7353;; Named pattern for expanding thread pointer reference. 7354(define_expand "get_thread_pointer<mode>" 7355 [(match_operand:P 0 "register_operand" "=d")] 7356 "HAVE_AS_TLS" 7357{ 7358 mips_expand_thread_pointer (operands[0]); 7359 DONE; 7360}) 7361 7362;; __builtin_mips_get_fcsr: move the FCSR into operand 0. 7363(define_expand "mips_get_fcsr" 7364 [(set (match_operand:SI 0 "register_operand") 7365 (unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))] 7366 "TARGET_HARD_FLOAT_ABI" 7367{ 7368 if (TARGET_MIPS16) 7369 { 7370 mips16_expand_get_fcsr (operands[0]); 7371 DONE; 7372 } 7373}) 7374 7375(define_insn "*mips_get_fcsr" 7376 [(set (match_operand:SI 0 "register_operand" "=d") 7377 (unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))] 7378 "TARGET_HARD_FLOAT" 7379 "cfc1\t%0,$31") 7380 7381;; See tls_get_tp_mips16_<mode> for why this form is used. 7382(define_insn "mips_get_fcsr_mips16_<mode>" 7383 [(set (reg:SI GET_FCSR_REGNUM) 7384 (unspec:SI [(match_operand:P 0 "call_insn_operand" "dS")] 7385 UNSPEC_GET_FCSR)) 7386 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM)) 7387 (clobber (reg:P RETURN_ADDR_REGNUM))] 7388 "TARGET_HARD_FLOAT_ABI && TARGET_MIPS16" 7389 { return MIPS_CALL ("jal", operands, 0, -1); } 7390 [(set_attr "type" "call") 7391 (set_attr "insn_count" "3")]) 7392 7393;; __builtin_mips_set_fcsr: move operand 0 into the FCSR. 7394(define_expand "mips_set_fcsr" 7395 [(unspec_volatile [(match_operand:SI 0 "register_operand")] 7396 UNSPEC_SET_FCSR)] 7397 "TARGET_HARD_FLOAT_ABI" 7398{ 7399 if (TARGET_MIPS16) 7400 { 7401 mips16_expand_set_fcsr (operands[0]); 7402 DONE; 7403 } 7404}) 7405 7406(define_insn "*mips_set_fcsr" 7407 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] 7408 UNSPEC_SET_FCSR)] 7409 "TARGET_HARD_FLOAT" 7410 "ctc1\t%0,$31") 7411 7412;; See tls_get_tp_mips16_<mode> for why this form is used. 7413(define_insn "mips_set_fcsr_mips16_<mode>" 7414 [(unspec_volatile:SI [(match_operand:P 0 "call_insn_operand" "dS") 7415 (reg:SI SET_FCSR_REGNUM)] UNSPEC_SET_FCSR) 7416 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM)) 7417 (clobber (reg:P RETURN_ADDR_REGNUM))] 7418 "TARGET_HARD_FLOAT_ABI && TARGET_MIPS16" 7419 { return MIPS_CALL ("jal", operands, 0, -1); } 7420 [(set_attr "type" "call") 7421 (set_attr "insn_count" "3")]) 7422 7423;; Synchronization instructions. 7424 7425(include "sync.md") 7426 7427; The MIPS Paired-Single Floating Point and MIPS-3D Instructions. 7428 7429(include "mips-ps-3d.md") 7430 7431; The MIPS DSP Instructions. 7432 7433(include "mips-dsp.md") 7434 7435; The MIPS DSP REV 2 Instructions. 7436 7437(include "mips-dspr2.md") 7438 7439; MIPS fixed-point instructions. 7440(include "mips-fixed.md") 7441 7442; microMIPS patterns. 7443(include "micromips.md") 7444 7445; ST-Microelectronics Loongson-2E/2F-specific patterns. 7446(include "loongson.md") 7447 7448(define_c_enum "unspec" [ 7449 UNSPEC_ADDRESS_FIRST 7450]) 7451