1; Options for the IA-32 and AMD64 ports of the compiler.
2
3; Copyright (C) 2005-2015 Free Software Foundation, Inc.
4;
5; This file is part of GCC.
6;
7; GCC is free software; you can redistribute it and/or modify it under
8; the terms of the GNU General Public License as published by the Free
9; Software Foundation; either version 3, or (at your option) any later
10; version.
11;
12; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
15; for more details.
16;
17; You should have received a copy of the GNU General Public License
18; along with GCC; see the file COPYING3.  If not see
19; <http://www.gnu.org/licenses/>.
20
21HeaderInclude
22config/i386/i386-opts.h
23
24; Bit flags that specify the ISA we are compiling for.
25Variable
26HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT
27
28; A mask of ix86_isa_flags that includes bit X if X was set or cleared
29; on the command line.
30Variable
31HOST_WIDE_INT ix86_isa_flags_explicit
32
33TargetVariable
34int recip_mask = RECIP_MASK_DEFAULT
35
36Variable
37int recip_mask_explicit
38
39TargetSave
40int x_recip_mask_explicit
41
42;; Definitions to add to the cl_target_option structure
43;; -march= processor
44TargetSave
45unsigned char arch
46
47;; -mtune= processor
48TargetSave
49unsigned char tune
50
51;; -march= processor-string
52TargetSave
53const char *x_ix86_arch_string
54
55;; -mtune= processor-string
56TargetSave
57const char *x_ix86_tune_string
58
59;; CPU schedule model
60TargetSave
61unsigned char schedule
62
63;; True if processor has SSE prefetch instruction.
64TargetSave
65unsigned char prefetch_sse
66
67;; branch cost
68TargetSave
69unsigned char branch_cost
70
71;; which flags were passed by the user
72TargetSave
73HOST_WIDE_INT x_ix86_isa_flags_explicit
74
75;; which flags were passed by the user
76Variable
77int ix86_target_flags_explicit
78
79;; which flags were passed by the user
80TargetSave
81HOST_WIDE_INT x_ix86_target_flags_explicit
82
83;; whether -mtune was not specified
84TargetSave
85unsigned char tune_defaulted
86
87;; whether -march was specified
88TargetSave
89unsigned char arch_specified
90
91;; -mcmodel= model
92TargetSave
93enum cmodel x_ix86_cmodel
94
95;; -mabi=
96TargetSave
97enum calling_abi x_ix86_abi
98
99;; -masm=
100TargetSave
101enum asm_dialect x_ix86_asm_dialect
102
103;; -mbranch-cost=
104TargetSave
105int x_ix86_branch_cost
106
107;; -mdump-tune-features= 
108TargetSave
109int x_ix86_dump_tunes
110
111;; -mstackrealign=
112TargetSave
113int x_ix86_force_align_arg_pointer
114
115;; -mforce-drap= 
116TargetSave
117int x_ix86_force_drap
118
119;; -mincoming-stack-boundary=
120TargetSave
121int x_ix86_incoming_stack_boundary_arg
122
123;; -maddress-mode=
124TargetSave
125enum pmode x_ix86_pmode
126
127;; -mpreferred-stack-boundary= 
128TargetSave
129int x_ix86_preferred_stack_boundary_arg
130
131;; -mrecip=
132TargetSave
133const char *x_ix86_recip_name
134
135;; -mregparm=
136TargetSave
137int x_ix86_regparm
138
139;; -mlarge-data-threshold=
140TargetSave
141int x_ix86_section_threshold
142
143;; -msse2avx=
144TargetSave
145int x_ix86_sse2avx
146
147;; -mstack-protector-guard=
148TargetSave
149enum stack_protector_guard x_ix86_stack_protector_guard
150
151;; -mstringop-strategy=
152TargetSave
153enum stringop_alg x_ix86_stringop_alg
154
155;; -mtls-dialect=
156TargetSave
157enum tls_dialect x_ix86_tls_dialect
158
159;; -mtune-ctrl=
160TargetSave
161const char *x_ix86_tune_ctrl_string
162
163;; -mmemcpy-strategy=
164TargetSave
165const char *x_ix86_tune_memcpy_strategy
166
167;; -mmemset-strategy=
168TargetSave
169const char *x_ix86_tune_memset_strategy
170
171;; -mno-default=
172TargetSave
173int x_ix86_tune_no_default
174
175;; -mveclibabi=
176TargetSave
177enum ix86_veclibabi x_ix86_veclibabi_type
178
179;; x86 options
180m128bit-long-double
181Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
182sizeof(long double) is 16
183
184m80387
185Target Report Mask(80387) Save
186Use hardware fp
187
188m96bit-long-double
189Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
190sizeof(long double) is 12
191
192mlong-double-80
193Target Report RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save
194Use 80-bit long double
195
196mlong-double-64
197Target Report RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save
198Use 64-bit long double
199
200mlong-double-128
201Target Report RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save
202Use 128-bit long double
203
204maccumulate-outgoing-args
205Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
206Reserve space for outgoing arguments in the function prologue
207
208malign-double
209Target Report Mask(ALIGN_DOUBLE) Save
210Align some doubles on dword boundary
211
212malign-functions=
213Target RejectNegative Joined UInteger
214Function starts are aligned to this power of 2
215
216malign-jumps=
217Target RejectNegative Joined UInteger
218Jump targets are aligned to this power of 2
219
220malign-loops=
221Target RejectNegative Joined UInteger
222Loop code aligned to this power of 2
223
224malign-stringops
225Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
226Align destination of the string operations
227
228malign-data=
229Target RejectNegative Joined Var(ix86_align_data_type) Enum(ix86_align_data) Init(ix86_align_data_type_compat)
230Use the given data alignment
231
232Enum
233Name(ix86_align_data) Type(enum ix86_align_data)
234Known data alignment choices (for use with the -malign-data= option):
235
236EnumValue
237Enum(ix86_align_data) String(compat) Value(ix86_align_data_type_compat)
238
239EnumValue
240Enum(ix86_align_data) String(abi) Value(ix86_align_data_type_abi)
241
242EnumValue
243Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline)
244
245march=
246Target RejectNegative Joined Var(ix86_arch_string)
247Generate code for given CPU
248
249masm=
250Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT)
251Use given assembler dialect
252
253Enum
254Name(asm_dialect) Type(enum asm_dialect)
255Known assembler dialects (for use with the -masm-dialect= option):
256
257EnumValue
258Enum(asm_dialect) String(intel) Value(ASM_INTEL)
259
260EnumValue
261Enum(asm_dialect) String(att) Value(ASM_ATT)
262
263mbranch-cost=
264Target RejectNegative Joined UInteger Var(ix86_branch_cost)
265Branches are this expensive (1-5, arbitrary units)
266
267mlarge-data-threshold=
268Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(DEFAULT_LARGE_SECTION_THRESHOLD)
269Data greater than given threshold will go into .ldata section in x86-64 medium model
270
271mcmodel=
272Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32)
273Use given x86-64 code model
274
275Enum
276Name(cmodel) Type(enum cmodel)
277Known code models (for use with the -mcmodel= option):
278
279EnumValue
280Enum(cmodel) String(small) Value(CM_SMALL)
281
282EnumValue
283Enum(cmodel) String(medium) Value(CM_MEDIUM)
284
285EnumValue
286Enum(cmodel) String(large) Value(CM_LARGE)
287
288EnumValue
289Enum(cmodel) String(32) Value(CM_32)
290
291EnumValue
292Enum(cmodel) String(kernel) Value(CM_KERNEL)
293
294maddress-mode=
295Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI)
296Use given address mode
297
298Enum
299Name(pmode) Type(enum pmode)
300Known address mode (for use with the -maddress-mode= option):
301
302EnumValue
303Enum(pmode) String(short) Value(PMODE_SI)
304
305EnumValue
306Enum(pmode) String(long) Value(PMODE_DI)
307
308mcpu=
309Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead)
310
311mfancy-math-387
312Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
313Generate sin, cos, sqrt for FPU
314
315mforce-drap
316Target Report Var(ix86_force_drap)
317Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack
318
319mfp-ret-in-387
320Target Report Mask(FLOAT_RETURNS) Save
321Return values of functions in FPU registers
322
323mfpmath=
324Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save
325Generate floating point mathematics using given instruction set
326
327Enum
328Name(fpmath_unit) Type(enum fpmath_unit)
329Valid arguments to -mfpmath=:
330
331EnumValue
332Enum(fpmath_unit) String(387) Value(FPMATH_387)
333
334EnumValue
335Enum(fpmath_unit) String(sse) Value(FPMATH_SSE)
336
337EnumValue
338Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
339
340EnumValue
341Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
342
343EnumValue
344Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
345
346EnumValue
347Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
348
349EnumValue
350Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
351
352mhard-float
353Target RejectNegative Mask(80387) Save
354Use hardware fp
355
356mieee-fp
357Target Report Mask(IEEE_FP) Save
358Use IEEE math for fp comparisons
359
360minline-all-stringops
361Target Report Mask(INLINE_ALL_STRINGOPS) Save
362Inline all known string operations
363
364minline-stringops-dynamically
365Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
366Inline memset/memcpy string operations, but perform inline version only for small blocks
367
368mintel-syntax
369Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead)
370;; Deprecated
371
372mms-bitfields
373Target Report Mask(MS_BITFIELD_LAYOUT) Save
374Use native (MS) bitfield layout
375
376mno-align-stringops
377Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
378
379mno-fancy-math-387
380Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save
381
382mno-push-args
383Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save
384
385mno-red-zone
386Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save
387
388momit-leaf-frame-pointer
389Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
390Omit the frame pointer in leaf functions
391
392mpc32
393Target RejectNegative Report
394Set 80387 floating-point precision to 32-bit
395
396mpc64
397Target RejectNegative Report
398Set 80387 floating-point precision to 64-bit
399
400mpc80
401Target RejectNegative Report
402Set 80387 floating-point precision to 80-bit
403
404mpreferred-stack-boundary=
405Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg)
406Attempt to keep stack aligned to this power of 2
407
408mincoming-stack-boundary=
409Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg)
410Assume incoming stack aligned to this power of 2
411
412mpush-args
413Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
414Use push instructions to save outgoing arguments
415
416mred-zone
417Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
418Use red-zone in the x86-64 code
419
420mregparm=
421Target RejectNegative Joined UInteger Var(ix86_regparm)
422Number of registers used to pass integer arguments
423
424mrtd
425Target Report Mask(RTD) Save
426Alternate calling convention
427
428msoft-float
429Target InverseMask(80387) Save
430Do not use hardware fp
431
432msseregparm
433Target RejectNegative Mask(SSEREGPARM) Save
434Use SSE register passing conventions for SF and DF mode
435
436mstackrealign
437Target Report Var(ix86_force_align_arg_pointer) Init(-1)
438Realign stack in prologue
439
440mstack-arg-probe
441Target Report Mask(STACK_PROBE) Save
442Enable stack probing
443
444mmemcpy-strategy=
445Target RejectNegative Joined Var(ix86_tune_memcpy_strategy)
446Specify memcpy expansion strategy when expected size is known
447
448mmemset-strategy=
449Target RejectNegative Joined Var(ix86_tune_memset_strategy)
450Specify memset expansion strategy when expected size is known
451
452mstringop-strategy=
453Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop)
454Chose strategy to generate stringop using
455
456Enum
457Name(stringop_alg) Type(enum stringop_alg)
458Valid arguments to -mstringop-strategy=:
459
460EnumValue
461Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte)
462
463EnumValue
464Enum(stringop_alg) String(libcall) Value(libcall)
465
466EnumValue
467Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte)
468
469EnumValue
470Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte)
471
472EnumValue
473Enum(stringop_alg) String(byte_loop) Value(loop_1_byte)
474
475EnumValue
476Enum(stringop_alg) String(loop) Value(loop)
477
478EnumValue
479Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop)
480
481EnumValue
482Enum(stringop_alg) String(vector_loop) Value(vector_loop)
483
484mtls-dialect=
485Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU)
486Use given thread-local storage dialect
487
488Enum
489Name(tls_dialect) Type(enum tls_dialect)
490Known TLS dialects (for use with the -mtls-dialect= option):
491
492EnumValue
493Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU)
494
495EnumValue
496Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2)
497
498mtls-direct-seg-refs
499Target Report Mask(TLS_DIRECT_SEG_REFS)
500Use direct references against %gs when accessing tls data
501
502mtune=
503Target RejectNegative Joined Var(ix86_tune_string)
504Schedule code for given CPU
505
506mtune-ctrl=
507Target RejectNegative Joined Var(ix86_tune_ctrl_string)
508Fine grain control of tune features
509
510mno-default
511Target RejectNegative Var(ix86_tune_no_default) Init(0)
512Clear all tune features
513
514mdump-tune-features
515Target RejectNegative Var(ix86_dump_tunes) Init(0)
516
517mabi=
518Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI)
519Generate code that conforms to the given ABI
520
521Enum
522Name(calling_abi) Type(enum calling_abi)
523Known ABIs (for use with the -mabi= option):
524
525EnumValue
526Enum(calling_abi) String(sysv) Value(SYSV_ABI)
527
528EnumValue
529Enum(calling_abi) String(ms) Value(MS_ABI)
530
531mveclibabi=
532Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none)
533Vector library ABI to use
534
535Enum
536Name(ix86_veclibabi) Type(enum ix86_veclibabi)
537Known vectorization library ABIs (for use with the -mveclibabi= option):
538
539EnumValue
540Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml)
541
542EnumValue
543Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml)
544
545mvect8-ret-in-mem
546Target Report Mask(VECT8_RETURNS) Save
547Return 8-byte vectors in memory
548
549mrecip
550Target Report Mask(RECIP) Save
551Generate reciprocals instead of divss and sqrtss.
552
553mrecip=
554Target Report RejectNegative Joined Var(ix86_recip_name)
555Control generation of reciprocal estimates.
556
557mcld
558Target Report Mask(CLD) Save
559Generate cld instruction in the function prologue.
560
561mvzeroupper
562Target Report Mask(VZEROUPPER) Save
563Generate vzeroupper instruction before a transfer of control flow out of
564the function.
565
566mdispatch-scheduler
567Target RejectNegative Var(flag_dispatch_scheduler)
568Do dispatch scheduling if processor is bdver1 or bdver2 or bdver3 or bdver4 and Haifa scheduling
569is selected.
570
571mprefer-avx128
572Target Report Mask(PREFER_AVX128) SAVE
573Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
574
575;; ISA support
576
577m32
578Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
579Generate 32bit i386 code
580
581m64
582Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save
583Generate 64bit x86-64 code
584
585mx32
586Target RejectNegative Negative(m16) Report Mask(ABI_X32) Var(ix86_isa_flags) Save
587Generate 32bit x86-64 code
588
589m16
590Target RejectNegative Negative(m32) Report Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
591Generate 16bit i386 code
592
593mmmx
594Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save
595Support MMX built-in functions
596
597m3dnow
598Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save
599Support 3DNow! built-in functions
600
601m3dnowa
602Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
603Support Athlon 3Dnow! built-in functions
604
605msse
606Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save
607Support MMX and SSE built-in functions and code generation
608
609msse2
610Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save
611Support MMX, SSE and SSE2 built-in functions and code generation
612
613msse3
614Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save
615Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
616
617mssse3
618Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save
619Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
620
621msse4.1
622Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save
623Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
624
625msse4.2
626Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
627Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
628
629msse4
630Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
631Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
632
633mno-sse4
634Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save
635Do not support SSE4.1 and SSE4.2 built-in functions and code generation
636
637msse5
638Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed)
639;; Deprecated
640
641mavx
642Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save
643Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation
644
645mavx2
646Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save
647Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation
648
649mavx512f
650Target Report Mask(ISA_AVX512F) Var(ix86_isa_flags) Save
651Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation
652
653mavx512pf
654Target Report Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save
655Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation
656
657mavx512er
658Target Report Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save
659Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation
660
661mavx512cd
662Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save
663Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation
664
665mavx512dq
666Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save
667Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation
668
669mavx512bw
670Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save
671Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation
672
673mavx512vl
674Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save
675Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation
676
677mavx512ifma
678Target Report Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save
679Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation
680
681mavx512vbmi
682Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save
683Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation
684
685mfma
686Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
687Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation
688
689msse4a
690Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save
691Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
692
693mfma4
694Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save
695Support FMA4 built-in functions and code generation 
696
697mxop
698Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save
699Support XOP built-in functions and code generation 
700
701mlwp
702Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save
703Support LWP built-in functions and code generation 
704
705mabm
706Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save
707Support code generation of Advanced Bit Manipulation (ABM) instructions.
708
709mpopcnt
710Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
711Support code generation of popcnt instruction.
712
713mbmi
714Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save
715Support BMI built-in functions and code generation
716
717mbmi2
718Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save
719Support BMI2 built-in functions and code generation
720
721mlzcnt
722Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save
723Support LZCNT built-in function and code generation
724
725mhle
726Target Report Mask(ISA_HLE) Var(ix86_isa_flags) Save
727Support Hardware Lock Elision prefixes
728
729mrdseed
730Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save
731Support RDSEED instruction
732
733mprfchw
734Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save
735Support PREFETCHW instruction
736
737madx
738Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save
739Support flag-preserving add-carry instructions
740
741mclflushopt
742Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save
743Support CLFLUSHOPT instructions
744
745mclwb
746Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save
747Support CLWB instruction
748
749mpcommit
750Target Report Mask(ISA_PCOMMIT) Var(ix86_isa_flags) Save
751Support PCOMMIT instruction
752
753mfxsr
754Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save
755Support FXSAVE and FXRSTOR instructions
756
757mxsave
758Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save
759Support XSAVE and XRSTOR instructions
760
761mxsaveopt
762Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save
763Support XSAVEOPT instruction
764
765mxsavec
766Target Report Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save
767Support XSAVEC instructions
768
769mxsaves
770Target Report Mask(ISA_XSAVES) Var(ix86_isa_flags) Save
771Support XSAVES and XRSTORS instructions
772
773mtbm
774Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save
775Support TBM built-in functions and code generation
776
777mcx16
778Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save
779Support code generation of cmpxchg16b instruction.
780
781msahf
782Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save
783Support code generation of sahf instruction in 64bit x86-64 code.
784
785mmovbe
786Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save
787Support code generation of movbe instruction.
788
789mcrc32
790Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save
791Support code generation of crc32 instruction.
792
793maes
794Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save
795Support AES built-in functions and code generation
796
797msha
798Target Report Mask(ISA_SHA) Var(ix86_isa_flags) Save
799Support SHA1 and SHA256 built-in functions and code generation
800
801mpclmul
802Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save
803Support PCLMUL built-in functions and code generation
804
805msse2avx
806Target Report Var(ix86_sse2avx)
807Encode SSE instructions with VEX prefix
808
809mfsgsbase
810Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save
811Support FSGSBASE built-in functions and code generation
812
813mrdrnd
814Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save
815Support RDRND built-in functions and code generation
816
817mf16c
818Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save
819Support F16C built-in functions and code generation
820
821mprefetchwt1
822Target Report Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save
823Support PREFETCHWT1 built-in functions and code generation
824
825mfentry
826Target Report Var(flag_fentry) Init(-1)
827Emit profiling counter call at function entry before prologue.
828
829mrecord-mcount
830Target Report Var(flag_record_mcount) Init(0)
831Generate __mcount_loc section with all mcount or __fentry__ calls.
832
833mnop-mcount
834Target Report Var(flag_nop_mcount) Init(0)
835Generate mcount/__fentry__ calls as nops. To activate they need to be
836patched in.
837
838mskip-rax-setup
839Target Report Var(flag_skip_rax_setup) Init(0)
840Skip setting up RAX register when passing variable arguments.
841
842m8bit-idiv
843Target Report Mask(USE_8BIT_IDIV) Save
844Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check
845
846mavx256-split-unaligned-load
847Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save
848Split 32-byte AVX unaligned load
849
850mavx256-split-unaligned-store
851Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
852Split 32-byte AVX unaligned store
853
854mrtm
855Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save
856Support RTM built-in functions and code generation
857
858mmpx
859Target Report Mask(ISA_MPX) Var(ix86_isa_flags) Save
860Support MPX code generation
861
862mmwaitx
863Target Report Mask(ISA_MWAITX) Var(ix86_isa_flags) Save
864Support MWAITX and MONITORX built-in functions and code generation
865
866mstack-protector-guard=
867Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS)
868Use given stack-protector guard
869
870Enum
871Name(stack_protector_guard) Type(enum stack_protector_guard)
872Known stack protector guard (for use with the -mstack-protector-guard= option):
873
874EnumValue
875Enum(stack_protector_guard) String(tls) Value(SSP_TLS)
876
877EnumValue
878Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
879