1303231Sdim/* Definitions of target machine for GCC for IA-32. 2303231Sdim Copyright (C) 1988-2015 Free Software Foundation, Inc. 3353358Sdim 4353358SdimThis file is part of GCC. 5353358Sdim 6303231SdimGCC is free software; you can redistribute it and/or modify 7303231Sdimit under the terms of the GNU General Public License as published by 8303231Sdimthe Free Software Foundation; either version 3, or (at your option) 9303231Sdimany later version. 10303231Sdim 11303231SdimGCC is distributed in the hope that it will be useful, 12303231Sdimbut WITHOUT ANY WARRANTY; without even the implied warranty of 13303231SdimMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14303231SdimGNU General Public License for more details. 15341825Sdim 16303231SdimUnder Section 7 of GPL version 3, you are granted additional 17303231Sdimpermissions described in the GCC Runtime Library Exception, version 18303231Sdim3.1, as published by the Free Software Foundation. 19303231Sdim 20303231SdimYou should have received a copy of the GNU General Public License and 21303231Sdima copy of the GCC Runtime Library Exception along with this program; 22341825Sdimsee the files COPYING3 and COPYING.RUNTIME respectively. If not, see 23303231Sdim<http://www.gnu.org/licenses/>. */ 24341825Sdim 25303231Sdim/* The purpose of this file is to define the characteristics of the i386, 26303231Sdim independent of assembler syntax or operating system. 27341825Sdim 28303231Sdim Three other files build on this one to describe a specific assembler syntax: 29303231Sdim bsd386.h, att386.h, and sun386.h. 30303231Sdim 31303231Sdim The actual tm.h file for a particular system should include 32303231Sdim this file, and then the file for the appropriate assembler syntax. 33303231Sdim 34341825Sdim Many macros that specify assembler syntax are omitted entirely from 35341825Sdim this file because they really belong in the files for particular 36341825Sdim assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 37341825Sdim ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 38341825Sdim that start with ASM_ or end in ASM_OP. */ 39341825Sdim 40341825Sdim/* Redefines for option macros. */ 41341825Sdim 42341825Sdim#define TARGET_64BIT TARGET_ISA_64BIT 43341825Sdim#define TARGET_64BIT_P(x) TARGET_ISA_64BIT_P(x) 44341825Sdim#define TARGET_MMX TARGET_ISA_MMX 45341825Sdim#define TARGET_MMX_P(x) TARGET_ISA_MMX_P(x) 46341825Sdim#define TARGET_3DNOW TARGET_ISA_3DNOW 47360784Sdim#define TARGET_3DNOW_P(x) TARGET_ISA_3DNOW_P(x) 48341825Sdim#define TARGET_3DNOW_A TARGET_ISA_3DNOW_A 49341825Sdim#define TARGET_3DNOW_A_P(x) TARGET_ISA_3DNOW_A_P(x) 50341825Sdim#define TARGET_SSE TARGET_ISA_SSE 51341825Sdim#define TARGET_SSE_P(x) TARGET_ISA_SSE_P(x) 52341825Sdim#define TARGET_SSE2 TARGET_ISA_SSE2 53341825Sdim#define TARGET_SSE2_P(x) TARGET_ISA_SSE2_P(x) 54341825Sdim#define TARGET_SSE3 TARGET_ISA_SSE3 55341825Sdim#define TARGET_SSE3_P(x) TARGET_ISA_SSE3_P(x) 56341825Sdim#define TARGET_SSSE3 TARGET_ISA_SSSE3 57341825Sdim#define TARGET_SSSE3_P(x) TARGET_ISA_SSSE3_P(x) 58341825Sdim#define TARGET_SSE4_1 TARGET_ISA_SSE4_1 59341825Sdim#define TARGET_SSE4_1_P(x) TARGET_ISA_SSE4_1_P(x) 60341825Sdim#define TARGET_SSE4_2 TARGET_ISA_SSE4_2 61341825Sdim#define TARGET_SSE4_2_P(x) TARGET_ISA_SSE4_2_P(x) 62341825Sdim#define TARGET_AVX TARGET_ISA_AVX 63341825Sdim#define TARGET_AVX_P(x) TARGET_ISA_AVX_P(x) 64341825Sdim#define TARGET_AVX2 TARGET_ISA_AVX2 65341825Sdim#define TARGET_AVX2_P(x) TARGET_ISA_AVX2_P(x) 66360784Sdim#define TARGET_AVX512F TARGET_ISA_AVX512F 67341825Sdim#define TARGET_AVX512F_P(x) TARGET_ISA_AVX512F_P(x) 68341825Sdim#define TARGET_AVX512PF TARGET_ISA_AVX512PF 69341825Sdim#define TARGET_AVX512PF_P(x) TARGET_ISA_AVX512PF_P(x) 70341825Sdim#define TARGET_AVX512ER TARGET_ISA_AVX512ER 71341825Sdim#define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x) 72341825Sdim#define TARGET_AVX512CD TARGET_ISA_AVX512CD 73341825Sdim#define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x) 74341825Sdim#define TARGET_AVX512DQ TARGET_ISA_AVX512DQ 75341825Sdim#define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x) 76341825Sdim#define TARGET_AVX512BW TARGET_ISA_AVX512BW 77341825Sdim#define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x) 78341825Sdim#define TARGET_AVX512VL TARGET_ISA_AVX512VL 79341825Sdim#define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x) 80341825Sdim#define TARGET_AVX512VBMI TARGET_ISA_AVX512VBMI 81341825Sdim#define TARGET_AVX512VBMI_P(x) TARGET_ISA_AVX512VBMI_P(x) 82341825Sdim#define TARGET_AVX512IFMA TARGET_ISA_AVX512IFMA 83341825Sdim#define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x) 84341825Sdim#define TARGET_FMA TARGET_ISA_FMA 85341825Sdim#define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) 86341825Sdim#define TARGET_SSE4A TARGET_ISA_SSE4A 87341825Sdim#define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x) 88303231Sdim#define TARGET_FMA4 TARGET_ISA_FMA4 89303231Sdim#define TARGET_FMA4_P(x) TARGET_ISA_FMA4_P(x) 90341825Sdim#define TARGET_XOP TARGET_ISA_XOP 91341825Sdim#define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x) 92341825Sdim#define TARGET_LWP TARGET_ISA_LWP 93341825Sdim#define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x) 94303231Sdim#define TARGET_ROUND TARGET_ISA_ROUND 95303231Sdim#define TARGET_ABM TARGET_ISA_ABM 96303231Sdim#define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x) 97303231Sdim#define TARGET_BMI TARGET_ISA_BMI 98303231Sdim#define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x) 99303231Sdim#define TARGET_BMI2 TARGET_ISA_BMI2 100303231Sdim#define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x) 101303231Sdim#define TARGET_LZCNT TARGET_ISA_LZCNT 102303231Sdim#define TARGET_LZCNT_P(x) TARGET_ISA_LZCNT_P(x) 103341825Sdim#define TARGET_TBM TARGET_ISA_TBM 104341825Sdim#define TARGET_TBM_P(x) TARGET_ISA_TBM_P(x) 105341825Sdim#define TARGET_POPCNT TARGET_ISA_POPCNT 106341825Sdim#define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x) 107341825Sdim#define TARGET_SAHF TARGET_ISA_SAHF 108303231Sdim#define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x) 109341825Sdim#define TARGET_MOVBE TARGET_ISA_MOVBE 110303231Sdim#define TARGET_MOVBE_P(x) TARGET_ISA_MOVBE_P(x) 111303231Sdim#define TARGET_CRC32 TARGET_ISA_CRC32 112303231Sdim#define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x) 113303231Sdim#define TARGET_AES TARGET_ISA_AES 114303231Sdim#define TARGET_AES_P(x) TARGET_ISA_AES_P(x) 115303231Sdim#define TARGET_SHA TARGET_ISA_SHA 116341825Sdim#define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x) 117303231Sdim#define TARGET_CLFLUSHOPT TARGET_ISA_CLFLUSHOPT 118341825Sdim#define TARGET_CLFLUSHOPT_P(x) TARGET_ISA_CLFLUSHOPT_P(x) 119341825Sdim#define TARGET_XSAVEC TARGET_ISA_XSAVEC 120341825Sdim#define TARGET_XSAVEC_P(x) TARGET_ISA_XSAVEC_P(x) 121341825Sdim#define TARGET_XSAVES TARGET_ISA_XSAVES 122341825Sdim#define TARGET_XSAVES_P(x) TARGET_ISA_XSAVES_P(x) 123341825Sdim#define TARGET_PCLMUL TARGET_ISA_PCLMUL 124341825Sdim#define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x) 125341825Sdim#define TARGET_CMPXCHG16B TARGET_ISA_CX16 126303231Sdim#define TARGET_CMPXCHG16B_P(x) TARGET_ISA_CX16_P(x) 127303231Sdim#define TARGET_FSGSBASE TARGET_ISA_FSGSBASE 128341825Sdim#define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x) 129341825Sdim#define TARGET_RDRND TARGET_ISA_RDRND 130341825Sdim#define TARGET_RDRND_P(x) TARGET_ISA_RDRND_P(x) 131341825Sdim#define TARGET_F16C TARGET_ISA_F16C 132303231Sdim#define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x) 133303231Sdim#define TARGET_RTM TARGET_ISA_RTM 134341825Sdim#define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x) 135341825Sdim#define TARGET_HLE TARGET_ISA_HLE 136341825Sdim#define TARGET_HLE_P(x) TARGET_ISA_HLE_P(x) 137360784Sdim#define TARGET_RDSEED TARGET_ISA_RDSEED 138341825Sdim#define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x) 139341825Sdim#define TARGET_PRFCHW TARGET_ISA_PRFCHW 140341825Sdim#define TARGET_PRFCHW_P(x) TARGET_ISA_PRFCHW_P(x) 141341825Sdim#define TARGET_ADX TARGET_ISA_ADX 142341825Sdim#define TARGET_ADX_P(x) TARGET_ISA_ADX_P(x) 143341825Sdim#define TARGET_FXSR TARGET_ISA_FXSR 144353358Sdim#define TARGET_FXSR_P(x) TARGET_ISA_FXSR_P(x) 145341825Sdim#define TARGET_XSAVE TARGET_ISA_XSAVE 146341825Sdim#define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x) 147341825Sdim#define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT 148341825Sdim#define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x) 149341825Sdim#define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1 150341825Sdim#define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x) 151341825Sdim#define TARGET_MPX TARGET_ISA_MPX 152341825Sdim#define TARGET_MPX_P(x) TARGET_ISA_MPX_P(x) 153341825Sdim#define TARGET_PCOMMIT TARGET_ISA_PCOMMIT 154341825Sdim#define TARGET_PCOMMIT_P(x) TARGET_ISA_PCOMMIT_P(x) 155303231Sdim#define TARGET_CLWB TARGET_ISA_CLWB 156303231Sdim#define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x) 157344779Sdim#define TARGET_MWAITX TARGET_ISA_MWAITX 158344779Sdim#define TARGET_MWAITX_P(x) TARGET_ISA_MWAITX_P(x) 159344779Sdim 160344779Sdim#define TARGET_LP64 TARGET_ABI_64 161344779Sdim#define TARGET_LP64_P(x) TARGET_ABI_64_P(x) 162344779Sdim#define TARGET_X32 TARGET_ABI_X32 163344779Sdim#define TARGET_X32_P(x) TARGET_ABI_X32_P(x) 164344779Sdim#define TARGET_16BIT TARGET_CODE16 165344779Sdim#define TARGET_16BIT_P(x) TARGET_CODE16_P(x) 166341825Sdim 167341825Sdim/* SSE4.1 defines round instructions */ 168341825Sdim#define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1 169341825Sdim#define TARGET_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0) 170303231Sdim 171303231Sdim#include "config/vxworks-dummy.h" 172341825Sdim 173341825Sdim#include "config/i386/i386-opts.h" 174341825Sdim 175341825Sdim#define MAX_STRINGOP_ALGS 4 176341825Sdim 177341825Sdim/* Specify what algorithm to use for stringops on known size. 178341825Sdim When size is unknown, the UNKNOWN_SIZE alg is used. When size is 179341825Sdim known at compile time or estimated via feedback, the SIZE array 180341825Sdim is walked in order until MAX is greater then the estimate (or -1 181341825Sdim means infinity). Corresponding ALG is used then. 182341825Sdim When NOALIGN is true the code guaranting the alignment of the memory 183341825Sdim block is skipped. 184341825Sdim 185341825Sdim For example initializer: 186341825Sdim {{256, loop}, {-1, rep_prefix_4_byte}} 187341825Sdim will use loop for blocks smaller or equal to 256 bytes, rep prefix will 188341825Sdim be used otherwise. */ 189303231Sdimstruct stringop_algs 190303231Sdim{ 191303231Sdim const enum stringop_alg unknown_size; 192303231Sdim const struct stringop_strategy { 193341825Sdim const int max; 194341825Sdim const enum stringop_alg alg; 195341825Sdim int noalign; 196341825Sdim } size [MAX_STRINGOP_ALGS]; 197303231Sdim}; 198341825Sdim 199341825Sdim/* Define the specific costs for a given cpu */ 200341825Sdim 201303231Sdimstruct processor_costs { 202341825Sdim const int add; /* cost of an add instruction */ 203341825Sdim const int lea; /* cost of a lea instruction */ 204303231Sdim const int shift_var; /* variable shift costs */ 205303231Sdim const int shift_const; /* constant shift costs */ 206341825Sdim const int mult_init[5]; /* cost of starting a multiply 207341825Sdim in QImode, HImode, SImode, DImode, TImode*/ 208341825Sdim const int mult_bit; /* cost of multiply per each bit set */ 209341825Sdim const int divide[5]; /* cost of a divide/mod 210341825Sdim in QImode, HImode, SImode, DImode, TImode*/ 211341825Sdim int movsx; /* The cost of movsx operation. */ 212341825Sdim int movzx; /* The cost of movzx operation. */ 213303231Sdim const int large_insn; /* insns larger than this cost more */ 214341825Sdim const int move_ratio; /* The threshold of number of scalar 215341825Sdim memory-to-memory move insns. */ 216341825Sdim const int movzbl_load; /* cost of loading using movzbl */ 217341825Sdim const int int_load[3]; /* cost of loading integer registers 218341825Sdim in QImode, HImode and SImode relative 219341825Sdim to reg-reg move (2). */ 220341825Sdim const int int_store[3]; /* cost of storing integer register 221341825Sdim in QImode, HImode and SImode */ 222341825Sdim const int fp_move; /* cost of reg,reg fld/fst */ 223341825Sdim const int fp_load[3]; /* cost of loading FP register 224341825Sdim in SFmode, DFmode and XFmode */ 225341825Sdim const int fp_store[3]; /* cost of storing FP register 226341825Sdim in SFmode, DFmode and XFmode */ 227341825Sdim const int mmx_move; /* cost of moving MMX register. */ 228341825Sdim const int mmx_load[2]; /* cost of loading MMX register 229341825Sdim in SImode and DImode */ 230341825Sdim const int mmx_store[2]; /* cost of storing MMX register 231341825Sdim in SImode and DImode */ 232341825Sdim const int sse_move; /* cost of moving SSE register. */ 233341825Sdim const int sse_load[3]; /* cost of loading SSE register 234341825Sdim in SImode, DImode and TImode*/ 235341825Sdim const int sse_store[3]; /* cost of storing SSE register 236341825Sdim in SImode, DImode and TImode*/ 237341825Sdim const int mmxsse_to_integer; /* cost of moving mmxsse register to 238341825Sdim integer and vice versa. */ 239341825Sdim const int l1_cache_size; /* size of l1 cache, in kilobytes. */ 240341825Sdim const int l2_cache_size; /* size of l2 cache, in kilobytes. */ 241341825Sdim const int prefetch_block; /* bytes moved to cache for prefetch. */ 242341825Sdim const int simultaneous_prefetches; /* number of parallel prefetch 243341825Sdim operations. */ 244341825Sdim const int branch_cost; /* Default value for BRANCH_COST. */ 245341825Sdim const int fadd; /* cost of FADD and FSUB instructions. */ 246341825Sdim const int fmul; /* cost of FMUL instruction. */ 247341825Sdim const int fdiv; /* cost of FDIV instruction. */ 248341825Sdim const int fabs; /* cost of FABS instruction. */ 249341825Sdim const int fchs; /* cost of FCHS instruction. */ 250341825Sdim const int fsqrt; /* cost of FSQRT instruction. */ 251341825Sdim /* Specify what algorithm 252341825Sdim to use for stringops on unknown size. */ 253341825Sdim struct stringop_algs *memcpy, *memset; 254341825Sdim const int scalar_stmt_cost; /* Cost of any scalar operation, excluding 255341825Sdim load and store. */ 256341825Sdim const int scalar_load_cost; /* Cost of scalar load. */ 257341825Sdim const int scalar_store_cost; /* Cost of scalar store. */ 258341825Sdim const int vec_stmt_cost; /* Cost of any vector operation, excluding 259341825Sdim load, store, vector-to-scalar and 260341825Sdim scalar-to-vector operation. */ 261341825Sdim const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ 262341825Sdim const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ 263341825Sdim const int vec_align_load_cost; /* Cost of aligned vector load. */ 264341825Sdim const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ 265341825Sdim const int vec_store_cost; /* Cost of vector store. */ 266341825Sdim const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer 267341825Sdim cost model. */ 268341825Sdim const int cond_not_taken_branch_cost;/* Cost of not taken branch for 269341825Sdim vectorizer cost model. */ 270303231Sdim}; 271303231Sdim 272341825Sdimextern const struct processor_costs *ix86_cost; 273303231Sdimextern const struct processor_costs ix86_size_cost; 274303231Sdim 275341825Sdim#define ix86_cur_cost() \ 276341825Sdim (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) 277341825Sdim 278341825Sdim/* Macros used in the machine description to test the flags. */ 279303231Sdim 280341825Sdim/* configure can arrange to change it. */ 281341825Sdim 282341825Sdim#ifndef TARGET_CPU_DEFAULT 283341825Sdim#define TARGET_CPU_DEFAULT PROCESSOR_GENERIC 284341825Sdim#endif 285341825Sdim 286341825Sdim#ifndef TARGET_FPMATH_DEFAULT 287341825Sdim#define TARGET_FPMATH_DEFAULT \ 288341825Sdim (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) 289341825Sdim#endif 290341825Sdim 291341825Sdim#ifndef TARGET_FPMATH_DEFAULT_P 292341825Sdim#define TARGET_FPMATH_DEFAULT_P(x) \ 293341825Sdim (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387) 294341825Sdim#endif 295341825Sdim 296341825Sdim#define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS 297341825Sdim#define TARGET_FLOAT_RETURNS_IN_80387_P(x) TARGET_FLOAT_RETURNS_P(x) 298341825Sdim 299341825Sdim/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 300341825Sdim compile-time constant. */ 301341825Sdim#ifdef IN_LIBGCC2 302341825Sdim#undef TARGET_64BIT 303341825Sdim#ifdef __x86_64__ 304341825Sdim#define TARGET_64BIT 1 305341825Sdim#else 306341825Sdim#define TARGET_64BIT 0 307341825Sdim#endif 308341825Sdim#else 309341825Sdim#ifndef TARGET_BI_ARCH 310303231Sdim#undef TARGET_64BIT 311341825Sdim#undef TARGET_64BIT_P 312341825Sdim#if TARGET_64BIT_DEFAULT 313341825Sdim#define TARGET_64BIT 1 314341825Sdim#define TARGET_64BIT_P(x) 1 315341825Sdim#else 316341825Sdim#define TARGET_64BIT 0 317341825Sdim#define TARGET_64BIT_P(x) 0 318341825Sdim#endif 319341825Sdim#endif 320341825Sdim#endif 321341825Sdim 322341825Sdim#define HAS_LONG_COND_BRANCH 1 323341825Sdim#define HAS_LONG_UNCOND_BRANCH 1 324341825Sdim 325341825Sdim#define TARGET_386 (ix86_tune == PROCESSOR_I386) 326341825Sdim#define TARGET_486 (ix86_tune == PROCESSOR_I486) 327341825Sdim#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 328341825Sdim#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 329341825Sdim#define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) 330303231Sdim#define TARGET_K6 (ix86_tune == PROCESSOR_K6) 331341825Sdim#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 332341825Sdim#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 333341825Sdim#define TARGET_K8 (ix86_tune == PROCESSOR_K8) 334341825Sdim#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 335341825Sdim#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) 336341825Sdim#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) 337341825Sdim#define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM) 338341825Sdim#define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE) 339341825Sdim#define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL) 340341825Sdim#define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL) 341341825Sdim#define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT) 342341825Sdim#define TARGET_KNL (ix86_tune == PROCESSOR_KNL) 343341825Sdim#define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) 344341825Sdim#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) 345341825Sdim#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) 346341825Sdim#define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) 347341825Sdim#define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) 348341825Sdim#define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3) 349341825Sdim#define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4) 350341825Sdim#define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) 351341825Sdim#define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2) 352341825Sdim 353341825Sdim/* Feature tests against the various tunings. */ 354341825Sdimenum ix86_tune_indices { 355341825Sdim#undef DEF_TUNE 356341825Sdim#define DEF_TUNE(tune, name, selector) tune, 357303231Sdim#include "x86-tune.def" 358303231Sdim#undef DEF_TUNE 359341825SdimX86_TUNE_LAST 360341825Sdim}; 361341825Sdim 362341825Sdimextern unsigned char ix86_tune_features[X86_TUNE_LAST]; 363341825Sdim 364341825Sdim#define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] 365341825Sdim#define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] 366341825Sdim#define TARGET_ZERO_EXTEND_WITH_AND \ 367341825Sdim ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] 368341825Sdim#define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] 369341825Sdim#define TARGET_BRANCH_PREDICTION_HINTS \ 370303231Sdim ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] 371303231Sdim#define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] 372341825Sdim#define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] 373341825Sdim#define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] 374341825Sdim#define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] 375341825Sdim#define TARGET_PARTIAL_FLAG_REG_STALL \ 376341825Sdim ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] 377341825Sdim#define TARGET_LCP_STALL \ 378341825Sdim ix86_tune_features[X86_TUNE_LCP_STALL] 379341825Sdim#define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] 380341825Sdim#define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] 381341825Sdim#define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] 382341825Sdim#define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] 383341825Sdim#define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] 384303231Sdim#define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] 385341825Sdim#define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] 386341825Sdim#define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] 387341825Sdim#define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] 388341825Sdim#define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] 389341825Sdim#define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] 390341825Sdim#define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \ 391341825Sdim ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES] 392341825Sdim#define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] 393341825Sdim#define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] 394341825Sdim#define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] 395303231Sdim#define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] 396341825Sdim#define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP] 397341825Sdim#define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP] 398341825Sdim#define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH] 399341825Sdim#define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH] 400303231Sdim#define TARGET_INTEGER_DFMODE_MOVES \ 401341825Sdim ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] 402341825Sdim#define TARGET_PARTIAL_REG_DEPENDENCY \ 403341825Sdim ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] 404341825Sdim#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 405341825Sdim ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] 406341825Sdim#define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ 407341825Sdim ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] 408303231Sdim#define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ 409341825Sdim ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] 410341825Sdim#define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ 411341825Sdim ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] 412341825Sdim#define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] 413341825Sdim#define TARGET_SSE_TYPELESS_STORES \ 414341825Sdim ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] 415341825Sdim#define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] 416341825Sdim#define TARGET_MEMORY_MISMATCH_STALL \ 417341825Sdim ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] 418341825Sdim#define TARGET_PROLOGUE_USING_MOVE \ 419303231Sdim ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] 420341825Sdim#define TARGET_EPILOGUE_USING_MOVE \ 421341825Sdim ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] 422341825Sdim#define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] 423341825Sdim#define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] 424341825Sdim#define TARGET_INTER_UNIT_MOVES_TO_VEC \ 425341825Sdim ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC] 426341825Sdim#define TARGET_INTER_UNIT_MOVES_FROM_VEC \ 427341825Sdim ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC] 428341825Sdim#define TARGET_INTER_UNIT_CONVERSIONS \ 429341825Sdim ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] 430344779Sdim#define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] 431344779Sdim#define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] 432344779Sdim#define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] 433344779Sdim#define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] 434344779Sdim#define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] 435344779Sdim#define TARGET_PAD_SHORT_FUNCTION \ 436344779Sdim ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION] 437344779Sdim#define TARGET_EXT_80387_CONSTANTS \ 438344779Sdim ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] 439341825Sdim#define TARGET_AVOID_VECTOR_DECODE \ 440341825Sdim ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] 441341825Sdim#define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ 442341825Sdim ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] 443341825Sdim#define TARGET_SLOW_IMUL_IMM32_MEM \ 444341825Sdim ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] 445303231Sdim#define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] 446303231Sdim#define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] 447341825Sdim#define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] 448341825Sdim#define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] 449303231Sdim#define TARGET_USE_VECTOR_FP_CONVERTS \ 450341825Sdim ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] 451341825Sdim#define TARGET_USE_VECTOR_CONVERTS \ 452341825Sdim ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] 453341825Sdim#define TARGET_SLOW_PSHUFB \ 454341825Sdim ix86_tune_features[X86_TUNE_SLOW_PSHUFB] 455341825Sdim#define TARGET_VECTOR_PARALLEL_EXECUTION \ 456341825Sdim ix86_tune_features[X86_TUNE_VECTOR_PARALLEL_EXECUTION] 457341825Sdim#define TARGET_AVOID_4BYTE_PREFIXES \ 458341825Sdim ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES] 459341825Sdim#define TARGET_FUSE_CMP_AND_BRANCH_32 \ 460341825Sdim ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] 461341825Sdim#define TARGET_FUSE_CMP_AND_BRANCH_64 \ 462303231Sdim ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64] 463303231Sdim#define TARGET_FUSE_CMP_AND_BRANCH \ 464341825Sdim (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \ 465341825Sdim : TARGET_FUSE_CMP_AND_BRANCH_32) 466303231Sdim#define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \ 467341825Sdim ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS] 468341825Sdim#define TARGET_FUSE_ALU_AND_BRANCH \ 469341825Sdim ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH] 470341825Sdim#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] 471341825Sdim#define TARGET_AVOID_LEA_FOR_ADDR \ 472341825Sdim ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR] 473341825Sdim#define TARGET_VECTORIZE_DOUBLE \ 474341825Sdim ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE] 475341825Sdim#define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \ 476341825Sdim ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL] 477341825Sdim#define TARGET_AVX128_OPTIMAL \ 478303231Sdim ix86_tune_features[X86_TUNE_AVX128_OPTIMAL] 479303231Sdim#define TARGET_REASSOC_INT_TO_PARALLEL \ 480341825Sdim ix86_tune_features[X86_TUNE_REASSOC_INT_TO_PARALLEL] 481341825Sdim#define TARGET_REASSOC_FP_TO_PARALLEL \ 482341825Sdim ix86_tune_features[X86_TUNE_REASSOC_FP_TO_PARALLEL] 483303231Sdim#define TARGET_GENERAL_REGS_SSE_SPILL \ 484341825Sdim ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL] 485341825Sdim#define TARGET_AVOID_MEM_OPND_FOR_CMOVE \ 486341825Sdim ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE] 487341825Sdim#define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \ 488341825Sdim ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS] 489341825Sdim#define TARGET_ADJUST_UNROLL \ 490341825Sdim ix86_tune_features[X86_TUNE_ADJUST_UNROLL] 491341825Sdim#define TARGET_AVOID_FALSE_DEP_FOR_BMI \ 492341825Sdim ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] 493303231Sdim 494341825Sdim/* Feature tests against the various architecture variations. */ 495303231Sdimenum ix86_arch_indices { 496341825Sdim X86_ARCH_CMOV, 497303231Sdim X86_ARCH_CMPXCHG, 498341825Sdim X86_ARCH_CMPXCHG8B, 499360784Sdim X86_ARCH_XADD, 500341825Sdim X86_ARCH_BSWAP, 501341825Sdim 502341825Sdim X86_ARCH_LAST 503303231Sdim}; 504341825Sdim 505341825Sdimextern unsigned char ix86_arch_features[X86_ARCH_LAST]; 506341825Sdim 507341825Sdim#define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] 508341825Sdim#define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] 509341825Sdim#define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] 510341825Sdim#define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] 511341825Sdim#define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] 512341825Sdim 513341825Sdim/* For sane SSE instruction set generation we need fcomi instruction. 514303231Sdim It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic 515341825Sdim expands to a sequence that includes conditional move. */ 516303231Sdim#define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) 517341825Sdim 518341825Sdim#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) 519341825Sdim 520341825Sdimextern unsigned char x86_prefetch_sse; 521341825Sdim#define TARGET_PREFETCH_SSE x86_prefetch_sse 522341825Sdim 523341825Sdim#define ASSEMBLER_DIALECT (ix86_asm_dialect) 524341825Sdim 525341825Sdim#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 526341825Sdim#define TARGET_MIX_SSE_I387 \ 527341825Sdim ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) 528341825Sdim 529341825Sdim#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 530341825Sdim#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) 531341825Sdim#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) 532341825Sdim#define TARGET_SUN_TLS 0 533341825Sdim 534303231Sdim#ifndef TARGET_64BIT_DEFAULT 535303231Sdim#define TARGET_64BIT_DEFAULT 0 536303231Sdim#endif 537341825Sdim#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 538341825Sdim#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 539303231Sdim#endif 540341825Sdim 541341825Sdim#define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL) 542341825Sdim#define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS) 543341825Sdim 544360784Sdim/* Fence to use after loop using storent. */ 545341825Sdim 546341825Sdimextern tree x86_mfence; 547341825Sdim#define FENCE_FOLLOWING_MOVNT x86_mfence 548341825Sdim 549341825Sdim/* Once GDB has been enhanced to deal with functions without frame 550341825Sdim pointers, we can change this to allow for elimination of 551341825Sdim the frame pointer in leaf functions. */ 552341825Sdim#define TARGET_DEFAULT 0 553341825Sdim 554341825Sdim/* Extra bits to force. */ 555303231Sdim#define TARGET_SUBTARGET_DEFAULT 0 556303231Sdim#define TARGET_SUBTARGET_ISA_DEFAULT 0 557341825Sdim 558341825Sdim/* Extra bits to force on w/ 32-bit mode. */ 559341825Sdim#define TARGET_SUBTARGET32_DEFAULT 0 560341825Sdim#define TARGET_SUBTARGET32_ISA_DEFAULT 0 561341825Sdim 562303231Sdim/* Extra bits to force on w/ 64-bit mode. */ 563341825Sdim#define TARGET_SUBTARGET64_DEFAULT 0 564341825Sdim#define TARGET_SUBTARGET64_ISA_DEFAULT 0 565303231Sdim 566341825Sdim/* Replace MACH-O, ifdefs by in-line tests, where possible. 567341825Sdim (a) Macros defined in config/i386/darwin.h */ 568341825Sdim#define TARGET_MACHO 0 569341825Sdim#define TARGET_MACHO_BRANCH_ISLANDS 0 570341825Sdim#define MACHOPIC_ATT_STUB 0 571341825Sdim/* (b) Macros defined in config/darwin.h */ 572341825Sdim#define MACHO_DYNAMIC_NO_PIC_P 0 573341825Sdim#define MACHOPIC_INDIRECT 0 574341825Sdim#define MACHOPIC_PURE 0 575303231Sdim 576341825Sdim/* For the RDOS */ 577341825Sdim#define TARGET_RDOS 0 578341825Sdim 579303231Sdim/* For the Windows 64-bit ABI. */ 580360784Sdim#define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 581341825Sdim 582303231Sdim/* For the Windows 32-bit ABI. */ 583303231Sdim#define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 584341825Sdim 585341825Sdim/* This is re-defined by cygming.h. */ 586341825Sdim#define TARGET_SEH 0 587341825Sdim 588341825Sdim/* This is re-defined by cygming.h. */ 589341825Sdim#define TARGET_PECOFF 0 590341825Sdim 591341825Sdim/* The default abi used by target. */ 592341825Sdim#define DEFAULT_ABI SYSV_ABI 593341825Sdim 594303231Sdim/* The default TLS segment register used by target. */ 595303231Sdim#define DEFAULT_TLS_SEG_REG (TARGET_64BIT ? SEG_FS : SEG_GS) 596341825Sdim 597341825Sdim/* Subtargets may reset this to 1 in order to enable 96-bit long double 598341825Sdim with the rounding mode forced to 53 bits. */ 599341825Sdim#define TARGET_96_ROUND_53_LONG_DOUBLE 0 600341825Sdim 601341825Sdim/* -march=native handling only makes sense with compiler running on 602353358Sdim an x86 or x86_64 chip. If changing this condition, also change 603353358Sdim the condition in driver-i386.c. */ 604353358Sdim#if defined(__i386__) || defined(__x86_64__) 605353358Sdim/* In driver-i386.c. */ 606341825Sdimextern const char *host_detect_local_cpu (int argc, const char **argv); 607341825Sdim#define EXTRA_SPEC_FUNCTIONS \ 608341825Sdim { "local_cpu_detect", host_detect_local_cpu }, 609341825Sdim#define HAVE_LOCAL_CPU_DETECT 610341825Sdim#endif 611341825Sdim 612341825Sdim#if TARGET_64BIT_DEFAULT 613341825Sdim#define OPT_ARCH64 "!m32" 614353358Sdim#define OPT_ARCH32 "m32" 615341825Sdim#else 616341825Sdim#define OPT_ARCH64 "m64|mx32" 617341825Sdim#define OPT_ARCH32 "m64|mx32:;" 618341825Sdim#endif 619341825Sdim 620341825Sdim/* Support for configure-time defaults of some command line options. 621341825Sdim The order here is important so that -march doesn't squash the 622341825Sdim tune or cpu values. */ 623341825Sdim#define OPTION_DEFAULT_SPECS \ 624341825Sdim {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 625341825Sdim {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 626341825Sdim {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 627341825Sdim {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 628341825Sdim {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 629341825Sdim {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 630341825Sdim {"arch", "%{!march=*:-march=%(VALUE)}"}, \ 631341825Sdim {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ 632341825Sdim {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, 633341825Sdim 634341825Sdim/* Specs for the compiler proper */ 635303231Sdim 636341825Sdim#ifndef CC1_CPU_SPEC 637341825Sdim#define CC1_CPU_SPEC_1 "" 638341825Sdim 639341825Sdim#ifndef HAVE_LOCAL_CPU_DETECT 640341825Sdim#define CC1_CPU_SPEC CC1_CPU_SPEC_1 641341825Sdim#else 642341825Sdim#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ 643341825Sdim"%{march=native:%>march=native %:local_cpu_detect(arch) \ 644341825Sdim %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ 645341825Sdim%{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" 646341825Sdim#endif 647341825Sdim#endif 648341825Sdim 649341825Sdim/* Target CPU builtins. */ 650360784Sdim#define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () 651341825Sdim 652341825Sdim/* Target Pragmas. */ 653341825Sdim#define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () 654341825Sdim 655341825Sdim#ifndef CC1_SPEC 656341825Sdim#define CC1_SPEC "%(cc1_cpu) " 657353358Sdim#endif 658353358Sdim 659341825Sdim/* This macro defines names of additional specifications to put in the 660341825Sdim specs that can be used in various specifications like CC1_SPEC. Its 661341825Sdim definition is an initializer with a subgrouping for each command option. 662341825Sdim 663341825Sdim Each subgrouping contains a string constant, that defines the 664341825Sdim specification name, and a string constant that used by the GCC driver 665341825Sdim program. 666341825Sdim 667360784Sdim Do not define this macro if it does not need to do anything. */ 668341825Sdim 669341825Sdim#ifndef SUBTARGET_EXTRA_SPECS 670341825Sdim#define SUBTARGET_EXTRA_SPECS 671341825Sdim#endif 672341825Sdim 673341825Sdim#define EXTRA_SPECS \ 674341825Sdim { "cc1_cpu", CC1_CPU_SPEC }, \ 675341825Sdim SUBTARGET_EXTRA_SPECS 676341825Sdim 677341825Sdim 678353358Sdim/* Set the value of FLT_EVAL_METHOD in float.h. When using only the 679353358Sdim FPU, assume that the fpcw is set to extended precision; when using 680353358Sdim only SSE, rounding is correct; when using both SSE and the FPU, 681353358Sdim the rounding precision is indeterminate, since either may be chosen 682341825Sdim apparently at random. */ 683341825Sdim#define TARGET_FLT_EVAL_METHOD \ 684341825Sdim (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) 685341825Sdim 686341825Sdim/* Whether to allow x87 floating-point arithmetic on MODE (one of 687341825Sdim SFmode, DFmode and XFmode) in the current excess precision 688341825Sdim configuration. */ 689341825Sdim#define X87_ENABLE_ARITH(MODE) \ 690341825Sdim (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode) 691341825Sdim 692341825Sdim/* Likewise, whether to allow direct conversions from integer mode 693341825Sdim IMODE (HImode, SImode or DImode) to MODE. */ 694341825Sdim#define X87_ENABLE_FLOAT(MODE, IMODE) \ 695341825Sdim (flag_excess_precision == EXCESS_PRECISION_FAST \ 696341825Sdim || (MODE) == XFmode \ 697341825Sdim || ((MODE) == DFmode && (IMODE) == SImode) \ 698341825Sdim || (IMODE) == HImode) 699341825Sdim 700341825Sdim/* target machine storage layout */ 701341825Sdim 702341825Sdim#define SHORT_TYPE_SIZE 16 703341825Sdim#define INT_TYPE_SIZE 32 704341825Sdim#define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 705341825Sdim#define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 706341825Sdim#define LONG_LONG_TYPE_SIZE 64 707341825Sdim#define FLOAT_TYPE_SIZE 32 708341825Sdim#define DOUBLE_TYPE_SIZE 64 709353358Sdim#define LONG_DOUBLE_TYPE_SIZE \ 710353358Sdim (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80)) 711353358Sdim 712353358Sdim#define WIDEST_HARDWARE_FP_SIZE 80 713341825Sdim 714341825Sdim#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 715341825Sdim#define MAX_BITS_PER_WORD 64 716341825Sdim#else 717341825Sdim#define MAX_BITS_PER_WORD 32 718341825Sdim#endif 719341825Sdim 720341825Sdim/* Define this if most significant byte of a word is the lowest numbered. */ 721303231Sdim/* That is true on the 80386. */ 722303231Sdim 723303231Sdim#define BITS_BIG_ENDIAN 0 724303231Sdim 725303231Sdim/* Define this if most significant byte of a word is the lowest numbered. */ 726303231Sdim/* That is not true on the 80386. */ 727341825Sdim#define BYTES_BIG_ENDIAN 0 728341825Sdim 729341825Sdim/* Define this if most significant word of a multiword number is the lowest 730341825Sdim numbered. */ 731341825Sdim/* Not true for 80386 */ 732341825Sdim#define WORDS_BIG_ENDIAN 0 733341825Sdim 734341825Sdim/* Width of a word, in units (bytes). */ 735341825Sdim#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 736360784Sdim 737341825Sdim#ifndef IN_LIBGCC2 738341825Sdim#define MIN_UNITS_PER_WORD 4 739341825Sdim#endif 740341825Sdim 741341825Sdim/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 742341825Sdim#define PARM_BOUNDARY BITS_PER_WORD 743341825Sdim 744341825Sdim/* Boundary (in *bits*) on which stack pointer should be aligned. */ 745341825Sdim#define STACK_BOUNDARY \ 746360784Sdim (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) 747341825Sdim 748341825Sdim/* Stack boundary of the main function guaranteed by OS. */ 749341825Sdim#define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) 750341825Sdim 751341825Sdim/* Minimum stack boundary. */ 752341825Sdim#define MIN_STACK_BOUNDARY BITS_PER_WORD 753341825Sdim 754341825Sdim/* Boundary (in *bits*) on which the stack pointer prefers to be 755341825Sdim aligned; the compiler cannot rely on having this alignment. */ 756341825Sdim#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 757341825Sdim 758341825Sdim/* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for 759341825Sdim both 32bit and 64bit, to support codes that need 128 bit stack 760341825Sdim alignment for SSE instructions, but can't realign the stack. */ 761341825Sdim#define PREFERRED_STACK_BOUNDARY_DEFAULT 128 762341825Sdim 763341825Sdim/* 1 if -mstackrealign should be turned on by default. It will 764341825Sdim generate an alternate prologue and epilogue that realigns the 765341825Sdim runtime stack if nessary. This supports mixing codes that keep a 766341825Sdim 4-byte aligned stack, as specified by i386 psABI, with codes that 767341825Sdim need a 16-byte aligned stack, as required by SSE instructions. */ 768341825Sdim#define STACK_REALIGN_DEFAULT 0 769341825Sdim 770341825Sdim/* Boundary (in *bits*) on which the incoming stack is aligned. */ 771341825Sdim#define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary 772341825Sdim 773341825Sdim/* According to Windows x64 software convention, the maximum stack allocatable 774303231Sdim in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of 775341825Sdim instructions allowed to adjust the stack pointer in the epilog, forcing the 776341825Sdim use of frame pointer for frames larger than 2 GB. This theorical limit 777341825Sdim is reduced by 256, an over-estimated upper bound for the stack use by the 778341825Sdim prologue. 779341825Sdim We define only one threshold for both the prolog and the epilog. When the 780341825Sdim frame size is larger than this threshold, we allocate the area to save SSE 781341825Sdim regs, then save them, and then allocate the remaining. There is no SEH 782341825Sdim unwind info for this later allocation. */ 783341825Sdim#define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) 784341825Sdim 785341825Sdim/* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is 786341825Sdim mandatory for the 64-bit ABI, and may or may not be true for other 787303231Sdim operating systems. */ 788303231Sdim#define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT 789303231Sdim 790303231Sdim/* Minimum allocation boundary for the code of a function. */ 791303231Sdim#define FUNCTION_BOUNDARY 8 792303231Sdim 793303231Sdim/* C++ stores the virtual bit in the lowest bit of function pointers. */ 794303231Sdim#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 795303231Sdim 796/* Minimum size in bits of the largest boundary to which any 797 and all fundamental data types supported by the hardware 798 might need to be aligned. No data type wants to be aligned 799 rounder than this. 800 801 Pentium+ prefers DFmode values to be aligned to 64 bit boundary 802 and Pentium Pro XFmode values at 128 bit boundaries. 803 804 When increasing the maximum, also update 805 TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */ 806 807#define BIGGEST_ALIGNMENT \ 808 (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128)) 809 810/* Maximum stack alignment. */ 811#define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT 812 813/* Alignment value for attribute ((aligned)). It is a constant since 814 it is the part of the ABI. We shouldn't change it with -mavx. */ 815#define ATTRIBUTE_ALIGNED_VALUE 128 816 817/* Decide whether a variable of mode MODE should be 128 bit aligned. */ 818#define ALIGN_MODE_128(MODE) \ 819 ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) 820 821/* The published ABIs say that doubles should be aligned on word 822 boundaries, so lower the alignment for structure fields unless 823 -malign-double is set. */ 824 825/* ??? Blah -- this macro is used directly by libobjc. Since it 826 supports no vector modes, cut out the complexity and fall back 827 on BIGGEST_FIELD_ALIGNMENT. */ 828#ifdef IN_TARGET_LIBS 829#ifdef __x86_64__ 830#define BIGGEST_FIELD_ALIGNMENT 128 831#else 832#define BIGGEST_FIELD_ALIGNMENT 32 833#endif 834#else 835#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 836 x86_field_alignment (FIELD, COMPUTED) 837#endif 838 839/* If defined, a C expression to compute the alignment given to a 840 constant that is being placed in memory. EXP is the constant 841 and ALIGN is the alignment that the object would ordinarily have. 842 The value of this macro is used instead of that alignment to align 843 the object. 844 845 If this macro is not defined, then ALIGN is used. 846 847 The typical use of this macro is to increase alignment for string 848 constants to be word aligned so that `strcpy' calls that copy 849 constants can be done inline. */ 850 851#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 852 853/* If defined, a C expression to compute the alignment for a static 854 variable. TYPE is the data type, and ALIGN is the alignment that 855 the object would ordinarily have. The value of this macro is used 856 instead of that alignment to align the object. 857 858 If this macro is not defined, then ALIGN is used. 859 860 One use of this macro is to increase alignment of medium-size 861 data to make it all fit in fewer cache lines. Another is to 862 cause character arrays to be word-aligned so that `strcpy' calls 863 that copy constants to character arrays can be done inline. */ 864 865#define DATA_ALIGNMENT(TYPE, ALIGN) \ 866 ix86_data_alignment ((TYPE), (ALIGN), true) 867 868/* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates 869 some alignment increase, instead of optimization only purposes. E.g. 870 AMD x86-64 psABI says that variables with array type larger than 15 bytes 871 must be aligned to 16 byte boundaries. 872 873 If this macro is not defined, then ALIGN is used. */ 874 875#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ 876 ix86_data_alignment ((TYPE), (ALIGN), false) 877 878/* If defined, a C expression to compute the alignment for a local 879 variable. TYPE is the data type, and ALIGN is the alignment that 880 the object would ordinarily have. The value of this macro is used 881 instead of that alignment to align the object. 882 883 If this macro is not defined, then ALIGN is used. 884 885 One use of this macro is to increase alignment of medium-size 886 data to make it all fit in fewer cache lines. */ 887 888#define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 889 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) 890 891/* If defined, a C expression to compute the alignment for stack slot. 892 TYPE is the data type, MODE is the widest mode available, and ALIGN 893 is the alignment that the slot would ordinarily have. The value of 894 this macro is used instead of that alignment to align the slot. 895 896 If this macro is not defined, then ALIGN is used when TYPE is NULL, 897 Otherwise, LOCAL_ALIGNMENT will be used. 898 899 One use of this macro is to set alignment of stack slot to the 900 maximum alignment of all possible modes which the slot may have. */ 901 902#define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ 903 ix86_local_alignment ((TYPE), (MODE), (ALIGN)) 904 905/* If defined, a C expression to compute the alignment for a local 906 variable DECL. 907 908 If this macro is not defined, then 909 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. 910 911 One use of this macro is to increase alignment of medium-size 912 data to make it all fit in fewer cache lines. */ 913 914#define LOCAL_DECL_ALIGNMENT(DECL) \ 915 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) 916 917/* If defined, a C expression to compute the minimum required alignment 918 for dynamic stack realignment purposes for EXP (a TYPE or DECL), 919 MODE, assuming normal alignment ALIGN. 920 921 If this macro is not defined, then (ALIGN) will be used. */ 922 923#define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ 924 ix86_minimum_alignment (EXP, MODE, ALIGN) 925 926 927/* Set this nonzero if move instructions will actually fail to work 928 when given unaligned data. */ 929#define STRICT_ALIGNMENT 0 930 931/* If bit field type is int, don't let it cross an int, 932 and give entire struct the alignment of an int. */ 933/* Required on the 386 since it doesn't have bit-field insns. */ 934#define PCC_BITFIELD_TYPE_MATTERS 1 935 936/* Standard register usage. */ 937 938/* This processor has special stack-like registers. See reg-stack.c 939 for details. */ 940 941#define STACK_REGS 942 943#define IS_STACK_MODE(MODE) \ 944 (((MODE) == SFmode && !(TARGET_SSE && TARGET_SSE_MATH)) \ 945 || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \ 946 || (MODE) == XFmode) 947 948/* Number of actual hardware registers. 949 The hardware registers are assigned numbers for the compiler 950 from 0 to just below FIRST_PSEUDO_REGISTER. 951 All registers that the compiler knows about must be given numbers, 952 even those that are not normally considered general registers. 953 954 In the 80386 we give the 8 general purpose registers the numbers 0-7. 955 We number the floating point registers 8-15. 956 Note that registers 0-7 can be accessed as a short or int, 957 while only 0-3 may be used with byte `mov' instructions. 958 959 Reg 16 does not correspond to any hardware register, but instead 960 appears in the RTL as an argument pointer prior to reload, and is 961 eliminated during reloading in favor of either the stack or frame 962 pointer. */ 963 964#define FIRST_PSEUDO_REGISTER 81 965 966/* Number of hardware registers that go into the DWARF-2 unwind info. 967 If not defined, equals FIRST_PSEUDO_REGISTER. */ 968 969#define DWARF_FRAME_REGISTERS 17 970 971/* 1 for registers that have pervasive standard uses 972 and are not available for the register allocator. 973 On the 80386, the stack pointer is such, as is the arg pointer. 974 975 REX registers are disabled for 32bit targets in 976 TARGET_CONDITIONAL_REGISTER_USAGE. */ 977 978#define FIXED_REGISTERS \ 979/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 980{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 981/*arg,flags,fpsr,fpcr,frame*/ \ 982 1, 1, 1, 1, 1, \ 983/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 984 0, 0, 0, 0, 0, 0, 0, 0, \ 985/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 986 0, 0, 0, 0, 0, 0, 0, 0, \ 987/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 988 0, 0, 0, 0, 0, 0, 0, 0, \ 989/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 990 0, 0, 0, 0, 0, 0, 0, 0, \ 991/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ 992 0, 0, 0, 0, 0, 0, 0, 0, \ 993/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ 994 0, 0, 0, 0, 0, 0, 0, 0, \ 995/* k0, k1, k2, k3, k4, k5, k6, k7*/ \ 996 0, 0, 0, 0, 0, 0, 0, 0, \ 997/* b0, b1, b2, b3*/ \ 998 0, 0, 0, 0 } 999 1000/* 1 for registers not available across function calls. 1001 These must include the FIXED_REGISTERS and also any 1002 registers that can be used without being saved. 1003 The latter must include the registers where values are returned 1004 and the register where structure-value addresses are passed. 1005 Aside from that, you can include as many other registers as you like. 1006 1007 Value is set to 1 if the register is call used unconditionally. 1008 Bit one is set if the register is call used on TARGET_32BIT ABI. 1009 Bit two is set if the register is call used on TARGET_64BIT ABI. 1010 Bit three is set if the register is call used on TARGET_64BIT_MS_ABI. 1011 1012 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ 1013 1014#define CALL_USED_REGISTERS \ 1015/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 1016{ 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1017/*arg,flags,fpsr,fpcr,frame*/ \ 1018 1, 1, 1, 1, 1, \ 1019/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 1020 1, 1, 1, 1, 1, 1, 6, 6, \ 1021/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 1022 1, 1, 1, 1, 1, 1, 1, 1, \ 1023/* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 1024 1, 1, 1, 1, 2, 2, 2, 2, \ 1025/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 1026 6, 6, 6, 6, 6, 6, 6, 6, \ 1027/*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ 1028 6, 6, 6, 6, 6, 6, 6, 6, \ 1029/*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ 1030 6, 6, 6, 6, 6, 6, 6, 6, \ 1031 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ 1032 1, 1, 1, 1, 1, 1, 1, 1, \ 1033/* b0, b1, b2, b3*/ \ 1034 1, 1, 1, 1 } 1035 1036/* Order in which to allocate registers. Each register must be 1037 listed once, even those in FIXED_REGISTERS. List frame pointer 1038 late and fixed registers last. Note that, in general, we prefer 1039 registers listed in CALL_USED_REGISTERS, keeping the others 1040 available for storage of persistent values. 1041 1042 The ADJUST_REG_ALLOC_ORDER actually overwrite the order, 1043 so this is just empty initializer for array. */ 1044 1045#define REG_ALLOC_ORDER \ 1046{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 1047 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 1048 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 1049 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \ 1050 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, \ 1051 78, 79, 80 } 1052 1053/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order 1054 to be rearranged based on a particular function. When using sse math, 1055 we want to allocate SSE before x87 registers and vice versa. */ 1056 1057#define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () 1058 1059 1060#define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) 1061 1062/* Return number of consecutive hard regs needed starting at reg REGNO 1063 to hold something of mode MODE. 1064 This is ordinarily the length in words of a value of mode MODE 1065 but can be less for certain modes in special long registers. 1066 1067 Actually there are no two word move instructions for consecutive 1068 registers. And only registers 0-3 may have mov byte instructions 1069 applied to them. */ 1070 1071#define HARD_REGNO_NREGS(REGNO, MODE) \ 1072 (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 1073 || MASK_REGNO_P (REGNO) || BND_REGNO_P (REGNO) \ 1074 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1075 : ((MODE) == XFmode \ 1076 ? (TARGET_64BIT ? 2 : 3) \ 1077 : (MODE) == XCmode \ 1078 ? (TARGET_64BIT ? 4 : 6) \ 1079 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 1080 1081#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ 1082 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ 1083 ? (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 1084 ? 0 \ 1085 : ((MODE) == XFmode || (MODE) == XCmode)) \ 1086 : 0) 1087 1088#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) 1089 1090#define VALID_AVX256_REG_MODE(MODE) \ 1091 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1092 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ 1093 || (MODE) == V4DFmode) 1094 1095#define VALID_AVX256_REG_OR_OI_MODE(MODE) \ 1096 (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode) 1097 1098#define VALID_AVX512F_SCALAR_MODE(MODE) \ 1099 ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \ 1100 || (MODE) == SFmode) 1101 1102#define VALID_AVX512F_REG_MODE(MODE) \ 1103 ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \ 1104 || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \ 1105 || (MODE) == V4TImode) 1106 1107#define VALID_AVX512VL_128_REG_MODE(MODE) \ 1108 ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \ 1109 || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode) 1110 1111#define VALID_SSE2_REG_MODE(MODE) \ 1112 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1113 || (MODE) == V2DImode || (MODE) == DFmode) 1114 1115#define VALID_SSE_REG_MODE(MODE) \ 1116 ((MODE) == V1TImode || (MODE) == TImode \ 1117 || (MODE) == V4SFmode || (MODE) == V4SImode \ 1118 || (MODE) == SFmode || (MODE) == TFmode) 1119 1120#define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1121 ((MODE) == V2SFmode || (MODE) == SFmode) 1122 1123#define VALID_MMX_REG_MODE(MODE) \ 1124 ((MODE == V1DImode) || (MODE) == DImode \ 1125 || (MODE) == V2SImode || (MODE) == SImode \ 1126 || (MODE) == V4HImode || (MODE) == V8QImode) 1127 1128#define VALID_BND_REG_MODE(MODE) \ 1129 (TARGET_64BIT ? (MODE) == BND64mode : (MODE) == BND32mode) 1130 1131#define VALID_DFP_MODE_P(MODE) \ 1132 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) 1133 1134#define VALID_FP_MODE_P(MODE) \ 1135 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 1136 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 1137 1138#define VALID_INT_MODE_P(MODE) \ 1139 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1140 || (MODE) == DImode \ 1141 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1142 || (MODE) == CDImode \ 1143 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 1144 || (MODE) == TFmode || (MODE) == TCmode))) 1145 1146/* Return true for modes passed in SSE registers. */ 1147#define SSE_REG_MODE_P(MODE) \ 1148 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ 1149 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1150 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1151 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1152 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ 1153 || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \ 1154 || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \ 1155 || (MODE) == V16SFmode) 1156 1157#define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode) 1158 1159#define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode) 1160 1161/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 1162 1163#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1164 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 1165 1166/* Value is 1 if it is a good idea to tie two pseudo registers 1167 when one has mode MODE1 and one has mode MODE2. 1168 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1169 for any hard reg, then this must be 0 for correct output. */ 1170 1171#define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) 1172 1173/* It is possible to write patterns to move flags; but until someone 1174 does it, */ 1175#define AVOID_CCMODE_COPIES 1176 1177/* Specify the modes required to caller save a given hard regno. 1178 We do this on i386 to prevent flags from being saved at all. 1179 1180 Kill any attempts to combine saving of modes. */ 1181 1182#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1183 (CC_REGNO_P (REGNO) ? VOIDmode \ 1184 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1185 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ 1186 : (MODE) == HImode && !(TARGET_PARTIAL_REG_STALL \ 1187 || MASK_REGNO_P (REGNO)) ? SImode \ 1188 : (MODE) == QImode && !(TARGET_64BIT || QI_REGNO_P (REGNO) \ 1189 || MASK_REGNO_P (REGNO)) ? SImode \ 1190 : (MODE)) 1191 1192/* The only ABI that saves SSE registers across calls is Win64 (thus no 1193 need to check the current ABI here), and with AVX enabled Win64 only 1194 guarantees that the low 16 bytes are saved. */ 1195#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 1196 (SSE_REGNO_P (REGNO) && GET_MODE_SIZE (MODE) > 16) 1197 1198/* Specify the registers used for certain standard purposes. 1199 The values of these macros are register numbers. */ 1200 1201/* on the 386 the pc register is %eip, and is not usable as a general 1202 register. The ordinary mov instructions won't work */ 1203/* #define PC_REGNUM */ 1204 1205/* Register to use for pushing function arguments. */ 1206#define STACK_POINTER_REGNUM 7 1207 1208/* Base register for access to local variables of the function. */ 1209#define HARD_FRAME_POINTER_REGNUM 6 1210 1211/* Base register for access to local variables of the function. */ 1212#define FRAME_POINTER_REGNUM 20 1213 1214/* First floating point reg */ 1215#define FIRST_FLOAT_REG 8 1216 1217/* First & last stack-like regs */ 1218#define FIRST_STACK_REG FIRST_FLOAT_REG 1219#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1220 1221#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1222#define LAST_SSE_REG (FIRST_SSE_REG + 7) 1223 1224#define FIRST_MMX_REG (LAST_SSE_REG + 1) /*29*/ 1225#define LAST_MMX_REG (FIRST_MMX_REG + 7) 1226 1227#define FIRST_REX_INT_REG (LAST_MMX_REG + 1) /*37*/ 1228#define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1229 1230#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) /*45*/ 1231#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1232 1233#define FIRST_EXT_REX_SSE_REG (LAST_REX_SSE_REG + 1) /*53*/ 1234#define LAST_EXT_REX_SSE_REG (FIRST_EXT_REX_SSE_REG + 15) /*68*/ 1235 1236#define FIRST_MASK_REG (LAST_EXT_REX_SSE_REG + 1) /*69*/ 1237#define LAST_MASK_REG (FIRST_MASK_REG + 7) /*76*/ 1238 1239#define FIRST_BND_REG (LAST_MASK_REG + 1) /*77*/ 1240#define LAST_BND_REG (FIRST_BND_REG + 3) /*80*/ 1241 1242/* Override this in other tm.h files to cope with various OS lossage 1243 requiring a frame pointer. */ 1244#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1245#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1246#endif 1247 1248/* Make sure we can access arbitrary call frames. */ 1249#define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1250 1251/* Base register for access to arguments of the function. */ 1252#define ARG_POINTER_REGNUM 16 1253 1254/* Register to hold the addressing base for position independent 1255 code access to data items. We don't use PIC pointer for 64bit 1256 mode. Define the regnum to dummy value to prevent gcc from 1257 pessimizing code dealing with EBX. 1258 1259 To avoid clobbering a call-saved register unnecessarily, we renumber 1260 the pic register when possible. The change is visible after the 1261 prologue has been emitted. */ 1262 1263#define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG) 1264 1265#define PIC_OFFSET_TABLE_REGNUM \ 1266 (ix86_use_pseudo_pic_reg () \ 1267 ? (pic_offset_table_rtx \ 1268 ? INVALID_REGNUM \ 1269 : REAL_PIC_OFFSET_TABLE_REGNUM) \ 1270 : INVALID_REGNUM) 1271 1272#define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1273 1274/* This is overridden by <cygwin.h>. */ 1275#define MS_AGGREGATE_RETURN 0 1276 1277#define KEEP_AGGREGATE_RETURN_POINTER 0 1278 1279/* Define the classes of registers for register constraints in the 1280 machine description. Also define ranges of constants. 1281 1282 One of the classes must always be named ALL_REGS and include all hard regs. 1283 If there is more than one class, another class must be named NO_REGS 1284 and contain no registers. 1285 1286 The name GENERAL_REGS must be the name of a class (or an alias for 1287 another name such as ALL_REGS). This is the class of registers 1288 that is allowed by "g" or "r" in a register constraint. 1289 Also, registers outside this class are allocated only when 1290 instructions express preferences for them. 1291 1292 The classes must be numbered in nondecreasing order; that is, 1293 a larger-numbered class must never be contained completely 1294 in a smaller-numbered class. 1295 1296 For any two classes, it is very desirable that there be another 1297 class that represents their union. 1298 1299 It might seem that class BREG is unnecessary, since no useful 386 1300 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1301 and the "b" register constraint is useful in asms for syscalls. 1302 1303 The flags, fpsr and fpcr registers are in no class. */ 1304 1305enum reg_class 1306{ 1307 NO_REGS, 1308 AREG, DREG, CREG, BREG, SIREG, DIREG, 1309 AD_REGS, /* %eax/%edx for DImode */ 1310 Q_REGS, /* %eax %ebx %ecx %edx */ 1311 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1312 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1313 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1314 CLOBBERED_REGS, /* call-clobbered integer registers */ 1315 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp 1316 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ 1317 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1318 FLOAT_REGS, 1319 SSE_FIRST_REG, 1320 NO_REX_SSE_REGS, 1321 SSE_REGS, 1322 EVEX_SSE_REGS, 1323 BND_REGS, 1324 ALL_SSE_REGS, 1325 MMX_REGS, 1326 FP_TOP_SSE_REGS, 1327 FP_SECOND_SSE_REGS, 1328 FLOAT_SSE_REGS, 1329 FLOAT_INT_REGS, 1330 INT_SSE_REGS, 1331 FLOAT_INT_SSE_REGS, 1332 MASK_EVEX_REGS, 1333 MASK_REGS, 1334 ALL_REGS, LIM_REG_CLASSES 1335}; 1336 1337#define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1338 1339#define INTEGER_CLASS_P(CLASS) \ 1340 reg_class_subset_p ((CLASS), GENERAL_REGS) 1341#define FLOAT_CLASS_P(CLASS) \ 1342 reg_class_subset_p ((CLASS), FLOAT_REGS) 1343#define SSE_CLASS_P(CLASS) \ 1344 reg_class_subset_p ((CLASS), ALL_SSE_REGS) 1345#define MMX_CLASS_P(CLASS) \ 1346 ((CLASS) == MMX_REGS) 1347#define MAYBE_INTEGER_CLASS_P(CLASS) \ 1348 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1349#define MAYBE_FLOAT_CLASS_P(CLASS) \ 1350 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1351#define MAYBE_SSE_CLASS_P(CLASS) \ 1352 reg_classes_intersect_p ((CLASS), ALL_SSE_REGS) 1353#define MAYBE_MMX_CLASS_P(CLASS) \ 1354 reg_classes_intersect_p ((CLASS), MMX_REGS) 1355#define MAYBE_MASK_CLASS_P(CLASS) \ 1356 reg_classes_intersect_p ((CLASS), MASK_REGS) 1357 1358#define Q_CLASS_P(CLASS) \ 1359 reg_class_subset_p ((CLASS), Q_REGS) 1360 1361#define MAYBE_NON_Q_CLASS_P(CLASS) \ 1362 reg_classes_intersect_p ((CLASS), NON_Q_REGS) 1363 1364/* Give names of register classes as strings for dump file. */ 1365 1366#define REG_CLASS_NAMES \ 1367{ "NO_REGS", \ 1368 "AREG", "DREG", "CREG", "BREG", \ 1369 "SIREG", "DIREG", \ 1370 "AD_REGS", \ 1371 "Q_REGS", "NON_Q_REGS", \ 1372 "INDEX_REGS", \ 1373 "LEGACY_REGS", \ 1374 "CLOBBERED_REGS", \ 1375 "GENERAL_REGS", \ 1376 "FP_TOP_REG", "FP_SECOND_REG", \ 1377 "FLOAT_REGS", \ 1378 "SSE_FIRST_REG", \ 1379 "NO_REX_SSE_REGS", \ 1380 "SSE_REGS", \ 1381 "EVEX_SSE_REGS", \ 1382 "BND_REGS", \ 1383 "ALL_SSE_REGS", \ 1384 "MMX_REGS", \ 1385 "FP_TOP_SSE_REGS", \ 1386 "FP_SECOND_SSE_REGS", \ 1387 "FLOAT_SSE_REGS", \ 1388 "FLOAT_INT_REGS", \ 1389 "INT_SSE_REGS", \ 1390 "FLOAT_INT_SSE_REGS", \ 1391 "MASK_EVEX_REGS", \ 1392 "MASK_REGS", \ 1393 "ALL_REGS" } 1394 1395/* Define which registers fit in which classes. This is an initializer 1396 for a vector of HARD_REG_SET of length N_REG_CLASSES. 1397 1398 Note that CLOBBERED_REGS are calculated by 1399 TARGET_CONDITIONAL_REGISTER_USAGE. */ 1400 1401#define REG_CLASS_CONTENTS \ 1402{ { 0x00, 0x0, 0x0 }, \ 1403 { 0x01, 0x0, 0x0 }, /* AREG */ \ 1404 { 0x02, 0x0, 0x0 }, /* DREG */ \ 1405 { 0x04, 0x0, 0x0 }, /* CREG */ \ 1406 { 0x08, 0x0, 0x0 }, /* BREG */ \ 1407 { 0x10, 0x0, 0x0 }, /* SIREG */ \ 1408 { 0x20, 0x0, 0x0 }, /* DIREG */ \ 1409 { 0x03, 0x0, 0x0 }, /* AD_REGS */ \ 1410 { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \ 1411 { 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \ 1412 { 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \ 1413 { 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ 1414 { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \ 1415 { 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \ 1416 { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ 1417 { 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ 1418 { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \ 1419 { 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \ 1420{ 0x1fe00000, 0x000000, 0x0 }, /* NO_REX_SSE_REGS */ \ 1421{ 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \ 1422 { 0x0,0xffe00000, 0x1f }, /* EVEX_SSE_REGS */ \ 1423 { 0x0, 0x0,0x1e000 }, /* BND_REGS */ \ 1424{ 0x1fe00000,0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \ 1425{ 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \ 1426{ 0x1fe00100,0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \ 1427{ 0x1fe00200,0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \ 1428{ 0x1fe0ff00,0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \ 1429{ 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \ 1430{ 0x1ff100ff,0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \ 1431{ 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \ 1432 { 0x0, 0x0, 0x1fc0 }, /* MASK_EVEX_REGS */ \ 1433 { 0x0, 0x0, 0x1fe0 }, /* MASK_REGS */ \ 1434{ 0xffffffff,0xffffffff,0x1ffff } \ 1435} 1436 1437/* The same information, inverted: 1438 Return the class number of the smallest class containing 1439 reg number REGNO. This could be a conditional expression 1440 or could index an array. */ 1441 1442#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1443 1444/* When this hook returns true for MODE, the compiler allows 1445 registers explicitly used in the rtl to be used as spill registers 1446 but prevents the compiler from extending the lifetime of these 1447 registers. */ 1448#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 1449 1450#define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X))) 1451#define QI_REGNO_P(N) IN_RANGE ((N), AX_REG, BX_REG) 1452 1453#define GENERAL_REG_P(X) \ 1454 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1455#define GENERAL_REGNO_P(N) \ 1456 (IN_RANGE ((N), AX_REG, SP_REG) || REX_INT_REGNO_P (N)) 1457 1458#define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X))) 1459#define ANY_QI_REGNO_P(N) \ 1460 (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N)) 1461 1462#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1463#define REX_INT_REGNO_P(N) \ 1464 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) 1465 1466#define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X))) 1467#define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) 1468 1469#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1470#define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N)) 1471 1472#define X87_FLOAT_MODE_P(MODE) \ 1473 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) 1474 1475#define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X))) 1476#define SSE_REGNO_P(N) \ 1477 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ 1478 || REX_SSE_REGNO_P (N) \ 1479 || EXT_REX_SSE_REGNO_P (N)) 1480 1481#define REX_SSE_REGNO_P(N) \ 1482 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) 1483 1484#define EXT_REX_SSE_REGNO_P(N) \ 1485 IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG) 1486 1487#define SSE_REGNO(N) \ 1488 ((N) < 8 ? FIRST_SSE_REG + (N) \ 1489 : (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \ 1490 : (FIRST_EXT_REX_SSE_REG + (N) - 16)) 1491 1492#define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X))) 1493#define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG) 1494#define ANY_MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X))) 1495 1496#define SSE_FLOAT_MODE_P(MODE) \ 1497 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1498 1499#define FMA4_VEC_FLOAT_MODE_P(MODE) \ 1500 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ 1501 || (MODE) == V8SFmode || (MODE) == V4DFmode)) 1502 1503#define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X))) 1504#define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) 1505 1506#define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_STACK_REG) 1507 1508#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1509#define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1510 1511#define BND_REGNO_P(N) IN_RANGE ((N), FIRST_BND_REG, LAST_BND_REG) 1512#define ANY_BND_REG_P(X) (REG_P (X) && BND_REGNO_P (REGNO (X))) 1513 1514/* The class value for index registers, and the one for base regs. */ 1515 1516#define INDEX_REG_CLASS INDEX_REGS 1517#define BASE_REG_CLASS GENERAL_REGS 1518 1519/* Place additional restrictions on the register class to use when it 1520 is necessary to be able to hold a value of mode MODE in a reload 1521 register for which class CLASS would ordinarily be used. 1522 1523 We avoid classes containing registers from multiple units due to 1524 the limitation in ix86_secondary_memory_needed. We limit these 1525 classes to their "natural mode" single unit register class, depending 1526 on the unit availability. 1527 1528 Please note that reg_class_subset_p is not commutative, so these 1529 conditions mean "... if (CLASS) includes ALL registers from the 1530 register set." */ 1531 1532#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1533 (((MODE) == QImode && !TARGET_64BIT \ 1534 && reg_class_subset_p (Q_REGS, (CLASS))) ? Q_REGS \ 1535 : (((MODE) == SImode || (MODE) == DImode) \ 1536 && reg_class_subset_p (GENERAL_REGS, (CLASS))) ? GENERAL_REGS \ 1537 : (SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH \ 1538 && reg_class_subset_p (SSE_REGS, (CLASS))) ? SSE_REGS \ 1539 : (X87_FLOAT_MODE_P (MODE) \ 1540 && reg_class_subset_p (FLOAT_REGS, (CLASS))) ? FLOAT_REGS \ 1541 : (CLASS)) 1542 1543/* If we are copying between general and FP registers, we need a memory 1544 location. The same is true for SSE and MMX registers. */ 1545#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1546 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1547 1548/* Get_secondary_mem widens integral modes to BITS_PER_WORD. 1549 There is no need to emit full 64 bit move on 64 bit targets 1550 for integral modes that can be moved using 32 bit move. */ 1551#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1552 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \ 1553 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 1554 : MODE) 1555 1556/* Return a class of registers that cannot change FROM mode to TO mode. */ 1557 1558#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1559 ix86_cannot_change_mode_class (FROM, TO, CLASS) 1560 1561/* Stack layout; function entry, exit and calling. */ 1562 1563/* Define this if pushing a word on the stack 1564 makes the stack pointer a smaller address. */ 1565#define STACK_GROWS_DOWNWARD 1566 1567/* Define this to nonzero if the nominal address of the stack frame 1568 is at the high-address end of the local variables; 1569 that is, each additional local variable allocated 1570 goes at a more negative offset in the frame. */ 1571#define FRAME_GROWS_DOWNWARD 1 1572 1573/* Offset within stack frame to start allocating local variables at. 1574 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1575 first local allocated. Otherwise, it is the offset to the BEGINNING 1576 of the first local allocated. */ 1577#define STARTING_FRAME_OFFSET 0 1578 1579/* If we generate an insn to push BYTES bytes, this says how many the stack 1580 pointer really advances by. On 386, we have pushw instruction that 1581 decrements by exactly 2 no matter what the position was, there is no pushb. 1582 1583 But as CIE data alignment factor on this arch is -4 for 32bit targets 1584 and -8 for 64bit targets, we need to make sure all stack pointer adjustments 1585 are in multiple of 4 for 32bit targets and 8 for 64bit targets. */ 1586 1587#define PUSH_ROUNDING(BYTES) \ 1588 (((BYTES) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD) 1589 1590/* If defined, the maximum amount of space required for outgoing arguments 1591 will be computed and placed into the variable `crtl->outgoing_args_size'. 1592 No space will be pushed onto the stack for each call; instead, the 1593 function prologue should increase the stack frame size by this amount. 1594 1595 In 32bit mode enabling argument accumulation results in about 5% code size 1596 growth becuase move instructions are less compact than push. In 64bit 1597 mode the difference is less drastic but visible. 1598 1599 FIXME: Unlike earlier implementations, the size of unwind info seems to 1600 actually grow with accumulation. Is that because accumulated args 1601 unwind info became unnecesarily bloated? 1602 1603 With the 64-bit MS ABI, we can generate correct code with or without 1604 accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code 1605 generated without accumulated args is terrible. 1606 1607 If stack probes are required, the space used for large function 1608 arguments on the stack must also be probed, so enable 1609 -maccumulate-outgoing-args so this happens in the prologue. */ 1610 1611#define ACCUMULATE_OUTGOING_ARGS \ 1612 ((TARGET_ACCUMULATE_OUTGOING_ARGS && optimize_function_for_speed_p (cfun)) \ 1613 || TARGET_STACK_PROBE || TARGET_64BIT_MS_ABI) 1614 1615/* If defined, a C expression whose value is nonzero when we want to use PUSH 1616 instructions to pass outgoing arguments. */ 1617 1618#define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1619 1620/* We want the stack and args grow in opposite directions, even if 1621 PUSH_ARGS is 0. */ 1622#define PUSH_ARGS_REVERSED 1 1623 1624/* Offset of first parameter from the argument pointer register value. */ 1625#define FIRST_PARM_OFFSET(FNDECL) 0 1626 1627/* Define this macro if functions should assume that stack space has been 1628 allocated for arguments even when their values are passed in registers. 1629 1630 The value of this macro is the size, in bytes, of the area reserved for 1631 arguments passed in registers for the function represented by FNDECL. 1632 1633 This space can be allocated by the caller, or be a part of the 1634 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1635 which. */ 1636#define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) 1637 1638#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ 1639 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI) 1640 1641/* Define how to find the value returned by a library function 1642 assuming the value has mode MODE. */ 1643 1644#define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) 1645 1646/* Define the size of the result block used for communication between 1647 untyped_call and untyped_return. The block contains a DImode value 1648 followed by the block used by fnsave and frstor. */ 1649 1650#define APPLY_RESULT_SIZE (8+108) 1651 1652/* 1 if N is a possible register number for function argument passing. */ 1653#define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1654 1655/* Define a data type for recording info about an argument list 1656 during the scan of that argument list. This data type should 1657 hold all necessary information about the function itself 1658 and about the args processed so far, enough to enable macros 1659 such as FUNCTION_ARG to determine where the next arg should go. */ 1660 1661typedef struct ix86_args { 1662 int words; /* # words passed so far */ 1663 int nregs; /* # registers available for passing */ 1664 int regno; /* next available register number */ 1665 int fastcall; /* fastcall or thiscall calling convention 1666 is used */ 1667 int sse_words; /* # sse words passed so far */ 1668 int sse_nregs; /* # sse registers available for passing */ 1669 int warn_avx512f; /* True when we want to warn 1670 about AVX512F ABI. */ 1671 int warn_avx; /* True when we want to warn about AVX ABI. */ 1672 int warn_sse; /* True when we want to warn about SSE ABI. */ 1673 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1674 int sse_regno; /* next available sse register number */ 1675 int mmx_words; /* # mmx words passed so far */ 1676 int mmx_nregs; /* # mmx registers available for passing */ 1677 int mmx_regno; /* next available mmx register number */ 1678 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1679 int caller; /* true if it is caller. */ 1680 int float_in_sse; /* Set to 1 or 2 for 32bit targets if 1681 SFmode/DFmode arguments should be passed 1682 in SSE registers. Otherwise 0. */ 1683 int bnd_regno; /* next available bnd register number */ 1684 int bnds_in_bt; /* number of bounds expected in BT. */ 1685 int force_bnd_pass; /* number of bounds expected for stdarg arg. */ 1686 int stdarg; /* Set to 1 if function is stdarg. */ 1687 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise 1688 MS_ABI for ms abi. */ 1689 tree decl; /* Callee decl. */ 1690} CUMULATIVE_ARGS; 1691 1692/* Initialize a variable CUM of type CUMULATIVE_ARGS 1693 for a call to a function whose data type is FNTYPE. 1694 For a library call, FNTYPE is 0. */ 1695 1696#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1697 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ 1698 (N_NAMED_ARGS) != -1) 1699 1700/* Output assembler code to FILE to increment profiler label # LABELNO 1701 for profiling a function entry. */ 1702 1703#define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) 1704 1705#define MCOUNT_NAME "_mcount" 1706 1707#define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__" 1708 1709#define PROFILE_COUNT_REGISTER "edx" 1710 1711/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1712 the stack pointer does not matter. The value is tested only in 1713 functions that have frame pointers. 1714 No definition is equivalent to always zero. */ 1715/* Note on the 386 it might be more efficient not to define this since 1716 we have to restore it ourselves from the frame pointer, in order to 1717 use pop */ 1718 1719#define EXIT_IGNORE_STACK 1 1720 1721/* Output assembler code for a block containing the constant parts 1722 of a trampoline, leaving space for the variable parts. */ 1723 1724/* On the 386, the trampoline contains two instructions: 1725 mov #STATIC,ecx 1726 jmp FUNCTION 1727 The trampoline is generated entirely at runtime. The operand of JMP 1728 is the address of FUNCTION relative to the instruction following the 1729 JMP (which is 5 bytes long). */ 1730 1731/* Length in units of the trampoline for entering a nested function. */ 1732 1733#define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10) 1734 1735/* Definitions for register eliminations. 1736 1737 This is an array of structures. Each structure initializes one pair 1738 of eliminable registers. The "from" register number is given first, 1739 followed by "to". Eliminations of the same "from" register are listed 1740 in order of preference. 1741 1742 There are two registers that can always be eliminated on the i386. 1743 The frame pointer and the arg pointer can be replaced by either the 1744 hard frame pointer or to the stack pointer, depending upon the 1745 circumstances. The hard frame pointer is not used before reload and 1746 so it is not eligible for elimination. */ 1747 1748#define ELIMINABLE_REGS \ 1749{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1750 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1751 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1752 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1753 1754/* Define the offset between two registers, one to be eliminated, and the other 1755 its replacement, at the start of a routine. */ 1756 1757#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1758 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1759 1760/* Addressing modes, and classification of registers for them. */ 1761 1762/* Macros to check register numbers against specific register classes. */ 1763 1764/* These assume that REGNO is a hard or pseudo reg number. 1765 They give nonzero only if REGNO is a hard reg of the suitable class 1766 or a pseudo reg currently allocated to a suitable hard reg. 1767 Since they use reg_renumber, they are safe only once reg_renumber 1768 has been allocated, which happens in reginfo.c during register 1769 allocation. */ 1770 1771#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1772 ((REGNO) < STACK_POINTER_REGNUM \ 1773 || REX_INT_REGNO_P (REGNO) \ 1774 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ 1775 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1776 1777#define REGNO_OK_FOR_BASE_P(REGNO) \ 1778 (GENERAL_REGNO_P (REGNO) \ 1779 || (REGNO) == ARG_POINTER_REGNUM \ 1780 || (REGNO) == FRAME_POINTER_REGNUM \ 1781 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1782 1783/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1784 and check its validity for a certain class. 1785 We have two alternate definitions for each of them. 1786 The usual definition accepts all pseudo regs; the other rejects 1787 them unless they have been allocated suitable hard regs. 1788 The symbol REG_OK_STRICT causes the latter definition to be used. 1789 1790 Most source files want to accept pseudo regs in the hope that 1791 they will get allocated to the class that the insn wants them to be in. 1792 Source files for reload pass need to be strict. 1793 After reload, it makes no difference, since pseudo regs have 1794 been eliminated by then. */ 1795 1796 1797/* Non strict versions, pseudos are ok. */ 1798#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1799 (REGNO (X) < STACK_POINTER_REGNUM \ 1800 || REX_INT_REGNO_P (REGNO (X)) \ 1801 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1802 1803#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1804 (GENERAL_REGNO_P (REGNO (X)) \ 1805 || REGNO (X) == ARG_POINTER_REGNUM \ 1806 || REGNO (X) == FRAME_POINTER_REGNUM \ 1807 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1808 1809/* Strict versions, hard registers only */ 1810#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1811#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1812 1813#ifndef REG_OK_STRICT 1814#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1815#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1816 1817#else 1818#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1819#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1820#endif 1821 1822/* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression 1823 that is a valid memory address for an instruction. 1824 The MODE argument is the machine mode for the MEM expression 1825 that wants to use this address. 1826 1827 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, 1828 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1829 1830 See legitimize_pic_address in i386.c for details as to what 1831 constitutes a legitimate address when -fpic is used. */ 1832 1833#define MAX_REGS_PER_ADDRESS 2 1834 1835#define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1836 1837/* Try a machine-dependent way of reloading an illegitimate address 1838 operand. If we find one, push the reload and jump to WIN. This 1839 macro is used in only one place: `find_reloads_address' in reload.c. */ 1840 1841#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, INDL, WIN) \ 1842do { \ 1843 if (ix86_legitimize_reload_address ((X), (MODE), (OPNUM), \ 1844 (int)(TYPE), (INDL))) \ 1845 goto WIN; \ 1846} while (0) 1847 1848/* If defined, a C expression to determine the base term of address X. 1849 This macro is used in only one place: `find_base_term' in alias.c. 1850 1851 It is always safe for this macro to not be defined. It exists so 1852 that alias analysis can understand machine-dependent addresses. 1853 1854 The typical use of this macro is to handle addresses containing 1855 a label_ref or symbol_ref within an UNSPEC. */ 1856 1857#define FIND_BASE_TERM(X) ix86_find_base_term (X) 1858 1859/* Nonzero if the constant value X is a legitimate general operand 1860 when generating PIC code. It is given that flag_pic is on and 1861 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1862 1863#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1864 1865#define SYMBOLIC_CONST(X) \ 1866 (GET_CODE (X) == SYMBOL_REF \ 1867 || GET_CODE (X) == LABEL_REF \ 1868 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 1869 1870/* Max number of args passed in registers. If this is more than 3, we will 1871 have problems with ebx (register #4), since it is a caller save register and 1872 is also used as the pic register in ELF. So for now, don't allow more than 1873 3 registers to be passed in registers. */ 1874 1875/* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ 1876#define X86_64_REGPARM_MAX 6 1877#define X86_64_MS_REGPARM_MAX 4 1878 1879#define X86_32_REGPARM_MAX 3 1880 1881#define REGPARM_MAX \ 1882 (TARGET_64BIT \ 1883 ? (TARGET_64BIT_MS_ABI \ 1884 ? X86_64_MS_REGPARM_MAX \ 1885 : X86_64_REGPARM_MAX) \ 1886 : X86_32_REGPARM_MAX) 1887 1888#define X86_64_SSE_REGPARM_MAX 8 1889#define X86_64_MS_SSE_REGPARM_MAX 4 1890 1891#define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) 1892 1893#define SSE_REGPARM_MAX \ 1894 (TARGET_64BIT \ 1895 ? (TARGET_64BIT_MS_ABI \ 1896 ? X86_64_MS_SSE_REGPARM_MAX \ 1897 : X86_64_SSE_REGPARM_MAX) \ 1898 : X86_32_SSE_REGPARM_MAX) 1899 1900#define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 1901 1902/* Specify the machine mode that this machine uses 1903 for the index in the tablejump instruction. */ 1904#define CASE_VECTOR_MODE \ 1905 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) 1906 1907/* Define this as 1 if `char' should by default be signed; else as 0. */ 1908#define DEFAULT_SIGNED_CHAR 1 1909 1910/* Max number of bytes we can move from memory to memory 1911 in one reasonably fast instruction. */ 1912#define MOVE_MAX 16 1913 1914/* MOVE_MAX_PIECES is the number of bytes at a time which we can 1915 move efficiently, as opposed to MOVE_MAX which is the maximum 1916 number of bytes we can move with a single instruction. */ 1917#define MOVE_MAX_PIECES UNITS_PER_WORD 1918 1919/* If a memory-to-memory move would take MOVE_RATIO or more simple 1920 move-instruction pairs, we will do a movmem or libcall instead. 1921 Increasing the value will always make code faster, but eventually 1922 incurs high cost in increased code size. 1923 1924 If you don't define this, a reasonable default is used. */ 1925 1926#define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) 1927 1928/* If a clear memory operation would take CLEAR_RATIO or more simple 1929 move-instruction sequences, we will do a clrmem or libcall instead. */ 1930 1931#define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) 1932 1933/* Define if shifts truncate the shift count which implies one can 1934 omit a sign-extension or zero-extension of a shift count. 1935 1936 On i386, shifts do truncate the count. But bit test instructions 1937 take the modulo of the bit offset operand. */ 1938 1939/* #define SHIFT_COUNT_TRUNCATED */ 1940 1941/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1942 is done just by pretending it is already truncated. */ 1943#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1944 1945/* A macro to update M and UNSIGNEDP when an object whose type is 1946 TYPE and which has the specified mode and signedness is to be 1947 stored in a register. This macro is only called when TYPE is a 1948 scalar type. 1949 1950 On i386 it is sometimes useful to promote HImode and QImode 1951 quantities to SImode. The choice depends on target type. */ 1952 1953#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1954do { \ 1955 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 1956 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 1957 (MODE) = SImode; \ 1958} while (0) 1959 1960/* Specify the machine mode that pointers have. 1961 After generation of rtl, the compiler makes no further distinction 1962 between pointers and any other objects of this machine mode. */ 1963#define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode) 1964 1965/* Specify the machine mode that bounds have. */ 1966#define BNDmode (ix86_pmode == PMODE_DI ? BND64mode : BND32mode) 1967 1968/* A C expression whose value is zero if pointers that need to be extended 1969 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 1970 greater then zero if they are zero-extended and less then zero if the 1971 ptr_extend instruction should be used. */ 1972 1973#define POINTERS_EXTEND_UNSIGNED 1 1974 1975/* A function address in a call instruction 1976 is a byte address (for indexing purposes) 1977 so give the MEM rtx a byte's mode. */ 1978#define FUNCTION_MODE QImode 1979 1980 1981/* A C expression for the cost of a branch instruction. A value of 1 1982 is the default; other values are interpreted relative to that. */ 1983 1984#define BRANCH_COST(speed_p, predictable_p) \ 1985 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) 1986 1987/* An integer expression for the size in bits of the largest integer machine 1988 mode that should actually be used. We allow pairs of registers. */ 1989#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) 1990 1991/* Define this macro as a C expression which is nonzero if accessing 1992 less than a word of memory (i.e. a `char' or a `short') is no 1993 faster than accessing a word of memory, i.e., if such access 1994 require more than one instruction or if there is no difference in 1995 cost between byte and (aligned) word loads. 1996 1997 When this macro is not defined, the compiler will access a field by 1998 finding the smallest containing object; when it is defined, a 1999 fullword load will be used if alignment permits. Unless bytes 2000 accesses are faster than word accesses, using word accesses is 2001 preferable since it may eliminate subsequent memory access if 2002 subsequent accesses occur to other fields in the same word of the 2003 structure, but to different bytes. */ 2004 2005#define SLOW_BYTE_ACCESS 0 2006 2007/* Nonzero if access to memory by shorts is slow and undesirable. */ 2008#define SLOW_SHORT_ACCESS 0 2009 2010/* Define this macro to be the value 1 if unaligned accesses have a 2011 cost many times greater than aligned accesses, for example if they 2012 are emulated in a trap handler. 2013 2014 When this macro is nonzero, the compiler will act as if 2015 `STRICT_ALIGNMENT' were nonzero when generating code for block 2016 moves. This can cause significantly more instructions to be 2017 produced. Therefore, do not set this macro nonzero if unaligned 2018 accesses only add a cycle or two to the time for a memory access. 2019 2020 If the value of this macro is always zero, it need not be defined. */ 2021 2022/* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 2023 2024/* Define this macro if it is as good or better to call a constant 2025 function address than to call an address kept in a register. 2026 2027 Desirable on the 386 because a CALL with a constant address is 2028 faster than one with a register address. */ 2029 2030#define NO_FUNCTION_CSE 2031 2032/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2033 return the mode to be used for the comparison. 2034 2035 For floating-point equality comparisons, CCFPEQmode should be used. 2036 VOIDmode should be used in all other cases. 2037 2038 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 2039 possible, to allow for more combinations. */ 2040 2041#define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 2042 2043/* Return nonzero if MODE implies a floating point inequality can be 2044 reversed. */ 2045 2046#define REVERSIBLE_CC_MODE(MODE) 1 2047 2048/* A C expression whose value is reversed condition code of the CODE for 2049 comparison done in CC_MODE mode. */ 2050#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) 2051 2052 2053/* Control the assembler format that we output, to the extent 2054 this does not vary between assemblers. */ 2055 2056/* How to refer to registers in assembler output. 2057 This sequence is indexed by compiler's hard-register-number (see above). */ 2058 2059/* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". 2060 For non floating point regs, the following are the HImode names. 2061 2062 For float regs, the stack top is sometimes referred to as "%st(0)" 2063 instead of just "%st". TARGET_PRINT_OPERAND handles this with the 2064 "y" code. */ 2065 2066#define HI_REGISTER_NAMES \ 2067{"ax","dx","cx","bx","si","di","bp","sp", \ 2068 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 2069 "argp", "flags", "fpsr", "fpcr", "frame", \ 2070 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 2071 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ 2072 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 2073 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \ 2074 "xmm16", "xmm17", "xmm18", "xmm19", \ 2075 "xmm20", "xmm21", "xmm22", "xmm23", \ 2076 "xmm24", "xmm25", "xmm26", "xmm27", \ 2077 "xmm28", "xmm29", "xmm30", "xmm31", \ 2078 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", \ 2079 "bnd0", "bnd1", "bnd2", "bnd3" } 2080 2081#define REGISTER_NAMES HI_REGISTER_NAMES 2082 2083/* Table of additional register names to use in user input. */ 2084 2085#define ADDITIONAL_REGISTER_NAMES \ 2086{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 2087 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 2088 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 2089 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 2090 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 2091 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ 2092 { "ymm0", 21}, { "ymm1", 22}, { "ymm2", 23}, { "ymm3", 24}, \ 2093 { "ymm4", 25}, { "ymm5", 26}, { "ymm6", 27}, { "ymm7", 28}, \ 2094 { "ymm8", 45}, { "ymm9", 46}, { "ymm10", 47}, { "ymm11", 48}, \ 2095 { "ymm12", 49}, { "ymm13", 50}, { "ymm14", 51}, { "ymm15", 52}, \ 2096 { "ymm16", 53}, { "ymm17", 54}, { "ymm18", 55}, { "ymm19", 56}, \ 2097 { "ymm20", 57}, { "ymm21", 58}, { "ymm22", 59}, { "ymm23", 60}, \ 2098 { "ymm24", 61}, { "ymm25", 62}, { "ymm26", 63}, { "ymm27", 64}, \ 2099 { "ymm28", 65}, { "ymm29", 66}, { "ymm30", 67}, { "ymm31", 68}, \ 2100 { "zmm0", 21}, { "zmm1", 22}, { "zmm2", 23}, { "zmm3", 24}, \ 2101 { "zmm4", 25}, { "zmm5", 26}, { "zmm6", 27}, { "zmm7", 28}, \ 2102 { "zmm8", 45}, { "zmm9", 46}, { "zmm10", 47}, { "zmm11", 48}, \ 2103 { "zmm12", 49}, { "zmm13", 50}, { "zmm14", 51}, { "zmm15", 52}, \ 2104 { "zmm16", 53}, { "zmm17", 54}, { "zmm18", 55}, { "zmm19", 56}, \ 2105 { "zmm20", 57}, { "zmm21", 58}, { "zmm22", 59}, { "zmm23", 60}, \ 2106 { "zmm24", 61}, { "zmm25", 62}, { "zmm26", 63}, { "zmm27", 64}, \ 2107 { "zmm28", 65}, { "zmm29", 66}, { "zmm30", 67}, { "zmm31", 68} } 2108 2109/* Note we are omitting these since currently I don't know how 2110to get gcc to use these, since they want the same but different 2111number as al, and ax. 2112*/ 2113 2114#define QI_REGISTER_NAMES \ 2115{"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 2116 2117/* These parallel the array above, and can be used to access bits 8:15 2118 of regs 0 through 3. */ 2119 2120#define QI_HIGH_REGISTER_NAMES \ 2121{"ah", "dh", "ch", "bh", } 2122 2123/* How to renumber registers for dbx and gdb. */ 2124 2125#define DBX_REGISTER_NUMBER(N) \ 2126 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 2127 2128extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 2129extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 2130extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 2131 2132extern int const x86_64_ms_sysv_extra_clobbered_registers[12]; 2133 2134/* Before the prologue, RA is at 0(%esp). */ 2135#define INCOMING_RETURN_ADDR_RTX \ 2136 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 2137 2138/* After the prologue, RA is at -4(AP) in the current frame. */ 2139#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2140 ((COUNT) == 0 \ 2141 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ 2142 -UNITS_PER_WORD)) \ 2143 : gen_rtx_MEM (Pmode, plus_constant (Pmode, FRAME, UNITS_PER_WORD))) 2144 2145/* PC is dbx register 8; let's use that column for RA. */ 2146#define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2147 2148/* Before the prologue, the top of the frame is at 4(%esp). */ 2149#define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2150 2151/* Describe how we implement __builtin_eh_return. */ 2152#define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) 2153#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) 2154 2155 2156/* Select a format to encode pointers in exception handling data. CODE 2157 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2158 true if the symbol may be affected by dynamic relocations. 2159 2160 ??? All x86 object file formats are capable of representing this. 2161 After all, the relocation needed is the same as for the call insn. 2162 Whether or not a particular assembler allows us to enter such, I 2163 guess we'll have to see. */ 2164#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2165 asm_preferred_eh_data_format ((CODE), (GLOBAL)) 2166 2167/* This is how to output an insn to push a register on the stack. 2168 It need not be very fast code. */ 2169 2170#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2171do { \ 2172 if (TARGET_64BIT) \ 2173 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 2174 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2175 else \ 2176 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2177} while (0) 2178 2179/* This is how to output an insn to pop a register from the stack. 2180 It need not be very fast code. */ 2181 2182#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2183do { \ 2184 if (TARGET_64BIT) \ 2185 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 2186 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2187 else \ 2188 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2189} while (0) 2190 2191/* This is how to output an element of a case-vector that is absolute. */ 2192 2193#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2194 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2195 2196/* This is how to output an element of a case-vector that is relative. */ 2197 2198#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2199 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2200 2201/* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ 2202 2203#define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ 2204{ \ 2205 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ 2206 (PTR) += TARGET_AVX ? 1 : 2; \ 2207} 2208 2209/* A C statement or statements which output an assembler instruction 2210 opcode to the stdio stream STREAM. The macro-operand PTR is a 2211 variable of type `char *' which points to the opcode name in 2212 its "internal" form--the form that is written in the machine 2213 description. */ 2214 2215#define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 2216 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) 2217 2218/* A C statement to output to the stdio stream FILE an assembler 2219 command to pad the location counter to a multiple of 1<<LOG 2220 bytes if it is within MAX_SKIP bytes. */ 2221 2222#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2223#undef ASM_OUTPUT_MAX_SKIP_PAD 2224#define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ 2225 if ((LOG) != 0) \ 2226 { \ 2227 if ((MAX_SKIP) == 0) \ 2228 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ 2229 else \ 2230 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ 2231 } 2232#endif 2233 2234/* Write the extra assembler code needed to declare a function 2235 properly. */ 2236 2237#undef ASM_OUTPUT_FUNCTION_LABEL 2238#define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ 2239 ix86_asm_output_function_label (FILE, NAME, DECL) 2240 2241/* Under some conditions we need jump tables in the text section, 2242 because the assembler cannot handle label differences between 2243 sections. This is the case for x86_64 on Mach-O for example. */ 2244 2245#define JUMP_TABLES_IN_TEXT_SECTION \ 2246 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ 2247 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) 2248 2249/* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2250 and switch back. For x86 we do this only to save a few bytes that 2251 would otherwise be unused in the text section. */ 2252#define CRT_MKSTR2(VAL) #VAL 2253#define CRT_MKSTR(x) CRT_MKSTR2(x) 2254 2255#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2256 asm (SECTION_OP "\n\t" \ 2257 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ 2258 TEXT_SECTION_ASM_OP); 2259 2260/* Default threshold for putting data in large sections 2261 with x86-64 medium memory model */ 2262#define DEFAULT_LARGE_SECTION_THRESHOLD 65536 2263 2264/* Which processor to tune code generation for. These must be in sync 2265 with processor_target_table in i386.c. */ 2266 2267enum processor_type 2268{ 2269 PROCESSOR_GENERIC = 0, 2270 PROCESSOR_I386, /* 80386 */ 2271 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 2272 PROCESSOR_PENTIUM, 2273 PROCESSOR_PENTIUMPRO, 2274 PROCESSOR_PENTIUM4, 2275 PROCESSOR_NOCONA, 2276 PROCESSOR_CORE2, 2277 PROCESSOR_NEHALEM, 2278 PROCESSOR_SANDYBRIDGE, 2279 PROCESSOR_HASWELL, 2280 PROCESSOR_BONNELL, 2281 PROCESSOR_SILVERMONT, 2282 PROCESSOR_KNL, 2283 PROCESSOR_INTEL, 2284 PROCESSOR_GEODE, 2285 PROCESSOR_K6, 2286 PROCESSOR_ATHLON, 2287 PROCESSOR_K8, 2288 PROCESSOR_AMDFAM10, 2289 PROCESSOR_BDVER1, 2290 PROCESSOR_BDVER2, 2291 PROCESSOR_BDVER3, 2292 PROCESSOR_BDVER4, 2293 PROCESSOR_BTVER1, 2294 PROCESSOR_BTVER2, 2295 PROCESSOR_max 2296}; 2297 2298extern enum processor_type ix86_tune; 2299extern enum processor_type ix86_arch; 2300 2301/* Size of the RED_ZONE area. */ 2302#define RED_ZONE_SIZE 128 2303/* Reserved area of the red zone for temporaries. */ 2304#define RED_ZONE_RESERVE 8 2305 2306extern unsigned int ix86_preferred_stack_boundary; 2307extern unsigned int ix86_incoming_stack_boundary; 2308 2309/* Smallest class containing REGNO. */ 2310extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 2311 2312enum ix86_fpcmp_strategy { 2313 IX86_FPCMP_SAHF, 2314 IX86_FPCMP_COMI, 2315 IX86_FPCMP_ARITH 2316}; 2317 2318/* To properly truncate FP values into integers, we need to set i387 control 2319 word. We can't emit proper mode switching code before reload, as spills 2320 generated by reload may truncate values incorrectly, but we still can avoid 2321 redundant computation of new control word by the mode switching pass. 2322 The fldcw instructions are still emitted redundantly, but this is probably 2323 not going to be noticeable problem, as most CPUs do have fast path for 2324 the sequence. 2325 2326 The machinery is to emit simple truncation instructions and split them 2327 before reload to instructions having USEs of two memory locations that 2328 are filled by this code to old and new control word. 2329 2330 Post-reload pass may be later used to eliminate the redundant fildcw if 2331 needed. */ 2332 2333enum ix86_entity 2334{ 2335 AVX_U128 = 0, 2336 I387_TRUNC, 2337 I387_FLOOR, 2338 I387_CEIL, 2339 I387_MASK_PM, 2340 MAX_386_ENTITIES 2341}; 2342 2343enum ix86_stack_slot 2344{ 2345 SLOT_TEMP = 0, 2346 SLOT_CW_STORED, 2347 SLOT_CW_TRUNC, 2348 SLOT_CW_FLOOR, 2349 SLOT_CW_CEIL, 2350 SLOT_CW_MASK_PM, 2351 MAX_386_STACK_LOCALS 2352}; 2353 2354enum avx_u128_state 2355{ 2356 AVX_U128_CLEAN, 2357 AVX_U128_DIRTY, 2358 AVX_U128_ANY 2359}; 2360 2361/* Define this macro if the port needs extra instructions inserted 2362 for mode switching in an optimizing compilation. */ 2363 2364#define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 2365 ix86_optimize_mode_switching[(ENTITY)] 2366 2367/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 2368 initializer for an array of integers. Each initializer element N 2369 refers to an entity that needs mode switching, and specifies the 2370 number of different modes that might need to be set for this 2371 entity. The position of the initializer in the initializer - 2372 starting counting at zero - determines the integer that is used to 2373 refer to the mode-switched entity in question. */ 2374 2375#define NUM_MODES_FOR_MODE_SWITCHING \ 2376 { AVX_U128_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 2377 2378 2379/* Avoid renaming of stack registers, as doing so in combination with 2380 scheduling just increases amount of live registers at time and in 2381 the turn amount of fxch instructions needed. 2382 2383 ??? Maybe Pentium chips benefits from renaming, someone can try.... 2384 2385 Don't rename evex to non-evex sse registers. */ 2386 2387#define HARD_REGNO_RENAME_OK(SRC, TARGET) (!STACK_REGNO_P (SRC) && \ 2388 (EXT_REX_SSE_REGNO_P (SRC) == \ 2389 EXT_REX_SSE_REGNO_P (TARGET))) 2390 2391 2392#define FASTCALL_PREFIX '@' 2393 2394/* Machine specific frame tracking during prologue/epilogue generation. */ 2395 2396#ifndef USED_FOR_TARGET 2397struct GTY(()) machine_frame_state 2398{ 2399 /* This pair tracks the currently active CFA as reg+offset. When reg 2400 is drap_reg, we don't bother trying to record here the real CFA when 2401 it might really be a DW_CFA_def_cfa_expression. */ 2402 rtx cfa_reg; 2403 HOST_WIDE_INT cfa_offset; 2404 2405 /* The current offset (canonically from the CFA) of ESP and EBP. 2406 When stack frame re-alignment is active, these may not be relative 2407 to the CFA. However, in all cases they are relative to the offsets 2408 of the saved registers stored in ix86_frame. */ 2409 HOST_WIDE_INT sp_offset; 2410 HOST_WIDE_INT fp_offset; 2411 2412 /* The size of the red-zone that may be assumed for the purposes of 2413 eliding register restore notes in the epilogue. This may be zero 2414 if no red-zone is in effect, or may be reduced from the real 2415 red-zone value by a maximum runtime stack re-alignment value. */ 2416 int red_zone_offset; 2417 2418 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid 2419 value within the frame. If false then the offset above should be 2420 ignored. Note that DRAP, if valid, *always* points to the CFA and 2421 thus has an offset of zero. */ 2422 BOOL_BITFIELD sp_valid : 1; 2423 BOOL_BITFIELD fp_valid : 1; 2424 BOOL_BITFIELD drap_valid : 1; 2425 2426 /* Indicate whether the local stack frame has been re-aligned. When 2427 set, the SP/FP offsets above are relative to the aligned frame 2428 and not the CFA. */ 2429 BOOL_BITFIELD realigned : 1; 2430}; 2431 2432/* Private to winnt.c. */ 2433struct seh_frame_state; 2434 2435struct GTY(()) machine_function { 2436 struct stack_local_entry *stack_locals; 2437 const char *some_ld_name; 2438 int varargs_gpr_size; 2439 int varargs_fpr_size; 2440 int optimize_mode_switching[MAX_386_ENTITIES]; 2441 2442 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE 2443 has been computed for. */ 2444 int use_fast_prologue_epilogue_nregs; 2445 2446 /* For -fsplit-stack support: A stack local which holds a pointer to 2447 the stack arguments for a function with a variable number of 2448 arguments. This is set at the start of the function and is used 2449 to initialize the overflow_arg_area field of the va_list 2450 structure. */ 2451 rtx split_stack_varargs_pointer; 2452 2453 /* This value is used for amd64 targets and specifies the current abi 2454 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ 2455 ENUM_BITFIELD(calling_abi) call_abi : 8; 2456 2457 /* Nonzero if the function accesses a previous frame. */ 2458 BOOL_BITFIELD accesses_prev_frame : 1; 2459 2460 /* Nonzero if the function requires a CLD in the prologue. */ 2461 BOOL_BITFIELD needs_cld : 1; 2462 2463 /* Set by ix86_compute_frame_layout and used by prologue/epilogue 2464 expander to determine the style used. */ 2465 BOOL_BITFIELD use_fast_prologue_epilogue : 1; 2466 2467 /* If true, the current function needs the default PIC register, not 2468 an alternate register (on x86) and must not use the red zone (on 2469 x86_64), even if it's a leaf function. We don't want the 2470 function to be regarded as non-leaf because TLS calls need not 2471 affect register allocation. This flag is set when a TLS call 2472 instruction is expanded within a function, and never reset, even 2473 if all such instructions are optimized away. Use the 2474 ix86_current_function_calls_tls_descriptor macro for a better 2475 approximation. */ 2476 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; 2477 2478 /* If true, the current function has a STATIC_CHAIN is placed on the 2479 stack below the return address. */ 2480 BOOL_BITFIELD static_chain_on_stack : 1; 2481 2482 /* If true, it is safe to not save/restore DRAP register. */ 2483 BOOL_BITFIELD no_drap_save_restore : 1; 2484 2485 /* During prologue/epilogue generation, the current frame state. 2486 Otherwise, the frame state at the end of the prologue. */ 2487 struct machine_frame_state fs; 2488 2489 /* During SEH output, this is non-null. */ 2490 struct seh_frame_state * GTY((skip(""))) seh; 2491}; 2492#endif 2493 2494#define ix86_stack_locals (cfun->machine->stack_locals) 2495#define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) 2496#define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) 2497#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 2498#define ix86_current_function_needs_cld (cfun->machine->needs_cld) 2499#define ix86_tls_descriptor_calls_expanded_in_cfun \ 2500 (cfun->machine->tls_descriptor_call_expanded_p) 2501/* Since tls_descriptor_call_expanded is not cleared, even if all TLS 2502 calls are optimized away, we try to detect cases in which it was 2503 optimized away. Since such instructions (use (reg REG_SP)), we can 2504 verify whether there's any such instruction live by testing that 2505 REG_SP is live. */ 2506#define ix86_current_function_calls_tls_descriptor \ 2507 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) 2508#define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) 2509 2510/* Control behavior of x86_file_start. */ 2511#define X86_FILE_START_VERSION_DIRECTIVE false 2512#define X86_FILE_START_FLTUSED false 2513 2514/* Flag to mark data that is in the large address area. */ 2515#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 2516#define SYMBOL_REF_FAR_ADDR_P(X) \ 2517 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) 2518 2519/* Flags to mark dllimport/dllexport. Used by PE ports, but handy to 2520 have defined always, to avoid ifdefing. */ 2521#define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) 2522#define SYMBOL_REF_DLLIMPORT_P(X) \ 2523 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) 2524 2525#define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) 2526#define SYMBOL_REF_DLLEXPORT_P(X) \ 2527 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) 2528 2529#define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4) 2530#define SYMBOL_REF_STUBVAR_P(X) \ 2531 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0) 2532 2533extern void debug_ready_dispatch (void); 2534extern void debug_dispatch_window (int); 2535 2536/* The value at zero is only defined for the BMI instructions 2537 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */ 2538#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2539 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 1 : 0) 2540#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2541 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 1 : 0) 2542 2543 2544/* Flags returned by ix86_get_callcvt (). */ 2545#define IX86_CALLCVT_CDECL 0x1 2546#define IX86_CALLCVT_STDCALL 0x2 2547#define IX86_CALLCVT_FASTCALL 0x4 2548#define IX86_CALLCVT_THISCALL 0x8 2549#define IX86_CALLCVT_REGPARM 0x10 2550#define IX86_CALLCVT_SSEREGPARM 0x20 2551 2552#define IX86_BASE_CALLCVT(FLAGS) \ 2553 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \ 2554 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) 2555 2556#define RECIP_MASK_NONE 0x00 2557#define RECIP_MASK_DIV 0x01 2558#define RECIP_MASK_SQRT 0x02 2559#define RECIP_MASK_VEC_DIV 0x04 2560#define RECIP_MASK_VEC_SQRT 0x08 2561#define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \ 2562 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 2563#define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 2564 2565#define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) 2566#define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) 2567#define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) 2568#define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) 2569 2570#define IX86_HLE_ACQUIRE (1 << 16) 2571#define IX86_HLE_RELEASE (1 << 17) 2572 2573/* For switching between functions with different target attributes. */ 2574#define SWITCHABLE_TARGET 1 2575 2576/* 2577Local variables: 2578version-control: t 2579End: 2580*/ 2581