178172Sru/* Definitions of target machine for GCC for IA-32. 2177760Sdas Copyright (C) 2002-2015 Free Software Foundation, Inc. 378172Sru 478172SruThis file is part of GCC. 578172Sru 678172SruGCC is free software; you can redistribute it and/or modify 778172Sruit under the terms of the GNU General Public License as published by 878172Sruthe Free Software Foundation; either version 3, or (at your option) 978172Sruany later version. 1078172Sru 1178172SruGCC is distributed in the hope that it will be useful, 1278172Srubut WITHOUT ANY WARRANTY; without even the implied warranty of 1378172SruMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1478172SruGNU General Public License for more details. 1578172Sru 1678172SruYou should have received a copy of the GNU General Public License 1778172Srualong with GCC; see the file COPYING3. If not see 1878172Sru<http://www.gnu.org/licenses/>. */ 1978172Sru 2078172Sru/* The x86_64 ABI specifies both XF and TF modes. 2178172Sru XFmode is __float80 is IEEE extended; TFmode is __float128 2278172Sru is IEEE quad. */ 2378172Sru 2478172SruFRACTIONAL_FLOAT_MODE (XF, 80, 12, ieee_extended_intel_96_format); 2578172SruFLOAT_MODE (TF, 16, ieee_quad_format); 2678172Sru 2778172Sru/* In ILP32 mode, XFmode has size 12 and alignment 4. 2878172Sru In LP64 mode, XFmode has size and alignment 16. */ 2978172SruADJUST_FLOAT_FORMAT (XF, (TARGET_128BIT_LONG_DOUBLE 30133724Sstefanf ? &ieee_extended_intel_128_format 3178172Sru : TARGET_96_ROUND_53_LONG_DOUBLE 3278172Sru ? &ieee_extended_intel_96_round_53_format 33133725Sstefanf : &ieee_extended_intel_96_format)); 34133724SstefanfADJUST_BYTESIZE (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 12); 35133725SstefanfADJUST_ALIGNMENT (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 4); 36133724Sstefanf 3778172Sru/* Add any extra modes needed to represent the condition code. 3878172Sru 39133724Sstefanf For the i386, we need separate modes when floating-point 40133724Sstefanf equality comparisons are being done. 4178172Sru 4278172Sru Add CCNO to indicate comparisons against zero that requires 4378172Sru Overflow flag to be unset. Sign bit test is used instead and 4478172Sru thus can be used to form "a&b>0" type of tests. 4578172Sru 46129864Sstefanf Add CCGC to indicate comparisons against zero that allows 47129864Sstefanf unspecified garbage in the Carry flag. This mode is used 48177760Sdas by inc/dec instructions. 49174561Sdas 50174561Sdas Add CCGOC to indicate comparisons against zero that allows 51129864Sstefanf unspecified garbage in the Carry and Overflow flag. This 52129864Sstefanf mode is used to simulate comparisons of (a-b) and (a+b) 53129864Sstefanf against zero using sub/cmp/add operations. 54129864Sstefanf 55129864Sstefanf Add CCA to indicate that only the Above flag is valid. 56129864Sstefanf Add CCC to indicate that only the Carry flag is valid. 57129864Sstefanf Add CCO to indicate that only the Overflow flag is valid. 58129864Sstefanf Add CCS to indicate that only the Sign flag is valid. 59129864Sstefanf Add CCZ to indicate that only the Zero flag is valid. */ 60129864Sstefanf 61174617SdasCC_MODE (CCGC); 62174617SdasCC_MODE (CCGOC); 6378172SruCC_MODE (CCNO); 6478172SruCC_MODE (CCA); 6578172SruCC_MODE (CCC); 6678172SruCC_MODE (CCO); 67CC_MODE (CCS); 68CC_MODE (CCZ); 69CC_MODE (CCFP); 70CC_MODE (CCFPU); 71 72/* Vector modes. Note that VEC_CONCAT patterns require vector 73 sizes twice as big as implemented in hardware. */ 74VECTOR_MODES (INT, 4); /* V4QI V2HI */ 75VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */ 76VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ 77VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ 78VECTOR_MODES (INT, 64); /* V64QI V32HI V16SI V8DI */ 79VECTOR_MODES (INT, 128); /* V128QI V64HI V32SI V16DI */ 80VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */ 81VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ 82VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ 83VECTOR_MODES (FLOAT, 64); /* V32HF V16SF V8DF */ 84VECTOR_MODES (FLOAT, 128); /* V64HF V32SF V16DF */ 85VECTOR_MODE (INT, TI, 1); /* V1TI */ 86VECTOR_MODE (INT, DI, 1); /* V1DI */ 87VECTOR_MODE (INT, SI, 1); /* V1SI */ 88VECTOR_MODE (INT, QI, 2); /* V2QI */ 89VECTOR_MODE (INT, QI, 12); /* V12QI */ 90VECTOR_MODE (INT, QI, 14); /* V14QI */ 91VECTOR_MODE (INT, HI, 6); /* V6HI */ 92 93POINTER_BOUNDS_MODE (BND32, 8); 94POINTER_BOUNDS_MODE (BND64, 16); 95 96INT_MODE (OI, 32); 97INT_MODE (XI, 64); 98 99/* Keep the OI and XI modes from confusing the compiler into thinking 100 that these modes could actually be used for computation. They are 101 only holders for vectors during data movement. */ 102#define MAX_BITSIZE_MODE_ANY_INT (128) 103 104/* The symbol Pmode stands for one of the above machine modes (usually SImode). 105 The tm.h file specifies which one. It is not a distinct mode. */ 106