1;; Instruction Classification for ARM for GNU compiler. 2 3;; Copyright (C) 1991-2015 Free Software Foundation, Inc. 4;; Contributed by ARM Ltd. 5 6;; This file is part of GCC. 7 8;; GCC is free software; you can redistribute it and/or modify it 9;; under the terms of the GNU General Public License as published 10;; by the Free Software Foundation; either version 3, or (at your 11;; option) any later version. 12 13;; GCC is distributed in the hope that it will be useful, but WITHOUT 14;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16;; License for more details. 17 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING3. If not see 20;; <http://www.gnu.org/licenses/>. 21 22; TYPE attribute is used to classify instructions for use in scheduling. 23; 24; Instruction classification: 25; 26; adc_imm add/subtract with carry and with an immediate operand. 27; adc_reg add/subtract with carry and no immediate operand. 28; adcs_imm as adc_imm, setting condition flags. 29; adcs_reg as adc_reg, setting condition flags. 30; adr calculate address. 31; alu_ext From ARMv8-A: any arithmetic instruction that has a 32; sign/zero-extended. 33; AArch64 Only. 34; source operand 35; alu_imm any arithmetic instruction that doesn't have a shifted 36; operand and has an immediate operand. This 37; excludes MOV, MVN and RSB(S) immediate. 38; alu_sreg any arithmetic instruction that doesn't have a shifted 39; or an immediate operand. This excludes 40; MOV and MVN but includes MOVT. This also excludes 41; DSP-kind instructions. This is also the default. 42; alu_shift_imm any arithmetic instruction that has a source operand 43; shifted by a constant. This excludes simple shifts. 44; alu_shift_reg as alu_shift_imm, with the shift amount specified in a 45; register. 46; alu_dsp_reg any DSP-kind instruction like QSUB8. 47; alus_ext From ARMv8-A: as alu_ext, setting condition flags. 48; AArch64 Only. 49; alus_imm as alu_imm, setting condition flags. 50; alus_sreg as alu_sreg, setting condition flags. 51; alus_shift_imm as alu_shift_imm, setting condition flags. 52; alus_shift_reg as alu_shift_reg, setting condition flags. 53; bfm bitfield move operation. 54; block blockage insn, this blocks all functional units. 55; branch branch. 56; call subroutine call. 57; clz count leading zeros (CLZ). 58; csel From ARMv8-A: conditional select. 59; extend extend instruction (SXTB, SXTH, UXTB, UXTH). 60; f_cvt conversion between float representations. 61; f_cvtf2i conversion between float and integral types. 62; f_cvti2f conversion between integral and float types. 63; f_flag transfer of co-processor flags to the CPSR. 64; f_load[d,s] double/single load from memory. Used for VFP unit. 65; f_mcr transfer arm to vfp reg. 66; f_mcrr transfer two arm regs to vfp reg. 67; f_minmax[d,s] double/single floating point minimum/maximum. 68; f_mrc transfer vfp to arm reg. 69; f_mrrc transfer vfp to two arm regs. 70; f_rint[d,s] double/single floating point rount to integral. 71; f_store[d,s] double/single store to memory. Used for VFP unit. 72; fadd[d,s] double/single floating-point scalar addition. 73; fcmp[d,s] double/single floating-point compare. 74; fconst[d,s] double/single load immediate. 75; fcsel From ARMv8-A: Floating-point conditional select. 76; fdiv[d,s] double/single precision floating point division. 77; ffarith[d,s] double/single floating point abs/neg/cpy. 78; ffma[d,s] double/single floating point fused multiply-accumulate. 79; float floating point arithmetic operation. 80; fmac[d,s] double/single floating point multiply-accumulate. 81; fmov floating point to floating point register move. 82; fmul[d,s] double/single floating point multiply. 83; fsqrt[d,s] double/single precision floating point square root. 84; load_acq load-acquire. 85; load_byte load byte(s) from memory to arm registers. 86; load1 load 1 word from memory to arm registers. 87; load2 load 2 words from memory to arm registers. 88; load3 load 3 words from memory to arm registers. 89; load4 load 4 words from memory to arm registers. 90; logic_imm any logical instruction that doesn't have a shifted 91; operand and has an immediate operand. 92; logic_reg any logical instruction that doesn't have a shifted 93; operand or an immediate operand. 94; logic_shift_imm any logical instruction that has a source operand 95; shifted by a constant. This excludes simple shifts. 96; logic_shift_reg as logic_shift_imm, with the shift amount specified in a 97; register. 98; logics_imm as logic_imm, setting condition flags. 99; logics_reg as logic_reg, setting condition flags. 100; logics_shift_imm as logic_shift_imm, setting condition flags. 101; logics_shift_reg as logic_shift_reg, setting condition flags. 102; mla integer multiply accumulate. 103; mlas integer multiply accumulate, flag setting. 104; mov_imm simple MOV instruction that moves an immediate to 105; register. This includes MOVW, but not MOVT. 106; mov_reg simple MOV instruction that moves a register to another 107; register. This includes MOVW, but not MOVT. 108; mov_shift simple MOV instruction, shifted operand by a constant. 109; mov_shift_reg simple MOV instruction, shifted operand by a register. 110; mrs system/special/co-processor register move. 111; mul integer multiply. 112; muls integer multiply, flag setting. 113; multiple more than one instruction, candidate for future 114; splitting, or better modeling. 115; mvn_imm inverting move instruction, immediate. 116; mvn_reg inverting move instruction, register. 117; mvn_shift inverting move instruction, shifted operand by a constant. 118; mvn_shift_reg inverting move instruction, shifted operand by a register. 119; no_insn an insn which does not represent an instruction in the 120; final output, thus having no impact on scheduling. 121; rbit reverse bits. 122; rev reverse bytes. 123; sdiv signed division. 124; shift_imm simple shift operation (LSL, LSR, ASR, ROR) with an 125; immediate. 126; shift_reg simple shift by a register. 127; smlad signed multiply accumulate dual. 128; smladx signed multiply accumulate dual reverse. 129; smlal signed multiply accumulate long. 130; smlald signed multiply accumulate long dual. 131; smlals signed multiply accumulate long, flag setting. 132; smlalxy signed multiply accumulate, 16x16-bit, 64-bit accumulate. 133; smlawx signed multiply accumulate, 32x16-bit, 32-bit accumulate. 134; smlawy signed multiply accumulate wide, 32x16-bit, 135; 32-bit accumulate. 136; smlaxy signed multiply accumulate, 16x16-bit, 32-bit accumulate. 137; smlsd signed multiply subtract dual. 138; smlsdx signed multiply subtract dual reverse. 139; smlsld signed multiply subtract long dual. 140; smmla signed most significant word multiply accumulate. 141; smmul signed most significant word multiply. 142; smmulr signed most significant word multiply, rounded. 143; smuad signed dual multiply add. 144; smuadx signed dual multiply add reverse. 145; smull signed multiply long. 146; smulls signed multiply long, flag setting. 147; smulwy signed multiply wide, 32x16-bit, 32-bit accumulate. 148; smulxy signed multiply, 16x16-bit, 32-bit accumulate. 149; smusd signed dual multiply subtract. 150; smusdx signed dual multiply subtract reverse. 151; store_rel store-release. 152; store1 store 1 word to memory from arm registers. 153; store2 store 2 words to memory from arm registers. 154; store3 store 3 words to memory from arm registers. 155; store4 store 4 (or more) words to memory from arm registers. 156; trap cause a trap in the kernel. 157; udiv unsigned division. 158; umaal unsigned multiply accumulate accumulate long. 159; umlal unsigned multiply accumulate long. 160; umlals unsigned multiply accumulate long, flag setting. 161; umull unsigned multiply long. 162; umulls unsigned multiply long, flag setting. 163; untyped insn without type information - default, and error, 164; case. 165; 166; The classification below is for instructions used by the Wireless MMX 167; Technology. Each attribute value is used to classify an instruction of the 168; same name or family. 169; 170; wmmx_tandc 171; wmmx_tbcst 172; wmmx_textrc 173; wmmx_textrm 174; wmmx_tinsr 175; wmmx_tmcr 176; wmmx_tmcrr 177; wmmx_tmia 178; wmmx_tmiaph 179; wmmx_tmiaxy 180; wmmx_tmrc 181; wmmx_tmrrc 182; wmmx_tmovmsk 183; wmmx_torc 184; wmmx_torvsc 185; wmmx_wabs 186; wmmx_wdiff 187; wmmx_wacc 188; wmmx_wadd 189; wmmx_waddbhus 190; wmmx_waddsubhx 191; wmmx_waligni 192; wmmx_walignr 193; wmmx_wand 194; wmmx_wandn 195; wmmx_wavg2 196; wmmx_wavg4 197; wmmx_wcmpeq 198; wmmx_wcmpgt 199; wmmx_wmac 200; wmmx_wmadd 201; wmmx_wmax 202; wmmx_wmerge 203; wmmx_wmiawxy 204; wmmx_wmiaxy 205; wmmx_wmin 206; wmmx_wmov 207; wmmx_wmul 208; wmmx_wmulw 209; wmmx_wldr 210; wmmx_wor 211; wmmx_wpack 212; wmmx_wqmiaxy 213; wmmx_wqmulm 214; wmmx_wqmulwm 215; wmmx_wror 216; wmmx_wsad 217; wmmx_wshufh 218; wmmx_wsll 219; wmmx_wsra 220; wmmx_wsrl 221; wmmx_wstr 222; wmmx_wsub 223; wmmx_wsubaddhx 224; wmmx_wunpckeh 225; wmmx_wunpckel 226; wmmx_wunpckih 227; wmmx_wunpckil 228; wmmx_wxor 229; 230; The classification below is for NEON instructions. 231; 232; neon_add 233; neon_add_q 234; neon_add_widen 235; neon_add_long 236; neon_qadd 237; neon_qadd_q 238; neon_add_halve 239; neon_add_halve_q 240; neon_add_halve_narrow_q 241; neon_sub 242; neon_sub_q 243; neon_sub_widen 244; neon_sub_long 245; neon_qsub 246; neon_qsub_q 247; neon_sub_halve 248; neon_sub_halve_q 249; neon_sub_halve_narrow_q 250; neon_abs 251; neon_abs_q 252; neon_neg 253; neon_neg_q 254; neon_qneg 255; neon_qneg_q 256; neon_qabs 257; neon_qabs_q 258; neon_abd 259; neon_abd_q 260; neon_abd_long 261; neon_minmax 262; neon_minmax_q 263; neon_compare 264; neon_compare_q 265; neon_compare_zero 266; neon_compare_zero_q 267; neon_arith_acc 268; neon_arith_acc_q 269; neon_reduc_add 270; neon_reduc_add_q 271; neon_reduc_add_long 272; neon_reduc_add_acc 273; neon_reduc_add_acc_q 274; neon_reduc_minmax 275; neon_reduc_minmax_q 276; neon_logic 277; neon_logic_q 278; neon_tst 279; neon_tst_q 280; neon_shift_imm 281; neon_shift_imm_q 282; neon_shift_imm_narrow_q 283; neon_shift_imm_long 284; neon_shift_reg 285; neon_shift_reg_q 286; neon_shift_acc 287; neon_shift_acc_q 288; neon_sat_shift_imm 289; neon_sat_shift_imm_q 290; neon_sat_shift_imm_narrow_q 291; neon_sat_shift_reg 292; neon_sat_shift_reg_q 293; neon_ins 294; neon_ins_q 295; neon_move 296; neon_move_q 297; neon_move_narrow_q 298; neon_permute 299; neon_permute_q 300; neon_zip 301; neon_zip_q 302; neon_tbl1 303; neon_tbl1_q 304; neon_tbl2 305; neon_tbl2_q 306; neon_tbl3 307; neon_tbl3_q 308; neon_tbl4 309; neon_tbl4_q 310; neon_bsl 311; neon_bsl_q 312; neon_cls 313; neon_cls_q 314; neon_cnt 315; neon_cnt_q 316; neon_ext 317; neon_ext_q 318; neon_rbit 319; neon_rbit_q 320; neon_rev 321; neon_rev_q 322; neon_mul_b 323; neon_mul_b_q 324; neon_mul_h 325; neon_mul_h_q 326; neon_mul_s 327; neon_mul_s_q 328; neon_mul_b_long 329; neon_mul_h_long 330; neon_mul_s_long 331; neon_mul_d_long 332; neon_mul_h_scalar 333; neon_mul_h_scalar_q 334; neon_mul_s_scalar 335; neon_mul_s_scalar_q 336; neon_mul_h_scalar_long 337; neon_mul_s_scalar_long 338; neon_sat_mul_b 339; neon_sat_mul_b_q 340; neon_sat_mul_h 341; neon_sat_mul_h_q 342; neon_sat_mul_s 343; neon_sat_mul_s_q 344; neon_sat_mul_b_long 345; neon_sat_mul_h_long 346; neon_sat_mul_s_long 347; neon_sat_mul_h_scalar 348; neon_sat_mul_h_scalar_q 349; neon_sat_mul_s_scalar 350; neon_sat_mul_s_scalar_q 351; neon_sat_mul_h_scalar_long 352; neon_sat_mul_s_scalar_long 353; neon_mla_b 354; neon_mla_b_q 355; neon_mla_h 356; neon_mla_h_q 357; neon_mla_s 358; neon_mla_s_q 359; neon_mla_b_long 360; neon_mla_h_long 361; neon_mla_s_long 362; neon_mla_h_scalar 363; neon_mla_h_scalar_q 364; neon_mla_s_scalar 365; neon_mla_s_scalar_q 366; neon_mla_h_scalar_long 367; neon_mla_s_scalar_long 368; neon_sat_mla_b_long 369; neon_sat_mla_h_long 370; neon_sat_mla_s_long 371; neon_sat_mla_h_scalar_long 372; neon_sat_mla_s_scalar_long 373; neon_to_gp 374; neon_to_gp_q 375; neon_from_gp 376; neon_from_gp_q 377; neon_ldr 378; neon_load1_1reg 379; neon_load1_1reg_q 380; neon_load1_2reg 381; neon_load1_2reg_q 382; neon_load1_3reg 383; neon_load1_3reg_q 384; neon_load1_4reg 385; neon_load1_4reg_q 386; neon_load1_all_lanes 387; neon_load1_all_lanes_q 388; neon_load1_one_lane 389; neon_load1_one_lane_q 390; neon_load2_2reg 391; neon_load2_2reg_q 392; neon_load2_4reg 393; neon_load2_4reg_q 394; neon_load2_all_lanes 395; neon_load2_all_lanes_q 396; neon_load2_one_lane 397; neon_load2_one_lane_q 398; neon_load3_3reg 399; neon_load3_3reg_q 400; neon_load3_all_lanes 401; neon_load3_all_lanes_q 402; neon_load3_one_lane 403; neon_load3_one_lane_q 404; neon_load4_4reg 405; neon_load4_4reg_q 406; neon_load4_all_lanes 407; neon_load4_all_lanes_q 408; neon_load4_one_lane 409; neon_load4_one_lane_q 410; neon_str 411; neon_store1_1reg 412; neon_store1_1reg_q 413; neon_store1_2reg 414; neon_store1_2reg_q 415; neon_store1_3reg 416; neon_store1_3reg_q 417; neon_store1_4reg 418; neon_store1_4reg_q 419; neon_store1_one_lane 420; neon_store1_one_lane_q 421; neon_store2_2reg 422; neon_store2_2reg_q 423; neon_store2_4reg 424; neon_store2_4reg_q 425; neon_store2_one_lane 426; neon_store2_one_lane_q 427; neon_store3_3reg 428; neon_store3_3reg_q 429; neon_store3_one_lane 430; neon_store3_one_lane_q 431; neon_store4_4reg 432; neon_store4_4reg_q 433; neon_store4_one_lane 434; neon_store4_one_lane_q 435; neon_fp_abs_s 436; neon_fp_abs_s_q 437; neon_fp_abs_d 438; neon_fp_abs_d_q 439; neon_fp_neg_s 440; neon_fp_neg_s_q 441; neon_fp_neg_d 442; neon_fp_neg_d_q 443; neon_fp_abd_s 444; neon_fp_abd_s_q 445; neon_fp_abd_d 446; neon_fp_abd_d_q 447; neon_fp_addsub_s 448; neon_fp_addsub_s_q 449; neon_fp_addsub_d 450; neon_fp_addsub_d_q 451; neon_fp_compare_s 452; neon_fp_compare_s_q 453; neon_fp_compare_d 454; neon_fp_compare_d_q 455; neon_fp_minmax_s 456; neon_fp_minmax_s_q 457; neon_fp_minmax_d 458; neon_fp_minmax_d_q 459; neon_fp_reduc_add_s 460; neon_fp_reduc_add_s_q 461; neon_fp_reduc_add_d 462; neon_fp_reduc_add_d_q 463; neon_fp_reduc_minmax_s 464; neon_fp_reduc_minmax_s_q 465; neon_fp_reduc_minmax_d 466; neon_fp_reduc_minmax_d_q 467; neon_fp_cvt_narrow_s_q 468; neon_fp_cvt_narrow_d_q 469; neon_fp_cvt_widen_h 470; neon_fp_cvt_widen_s 471; neon_fp_to_int_s 472; neon_fp_to_int_s_q 473; neon_fp_to_int_d 474; neon_fp_to_int_d_q 475; neon_int_to_fp_s 476; neon_int_to_fp_s_q 477; neon_int_to_fp_d 478; neon_int_to_fp_d_q 479; neon_fp_round_s 480; neon_fp_round_s_q 481; neon_fp_round_d 482; neon_fp_round_d_q 483; neon_fp_recpe_s 484; neon_fp_recpe_s_q 485; neon_fp_recpe_d 486; neon_fp_recpe_d_q 487; neon_fp_recps_s 488; neon_fp_recps_s_q 489; neon_fp_recps_d 490; neon_fp_recps_d_q 491; neon_fp_recpx_s 492; neon_fp_recpx_s_q 493; neon_fp_recpx_d 494; neon_fp_recpx_d_q 495; neon_fp_rsqrte_s 496; neon_fp_rsqrte_s_q 497; neon_fp_rsqrte_d 498; neon_fp_rsqrte_d_q 499; neon_fp_rsqrts_s 500; neon_fp_rsqrts_s_q 501; neon_fp_rsqrts_d 502; neon_fp_rsqrts_d_q 503; neon_fp_mul_s 504; neon_fp_mul_s_q 505; neon_fp_mul_s_scalar 506; neon_fp_mul_s_scalar_q 507; neon_fp_mul_d 508; neon_fp_mul_d_q 509; neon_fp_mul_d_scalar_q 510; neon_fp_mla_s 511; neon_fp_mla_s_q 512; neon_fp_mla_s_scalar 513; neon_fp_mla_s_scalar_q 514; neon_fp_mla_d 515; neon_fp_mla_d_q 516; neon_fp_mla_d_scalar_q 517; neon_fp_sqrt_s 518; neon_fp_sqrt_s_q 519; neon_fp_sqrt_d 520; neon_fp_sqrt_d_q 521; neon_fp_div_s 522; neon_fp_div_s_q 523; neon_fp_div_d 524; neon_fp_div_d_q 525; 526; The classification below is for Crypto instructions. 527; 528; crypto_aese 529; crypto_aesmc 530; crypto_sha1_xor 531; crypto_sha1_fast 532; crypto_sha1_slow 533; crypto_sha256_fast 534; crypto_sha256_slow 535 536(define_attr "type" 537 "adc_imm,\ 538 adc_reg,\ 539 adcs_imm,\ 540 adcs_reg,\ 541 adr,\ 542 alu_ext,\ 543 alu_imm,\ 544 alu_sreg,\ 545 alu_shift_imm,\ 546 alu_shift_reg,\ 547 alu_dsp_reg,\ 548 alus_ext,\ 549 alus_imm,\ 550 alus_sreg,\ 551 alus_shift_imm,\ 552 alus_shift_reg,\ 553 bfm,\ 554 block,\ 555 branch,\ 556 call,\ 557 clz,\ 558 no_insn,\ 559 csel,\ 560 crc,\ 561 extend,\ 562 f_cvt,\ 563 f_cvtf2i,\ 564 f_cvti2f,\ 565 f_flag,\ 566 f_loadd,\ 567 f_loads,\ 568 f_mcr,\ 569 f_mcrr,\ 570 f_minmaxd,\ 571 f_minmaxs,\ 572 f_mrc,\ 573 f_mrrc,\ 574 f_rintd,\ 575 f_rints,\ 576 f_stored,\ 577 f_stores,\ 578 faddd,\ 579 fadds,\ 580 fcmpd,\ 581 fcmps,\ 582 fconstd,\ 583 fconsts,\ 584 fcsel,\ 585 fdivd,\ 586 fdivs,\ 587 ffarithd,\ 588 ffariths,\ 589 ffmad,\ 590 ffmas,\ 591 float,\ 592 fmacd,\ 593 fmacs,\ 594 fmov,\ 595 fmuld,\ 596 fmuls,\ 597 fsqrts,\ 598 fsqrtd,\ 599 load_acq,\ 600 load_byte,\ 601 load1,\ 602 load2,\ 603 load3,\ 604 load4,\ 605 logic_imm,\ 606 logic_reg,\ 607 logic_shift_imm,\ 608 logic_shift_reg,\ 609 logics_imm,\ 610 logics_reg,\ 611 logics_shift_imm,\ 612 logics_shift_reg,\ 613 mla,\ 614 mlas,\ 615 mov_imm,\ 616 mov_reg,\ 617 mov_shift,\ 618 mov_shift_reg,\ 619 mrs,\ 620 mul,\ 621 muls,\ 622 multiple,\ 623 mvn_imm,\ 624 mvn_reg,\ 625 mvn_shift,\ 626 mvn_shift_reg,\ 627 nop,\ 628 rbit,\ 629 rev,\ 630 sdiv,\ 631 shift_imm,\ 632 shift_reg,\ 633 smlad,\ 634 smladx,\ 635 smlal,\ 636 smlald,\ 637 smlals,\ 638 smlalxy,\ 639 smlawx,\ 640 smlawy,\ 641 smlaxy,\ 642 smlsd,\ 643 smlsdx,\ 644 smlsld,\ 645 smmla,\ 646 smmul,\ 647 smmulr,\ 648 smuad,\ 649 smuadx,\ 650 smull,\ 651 smulls,\ 652 smulwy,\ 653 smulxy,\ 654 smusd,\ 655 smusdx,\ 656 store_rel,\ 657 store1,\ 658 store2,\ 659 store3,\ 660 store4,\ 661 trap,\ 662 udiv,\ 663 umaal,\ 664 umlal,\ 665 umlals,\ 666 umull,\ 667 umulls,\ 668 untyped,\ 669 wmmx_tandc,\ 670 wmmx_tbcst,\ 671 wmmx_textrc,\ 672 wmmx_textrm,\ 673 wmmx_tinsr,\ 674 wmmx_tmcr,\ 675 wmmx_tmcrr,\ 676 wmmx_tmia,\ 677 wmmx_tmiaph,\ 678 wmmx_tmiaxy,\ 679 wmmx_tmrc,\ 680 wmmx_tmrrc,\ 681 wmmx_tmovmsk,\ 682 wmmx_torc,\ 683 wmmx_torvsc,\ 684 wmmx_wabs,\ 685 wmmx_wabsdiff,\ 686 wmmx_wacc,\ 687 wmmx_wadd,\ 688 wmmx_waddbhus,\ 689 wmmx_waddsubhx,\ 690 wmmx_waligni,\ 691 wmmx_walignr,\ 692 wmmx_wand,\ 693 wmmx_wandn,\ 694 wmmx_wavg2,\ 695 wmmx_wavg4,\ 696 wmmx_wcmpeq,\ 697 wmmx_wcmpgt,\ 698 wmmx_wmac,\ 699 wmmx_wmadd,\ 700 wmmx_wmax,\ 701 wmmx_wmerge,\ 702 wmmx_wmiawxy,\ 703 wmmx_wmiaxy,\ 704 wmmx_wmin,\ 705 wmmx_wmov,\ 706 wmmx_wmul,\ 707 wmmx_wmulw,\ 708 wmmx_wldr,\ 709 wmmx_wor,\ 710 wmmx_wpack,\ 711 wmmx_wqmiaxy,\ 712 wmmx_wqmulm,\ 713 wmmx_wqmulwm,\ 714 wmmx_wror,\ 715 wmmx_wsad,\ 716 wmmx_wshufh,\ 717 wmmx_wsll,\ 718 wmmx_wsra,\ 719 wmmx_wsrl,\ 720 wmmx_wstr,\ 721 wmmx_wsub,\ 722 wmmx_wsubaddhx,\ 723 wmmx_wunpckeh,\ 724 wmmx_wunpckel,\ 725 wmmx_wunpckih,\ 726 wmmx_wunpckil,\ 727 wmmx_wxor,\ 728\ 729 neon_add,\ 730 neon_add_q,\ 731 neon_add_widen,\ 732 neon_add_long,\ 733 neon_qadd,\ 734 neon_qadd_q,\ 735 neon_add_halve,\ 736 neon_add_halve_q,\ 737 neon_add_halve_narrow_q,\ 738\ 739 neon_sub,\ 740 neon_sub_q,\ 741 neon_sub_widen,\ 742 neon_sub_long,\ 743 neon_qsub,\ 744 neon_qsub_q,\ 745 neon_sub_halve,\ 746 neon_sub_halve_q,\ 747 neon_sub_halve_narrow_q,\ 748\ 749 neon_abs,\ 750 neon_abs_q,\ 751 neon_neg,\ 752 neon_neg_q,\ 753 neon_qneg,\ 754 neon_qneg_q,\ 755 neon_qabs,\ 756 neon_qabs_q,\ 757 neon_abd,\ 758 neon_abd_q,\ 759 neon_abd_long,\ 760\ 761 neon_minmax,\ 762 neon_minmax_q,\ 763 neon_compare,\ 764 neon_compare_q,\ 765 neon_compare_zero,\ 766 neon_compare_zero_q,\ 767\ 768 neon_arith_acc,\ 769 neon_arith_acc_q,\ 770 neon_reduc_add,\ 771 neon_reduc_add_q,\ 772 neon_reduc_add_long,\ 773 neon_reduc_add_acc,\ 774 neon_reduc_add_acc_q,\ 775 neon_reduc_minmax,\ 776 neon_reduc_minmax_q,\ 777 neon_logic,\ 778 neon_logic_q,\ 779 neon_tst,\ 780 neon_tst_q,\ 781\ 782 neon_shift_imm,\ 783 neon_shift_imm_q,\ 784 neon_shift_imm_narrow_q,\ 785 neon_shift_imm_long,\ 786 neon_shift_reg,\ 787 neon_shift_reg_q,\ 788 neon_shift_acc,\ 789 neon_shift_acc_q,\ 790 neon_sat_shift_imm,\ 791 neon_sat_shift_imm_q,\ 792 neon_sat_shift_imm_narrow_q,\ 793 neon_sat_shift_reg,\ 794 neon_sat_shift_reg_q,\ 795\ 796 neon_ins,\ 797 neon_ins_q,\ 798 neon_move,\ 799 neon_move_q,\ 800 neon_move_narrow_q,\ 801 neon_permute,\ 802 neon_permute_q,\ 803 neon_zip,\ 804 neon_zip_q,\ 805 neon_tbl1,\ 806 neon_tbl1_q,\ 807 neon_tbl2,\ 808 neon_tbl2_q,\ 809 neon_tbl3,\ 810 neon_tbl3_q,\ 811 neon_tbl4,\ 812 neon_tbl4_q,\ 813\ 814 neon_bsl,\ 815 neon_bsl_q,\ 816 neon_cls,\ 817 neon_cls_q,\ 818 neon_cnt,\ 819 neon_cnt_q,\ 820 neon_dup,\ 821 neon_dup_q,\ 822 neon_ext,\ 823 neon_ext_q,\ 824 neon_rbit,\ 825 neon_rbit_q,\ 826 neon_rev,\ 827 neon_rev_q,\ 828\ 829 neon_mul_b,\ 830 neon_mul_b_q,\ 831 neon_mul_h,\ 832 neon_mul_h_q,\ 833 neon_mul_s,\ 834 neon_mul_s_q,\ 835 neon_mul_b_long,\ 836 neon_mul_h_long,\ 837 neon_mul_s_long,\ 838 neon_mul_d_long,\ 839 neon_mul_h_scalar,\ 840 neon_mul_h_scalar_q,\ 841 neon_mul_s_scalar,\ 842 neon_mul_s_scalar_q,\ 843 neon_mul_h_scalar_long,\ 844 neon_mul_s_scalar_long,\ 845\ 846 neon_sat_mul_b,\ 847 neon_sat_mul_b_q,\ 848 neon_sat_mul_h,\ 849 neon_sat_mul_h_q,\ 850 neon_sat_mul_s,\ 851 neon_sat_mul_s_q,\ 852 neon_sat_mul_b_long,\ 853 neon_sat_mul_h_long,\ 854 neon_sat_mul_s_long,\ 855 neon_sat_mul_h_scalar,\ 856 neon_sat_mul_h_scalar_q,\ 857 neon_sat_mul_s_scalar,\ 858 neon_sat_mul_s_scalar_q,\ 859 neon_sat_mul_h_scalar_long,\ 860 neon_sat_mul_s_scalar_long,\ 861\ 862 neon_mla_b,\ 863 neon_mla_b_q,\ 864 neon_mla_h,\ 865 neon_mla_h_q,\ 866 neon_mla_s,\ 867 neon_mla_s_q,\ 868 neon_mla_b_long,\ 869 neon_mla_h_long,\ 870 neon_mla_s_long,\ 871 neon_mla_h_scalar,\ 872 neon_mla_h_scalar_q,\ 873 neon_mla_s_scalar,\ 874 neon_mla_s_scalar_q,\ 875 neon_mla_h_scalar_long,\ 876 neon_mla_s_scalar_long,\ 877\ 878 neon_sat_mla_b_long,\ 879 neon_sat_mla_h_long,\ 880 neon_sat_mla_s_long,\ 881 neon_sat_mla_h_scalar_long,\ 882 neon_sat_mla_s_scalar_long,\ 883\ 884 neon_to_gp,\ 885 neon_to_gp_q,\ 886 neon_from_gp,\ 887 neon_from_gp_q,\ 888\ 889 neon_ldr,\ 890 neon_load1_1reg,\ 891 neon_load1_1reg_q,\ 892 neon_load1_2reg,\ 893 neon_load1_2reg_q,\ 894 neon_load1_3reg,\ 895 neon_load1_3reg_q,\ 896 neon_load1_4reg,\ 897 neon_load1_4reg_q,\ 898 neon_load1_all_lanes,\ 899 neon_load1_all_lanes_q,\ 900 neon_load1_one_lane,\ 901 neon_load1_one_lane_q,\ 902\ 903 neon_load2_2reg,\ 904 neon_load2_2reg_q,\ 905 neon_load2_4reg,\ 906 neon_load2_4reg_q,\ 907 neon_load2_all_lanes,\ 908 neon_load2_all_lanes_q,\ 909 neon_load2_one_lane,\ 910 neon_load2_one_lane_q,\ 911\ 912 neon_load3_3reg,\ 913 neon_load3_3reg_q,\ 914 neon_load3_all_lanes,\ 915 neon_load3_all_lanes_q,\ 916 neon_load3_one_lane,\ 917 neon_load3_one_lane_q,\ 918\ 919 neon_load4_4reg,\ 920 neon_load4_4reg_q,\ 921 neon_load4_all_lanes,\ 922 neon_load4_all_lanes_q,\ 923 neon_load4_one_lane,\ 924 neon_load4_one_lane_q,\ 925\ 926 neon_str,\ 927 neon_store1_1reg,\ 928 neon_store1_1reg_q,\ 929 neon_store1_2reg,\ 930 neon_store1_2reg_q,\ 931 neon_store1_3reg,\ 932 neon_store1_3reg_q,\ 933 neon_store1_4reg,\ 934 neon_store1_4reg_q,\ 935 neon_store1_one_lane,\ 936 neon_store1_one_lane_q,\ 937\ 938 neon_store2_2reg,\ 939 neon_store2_2reg_q,\ 940 neon_store2_4reg,\ 941 neon_store2_4reg_q,\ 942 neon_store2_one_lane,\ 943 neon_store2_one_lane_q,\ 944\ 945 neon_store3_3reg,\ 946 neon_store3_3reg_q,\ 947 neon_store3_one_lane,\ 948 neon_store3_one_lane_q,\ 949\ 950 neon_store4_4reg,\ 951 neon_store4_4reg_q,\ 952 neon_store4_one_lane,\ 953 neon_store4_one_lane_q,\ 954\ 955 neon_fp_abs_s,\ 956 neon_fp_abs_s_q,\ 957 neon_fp_abs_d,\ 958 neon_fp_abs_d_q,\ 959 neon_fp_neg_s,\ 960 neon_fp_neg_s_q,\ 961 neon_fp_neg_d,\ 962 neon_fp_neg_d_q,\ 963\ 964 neon_fp_abd_s,\ 965 neon_fp_abd_s_q,\ 966 neon_fp_abd_d,\ 967 neon_fp_abd_d_q,\ 968 neon_fp_addsub_s,\ 969 neon_fp_addsub_s_q,\ 970 neon_fp_addsub_d,\ 971 neon_fp_addsub_d_q,\ 972 neon_fp_compare_s,\ 973 neon_fp_compare_s_q,\ 974 neon_fp_compare_d,\ 975 neon_fp_compare_d_q,\ 976 neon_fp_minmax_s,\ 977 neon_fp_minmax_s_q,\ 978 neon_fp_minmax_d,\ 979 neon_fp_minmax_d_q,\ 980\ 981 neon_fp_reduc_add_s,\ 982 neon_fp_reduc_add_s_q,\ 983 neon_fp_reduc_add_d,\ 984 neon_fp_reduc_add_d_q,\ 985 neon_fp_reduc_minmax_s,\ 986 neon_fp_reduc_minmax_s_q,\ 987 neon_fp_reduc_minmax_d,\ 988 neon_fp_reduc_minmax_d_q,\ 989\ 990 neon_fp_cvt_narrow_s_q,\ 991 neon_fp_cvt_narrow_d_q,\ 992 neon_fp_cvt_widen_h,\ 993 neon_fp_cvt_widen_s,\ 994\ 995 neon_fp_to_int_s,\ 996 neon_fp_to_int_s_q,\ 997 neon_fp_to_int_d,\ 998 neon_fp_to_int_d_q,\ 999 neon_int_to_fp_s,\ 1000 neon_int_to_fp_s_q,\ 1001 neon_int_to_fp_d,\ 1002 neon_int_to_fp_d_q,\ 1003 neon_fp_round_s,\ 1004 neon_fp_round_s_q,\ 1005 neon_fp_round_d,\ 1006 neon_fp_round_d_q,\ 1007\ 1008 neon_fp_recpe_s,\ 1009 neon_fp_recpe_s_q,\ 1010 neon_fp_recpe_d,\ 1011 neon_fp_recpe_d_q,\ 1012 neon_fp_recps_s,\ 1013 neon_fp_recps_s_q,\ 1014 neon_fp_recps_d,\ 1015 neon_fp_recps_d_q,\ 1016 neon_fp_recpx_s,\ 1017 neon_fp_recpx_s_q,\ 1018 neon_fp_recpx_d,\ 1019 neon_fp_recpx_d_q,\ 1020\ 1021 neon_fp_rsqrte_s,\ 1022 neon_fp_rsqrte_s_q,\ 1023 neon_fp_rsqrte_d,\ 1024 neon_fp_rsqrte_d_q,\ 1025 neon_fp_rsqrts_s,\ 1026 neon_fp_rsqrts_s_q,\ 1027 neon_fp_rsqrts_d,\ 1028 neon_fp_rsqrts_d_q,\ 1029\ 1030 neon_fp_mul_s,\ 1031 neon_fp_mul_s_q,\ 1032 neon_fp_mul_s_scalar,\ 1033 neon_fp_mul_s_scalar_q,\ 1034 neon_fp_mul_d,\ 1035 neon_fp_mul_d_q,\ 1036 neon_fp_mul_d_scalar_q,\ 1037\ 1038 neon_fp_mla_s,\ 1039 neon_fp_mla_s_q,\ 1040 neon_fp_mla_s_scalar,\ 1041 neon_fp_mla_s_scalar_q,\ 1042 neon_fp_mla_d,\ 1043 neon_fp_mla_d_q,\ 1044 neon_fp_mla_d_scalar_q,\ 1045\ 1046 neon_fp_sqrt_s,\ 1047 neon_fp_sqrt_s_q,\ 1048 neon_fp_sqrt_d,\ 1049 neon_fp_sqrt_d_q,\ 1050 neon_fp_div_s,\ 1051 neon_fp_div_s_q,\ 1052 neon_fp_div_d,\ 1053 neon_fp_div_d_q,\ 1054\ 1055 crypto_aese,\ 1056 crypto_aesmc,\ 1057 crypto_sha1_xor,\ 1058 crypto_sha1_fast,\ 1059 crypto_sha1_slow,\ 1060 crypto_sha256_fast,\ 1061 crypto_sha256_slow" 1062 (const_string "untyped")) 1063 1064; Is this an (integer side) multiply with a 32-bit (or smaller) result? 1065(define_attr "mul32" "no,yes" 1066 (if_then_else 1067 (eq_attr "type" 1068 "smulxy,smlaxy,smulwy,smlawx,mul,muls,mla,mlas,smlawy,smuad,smuadx,\ 1069 smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,smlald,smlsld") 1070 (const_string "yes") 1071 (const_string "no"))) 1072 1073; Is this an (integer side) multiply with a 64-bit result? 1074(define_attr "mul64" "no,yes" 1075 (if_then_else 1076 (eq_attr "type" 1077 "smlalxy,umull,umulls,umaal,umlal,umlals,smull,smulls,smlal,smlals") 1078 (const_string "yes") 1079 (const_string "no"))) 1080 1081; YES if the "type" attribute assigned to the insn denotes an 1082; Advanced SIMD instruction, NO otherwise. 1083(define_attr "is_neon_type" "yes,no" 1084 (if_then_else (eq_attr "type" 1085 "neon_add, neon_add_q, neon_add_widen, neon_add_long,\ 1086 neon_qadd, neon_qadd_q, neon_add_halve, neon_add_halve_q,\ 1087 neon_add_halve_narrow_q,\ 1088 neon_sub, neon_sub_q, neon_sub_widen, neon_sub_long, neon_qsub,\ 1089 neon_qsub_q, neon_sub_halve, neon_sub_halve_q,\ 1090 neon_sub_halve_narrow_q,\ 1091 neon_abs, neon_abs_q, neon_neg, neon_neg_q, neon_qneg,\ 1092 neon_qneg_q, neon_qabs, neon_qabs_q, neon_abd, neon_abd_q,\ 1093 neon_abd_long, neon_minmax, neon_minmax_q, neon_compare,\ 1094 neon_compare_q, neon_compare_zero, neon_compare_zero_q,\ 1095 neon_arith_acc, neon_arith_acc_q, neon_reduc_add,\ 1096 neon_reduc_add_q, neon_reduc_add_long, neon_reduc_add_acc,\ 1097 neon_reduc_add_acc_q, neon_reduc_minmax, neon_reduc_minmax_q,\ 1098 neon_logic, neon_logic_q, neon_tst, neon_tst_q,\ 1099 neon_shift_imm, neon_shift_imm_q, neon_shift_imm_narrow_q,\ 1100 neon_shift_imm_long, neon_shift_reg, neon_shift_reg_q,\ 1101 neon_shift_acc, neon_shift_acc_q, neon_sat_shift_imm,\ 1102 neon_sat_shift_imm_q, neon_sat_shift_imm_narrow_q,\ 1103 neon_sat_shift_reg, neon_sat_shift_reg_q,\ 1104 neon_ins, neon_ins_q, neon_move, neon_move_q, neon_move_narrow_q,\ 1105 neon_permute, neon_permute_q, neon_zip, neon_zip_q, neon_tbl1,\ 1106 neon_tbl1_q, neon_tbl2, neon_tbl2_q, neon_tbl3, neon_tbl3_q,\ 1107 neon_tbl4, neon_tbl4_q, neon_bsl, neon_bsl_q, neon_cls,\ 1108 neon_cls_q, neon_cnt, neon_cnt_q, neon_dup, neon_dup_q,\ 1109 neon_ext, neon_ext_q, neon_rbit, neon_rbit_q,\ 1110 neon_rev, neon_rev_q, neon_mul_b, neon_mul_b_q, neon_mul_h,\ 1111 neon_mul_h_q, neon_mul_s, neon_mul_s_q, neon_mul_b_long,\ 1112 neon_mul_h_long, neon_mul_s_long, neon_mul_d_long, neon_mul_h_scalar,\ 1113 neon_mul_h_scalar_q, neon_mul_s_scalar, neon_mul_s_scalar_q,\ 1114 neon_mul_h_scalar_long, neon_mul_s_scalar_long, neon_sat_mul_b,\ 1115 neon_sat_mul_b_q, neon_sat_mul_h, neon_sat_mul_h_q,\ 1116 neon_sat_mul_s, neon_sat_mul_s_q, neon_sat_mul_b_long,\ 1117 neon_sat_mul_h_long, neon_sat_mul_s_long, neon_sat_mul_h_scalar,\ 1118 neon_sat_mul_h_scalar_q, neon_sat_mul_s_scalar,\ 1119 neon_sat_mul_s_scalar_q, neon_sat_mul_h_scalar_long,\ 1120 neon_sat_mul_s_scalar_long, neon_mla_b, neon_mla_b_q, neon_mla_h,\ 1121 neon_mla_h_q, neon_mla_s, neon_mla_s_q, neon_mla_b_long,\ 1122 neon_mla_h_long, neon_mla_s_long, neon_mla_h_scalar,\ 1123 neon_mla_h_scalar_q, neon_mla_s_scalar, neon_mla_s_scalar_q,\ 1124 neon_mla_h_scalar_long, neon_mla_s_scalar_long,\ 1125 neon_sat_mla_b_long, neon_sat_mla_h_long,\ 1126 neon_sat_mla_s_long, neon_sat_mla_h_scalar_long,\ 1127 neon_sat_mla_s_scalar_long,\ 1128 neon_to_gp, neon_to_gp_q, neon_from_gp, neon_from_gp_q,\ 1129 neon_ldr, neon_load1_1reg, neon_load1_1reg_q, neon_load1_2reg,\ 1130 neon_load1_2reg_q, neon_load1_3reg, neon_load1_3reg_q,\ 1131 neon_load1_4reg, neon_load1_4reg_q, neon_load1_all_lanes,\ 1132 neon_load1_all_lanes_q, neon_load1_one_lane, neon_load1_one_lane_q,\ 1133 neon_load2_2reg, neon_load2_2reg_q, neon_load2_4reg,\ 1134 neon_load2_4reg_q, neon_load2_all_lanes, neon_load2_all_lanes_q,\ 1135 neon_load2_one_lane, neon_load2_one_lane_q,\ 1136 neon_load3_3reg, neon_load3_3reg_q, neon_load3_all_lanes,\ 1137 neon_load3_all_lanes_q, neon_load3_one_lane, neon_load3_one_lane_q,\ 1138 neon_load4_4reg, neon_load4_4reg_q, neon_load4_all_lanes,\ 1139 neon_load4_all_lanes_q, neon_load4_one_lane, neon_load4_one_lane_q,\ 1140 neon_str, neon_store1_1reg, neon_store1_1reg_q, neon_store1_2reg,\ 1141 neon_store1_2reg_q, neon_store1_3reg, neon_store1_3reg_q,\ 1142 neon_store1_4reg, neon_store1_4reg_q, neon_store1_one_lane,\ 1143 neon_store1_one_lane_q, neon_store2_2reg, neon_store2_2reg_q,\ 1144 neon_store2_4reg, neon_store2_4reg_q, neon_store2_one_lane,\ 1145 neon_store2_one_lane_q, neon_store3_3reg, neon_store3_3reg_q,\ 1146 neon_store3_one_lane, neon_store3_one_lane_q, neon_store4_4reg,\ 1147 neon_store4_4reg_q, neon_store4_one_lane, neon_store4_one_lane_q,\ 1148 neon_fp_abd_s, neon_fp_abd_s_q, neon_fp_abd_d, neon_fp_abd_d_q,\ 1149 neon_fp_addsub_s, neon_fp_addsub_s_q, neon_fp_addsub_d,\ 1150 neon_fp_addsub_d_q, neon_fp_compare_s, neon_fp_compare_s_q,\ 1151 neon_fp_compare_d, neon_fp_compare_d_q, neon_fp_minmax_s,\ 1152 neon_fp_minmax_s_q, neon_fp_minmax_d, neon_fp_minmax_d_q,\ 1153 neon_fp_reduc_add_s, neon_fp_reduc_add_s_q, neon_fp_reduc_add_d,\ 1154 neon_fp_reduc_add_d_q, neon_fp_reduc_minmax_s, 1155 neon_fp_reduc_minmax_s_q, neon_fp_reduc_minmax_d,\ 1156 neon_fp_reduc_minmax_d_q,\ 1157 neon_fp_cvt_narrow_s_q, neon_fp_cvt_narrow_d_q,\ 1158 neon_fp_cvt_widen_h, neon_fp_cvt_widen_s, neon_fp_to_int_s,\ 1159 neon_fp_to_int_s_q, neon_int_to_fp_s, neon_int_to_fp_s_q,\ 1160 neon_fp_round_s, neon_fp_round_s_q, neon_fp_recpe_s,\ 1161 neon_fp_recpe_s_q,\ 1162 neon_fp_recpe_d, neon_fp_recpe_d_q, neon_fp_recps_s,\ 1163 neon_fp_recps_s_q, neon_fp_recps_d, neon_fp_recps_d_q,\ 1164 neon_fp_recpx_s, neon_fp_recpx_s_q, neon_fp_recpx_d,\ 1165 neon_fp_recpx_d_q, neon_fp_rsqrte_s, neon_fp_rsqrte_s_q,\ 1166 neon_fp_rsqrte_d, neon_fp_rsqrte_d_q, neon_fp_rsqrts_s,\ 1167 neon_fp_rsqrts_s_q, neon_fp_rsqrts_d, neon_fp_rsqrts_d_q,\ 1168 neon_fp_mul_s, neon_fp_mul_s_q, neon_fp_mul_s_scalar,\ 1169 neon_fp_mul_s_scalar_q, neon_fp_mul_d, neon_fp_mul_d_q,\ 1170 neon_fp_mul_d_scalar_q, neon_fp_mla_s, neon_fp_mla_s_q,\ 1171 neon_fp_mla_s_scalar, neon_fp_mla_s_scalar_q, neon_fp_mla_d,\ 1172 neon_fp_mla_d_q, neon_fp_mla_d_scalar_q, neon_fp_sqrt_s,\ 1173 neon_fp_sqrt_s_q, neon_fp_sqrt_d, neon_fp_sqrt_d_q,\ 1174 neon_fp_div_s, neon_fp_div_s_q, neon_fp_div_d, neon_fp_div_d_q, crypto_aese,\ 1175 crypto_aesmc, crypto_sha1_xor, crypto_sha1_fast, crypto_sha1_slow,\ 1176 crypto_sha256_fast, crypto_sha256_slow") 1177 (const_string "yes") 1178 (const_string "no"))) 1179