1;; Code and mode itertator and attribute definitions for the ARM backend 2;; Copyright (C) 2010-2015 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21 22;;---------------------------------------------------------------------------- 23;; Mode iterators 24;;---------------------------------------------------------------------------- 25 26;; A list of modes that are exactly 64 bits in size. This is used to expand 27;; some splits that are the same for all modes when operating on ARM 28;; registers. 29(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF]) 30 31(define_mode_iterator ANY128 [V2DI V2DF V16QI V8HI V4SI V4SF]) 32 33;; A list of integer modes that are up to one word long 34(define_mode_iterator QHSI [QI HI SI]) 35 36;; A list of integer modes that are less than a word 37(define_mode_iterator NARROW [QI HI]) 38 39;; A list of all the integer modes up to 64bit 40(define_mode_iterator QHSD [QI HI SI DI]) 41 42;; A list of the 32bit and 64bit integer modes 43(define_mode_iterator SIDI [SI DI]) 44 45;; A list of modes which the VFP unit can handle 46(define_mode_iterator SDF [(SF "TARGET_VFP") (DF "TARGET_VFP_DOUBLE")]) 47 48;; Integer element sizes implemented by IWMMXT. 49(define_mode_iterator VMMX [V2SI V4HI V8QI]) 50 51(define_mode_iterator VMMX2 [V4HI V2SI]) 52 53;; Integer element sizes for shifts. 54(define_mode_iterator VSHFT [V4HI V2SI DI]) 55 56;; Integer and float modes supported by Neon and IWMMXT. 57(define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) 58 59;; Integer and float modes supported by Neon and IWMMXT, except V2DI. 60(define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) 61 62;; Integer modes supported by Neon and IWMMXT 63(define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI]) 64 65;; Integer modes supported by Neon and IWMMXT, except V2DI 66(define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI]) 67 68;; Double-width vector modes. 69(define_mode_iterator VD [V8QI V4HI V2SI V2SF]) 70 71;; Double-width vector modes plus 64-bit elements. 72(define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI]) 73 74;; Double-width vector modes without floating-point elements. 75(define_mode_iterator VDI [V8QI V4HI V2SI]) 76 77;; Quad-width vector modes. 78(define_mode_iterator VQ [V16QI V8HI V4SI V4SF]) 79 80;; Quad-width vector modes plus 64-bit elements. 81(define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI]) 82 83;; Quad-width vector modes without floating-point elements. 84(define_mode_iterator VQI [V16QI V8HI V4SI]) 85 86;; Quad-width vector modes, with TImode added, for moves. 87(define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI]) 88 89;; Opaque structure types wider than TImode. 90(define_mode_iterator VSTRUCT [EI OI CI XI]) 91 92;; Opaque structure types used in table lookups (except vtbl1/vtbx1). 93(define_mode_iterator VTAB [TI EI OI]) 94 95;; Widenable modes. 96(define_mode_iterator VW [V8QI V4HI V2SI]) 97 98;; Narrowable modes. 99(define_mode_iterator VN [V8HI V4SI V2DI]) 100 101;; All supported vector modes (except singleton DImode). 102(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI]) 103 104;; All supported vector modes (except those with 64-bit integer elements). 105(define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF]) 106 107;; Supported integer vector modes (not 64 bit elements). 108(define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI]) 109 110;; Supported integer vector modes (not singleton DI) 111(define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) 112 113;; Vector modes, including 64-bit integer elements. 114(define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI]) 115 116;; Vector modes including 64-bit integer elements, but no floats. 117(define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI]) 118 119;; Vector modes for H, S and D types. 120(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) 121 122;; Vector modes for float->int conversions. 123(define_mode_iterator VCVTF [V2SF V4SF]) 124 125;; Vector modes form int->float conversions. 126(define_mode_iterator VCVTI [V2SI V4SI]) 127 128;; Vector modes for doubleword multiply-accumulate, etc. insns. 129(define_mode_iterator VMD [V4HI V2SI V2SF]) 130 131;; Vector modes for quadword multiply-accumulate, etc. insns. 132(define_mode_iterator VMQ [V8HI V4SI V4SF]) 133 134;; Above modes combined. 135(define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF]) 136 137;; As VMD, but integer modes only. 138(define_mode_iterator VMDI [V4HI V2SI]) 139 140;; As VMQ, but integer modes only. 141(define_mode_iterator VMQI [V8HI V4SI]) 142 143;; Above modes combined. 144(define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI]) 145 146;; Modes with 8-bit and 16-bit elements. 147(define_mode_iterator VX [V8QI V4HI V16QI V8HI]) 148 149;; Modes with 8-bit elements. 150(define_mode_iterator VE [V8QI V16QI]) 151 152;; Modes with 64-bit elements only. 153(define_mode_iterator V64 [DI V2DI]) 154 155;; Modes with 32-bit elements only. 156(define_mode_iterator V32 [V2SI V2SF V4SI V4SF]) 157 158;; Modes with 8-bit, 16-bit and 32-bit elements. 159(define_mode_iterator VU [V16QI V8HI V4SI]) 160 161;; Iterators used for fixed-point support. 162(define_mode_iterator FIXED [QQ HQ SQ UQQ UHQ USQ HA SA UHA USA]) 163 164(define_mode_iterator ADDSUB [V4QQ V2HQ V2HA]) 165 166(define_mode_iterator UQADDSUB [V4UQQ V2UHQ UQQ UHQ V2UHA UHA]) 167 168(define_mode_iterator QADDSUB [V4QQ V2HQ QQ HQ V2HA HA SQ SA]) 169 170(define_mode_iterator QMUL [HQ HA]) 171 172;; Modes for polynomial or float values. 173(define_mode_iterator VPF [V8QI V16QI V2SF V4SF]) 174 175;;---------------------------------------------------------------------------- 176;; Code iterators 177;;---------------------------------------------------------------------------- 178 179;; A list of condition codes used in compare instructions where 180;; the carry flag from the addition is used instead of doing the 181;; compare a second time. 182(define_code_iterator LTUGEU [ltu geu]) 183 184;; A list of ... 185(define_code_iterator ior_xor [ior xor]) 186 187;; Operations on two halves of a quadword vector. 188(define_code_iterator vqh_ops [plus smin smax umin umax]) 189 190;; Operations on two halves of a quadword vector, 191;; without unsigned variants (for use with *SFmode pattern). 192(define_code_iterator vqhs_ops [plus smin smax]) 193 194;; A list of widening operators 195(define_code_iterator SE [sign_extend zero_extend]) 196 197;; Right shifts 198(define_code_iterator rshifts [ashiftrt lshiftrt]) 199 200;; Iterator for integer conversions 201(define_code_iterator FIXUORS [fix unsigned_fix]) 202 203;; Binary operators whose second operand can be shifted. 204(define_code_iterator shiftable_ops [plus minus ior xor and]) 205 206;; plus and minus are the only shiftable_ops for which Thumb2 allows 207;; a stack pointer opoerand. The minus operation is a candidate for an rsub 208;; and hence only plus is supported. 209(define_code_attr t2_binop0 210 [(plus "rk") (minus "r") (ior "r") (xor "r") (and "r")]) 211 212;; The instruction to use when a shiftable_ops has a shift operation as 213;; its first operand. 214(define_code_attr arith_shift_insn 215 [(plus "add") (minus "rsb") (ior "orr") (xor "eor") (and "and")]) 216 217;;---------------------------------------------------------------------------- 218;; Int iterators 219;;---------------------------------------------------------------------------- 220 221(define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM 222 UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA]) 223 224(define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA]) 225 226(define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM 227 UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN]) 228 229(define_int_iterator NEON_VCVT [UNSPEC_NVRINTP UNSPEC_NVRINTM UNSPEC_NVRINTA]) 230 231(define_int_iterator VADDL [UNSPEC_VADDL_S UNSPEC_VADDL_U]) 232 233(define_int_iterator VADDW [UNSPEC_VADDW_S UNSPEC_VADDW_U]) 234 235(define_int_iterator VHADD [UNSPEC_VRHADD_S UNSPEC_VRHADD_U 236 UNSPEC_VHADD_S UNSPEC_VHADD_U]) 237 238(define_int_iterator VQADD [UNSPEC_VQADD_S UNSPEC_VQADD_U]) 239 240(define_int_iterator VADDHN [UNSPEC_VADDHN UNSPEC_VRADDHN]) 241 242(define_int_iterator VMLAL [UNSPEC_VMLAL_S UNSPEC_VMLAL_U]) 243 244(define_int_iterator VMLAL_LANE [UNSPEC_VMLAL_S_LANE UNSPEC_VMLAL_U_LANE]) 245 246(define_int_iterator VMLSL [UNSPEC_VMLSL_S UNSPEC_VMLSL_U]) 247 248(define_int_iterator VMLSL_LANE [UNSPEC_VMLSL_S_LANE UNSPEC_VMLSL_U_LANE]) 249 250(define_int_iterator VQDMULH [UNSPEC_VQDMULH UNSPEC_VQRDMULH]) 251 252(define_int_iterator VQDMULH_LANE [UNSPEC_VQDMULH_LANE UNSPEC_VQRDMULH_LANE]) 253 254(define_int_iterator VMULL [UNSPEC_VMULL_S UNSPEC_VMULL_U UNSPEC_VMULL_P]) 255 256(define_int_iterator VMULL_LANE [UNSPEC_VMULL_S_LANE UNSPEC_VMULL_U_LANE]) 257 258(define_int_iterator VSUBL [UNSPEC_VSUBL_S UNSPEC_VSUBL_U]) 259 260(define_int_iterator VSUBW [UNSPEC_VSUBW_S UNSPEC_VSUBW_U]) 261 262(define_int_iterator VHSUB [UNSPEC_VHSUB_S UNSPEC_VHSUB_U]) 263 264(define_int_iterator VQSUB [UNSPEC_VQSUB_S UNSPEC_VQSUB_U]) 265 266(define_int_iterator VSUBHN [UNSPEC_VSUBHN UNSPEC_VRSUBHN]) 267 268(define_int_iterator VABD [UNSPEC_VABD_S UNSPEC_VABD_U]) 269 270(define_int_iterator VABDL [UNSPEC_VABDL_S UNSPEC_VABDL_U]) 271 272(define_int_iterator VMAXMIN [UNSPEC_VMAX UNSPEC_VMAX_U 273 UNSPEC_VMIN UNSPEC_VMIN_U]) 274 275(define_int_iterator VMAXMINF [UNSPEC_VMAX UNSPEC_VMIN]) 276 277(define_int_iterator VPADDL [UNSPEC_VPADDL_S UNSPEC_VPADDL_U]) 278 279(define_int_iterator VPADAL [UNSPEC_VPADAL_S UNSPEC_VPADAL_U]) 280 281(define_int_iterator VPMAXMIN [UNSPEC_VPMAX UNSPEC_VPMAX_U 282 UNSPEC_VPMIN UNSPEC_VPMIN_U]) 283 284(define_int_iterator VPMAXMINF [UNSPEC_VPMAX UNSPEC_VPMIN]) 285 286(define_int_iterator VCVT_US [UNSPEC_VCVT_S UNSPEC_VCVT_U]) 287 288(define_int_iterator VCVT_US_N [UNSPEC_VCVT_S_N UNSPEC_VCVT_U_N]) 289 290(define_int_iterator VQMOVN [UNSPEC_VQMOVN_S UNSPEC_VQMOVN_U]) 291 292(define_int_iterator VMOVL [UNSPEC_VMOVL_S UNSPEC_VMOVL_U]) 293 294(define_int_iterator VSHL [UNSPEC_VSHL_S UNSPEC_VSHL_U 295 UNSPEC_VRSHL_S UNSPEC_VRSHL_U]) 296 297(define_int_iterator VQSHL [UNSPEC_VQSHL_S UNSPEC_VQSHL_U 298 UNSPEC_VQRSHL_S UNSPEC_VQRSHL_U]) 299 300(define_int_iterator VSHR_N [UNSPEC_VSHR_S_N UNSPEC_VSHR_U_N 301 UNSPEC_VRSHR_S_N UNSPEC_VRSHR_U_N]) 302 303(define_int_iterator VSHRN_N [UNSPEC_VSHRN_N UNSPEC_VRSHRN_N]) 304 305(define_int_iterator VQSHRN_N [UNSPEC_VQSHRN_S_N UNSPEC_VQSHRN_U_N 306 UNSPEC_VQRSHRN_S_N UNSPEC_VQRSHRN_U_N]) 307 308(define_int_iterator VQSHRUN_N [UNSPEC_VQSHRUN_N UNSPEC_VQRSHRUN_N]) 309 310(define_int_iterator VQSHL_N [UNSPEC_VQSHL_S_N UNSPEC_VQSHL_U_N]) 311 312(define_int_iterator VSHLL_N [UNSPEC_VSHLL_S_N UNSPEC_VSHLL_U_N]) 313 314(define_int_iterator VSRA_N [UNSPEC_VSRA_S_N UNSPEC_VSRA_U_N 315 UNSPEC_VRSRA_S_N UNSPEC_VRSRA_U_N]) 316 317(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W 318 UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW]) 319 320(define_int_iterator CRYPTO_UNARY [UNSPEC_AESMC UNSPEC_AESIMC]) 321 322(define_int_iterator CRYPTO_BINARY [UNSPEC_AESD UNSPEC_AESE 323 UNSPEC_SHA1SU1 UNSPEC_SHA256SU0]) 324 325(define_int_iterator CRYPTO_TERNARY [UNSPEC_SHA1SU0 UNSPEC_SHA256H 326 UNSPEC_SHA256H2 UNSPEC_SHA256SU1]) 327 328(define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M 329 UNSPEC_SHA1P]) 330 331;;---------------------------------------------------------------------------- 332;; Mode attributes 333;;---------------------------------------------------------------------------- 334 335;; Determine element size suffix from vector mode. 336(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) 337 338;; vtbl<n> suffix for NEON vector modes. 339(define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) 340 341;; (Opposite) mode to convert to/from for NEON mode conversions. 342(define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") 343 (V4SI "V4SF") (V4SF "V4SI")]) 344 345;; As above but in lower case. 346(define_mode_attr V_cvtto [(V2SI "v2sf") (V2SF "v2si") 347 (V4SI "v4sf") (V4SF "v4si")]) 348 349;; Define element mode for each vector mode. 350(define_mode_attr V_elem [(V8QI "QI") (V16QI "QI") 351 (V4HI "HI") (V8HI "HI") 352 (V2SI "SI") (V4SI "SI") 353 (V2SF "SF") (V4SF "SF") 354 (DI "DI") (V2DI "DI")]) 355 356;; Element modes for vector extraction, padded up to register size. 357 358(define_mode_attr V_ext [(V8QI "SI") (V16QI "SI") 359 (V4HI "SI") (V8HI "SI") 360 (V2SI "SI") (V4SI "SI") 361 (V2SF "SF") (V4SF "SF") 362 (DI "DI") (V2DI "DI")]) 363 364;; Mode of pair of elements for each vector mode, to define transfer 365;; size for structure lane/dup loads and stores. 366(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") 367 (V4HI "SI") (V8HI "SI") 368 (V2SI "V2SI") (V4SI "V2SI") 369 (V2SF "V2SF") (V4SF "V2SF") 370 (DI "V2DI") (V2DI "V2DI")]) 371 372;; Similar, for three elements. 373(define_mode_attr V_three_elem [(V8QI "BLK") (V16QI "BLK") 374 (V4HI "BLK") (V8HI "BLK") 375 (V2SI "BLK") (V4SI "BLK") 376 (V2SF "BLK") (V4SF "BLK") 377 (DI "EI") (V2DI "EI")]) 378 379;; Similar, for four elements. 380(define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI") 381 (V4HI "V4HI") (V8HI "V4HI") 382 (V2SI "V4SI") (V4SI "V4SI") 383 (V2SF "V4SF") (V4SF "V4SF") 384 (DI "OI") (V2DI "OI")]) 385 386;; Register width from element mode 387(define_mode_attr V_reg [(V8QI "P") (V16QI "q") 388 (V4HI "P") (V8HI "q") 389 (V2SI "P") (V4SI "q") 390 (V2SF "P") (V4SF "q") 391 (DI "P") (V2DI "q") 392 (SF "") (DF "P")]) 393 394;; Wider modes with the same number of elements. 395(define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")]) 396 397;; Narrower modes with the same number of elements. 398(define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")]) 399 400;; Narrower modes with double the number of elements. 401(define_mode_attr V_narrow_pack [(V4SI "V8HI") (V8HI "V16QI") (V2DI "V4SI") 402 (V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")]) 403 404;; Modes with half the number of equal-sized elements. 405(define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI") 406 (V4SI "V2SI") (V4SF "V2SF") (V2DF "DF") 407 (V2DI "DI")]) 408 409;; Same, but lower-case. 410(define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi") 411 (V4SI "v2si") (V4SF "v2sf") 412 (V2DI "di")]) 413 414;; Modes with twice the number of equal-sized elements. 415(define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI") 416 (V2SI "V4SI") (V2SF "V4SF") (DF "V2DF") 417 (DI "V2DI")]) 418 419;; Same, but lower-case. 420(define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi") 421 (V2SI "v4si") (V2SF "v4sf") 422 (DI "v2di")]) 423 424;; Modes with double-width elements. 425(define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI") 426 (V4HI "V2SI") (V8HI "V4SI") 427 (V2SI "DI") (V4SI "V2DI")]) 428 429;; Double-sized modes with the same element size. 430;; Used for neon_vdup_lane, where the second operand is double-sized 431;; even when the first one is quad. 432(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI") 433 (V4SI "V2SI") (V4SF "V2SF") 434 (V8QI "V8QI") (V4HI "V4HI") 435 (V2SI "V2SI") (V2SF "V2SF")]) 436 437;; Mode of result of comparison operations (and bit-select operand 1). 438(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") 439 (V4HI "V4HI") (V8HI "V8HI") 440 (V2SI "V2SI") (V4SI "V4SI") 441 (V2SF "V2SI") (V4SF "V4SI") 442 (DI "DI") (V2DI "V2DI")]) 443 444(define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") 445 (V4HI "v4hi") (V8HI "v8hi") 446 (V2SI "v2si") (V4SI "v4si") 447 (DI "di") (V2DI "v2di") 448 (V2SF "v2si") (V4SF "v4si")]) 449 450;; Get element type from double-width mode, for operations where we 451;; don't care about signedness. 452(define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8") 453 (V4HI "i16") (V8HI "i16") 454 (V2SI "i32") (V4SI "i32") 455 (DI "i64") (V2DI "i64") 456 (V2SF "f32") (V4SF "f32") 457 (SF "f32") (DF "f64")]) 458 459;; Same, but for operations which work on signed values. 460(define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8") 461 (V4HI "s16") (V8HI "s16") 462 (V2SI "s32") (V4SI "s32") 463 (DI "s64") (V2DI "s64") 464 (V2SF "f32") (V4SF "f32")]) 465 466;; Same, but for operations which work on unsigned values. 467(define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8") 468 (V4HI "u16") (V8HI "u16") 469 (V2SI "u32") (V4SI "u32") 470 (DI "u64") (V2DI "u64") 471 (V2SF "f32") (V4SF "f32")]) 472 473;; Element types for extraction of unsigned scalars. 474(define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8") 475 (V4HI "u16") (V8HI "u16") 476 (V2SI "32") (V4SI "32") 477 (V2SF "32") (V4SF "32")]) 478 479(define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8") 480 (V4HI "16") (V8HI "16") 481 (V2SI "32") (V4SI "32") 482 (DI "64") (V2DI "64") 483 (V2SF "32") (V4SF "32")]) 484 485(define_mode_attr V_elem_ch [(V8QI "b") (V16QI "b") 486 (V4HI "h") (V8HI "h") 487 (V2SI "s") (V4SI "s") 488 (DI "d") (V2DI "d") 489 (V2SF "s") (V4SF "s")]) 490 491;; Element sizes for duplicating ARM registers to all elements of a vector. 492(define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")]) 493 494;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.) 495(define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI") 496 (V4HI "TI") (V8HI "OI") 497 (V2SI "TI") (V4SI "OI") 498 (V2SF "TI") (V4SF "OI") 499 (DI "TI") (V2DI "OI")]) 500 501;; Same, but lower-case. 502(define_mode_attr V_pair [(V8QI "ti") (V16QI "oi") 503 (V4HI "ti") (V8HI "oi") 504 (V2SI "ti") (V4SI "oi") 505 (V2SF "ti") (V4SF "oi") 506 (DI "ti") (V2DI "oi")]) 507 508;; Extra suffix on some 64-bit insn names (to avoid collision with standard 509;; names which we don't want to define). 510(define_mode_attr V_suf64 [(V8QI "") (V16QI "") 511 (V4HI "") (V8HI "") 512 (V2SI "") (V4SI "") 513 (V2SF "") (V4SF "") 514 (DI "_neon") (V2DI "")]) 515 516 517;; Scalars to be presented to scalar multiplication instructions 518;; must satisfy the following constraints. 519;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7. 520;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15. 521 522;; This mode attribute is used to obtain the correct register constraints. 523 524(define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t") 525 (V8HI "x") (V4SI "t") (V4SF "t")]) 526 527;; Predicates used for setting type for neon instructions 528 529(define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false") 530 (V4HI "false") (V8HI "false") 531 (V2SI "false") (V4SI "false") 532 (V2SF "true") (V4SF "true") 533 (DI "false") (V2DI "false")]) 534 535(define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true") 536 (V4HI "true") (V8HI "true") 537 (V2SI "false") (V4SI "false") 538 (V2SF "false") (V4SF "false") 539 (DI "false") (V2DI "false")]) 540 541 542(define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false") 543 (V4HI "true") (V8HI "false") 544 (V2SI "true") (V4SI "false") 545 (V2SF "true") (V4SF "false") 546 (DI "true") (V2DI "false")]) 547 548(define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16") 549 (V4HI "4") (V8HI "8") 550 (V2SI "2") (V4SI "4") 551 (V2SF "2") (V4SF "4") 552 (DI "1") (V2DI "2") 553 (DF "1") (V2DF "2")]) 554 555;; Same as V_widen, but lower-case. 556(define_mode_attr V_widen_l [(V8QI "v8hi") (V4HI "v4si") ( V2SI "v2di")]) 557 558;; Widen. Result is half the number of elements, but widened to double-width. 559(define_mode_attr V_unpack [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")]) 560 561;; Conditions to be used in extend<mode>di patterns. 562(define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")]) 563(define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6") 564 (QI "&& arm_arch6")]) 565(define_mode_attr qhs_zextenddi_op [(SI "s_register_operand") 566 (HI "nonimmediate_operand") 567 (QI "nonimmediate_operand")]) 568(define_mode_attr qhs_extenddi_op [(SI "s_register_operand") 569 (HI "nonimmediate_operand") 570 (QI "arm_reg_or_extendqisi_mem_op")]) 571(define_mode_attr qhs_extenddi_cstr [(SI "r,0,r,r,r") (HI "r,0,rm,rm,r") (QI "r,0,rUq,rm,r")]) 572(define_mode_attr qhs_zextenddi_cstr [(SI "r,0,r,r") (HI "r,0,rm,r") (QI "r,0,rm,r")]) 573 574;; Mode attributes used for fixed-point support. 575(define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16") 576 (V2UHA "16") (UHA "16") 577 (V4QQ "8") (V2HQ "16") (QQ "8") (HQ "16") 578 (V2HA "16") (HA "16") (SQ "") (SA "")]) 579 580;; Mode attribute for vshll. 581(define_mode_attr V_innermode [(V8QI "QI") (V4HI "HI") (V2SI "SI")]) 582 583;; Mode attributes used for VFP support. 584(define_mode_attr F_constraint [(SF "t") (DF "w")]) 585(define_mode_attr vfp_type [(SF "s") (DF "d")]) 586(define_mode_attr vfp_double_cond [(SF "") (DF "&& TARGET_VFP_DOUBLE")]) 587 588;; Mode attribute used to build the "type" attribute. 589(define_mode_attr q [(V8QI "") (V16QI "_q") 590 (V4HI "") (V8HI "_q") 591 (V2SI "") (V4SI "_q") 592 (V2SF "") (V4SF "_q") 593 (DI "") (V2DI "_q") 594 (DF "") (V2DF "_q")]) 595 596(define_mode_attr pf [(V8QI "p") (V16QI "p") (V2SF "f") (V4SF "f")]) 597 598;;---------------------------------------------------------------------------- 599;; Code attributes 600;;---------------------------------------------------------------------------- 601 602;; Assembler mnemonics for vqh_ops and vqhs_ops iterators. 603(define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") 604 (umin "vmin") (umax "vmax")]) 605 606;; Type attributes for vqh_ops and vqhs_ops iterators. 607(define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax") 608 (umin "minmax") (umax "minmax")]) 609 610;; Signs of above, where relevant. 611(define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u") 612 (umax "u")]) 613 614(define_code_attr cnb [(ltu "CC_C") (geu "CC")]) 615(define_code_attr optab [(ltu "ltu") (geu "geu")]) 616 617;; Assembler mnemonics for signedness of widening operations. 618(define_code_attr US [(sign_extend "s") (zero_extend "u")]) 619 620;; Signedness suffix for float->fixed conversions. Empty for signed 621;; conversion. 622(define_code_attr su_optab [(fix "") (unsigned_fix "u")]) 623 624;; Sign prefix to use in instruction type suffixes, i.e. s32, u32. 625(define_code_attr su [(fix "s") (unsigned_fix "u")]) 626 627;; Right shifts 628(define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")]) 629(define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")]) 630 631;;---------------------------------------------------------------------------- 632;; Int attributes 633;;---------------------------------------------------------------------------- 634 635;; Mapping between vector UNSPEC operations and the signed ('s'), 636;; unsigned ('u'), poly ('p') or float ('f') nature of their data type. 637(define_int_attr sup [ 638 (UNSPEC_VADDL_S "s") (UNSPEC_VADDL_U "u") 639 (UNSPEC_VADDW_S "s") (UNSPEC_VADDW_U "u") 640 (UNSPEC_VRHADD_S "s") (UNSPEC_VRHADD_U "u") 641 (UNSPEC_VHADD_S "s") (UNSPEC_VHADD_U "u") 642 (UNSPEC_VQADD_S "s") (UNSPEC_VQADD_U "u") 643 (UNSPEC_VMLAL_S "s") (UNSPEC_VMLAL_U "u") 644 (UNSPEC_VMLAL_S_LANE "s") (UNSPEC_VMLAL_U_LANE "u") 645 (UNSPEC_VMLSL_S "s") (UNSPEC_VMLSL_U "u") 646 (UNSPEC_VMLSL_S_LANE "s") (UNSPEC_VMLSL_U_LANE "u") 647 (UNSPEC_VMULL_S "s") (UNSPEC_VMULL_U "u") (UNSPEC_VMULL_P "p") 648 (UNSPEC_VMULL_S_LANE "s") (UNSPEC_VMULL_U_LANE "u") 649 (UNSPEC_VSUBL_S "s") (UNSPEC_VSUBL_U "u") 650 (UNSPEC_VSUBW_S "s") (UNSPEC_VSUBW_U "u") 651 (UNSPEC_VHSUB_S "s") (UNSPEC_VHSUB_U "u") 652 (UNSPEC_VQSUB_S "s") (UNSPEC_VQSUB_U "u") 653 (UNSPEC_VABD_S "s") (UNSPEC_VABD_U "u") 654 (UNSPEC_VABDL_S "s") (UNSPEC_VABDL_U "u") 655 (UNSPEC_VMAX "s") (UNSPEC_VMAX_U "u") 656 (UNSPEC_VMIN "s") (UNSPEC_VMIN_U "u") 657 (UNSPEC_VPADDL_S "s") (UNSPEC_VPADDL_U "u") 658 (UNSPEC_VPADAL_S "s") (UNSPEC_VPADAL_U "u") 659 (UNSPEC_VPMAX "s") (UNSPEC_VPMAX_U "u") 660 (UNSPEC_VPMIN "s") (UNSPEC_VPMIN_U "u") 661 (UNSPEC_VCVT_S "s") (UNSPEC_VCVT_U "u") 662 (UNSPEC_VCVT_S_N "s") (UNSPEC_VCVT_U_N "u") 663 (UNSPEC_VQMOVN_S "s") (UNSPEC_VQMOVN_U "u") 664 (UNSPEC_VMOVL_S "s") (UNSPEC_VMOVL_U "u") 665 (UNSPEC_VSHL_S "s") (UNSPEC_VSHL_U "u") 666 (UNSPEC_VRSHL_S "s") (UNSPEC_VRSHL_U "u") 667 (UNSPEC_VQSHL_S "s") (UNSPEC_VQSHL_U "u") 668 (UNSPEC_VQRSHL_S "s") (UNSPEC_VQRSHL_U "u") 669 (UNSPEC_VSHR_S_N "s") (UNSPEC_VSHR_U_N "u") 670 (UNSPEC_VRSHR_S_N "s") (UNSPEC_VRSHR_U_N "u") 671 (UNSPEC_VQSHRN_S_N "s") (UNSPEC_VQSHRN_U_N "u") 672 (UNSPEC_VQRSHRN_S_N "s") (UNSPEC_VQRSHRN_U_N "u") 673 (UNSPEC_VQSHL_S_N "s") (UNSPEC_VQSHL_U_N "u") 674 (UNSPEC_VSHLL_S_N "s") (UNSPEC_VSHLL_U_N "u") 675 (UNSPEC_VSRA_S_N "s") (UNSPEC_VSRA_U_N "u") 676 (UNSPEC_VRSRA_S_N "s") (UNSPEC_VRSRA_U_N "u") 677 678]) 679 680(define_int_attr r [ 681 (UNSPEC_VRHADD_S "r") (UNSPEC_VRHADD_U "r") 682 (UNSPEC_VHADD_S "") (UNSPEC_VHADD_U "") 683 (UNSPEC_VADDHN "") (UNSPEC_VRADDHN "r") 684 (UNSPEC_VQDMULH "") (UNSPEC_VQRDMULH "r") 685 (UNSPEC_VQDMULH_LANE "") (UNSPEC_VQRDMULH_LANE "r") 686 (UNSPEC_VSUBHN "") (UNSPEC_VRSUBHN "r") 687]) 688 689(define_int_attr maxmin [ 690 (UNSPEC_VMAX "max") (UNSPEC_VMAX_U "max") 691 (UNSPEC_VMIN "min") (UNSPEC_VMIN_U "min") 692 (UNSPEC_VPMAX "max") (UNSPEC_VPMAX_U "max") 693 (UNSPEC_VPMIN "min") (UNSPEC_VPMIN_U "min") 694]) 695 696(define_int_attr shift_op [ 697 (UNSPEC_VSHL_S "shl") (UNSPEC_VSHL_U "shl") 698 (UNSPEC_VRSHL_S "rshl") (UNSPEC_VRSHL_U "rshl") 699 (UNSPEC_VQSHL_S "qshl") (UNSPEC_VQSHL_U "qshl") 700 (UNSPEC_VQRSHL_S "qrshl") (UNSPEC_VQRSHL_U "qrshl") 701 (UNSPEC_VSHR_S_N "shr") (UNSPEC_VSHR_U_N "shr") 702 (UNSPEC_VRSHR_S_N "rshr") (UNSPEC_VRSHR_U_N "rshr") 703 (UNSPEC_VSHRN_N "shrn") (UNSPEC_VRSHRN_N "rshrn") 704 (UNSPEC_VQRSHRN_S_N "qrshrn") (UNSPEC_VQRSHRN_U_N "qrshrn") 705 (UNSPEC_VQSHRN_S_N "qshrn") (UNSPEC_VQSHRN_U_N "qshrn") 706 (UNSPEC_VQSHRUN_N "qshrun") (UNSPEC_VQRSHRUN_N "qrshrun") 707 (UNSPEC_VSRA_S_N "sra") (UNSPEC_VSRA_U_N "sra") 708 (UNSPEC_VRSRA_S_N "rsra") (UNSPEC_VRSRA_U_N "rsra") 709]) 710 711;; Standard names for floating point to integral rounding instructions. 712(define_int_attr vrint_pattern [(UNSPEC_VRINTZ "btrunc") (UNSPEC_VRINTP "ceil") 713 (UNSPEC_VRINTA "round") (UNSPEC_VRINTM "floor") 714 (UNSPEC_VRINTR "nearbyint") (UNSPEC_VRINTX "rint")]) 715 716;; Suffixes for vrint instructions specifying rounding modes. 717(define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p") 718 (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m") 719 (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")]) 720 721;; Some of the vrint instuctions are predicable. 722(define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no") 723 (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no") 724 (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")]) 725 726(define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional") 727 (UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional") 728 (UNSPEC_VRINTR "nocond") (UNSPEC_VRINTX "nocond")]) 729 730(define_int_attr nvrint_variant [(UNSPEC_NVRINTZ "z") (UNSPEC_NVRINTP "p") 731 (UNSPEC_NVRINTA "a") (UNSPEC_NVRINTM "m") 732 (UNSPEC_NVRINTX "x") (UNSPEC_NVRINTN "n")]) 733 734(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") 735 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32CB "crc32cb") 736 (UNSPEC_CRC32CH "crc32ch") (UNSPEC_CRC32CW "crc32cw")]) 737 738(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI") 739 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32CB "QI") 740 (UNSPEC_CRC32CH "HI") (UNSPEC_CRC32CW "SI")]) 741 742(define_int_attr crypto_pattern [(UNSPEC_SHA1H "sha1h") (UNSPEC_AESMC "aesmc") 743 (UNSPEC_AESIMC "aesimc") (UNSPEC_AESD "aesd") 744 (UNSPEC_AESE "aese") (UNSPEC_SHA1SU1 "sha1su1") 745 (UNSPEC_SHA256SU0 "sha256su0") (UNSPEC_SHA1C "sha1c") 746 (UNSPEC_SHA1M "sha1m") (UNSPEC_SHA1P "sha1p") 747 (UNSPEC_SHA1SU0 "sha1su0") (UNSPEC_SHA256H "sha256h") 748 (UNSPEC_SHA256H2 "sha256h2") 749 (UNSPEC_SHA256SU1 "sha256su1")]) 750 751(define_int_attr crypto_type 752 [(UNSPEC_AESE "crypto_aese") (UNSPEC_AESD "crypto_aese") 753 (UNSPEC_AESMC "crypto_aesmc") (UNSPEC_AESIMC "crypto_aesmc") 754 (UNSPEC_SHA1C "crypto_sha1_slow") (UNSPEC_SHA1P "crypto_sha1_slow") 755 (UNSPEC_SHA1M "crypto_sha1_slow") (UNSPEC_SHA1SU1 "crypto_sha1_fast") 756 (UNSPEC_SHA1SU0 "crypto_sha1_xor") (UNSPEC_SHA256H "crypto_sha256_slow") 757 (UNSPEC_SHA256H2 "crypto_sha256_slow") (UNSPEC_SHA256SU0 "crypto_sha256_fast") 758 (UNSPEC_SHA256SU1 "crypto_sha256_slow")]) 759 760(define_int_attr crypto_size_sfx [(UNSPEC_SHA1H "32") (UNSPEC_AESMC "8") 761 (UNSPEC_AESIMC "8") (UNSPEC_AESD "8") 762 (UNSPEC_AESE "8") (UNSPEC_SHA1SU1 "32") 763 (UNSPEC_SHA256SU0 "32") (UNSPEC_SHA1C "32") 764 (UNSPEC_SHA1M "32") (UNSPEC_SHA1P "32") 765 (UNSPEC_SHA1SU0 "32") (UNSPEC_SHA256H "32") 766 (UNSPEC_SHA256H2 "32") (UNSPEC_SHA256SU1 "32")]) 767 768(define_int_attr crypto_mode [(UNSPEC_SHA1H "V4SI") (UNSPEC_AESMC "V16QI") 769 (UNSPEC_AESIMC "V16QI") (UNSPEC_AESD "V16QI") 770 (UNSPEC_AESE "V16QI") (UNSPEC_SHA1SU1 "V4SI") 771 (UNSPEC_SHA256SU0 "V4SI") (UNSPEC_SHA1C "V4SI") 772 (UNSPEC_SHA1M "V4SI") (UNSPEC_SHA1P "V4SI") 773 (UNSPEC_SHA1SU0 "V4SI") (UNSPEC_SHA256H "V4SI") 774 (UNSPEC_SHA256H2 "V4SI") (UNSPEC_SHA256SU1 "V4SI")]) 775 776;; Both kinds of return insn. 777(define_code_iterator returns [return simple_return]) 778(define_code_attr return_str [(return "") (simple_return "simple_")]) 779(define_code_attr return_simple_p [(return "false") (simple_return "true")]) 780(define_code_attr return_cond_false [(return " && USE_RETURN_INSN (FALSE)") 781 (simple_return " && use_simple_return_p ()")]) 782(define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)") 783 (simple_return " && use_simple_return_p ()")]) 784