1/* ia64.h -- Header file for ia64 opcode table 2 Copyright (C) 1998-2017 Free Software Foundation, Inc. 3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com> 4 5 This file is part of BFD, the Binary File Descriptor library. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software Foundation, 19 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 20 21#ifndef opcode_ia64_h 22#define opcode_ia64_h 23 24#include <sys/types.h> 25 26#include "bfd.h" 27 28#ifdef __cplusplus 29extern "C" { 30#endif 31 32typedef BFD_HOST_U_64_BIT ia64_insn; 33 34enum ia64_insn_type 35 { 36 IA64_TYPE_NIL = 0, /* illegal type */ 37 IA64_TYPE_A, /* integer alu (I- or M-unit) */ 38 IA64_TYPE_I, /* non-alu integer (I-unit) */ 39 IA64_TYPE_M, /* memory (M-unit) */ 40 IA64_TYPE_B, /* branch (B-unit) */ 41 IA64_TYPE_F, /* floating-point (F-unit) */ 42 IA64_TYPE_X, /* long encoding (X-unit) */ 43 IA64_TYPE_DYN, /* Dynamic opcode */ 44 IA64_NUM_TYPES 45 }; 46 47enum ia64_unit 48 { 49 IA64_UNIT_NIL = 0, /* illegal unit */ 50 IA64_UNIT_I, /* integer unit */ 51 IA64_UNIT_M, /* memory unit */ 52 IA64_UNIT_B, /* branching unit */ 53 IA64_UNIT_F, /* floating-point unit */ 54 IA64_UNIT_L, /* long "unit" */ 55 IA64_UNIT_X, /* may be integer or branch unit */ 56 IA64_NUM_UNITS 57 }; 58 59/* Changes to this enumeration must be propagated to the operand table in 60 bfd/cpu-ia64-opc.c 61 */ 62enum ia64_opnd 63 { 64 IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/ 65 66 /* constants */ 67 IA64_OPND_AR_CSD, /* application register csd (ar.csd) */ 68 IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */ 69 IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */ 70 IA64_OPND_C1, /* the constant 1 */ 71 IA64_OPND_C8, /* the constant 8 */ 72 IA64_OPND_C16, /* the constant 16 */ 73 IA64_OPND_GR0, /* gr0 */ 74 IA64_OPND_IP, /* instruction pointer (ip) */ 75 IA64_OPND_PR, /* predicate register (pr) */ 76 IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */ 77 IA64_OPND_PSR, /* processor status register (psr) */ 78 IA64_OPND_PSR_L, /* processor status register L (psr.l) */ 79 IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */ 80 81 /* register operands: */ 82 IA64_OPND_AR3, /* third application register # (bits 20-26) */ 83 IA64_OPND_B1, /* branch register # (bits 6-8) */ 84 IA64_OPND_B2, /* branch register # (bits 13-15) */ 85 IA64_OPND_CR3, /* third control register # (bits 20-26) */ 86 IA64_OPND_F1, /* first floating-point register # */ 87 IA64_OPND_F2, /* second floating-point register # */ 88 IA64_OPND_F3, /* third floating-point register # */ 89 IA64_OPND_F4, /* fourth floating-point register # */ 90 IA64_OPND_P1, /* first predicate # */ 91 IA64_OPND_P2, /* second predicate # */ 92 IA64_OPND_R1, /* first register # */ 93 IA64_OPND_R2, /* second register # */ 94 IA64_OPND_R3, /* third register # */ 95 IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ 96 IA64_OPND_DAHR3, /* dahr reg # ( bits 23-25) */ 97 98 /* memory operands: */ 99 IA64_OPND_MR3, /* memory at addr of third register # */ 100 101 /* indirect operands: */ 102 IA64_OPND_CPUID_R3, /* cpuid[reg] */ 103 IA64_OPND_DBR_R3, /* dbr[reg] */ 104 IA64_OPND_DTR_R3, /* dtr[reg] */ 105 IA64_OPND_ITR_R3, /* itr[reg] */ 106 IA64_OPND_IBR_R3, /* ibr[reg] */ 107 IA64_OPND_MSR_R3, /* msr[reg] */ 108 IA64_OPND_PKR_R3, /* pkr[reg] */ 109 IA64_OPND_PMC_R3, /* pmc[reg] */ 110 IA64_OPND_PMD_R3, /* pmd[reg] */ 111 IA64_OPND_DAHR_R3, /* dahr[reg] */ 112 IA64_OPND_RR_R3, /* rr[reg] */ 113 114 /* immediate operands: */ 115 IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */ 116 IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */ 117 IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */ 118 IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */ 119 IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */ 120 IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */ 121 IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */ 122 IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */ 123 IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */ 124 IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */ 125 IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */ 126 IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */ 127 IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */ 128 IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */ 129 IA64_OPND_SOF, /* 8-bit stack frame size */ 130 IA64_OPND_SOL, /* 8-bit size of locals */ 131 IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */ 132 IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */ 133 IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */ 134 IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */ 135 IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/ 136 IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */ 137 IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */ 138 IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ 139 IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ 140 IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ 141 IA64_OPND_IMMU16, /* unsigned 16-bit immediate (bits 6-9, 12-22, 36) */ 142 IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ 143 IA64_OPND_IMMU19, /* unsigned 19-bit immediate (bits 6-9, 12-25, 36) */ 144 IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ 145 IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ 146 IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */ 147 IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */ 148 IA64_OPND_IMMU62, /* unsigned 62-bit immediate */ 149 IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */ 150 IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */ 151 IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */ 152 IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */ 153 IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */ 154 IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */ 155 IA64_OPND_POS6, /* 6-bit count (bits 14-19) */ 156 IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */ 157 IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */ 158 IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */ 159 IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */ 160 IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */ 161 IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ 162 IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ 163 164 IA64_OPND_CNT6a, /* 6-bit count (bits 6-11) */ 165 IA64_OPND_STRD5b, /* 5-bit stride (bits 13-17) */ 166 167 IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ 168 }; 169 170enum ia64_dependency_mode 171{ 172 IA64_DV_RAW, 173 IA64_DV_WAW, 174 IA64_DV_WAR, 175}; 176 177enum ia64_dependency_semantics 178{ 179 IA64_DVS_NONE, 180 IA64_DVS_IMPLIED, 181 IA64_DVS_IMPLIEDF, 182 IA64_DVS_DATA, 183 IA64_DVS_INSTR, 184 IA64_DVS_SPECIFIC, 185 IA64_DVS_STOP, 186 IA64_DVS_OTHER, 187}; 188 189enum ia64_resource_specifier 190{ 191 IA64_RS_ANY, 192 IA64_RS_AR_K, 193 IA64_RS_AR_UNAT, 194 IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */ 195 IA64_RS_ARb, /* 48-63, 112-127 */ 196 IA64_RS_BR, 197 IA64_RS_CFM, 198 IA64_RS_CPUID, 199 IA64_RS_CR_IIB, 200 IA64_RS_CR_IRR, 201 IA64_RS_CR_LRR, 202 IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */ 203 IA64_RS_DAHR, 204 IA64_RS_DBR, 205 IA64_RS_FR, 206 IA64_RS_FRb, 207 IA64_RS_GR0, 208 IA64_RS_GR, 209 IA64_RS_IBR, 210 IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */ 211 IA64_RS_MSR, 212 IA64_RS_PKR, 213 IA64_RS_PMC, 214 IA64_RS_PMD, 215 IA64_RS_PR, /* non-rotating, 1-15 */ 216 IA64_RS_PRr, /* rotating, 16-62 */ 217 IA64_RS_PR63, 218 IA64_RS_RR, 219 220 IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */ 221 IA64_RS_CRX, /* CRs not in RS_CR */ 222 IA64_RS_PSR, /* PSR bits */ 223 IA64_RS_RSE, /* implementation-specific RSE resources */ 224 IA64_RS_AR_FPSR, 225 226}; 227 228enum ia64_rse_resource 229{ 230 IA64_RSE_N_STACKED_PHYS, 231 IA64_RSE_BOF, 232 IA64_RSE_STORE_REG, 233 IA64_RSE_LOAD_REG, 234 IA64_RSE_BSPLOAD, 235 IA64_RSE_RNATBITINDEX, 236 IA64_RSE_CFLE, 237 IA64_RSE_NDIRTY, 238}; 239 240/* Information about a given resource dependency */ 241struct ia64_dependency 242{ 243 /* Name of the resource */ 244 const char *name; 245 /* Does this dependency need further specification? */ 246 enum ia64_resource_specifier specifier; 247 /* Mode of dependency */ 248 enum ia64_dependency_mode mode; 249 /* Dependency semantics */ 250 enum ia64_dependency_semantics semantics; 251 /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */ 252#define REG_NONE (-1) 253 int regindex; 254 /* Special info on semantics */ 255 const char *info; 256}; 257 258/* Two arrays of indexes into the ia64_dependency table. 259 chks are dependencies to check for conflicts when an opcode is 260 encountered; regs are dependencies to register (mark as used) when an 261 opcode is used. chks correspond to readers (RAW) or writers (WAW or 262 WAR) of a resource, while regs correspond to writers (RAW or WAW) and 263 readers (WAR) of a resource. */ 264struct ia64_opcode_dependency 265{ 266 int nchks; 267 const unsigned short *chks; 268 int nregs; 269 const unsigned short *regs; 270}; 271 272/* encode/extract the note/index for a dependency */ 273#define RDEP(N,X) (((N)<<11)|(X)) 274#define NOTE(X) (((X)>>11)&0x1F) 275#define DEP(X) ((X)&0x7FF) 276 277/* A template descriptor describes the execution units that are active 278 for each of the three slots. It also specifies the location of 279 instruction group boundaries that may be present between two slots. */ 280struct ia64_templ_desc 281 { 282 int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */ 283 enum ia64_unit exec_unit[3]; 284 const char *name; 285 }; 286 287/* The opcode table is an array of struct ia64_opcode. */ 288 289struct ia64_opcode 290 { 291 /* The opcode name. */ 292 const char *name; 293 294 /* The type of the instruction: */ 295 enum ia64_insn_type type; 296 297 /* Number of output operands: */ 298 int num_outputs; 299 300 /* The opcode itself. Those bits which will be filled in with 301 operands are zeroes. */ 302 ia64_insn opcode; 303 304 /* The opcode mask. This is used by the disassembler. This is a 305 mask containing ones indicating those bits which must match the 306 opcode field, and zeroes indicating those bits which need not 307 match (and are presumably filled in by operands). */ 308 ia64_insn mask; 309 310 /* An array of operand codes. Each code is an index into the 311 operand table. They appear in the order which the operands must 312 appear in assembly code, and are terminated by a zero. */ 313 enum ia64_opnd operands[5]; 314 315 /* One bit flags for the opcode. These are primarily used to 316 indicate specific processors and environments support the 317 instructions. The defined values are listed below. */ 318 unsigned int flags; 319 320 /* Used by ia64_find_next_opcode (). */ 321 short ent_index; 322 323 /* Opcode dependencies. */ 324 const struct ia64_opcode_dependency *dependencies; 325 }; 326 327/* Values defined for the flags field of a struct ia64_opcode. */ 328 329#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */ 330#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */ 331#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */ 332#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */ 333#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */ 334#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */ 335#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */ 336#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */ 337#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */ 338#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */ 339#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */ 340 341/* A macro to extract the major opcode from an instruction. */ 342#define IA64_OP(i) (((i) >> 37) & 0xf) 343 344enum ia64_operand_class 345 { 346 IA64_OPND_CLASS_CST, /* constant */ 347 IA64_OPND_CLASS_REG, /* register */ 348 IA64_OPND_CLASS_IND, /* indirect register */ 349 IA64_OPND_CLASS_ABS, /* absolute value */ 350 IA64_OPND_CLASS_REL, /* IP-relative value */ 351 }; 352 353/* The operands table is an array of struct ia64_operand. */ 354 355struct ia64_operand 356{ 357 enum ia64_operand_class op_class; 358 359 /* Set VALUE as the operand bits for the operand of type SELF in the 360 instruction pointed to by CODE. If an error occurs, *CODE is not 361 modified and the returned string describes the cause of the 362 error. If no error occurs, NULL is returned. */ 363 const char *(*insert) (const struct ia64_operand *self, ia64_insn value, 364 ia64_insn *code); 365 366 /* Extract the operand bits for an operand of type SELF from 367 instruction CODE store them in *VALUE. If an error occurs, the 368 cause of the error is described by the string returned. If no 369 error occurs, NULL is returned. */ 370 const char *(*extract) (const struct ia64_operand *self, ia64_insn code, 371 ia64_insn *value); 372 373 /* A string whose meaning depends on the operand class. */ 374 375 const char *str; 376 377 struct bit_field 378 { 379 /* The number of bits in the operand. */ 380 int bits; 381 382 /* How far the operand is left shifted in the instruction. */ 383 int shift; 384 } 385 field[4]; /* no operand has more than this many bit-fields */ 386 387 unsigned int flags; 388 389 const char *desc; /* brief description */ 390}; 391 392/* Values defined for the flags field of a struct ia64_operand. */ 393 394/* Disassemble as signed decimal (instead of hex): */ 395#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0) 396/* Disassemble as unsigned decimal (instead of hex): */ 397#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1) 398 399extern const struct ia64_templ_desc ia64_templ_desc[16]; 400 401/* The tables are sorted by major opcode number and are otherwise in 402 the order in which the disassembler should consider instructions. */ 403extern struct ia64_opcode ia64_opcodes_a[]; 404extern struct ia64_opcode ia64_opcodes_i[]; 405extern struct ia64_opcode ia64_opcodes_m[]; 406extern struct ia64_opcode ia64_opcodes_b[]; 407extern struct ia64_opcode ia64_opcodes_f[]; 408extern struct ia64_opcode ia64_opcodes_d[]; 409 410 411extern struct ia64_opcode *ia64_find_opcode (const char *); 412extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *); 413 414extern struct ia64_opcode *ia64_dis_opcode (ia64_insn, 415 enum ia64_insn_type); 416 417extern void ia64_free_opcode (struct ia64_opcode *); 418extern const struct ia64_dependency *ia64_find_dependency (int); 419 420/* To avoid circular library dependencies, this array is implemented 421 in bfd/cpu-ia64-opc.c: */ 422extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT]; 423 424#ifdef __cplusplus 425} 426#endif 427 428#endif /* opcode_ia64_h */ 429