12015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> 2 3 * arm.h (ARM_EXT2_V6T2_V8M): New extension bit. 4 (ARM_AEXT2_V8A): New architecture extension bitfield. 5 (ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. 6 (ARM_AEXT_V8M_BASE): New architecture extension bitfield. 7 (ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M. 8 (ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension 9 bitfield. 10 (ARM_ARCH_V6KT2): Likewise. 11 (ARM_ARCH_V6ZT2): Likewise. 12 (ARM_ARCH_V6KZT2): Likewise. 13 (ARM_ARCH_V7): Likewise. 14 (ARM_ARCH_V7A): Likewise. 15 (ARM_ARCH_V7VE): Likewise. 16 (ARM_ARCH_V7R): Likewise. 17 (ARM_ARCH_V7M): Likewise. 18 (ARM_ARCH_V7EM): Likewise. 19 (ARM_ARCH_V8A): Likewise. 20 (ARM_ARCH_V8M_BASE): New architecture bitfield. 21 (ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M. 22 (ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension 23 bitfield and reindent. 24 (ARM_ARCH_V7A_MP_SEC): Likewise. 25 (ARM_ARCH_V7R_IDIV): Likewise. 26 (ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. 27 (ARM_ARCH_V8A_SIMD): Likewise. 28 (ARM_ARCH_V8A_CRYPTOV1): Likewise. 29 302015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> 31 32 * arm.h (ARM_EXT2_ATOMICS): New extension bit. 33 (ARM_EXT2_V8M): Likewise. 34 (ARM_EXT_V8): Adjust comment with regards to atomics and remove 35 mention of legacy use for that bit. 36 (ARM_AEXT2_V8_1A): New architecture extension bitfield. 37 (ARM_AEXT2_V8_2A): Likewise. 38 (ARM_AEXT_V8M_MAIN): Likewise. 39 (ARM_AEXT2_V8M): Likewise. 40 (ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield. 41 (ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A. 42 (ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A. 43 (ARM_ARCH_V8M_MAIN): New architecture feature bitfield. 44 (ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield 45 and reindent. 46 (ARM_ARCH_V8A_SIMD): Likewise. 47 (ARM_ARCH_V8A_CRYPTOV1): Likewise. 48 (ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of 49 feature bits. 50 (ARM_ARCH_V8_1A_SIMD): Likewise. 51 (ARM_ARCH_V8_1A_CRYPTOV1): Likewise. 52 532015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> 54 55 * arm.h (ARM_ARCH_THUMB2): Add comment explaining its meaning and 56 remove extension bit not including any Thumb-2 instruction. 57 582015-12-15 Matthew Wahab <matthew.wahab@arm.com> 59 60 * arm.h (ARM_ARCH_V8_1A): Add the CRC_EXT_ARMV8 co-processor 61 feature macro. 62 (ARM_ARCH_V8_2A): Likewise. 63 642015-12-14 Matthew Wahab <matthew.wahab@arm.com> 65 66 * aarch64.h (enum aarch64_opnd_qualifier): Add 67 AARCH64_OPND_QLF_V_2H. 68 692015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp> 70 71 * rx.h: Add new instructions. 72 732015-12-11 Matthew Wahab <matthew.wahab@arm.com> 74 75 * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB. 76 * aarch64-asm-2.c: Regenerate. 77 * aarch64-dis-2.c: Regenerate. 78 * aarch64-opc-2.c: Regenerate. 79 * aarch64-opc.c (aarch64_hint_options): Add "csync". 80 (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB. 81 * aarch64-tbl.h (aarch64_feature_stat_profile): New. 82 (STAT_PROFILE): New. 83 (aarch64_opcode_table): Add "psb". 84 (AARCH64_OPERANDS): Add "BARRIER_PSB". 85 862015-12-11 Matthew Wahab <matthew.wahab@arm.com> 87 88 * aarch64.h (aarch64_hint_options): Declare. 89 (aarch64_opnd_info): Add field hint_option. 90 912015-12-11 Matthew Wahab <matthew.wahab@arm.com> 92 93 * aarch64.h (AARCH64_FEATURE_PROFILE): New. 94 952015-12-10 Matthew Wahab <matthew.wahab@arm.com> 96 97 * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare. 98 992015-12-10 Matthew Wahab <matthew.wahab@arm.com> 100 101 * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags. 102 (aarch64_sys_ins_reg_has_xt): Declare. 103 1042015-12-10 Matthew Wahab <matthew.wahab@arm.com> 105 106 * aarch64.h (AARCH64_FEATURE_RAS): New. 107 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS. 108 1092015-12-10 Matthew Wahab <matthew.wahab@arm.com> 110 111 * aarch64.h (AARCH64_FEATURE_F16): Fix clash with 112 AARCH64_FEATURE_V8_1. 113 (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC. 114 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and 115 AARCH64_FEATURE_V8_1. 116 1172015-12-04 Claudiu Zissulescu <claziss@synopsys.com> 118 119 * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32]. 120 1212015-11-27 Matthew Wahab <matthew.wahab@arm.com> 122 123 * aarch64.h (aarch64_op): Add OP_BFC. 124 1252015-11-27 Matthew Wahab <matthew.wahab@arm.com> 126 127 * aarch64.h (AARCH64_FEATURE_F16): New. 128 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2 129 features. 130 1312015-11-20 Matthew Wahab <matthew.wahab@arm.com> 132 133 * aarch64.h (AARCH64_FEATURE_V8_1): New. 134 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1. 135 1362015-11-19 Matthew Wahab <matthew.wahab@arm.com> 137 138 * arm.h (ARM_EXT2_V8_2A): New. 139 (ARM_ARCH_V8_2A): New. 140 1412015-11-19 Matthew Wahab <matthew.wahab@arm.com> 142 143 * aarch64.h (AARCH64_FEATURE_V8_2): New. 144 (AARCH64_ARCH_V8_2): New. 145 1462015-11-11 Alan Modra <amodra@gmail.com> 147 Peter Bergner <bergner@vnet.ibm.com> 148 149 * ppc.h (PPC_OPCODE_POWER9): New define. 150 (PPC_OPCODE_VSX3): Likewise. 151 1522015-11-02 Nick Clifton <nickc@redhat.com> 153 154 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes. 155 1562015-11-02 Nick Clifton <nickc@redhat.com> 157 158 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect. 159 1602015-10-28 Yao Qi <yao.qi@linaro.org> 161 162 * aarch64.h (aarch64_decode_insn): Update declaration. 163 1642015-10-07 Yao Qi <yao.qi@linaro.org> 165 166 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed. 167 <name>: New field. 168 1692015-10-07 Yao Qi <yao.qi@linaro.org> 170 171 * aarch64.h [__cplusplus]: Wrap in extern "C". 172 1732015-10-07 Claudiu Zissulescu <claziss@synopsys.com> 174 Cupertino Miranda <cmiranda@synopsys.com> 175 176 * arc-func.h: New file. 177 * arc.h: Likewise. 178 1792015-10-02 Yao Qi <yao.qi@linaro.org> 180 181 * aarch64.h (aarch64_zero_register_p): Move the declaration 182 to column one. 183 1842015-10-02 Yao Qi <yao.qi@linaro.org> 185 186 * aarch64.h (aarch64_decode_insn): Declare it. 187 1882015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com> 189 190 * s390.h (S390_INSTR_FLAG_HTM): New flag. 191 (S390_INSTR_FLAG_VX): New flag. 192 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask. 193 1942015-09-26 James Bowman <james.bowman@ftdichip.com> 195 196 * ft32.h: Add instruction macros FT32_*() 197 1982015-09-23 Nick Clifton <nickc@redhat.com> 199 200 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left 201 shifting. 202 2032015-09-22 Nick Clifton <nickc@redhat.com> 204 205 * rx.h (enum RX_Size): Add RX_Bad_Size entry. 206 2072015-09-09 Daniel Santos <daniel.santos@pobox.com> 208 209 * visium.h (gen_reg_table): Make static. 210 (fp_reg_table): Likewise. 211 (cc_table): Likewise. 212 2132015-07-20 Matthew Wahab <matthew.wahab@arm.com> 214 215 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ. 216 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2. 217 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ. 218 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2. 219 2202015-07-03 Alan Modra <amodra@gmail.com> 221 222 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define. 223 2242015-07-01 Sandra Loosemore <sandra@codesourcery.com> 225 Cesar Philippidis <cesar@codesourcery.com> 226 227 * nios2.h (enum iw_format_type): Add R2 formats. 228 (enum overflow_type): Add signed_immed12_overflow and 229 enumeration_overflow for R2. 230 (struct nios2_opcode): Document new argument letters for R2. 231 (REG_3BIT, REG_LDWM, REG_POP): Define. 232 (includes): Include nios2r2.h. 233 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare. 234 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare. 235 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare. 236 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare. 237 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare. 238 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): 239 Declare. 240 * nios2r2.h: New file. 241 2422015-06-19 Peter Bergner <bergner@vnet.ibm.com> 243 244 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New. 245 (ppc_optional_operand_value): New inline function. 246 2472015-06-04 Matthew Wahab <matthew.wahab@arm.com> 248 249 * aarch64.h (AARCH64_V8_1): New. 250 2512015-06-03 Matthew Wahab <matthew.wahab@arm.com> 252 253 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New. 254 (ARM_ARCH_V8_1A): New. 255 (ARM_ARCH_V8_1A_FP): New. 256 (ARM_ARCH_V8_1A_SIMD): New. 257 (ARM_ARCH_V8_1A_CRYPTOV1): New. 258 (ARM_FEATURE_CORE): New. 259 2602015-06-02 Matthew Wahab <matthew.wahab@arm.com> 261 262 * arm.h (ARM_EXT2_PAN): New. 263 (ARM_FEATURE_CORE_HIGH): New. 264 2652015-06-02 Matthew Wahab <matthew.wahab@arm.com> 266 267 * arm.h (ARM_FEATURE_ALL): New. 268 2692015-06-02 Matthew Wahab <matthew.wahab@arm.com> 270 271 * aarch64.h (AARCH64_FEATURE_RDMA): New. 272 2732015-06-02 Matthew Wahab <matthew.wahab@arm.com> 274 275 * aarch64.h (AARCH64_FEATURE_LOR): New. 276 2772015-06-01 Matthew Wahab <matthew.wahab@arm.com> 278 279 * aarch64.h (AARCH64_FEATURE_PAN): New. 280 (aarch64_sys_reg_supported_p): Declare. 281 (aarch64_pstatefield_supported_p): Declare. 282 2832015-04-30 DJ Delorie <dj@redhat.com> 284 285 * rl78.h (RL78_Dis_Isa): New. 286 (rl78_decode_opcode): Add ISA parameter. 287 2882015-03-24 Terry Guo <terry.guo@arm.com> 289 290 * arm.h (arm_feature_set): Extended to provide more available bits. 291 (ARM_ANY): Updated to follow above new definition. 292 (ARM_CPU_HAS_FEATURE): Likewise. 293 (ARM_CPU_IS_ANY): Likewise. 294 (ARM_MERGE_FEATURE_SETS): Likewise. 295 (ARM_CLEAR_FEATURE): Likewise. 296 (ARM_FEATURE): Likewise. 297 (ARM_FEATURE_COPY): New macro. 298 (ARM_FEATURE_EQUAL): Likewise. 299 (ARM_FEATURE_ZERO): Likewise. 300 (ARM_FEATURE_CORE_EQUAL): Likewise. 301 (ARM_FEATURE_LOW): Likewise. 302 (ARM_FEATURE_CORE_LOW): Likewise. 303 (ARM_FEATURE_CORE_COPROC): Likewise. 304 3052015-02-19 Pedro Alves <palves@redhat.com> 306 307 * cgen.h [__cplusplus]: Wrap in extern "C". 308 * msp430-decode.h [__cplusplus]: Likewise. 309 * nios2.h [__cplusplus]: Likewise. 310 * rl78.h [__cplusplus]: Likewise. 311 * rx.h [__cplusplus]: Likewise. 312 * tilegx.h [__cplusplus]: Likewise. 313 3142015-01-28 James Bowman <james.bowman@ftdichip.com> 315 316 * ft32.h: New file. 317 3182015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com> 319 320 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. 321 3222015-01-01 Alan Modra <amodra@gmail.com> 323 324 Update year range in copyright notice of all files. 325 3262014-12-27 Anthony Green <green@moxielogic.com> 327 328 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from 329 MOXIE_F1_AiB4 and MOXIE_F1_ABi2. 330 3312014-12-06 Eric Botcazou <ebotcazou@adacore.com> 332 333 * visium.h: New file. 334 3352014-11-28 Sandra Loosemore <sandra@codesourcery.com> 336 337 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete. 338 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete. 339 (NIOS2_INSN_OPTARG): Renumber. 340 3412014-11-21 Terry Guo <terry.guo@arm.com> 342 343 * arm.h (FPU_VFP_EXT_ARMV8xD): New macro. 344 (FPU_VFP_V5D16): Likewise. 345 (FPU_VFP_V5_SP_D16): Likewise. 346 (FPU_ARCH_VFP_V5D16): Likewise. 347 (FPU_ARCH_VFP_V5_SP_D16): Likewise. 348 3492014-11-06 Sandra Loosemore <sandra@codesourcery.com> 350 351 * nios2.h (nios2_find_opcode_hash): Add mach parameter to 352 declaration. Fix obsolete comment. 353 3542014-10-23 Sandra Loosemore <sandra@codesourcery.com> 355 356 * nios2.h (enum iw_format_type): New. 357 (struct nios2_opcode): Update comments. Add size and format fields. 358 (NIOS2_INSN_OPTARG): New. 359 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New. 360 (struct nios2_reg): Add regtype field. 361 (GET_INSN_FIELD, SET_INSN_FIELD): Delete. 362 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete. 363 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete. 364 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete. 365 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete. 366 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete. 367 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete. 368 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete. 369 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete. 370 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete. 371 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete. 372 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete. 373 (OP_MASK_OP, OP_SH_OP): Delete. 374 (OP_MASK_IOP, OP_SH_IOP): Delete. 375 (OP_MASK_IRD, OP_SH_IRD): Delete. 376 (OP_MASK_IRT, OP_SH_IRT): Delete. 377 (OP_MASK_IRS, OP_SH_IRS): Delete. 378 (OP_MASK_ROP, OP_SH_ROP): Delete. 379 (OP_MASK_RRD, OP_SH_RRD): Delete. 380 (OP_MASK_RRT, OP_SH_RRT): Delete. 381 (OP_MASK_RRS, OP_SH_RRS): Delete. 382 (OP_MASK_JOP, OP_SH_JOP): Delete. 383 (OP_MASK_IMM26, OP_SH_IMM26): Delete. 384 (OP_MASK_RCTL, OP_SH_RCTL): Delete. 385 (OP_MASK_IMM5, OP_SH_IMM5): Delete. 386 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete. 387 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete. 388 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete. 389 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete. 390 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete. 391 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete. 392 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete. 393 (OP_MASK_<insn>, OP_MASK): Delete. 394 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete. 395 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete. 396 Include nios2r1.h to define new instruction opcode constants 397 and accessors. 398 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes. 399 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes. 400 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes. 401 (NUMOPCODES, NUMREGISTERS): Delete. 402 * nios2r1.h: New file. 403 4042014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com> 405 406 * sparc.h (HWCAP2_VIS3B): Documentation improved. 407 4082014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com> 409 410 * sparc.h (sparc_opcode): new field `hwcaps2'. 411 (HWCAP2_FJATHPLUS): New define. 412 (HWCAP2_VIS3B): Likewise. 413 (HWCAP2_ADP): Likewise. 414 (HWCAP2_SPARC5): Likewise. 415 (HWCAP2_MWAIT): Likewise. 416 (HWCAP2_XMPMUL): Likewise. 417 (HWCAP2_XMONT): Likewise. 418 (HWCAP2_NSEC): Likewise. 419 (HWCAP2_FJATHHPC): Likewise. 420 (HWCAP2_FJDES): Likewise. 421 (HWCAP2_FJAES): Likewise. 422 Document the new operand kind `{', corresponding to the mcdper 423 ancillary state register. 424 Document the new operand kind }, which represents frsd floating 425 point registers (double precision) which must be the same than 426 frs1 in its containing instruction. 427 4282014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com> 429 430 * nds32.h: Add new opcode declaration. 431 4322014-09-15 Andrew Bennett <andrew.bennett@imgtec.com> 433 Matthew Fortune <matthew.fortune@imgtec.com> 434 435 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT, 436 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6 437 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B, 438 +I, +O, +R, +:, +\, +", +; 439 (mips_check_prev_operand): New struct. 440 (INSN2_FORBIDDEN_SLOT): New define. 441 (INSN_ISA32R6): New define. 442 (INSN_ISA64R6): New define. 443 (INSN_UPTO32R6): New define. 444 (INSN_UPTO64R6): New define. 445 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6. 446 (ISA_MIPS32R6): New define. 447 (ISA_MIPS64R6): New define. 448 (CPU_MIPS32R6): New define. 449 (CPU_MIPS64R6): New define. 450 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6. 451 4522014-09-03 Jiong Wang <jiong.wang@arm.com> 453 454 * aarch64.h (AARCH64_FEATURE_LSE): New feature added. 455 (aarch64_opnd): Add AARCH64_OPND_PAIRREG. 456 (aarch64_insn_class): Add lse_atomic. 457 (F_LSE_SZ): New field added. 458 (opcode_has_special_coder): Recognize F_LSE_SZ. 459 4602014-08-26 Maciej W. Rozycki <macro@codesourcery.com> 461 462 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B' 463 over to `+J'. 464 4652014-07-29 Matthew Fortune <matthew.fortune@imgtec.com> 466 467 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to... 468 (INSN_LOAD_COPROC): New define. 469 (INSN_COPROC_MOVE_DELAY): Rename to... 470 (INSN_COPROC_MOVE): New define. 471 4722014-07-01 Barney Stratford <barney_stratford@fastmail.fm> 473 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com> 474 Pitchumani Sivanupandi <pitchumani.s@atmel.com> 475 Soundararajan <Sounderarajan.D@atmel.com> 476 477 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA. 478 (AVR_ISA_2xxxa): Define ISA without LPM. 479 (AVR_ISA_AVRTINY): Define avrtiny arch ISA. 480 Add doc for contraint used in 16 bit lds/sts. 481 Adjust ISA group for icall, ijmp, pop and push. 482 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints. 483 4842014-05-19 Nick Clifton <nickc@redhat.com> 485 486 * msp430.h (struct msp430_operand_s): Add vshift field. 487 4882014-05-07 Andrew Bennett <andrew.bennett@imgtec.com> 489 490 * mips.h (INSN_ISA_MASK): Updated. 491 (INSN_ISA32R3): New define. 492 (INSN_ISA32R5): New define. 493 (INSN_ISA64R3): New define. 494 (INSN_ISA64R5): New define. 495 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32 496 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered. 497 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and 498 mips64r5. 499 (INSN_UPTO32R3): New define. 500 (INSN_UPTO32R5): New define. 501 (INSN_UPTO64R3): New define. 502 (INSN_UPTO64R5): New define. 503 (ISA_MIPS32R3): New define. 504 (ISA_MIPS32R5): New define. 505 (ISA_MIPS64R3): New define. 506 (ISA_MIPS64R5): New define. 507 (CPU_MIPS32R3): New define. 508 (CPU_MIPS32R5): New define. 509 (CPU_MIPS64R3): New define. 510 (CPU_MIPS64R5): New define. 511 5122014-05-01 Richard Sandiford <rdsandiford@googlemail.com> 513 514 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values. 515 5162014-04-23 Andrew Bennett <andrew.bennett@imgtec.com> 517 518 * mips.h (ASE_XPA): New define. 519 5202014-04-22 Christian Svensson <blue@cmd.nu> 521 522 * or32.h: Delete. 523 5242014-03-05 Alan Modra <amodra@gmail.com> 525 526 Update copyright years. 527 5282013-12-16 Andrew Bennett <andrew.bennett@imgtec.com> 529 530 * mips.h: Updated description of +o, +u, +v and +w for MIPS and 531 microMIPS. 532 5332013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com> 534 Wei-Cheng Wang <cole945@gmail.com> 535 536 * nds32.h: New file for Andes NDS32. 537 5382013-12-07 Mike Frysinger <vapier@gentoo.org> 539 540 * bfin.h: Remove +x file mode. 541 5422013-11-20 Yufeng Zhang <yufeng.zhang@arm.com> 543 544 * aarch64.h (aarch64_pstatefields): Change element type to 545 aarch64_sys_reg. 546 5472013-11-18 Renlin Li <Renlin.Li@arm.com> 548 549 * arm.h (ARM_AEXT_V7VE): New define. 550 (ARM_ARCH_V7VE): New define. 551 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed. 552 5532013-11-18 Yufeng Zhang <yufeng.zhang@arm.com> 554 555 Revert 556 557 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com> 558 559 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration. 560 (aarch64_sys_reg_writeonly_p): Ditto. 561 5622013-11-15 Yufeng Zhang <yufeng.zhang@arm.com> 563 564 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration. 565 (aarch64_sys_reg_writeonly_p): Ditto. 566 5672013-11-11 Catherine Moore <clm@codesourcery.com> 568 569 * mips.h (INSN_LOAD_MEMORY_DELAY): Rename to... 570 (INSN_LOAD_MEMORY): ...this. 571 5722013-11-05 Yufeng Zhang <yufeng.zhang@arm.com> 573 574 * aarch64.h (aarch64_sys_reg): New typedef. 575 (aarch64_sys_regs): Change to define with the new type. 576 (aarch64_sys_reg_deprecated_p): Declare. 577 5782013-11-05 Yufeng Zhang <yufeng.zhang@arm.com> 579 580 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND. 581 (enum aarch64_opnd): Add AARCH64_OPND_COND1. 582 5832013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> 584 585 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX. 586 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL. 587 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, 588 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. 589 For MIPS, update extension character sequences after +. 590 (ASE_MSA): New define. 591 (ASE_MSA64): New define. 592 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, 593 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. 594 For microMIPS, update extension character sequences after +. 595 5962013-08-23 Yuri Chornoivan <yurchor@ukr.net> 597 598 PR binutils/15834 599 * i960.h: Fix typos. 600 6012013-08-19 Richard Sandiford <rdsandiford@googlemail.com> 602 603 * mips.h: Remove references to "+I" and imm2_expr. 604 6052013-08-19 Richard Sandiford <rdsandiford@googlemail.com> 606 607 * mips.h (M_DEXT, M_DINS): Delete. 608 6092013-08-19 Richard Sandiford <rdsandiford@googlemail.com> 610 611 * mips.h (OP_OPTIONAL_REG): New mips_operand_type. 612 (mips_optional_operand_p): New function. 613 6142013-08-05 Eric Botcazou <ebotcazou@adacore.com> 615 Konrad Eisele <konrad@gaisler.com> 616 617 * sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_LEON. 618 6192013-08-04 J��rgen Urban <JuergenUrban@gmx.de> 620 Richard Sandiford <rdsandiford@googlemail.com> 621 622 * mips.h: Document new VU0 operand characters. 623 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types. 624 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R) 625 (OP_REG_R5900_ACC): New mips_reg_operand_types. 626 (INSN2_VU0_CHANNEL_SUFFIX): New macro. 627 (mips_vu0_channel_mask): Declare. 628 6292013-08-03 Richard Sandiford <rdsandiford@googlemail.com> 630 631 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand. 632 (mips_int_operand_min, mips_int_operand_max): New functions. 633 (mips_decode_pcrel_operand): Use mips_decode_int_operand. 634 6352013-08-01 Richard Sandiford <rdsandiford@googlemail.com> 636 637 * mips.h (mips_decode_reg_operand): New function. 638 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL) 639 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4) 640 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI): 641 New macros. 642 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D) 643 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T) 644 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S) 645 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z) 646 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D) 647 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD) 648 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG) 649 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP) 650 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP) 651 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other 652 macros to cover the gaps. 653 (INSN2_MOD_SP): Replace with... 654 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros. 655 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z) 656 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y) 657 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z) 658 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X): 659 Delete. 660 6612013-08-01 Richard Sandiford <rdsandiford@googlemail.com> 662 663 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31) 664 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH) 665 (MIPS16_INSN_COND_BRANCH): Delete. 666 6672013-07-24 Anna Tikhonova <anna.tikhonova@intel.com> 668 Kirill Yukhin <kirill.yukhin@intel.com> 669 Michael Zolotukhin <michael.v.zolotukhin@intel.com> 670 671 * i386.h (BND_PREFIX_OPCODE): New. 672 6732013-07-14 Richard Sandiford <rdsandiford@googlemail.com> 674 675 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and 676 OP_SAVE_RESTORE_LIST. 677 (decode_mips16_operand): Declare. 678 6792013-07-14 Richard Sandiford <rdsandiford@googlemail.com> 680 681 * mips.h (mips_operand_type, mips_reg_operand_type): New enums. 682 (mips_operand, mips_int_operand, mips_mapped_int_operand) 683 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand) 684 (mips_pcrel_operand): New structures. 685 (mips_insert_operand, mips_extract_operand, mips_signed_operand) 686 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions. 687 (decode_mips_operand, decode_micromips_operand): Declare. 688 6892013-07-14 Richard Sandiford <rdsandiford@googlemail.com> 690 691 * mips.h: Document MIPS16 "I" opcode. 692 6932013-07-07 Richard Sandiford <rdsandiford@googlemail.com> 694 695 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB) 696 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB) 697 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A) 698 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB) 699 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB) 700 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB) 701 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB) 702 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB) 703 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A) 704 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A) 705 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB) 706 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete. 707 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A): 708 Rename to... 709 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB) 710 (M_USD_AB): ...these. 711 7122013-07-07 Richard Sandiford <rdsandiford@googlemail.com> 713 714 * mips.h: Remove documentation of "[" and "]". Update documentation 715 of "k" and the MDMX formats. 716 7172013-07-07 Richard Sandiford <rdsandiford@googlemail.com> 718 719 * mips.h: Update documentation of "+s" and "+S". 720 7212013-07-07 Richard Sandiford <rdsandiford@googlemail.com> 722 723 * mips.h: Document "+i". 724 7252013-07-07 Richard Sandiford <rdsandiford@googlemail.com> 726 727 * mips.h: Remove "mi" documentation. Update "mh" documentation. 728 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI): 729 Delete. 730 (INSN2_WRITE_GPR_MHI): Rename to... 731 (INSN2_WRITE_GPR_MH): ...this. 732 7332013-07-07 Richard Sandiford <rdsandiford@googlemail.com> 734 735 * mips.h: Remove documentation of "+D" and "+T". 736 7372013-06-26 Richard Sandiford <rdsandiford@googlemail.com> 738 739 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT. 740 Use "source" rather than "destination" for microMIPS "G". 741 7422013-06-25 Maciej W. Rozycki <macro@codesourcery.com> 743 744 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum 745 values. 746 7472013-06-23 Richard Sandiford <rdsandiford@googlemail.com> 748 749 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS. 750 7512013-06-17 Catherine Moore <clm@codesourcery.com> 752 Maciej W. Rozycki <macro@codesourcery.com> 753 Chao-Ying Fu <fu@mips.com> 754 755 * mips.h (OP_SH_EVAOFFSET): Define. 756 (OP_MASK_EVAOFFSET): Define. 757 (INSN_ASE_MASK): Delete. 758 (ASE_EVA): Define. 759 (M_CACHEE_AB, M_CACHEE_OB): New. 760 (M_LBE_OB, M_LBE_AB): New. 761 (M_LBUE_OB, M_LBUE_AB): New. 762 (M_LHE_OB, M_LHE_AB): New. 763 (M_LHUE_OB, M_LHUE_AB): New. 764 (M_LLE_AB, M_LLE_OB): New. 765 (M_LWE_OB, M_LWE_AB): New. 766 (M_LWLE_AB, M_LWLE_OB): New. 767 (M_LWRE_AB, M_LWRE_OB): New. 768 (M_PREFE_AB, M_PREFE_OB): New. 769 (M_SCE_AB, M_SCE_OB): New. 770 (M_SBE_OB, M_SBE_AB): New. 771 (M_SHE_OB, M_SHE_AB): New. 772 (M_SWE_OB, M_SWE_AB): New. 773 (M_SWLE_AB, M_SWLE_OB): New. 774 (M_SWRE_AB, M_SWRE_OB): New. 775 (MICROMIPSOP_SH_EVAOFFSET): Define. 776 (MICROMIPSOP_MASK_EVAOFFSET): Define. 777 7782013-06-12 Sandra Loosemore <sandra@codesourcery.com> 779 780 * nios2.h (OP_MATCH_ERET): Correct eret encoding. 781 7822013-06-08 Catherine Moore <clm@codesourcery.com> 783 784 * mips.h (mips_opcode): Add ase field. 785 (INSN_ASE_MASK): Delete. 786 (INSN_DSP): Rename to ASE_DSP. Provide new value. 787 (INSN_DSPR2): Rename to ASE_DSPR2. Provide new value. 788 (INSN_MCU): Rename to ASE_MCU. Provide new value. 789 (INSN_MDMX): Rename to ASE_MDMX. Provide new value. 790 (INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value. 791 (INSN_MT): Rename to ASE_MT. Provide new value. 792 (INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value. 793 (INSN_VIRT): Rename to ASE_VIRT. Provide new value. 794 (INSN_VIRT64): Rename to ASE_VIRT64. Provide new value. 795 (opcode_is_member): Add ase argument. Check ase. 796 7972013-05-22 J��rgen Urban <JuergenUrban@gmx.de> 798 799 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros. 800 8012013-05-09 Andrew Pinski <apinski@cavium.com> 802 803 * mips.h (OP_MASK_CODE10): Correct definition. 804 (OP_SH_CODE10): Likewise. 805 Add a comment that "+J" is used now for OP_*CODE10. 806 (INSN_ASE_MASK): Update. 807 (INSN_VIRT): New macro. 808 (INSN_VIRT64): New macro 809 8102013-05-02 Nick Clifton <nickc@redhat.com> 811 812 * msp430.h: Add patterns for MSP430X instructions. 813 8142013-04-06 David S. Miller <davem@davemloft.net> 815 816 * sparc.h (F_PREFERRED): Define. 817 (F_PREF_ALIAS): Define. 818 8192013-04-03 Nick Clifton <nickc@redhat.com> 820 821 * v850.h (V850_INVERSE_PCREL): Define. 822 8232013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com> 824 825 PR binutils/15068 826 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor. 827 8282013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com> 829 830 PR binutils/15068 831 * tic6xc-insn-formats.h (FLD): Add use of bitfield array. 832 Add 16-bit opcodes. 833 * tic6xc-opcode-table.h: Add 16-bit insns. 834 * tic6x.h: Add support for 16-bit insns. 835 8362013-03-21 Michael Schewe <michael.schewe@gmx.net> 837 838 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd 839 and mov.b/w/l Rs,@(d:32,ERd). 840 8412013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com> 842 843 PR gas/15082 844 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro 845 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through 846 tic6x_operand_xregpair operand coding type. 847 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x' 848 opcode field, usu ORXREGD1324 for the src2 operand and remove the 849 TIC6X_FLAG_NO_CROSS. 850 8512013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com> 852 853 PR gas/15095 854 * tic6x.h (enum tic6x_coding_method): Add 855 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode 856 separately the msb and lsb of a register pair. This is needed to 857 encode the opcodes in the same way as TI assembler does. 858 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp 859 and rsqrdp opcodes to use the new field coding types. 860 8612013-03-12 Sebastian Huber <sebastian.huber@embedded-brains.de> 862 863 * nios2.h: Edit comment. 864 8652013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de> 866 867 * nios2.h (OPX_WRPRS): New define. 868 (OP_MATCH_WRPRS): Likewise. 869 8702013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de> 871 872 * nios2.h (OP_RDPRS): New define. 873 (OP_MATCH_RDPRS): Likewise. 874 8752013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 876 877 * arm.h (CRC_EXT_ARMV8): New constant. 878 (ARCH_CRC_ARMV8): New macro. 879 8802013-02-28 Yufeng Zhang <yufeng.zhang@arm.com> 881 882 * aarch64.h (AARCH64_FEATURE_CRC): New macro. 883 8842013-02-06 Sandra Loosemore <sandra@codesourcery.com> 885 Andrew Jenner <andrew@codesourcery.com> 886 887 Based on patches from Altera Corporation. 888 889 * nios2.h: New file. 890 8912013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> 892 893 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2. 894 8952013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com> 896 897 PR gas/15069 898 * tic6x-opcode-table.h: Fix encoding of BNOP instruction. 899 9002013-01-24 Nick Clifton <nickc@redhat.com> 901 902 * v850.h: Add e3v5 support. 903 9042013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> 905 906 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B. 907 9082013-01-10 Peter Bergner <bergner@vnet.ibm.com> 909 910 * ppc.h (PPC_OPCODE_POWER8): New define. 911 (PPC_OPCODE_HTM): Likewise. 912 9132013-01-10 Will Newton <will.newton@imgtec.com> 914 915 * metag.h: New file. 916 9172013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com> 918 919 * cr16.h (make_instruction): Rename to cr16_make_instruction. 920 (match_opcode): Rename to cr16_match_opcode. 921 9222013-01-04 Juergen Urban <JuergenUrban@gmx.de> 923 924 * mips.h: Add support for r5900 instructions including lq and sq. 925 9262013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com> 927 928 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c 929 (make_instruction,match_opcode): Added function prototypes. 930 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern. 931 9322012-12-17 Nick Clifton <nickc@redhat.com> 933 934 * tahoe.h: Add copyright notice. 935 9362012-11-23 Alan Modra <amodra@gmail.com> 937 938 * ppc.h (ppc_parse_cpu): Update prototype. 939 9402012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 941 942 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx 943 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes. 944 9452012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 946 947 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12. 948 9492012-09-27 Anthony Green <green@moxielogic.com> 950 951 * moxie.h (MOXIE_BAD): New define. 952 9532012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> 954 955 * ia64.h (ia64_opnd): Add new operand types. 956 9572012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 958 959 * arm.h (ARM_CPU_IS_ANY): New define. 960 9612012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 962 963 * arm.h (ARM_EXT_V8): New define. 964 (FPU_VFP_EXT_ARMV8): Likewise. 965 (FPU_NEON_EXT_ARMV8): Likewise. 966 (FPU_CRYPTO_EXT_ARMV8): Likewise. 967 (ARM_AEXT_V8A): Likewise. 968 (FPU_VFP_ARMV8): Likwise. 969 (FPU_NEON_ARMV8): Likewise. 970 (FPU_CRYPTO_ARMV8): Likewise. 971 (FPU_ARCH_VFP_ARMV8): Likewise. 972 (FPU_ARCH_NEON_VFP_ARMV8): Likewise. 973 (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8): Likewise. 974 (ARM_ARCH_V8A): Likwise. 975 (ARM_ARCH_V8A_FP): Likewise. 976 (ARM_ARCH_V8A_SIMD): Likewise. 977 (ARM_ARCH_V8A_CRYPTO): Likewise. 978 9792012-08-21 David S. Miller <davem@davemloft.net> 980 981 * sparc.h (F3F4): New macro. 982 9832012-08-13 Ian Bolton <ian.bolton@arm.com> 984 Laurent Desnogues <laurent.desnogues@arm.com> 985 Jim MacArthur <jim.macarthur@arm.com> 986 Marcus Shawcroft <marcus.shawcroft@arm.com> 987 Nigel Stephens <nigel.stephens@arm.com> 988 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> 989 Richard Earnshaw <rearnsha@arm.com> 990 Sofiane Naci <sofiane.naci@arm.com> 991 Tejas Belagod <tejas.belagod@arm.com> 992 Yufeng Zhang <yufeng.zhang@arm.com> 993 994 * aarch64.h: New file. 995 9962012-08-13 Richard Sandiford <rdsandiford@googlemail.com> 997 Maciej W. Rozycki <macro@codesourcery.com> 998 999 * mips.h (mips_opcode): Add the exclusions field. 1000 (OPCODE_IS_MEMBER): Remove macro. 1001 (cpu_is_member): New inline function. 1002 (opcode_is_member): Likewise. 1003 10042012-07-31 Chao-Ying Fu <fu@mips.com> 1005 Catherine Moore <clm@codesourcery.com> 1006 Maciej W. Rozycki <macro@codesourcery.com> 1007 1008 * mips.h: Document microMIPS DSP ASE usage. 1009 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for 1010 microMIPS DSP ASE support. 1011 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. 1012 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. 1013 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. 1014 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. 1015 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. 1016 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. 1017 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. 1018 10192012-07-06 Maciej W. Rozycki <macro@codesourcery.com> 1020 1021 * mips.h: Fix a typo in description. 1022 10232012-07-05 Sean Keys <skeys@ipdatasys.com> 1024 1025 * xgate.h: Changed the format string for mode XGATE_OP_DYA_MON. 1026 10272012-06-07 Georg-Johann Lay <avr@gjlay.de> 1028 1029 * avr.h: (AVR_ISA_XCH): New define. 1030 (AVR_ISA_XMEGA): Use it. 1031 (XCH, LAS, LAT, LAC): New XMEGA opcodes. 1032 10332012-05-15 James Murray <jsm@jsm-net.demon.co.uk> 1034 1035 * m68hc11.h: Add XGate definitions. 1036 (struct m68hc11_opcode): Add xg_mask field. 1037 10382012-05-14 Catherine Moore <clm@codesourcery.com> 1039 Maciej W. Rozycki <macro@codesourcery.com> 1040 Rhonda Wittels <rhonda@codesourcery.com> 1041 1042 * ppc.h (PPC_OPCODE_VLE): New definition. 1043 (PPC_OP_SA): New macro. 1044 (PPC_OP_SE_VLE): New macro. 1045 (PPC_OP): Use a variable shift amount. 1046 (powerpc_operand): Update comments. 1047 (PPC_OPSHIFT_INV): New macro. 1048 (PPC_OPERAND_CR): Replace with... 1049 (PPC_OPERAND_CR_BIT): ...this and 1050 (PPC_OPERAND_CR_REG): ...this. 1051 1052 10532012-05-03 Sean Keys <skeys@ipdatasys.com> 1054 1055 * xgate.h: Header file for XGATE assembler. 1056 10572012-04-27 David S. Miller <davem@davemloft.net> 1058 1059 * sparc.h: Document new arg code' )' for crypto RS3 1060 immediates. 1061 1062 * sparc.h (struct sparc_opcode): New field 'hwcaps'. 1063 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, 1064 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, 1065 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete. 1066 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC, 1067 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF, 1068 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU, 1069 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES, 1070 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1, 1071 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE, 1072 HWCAP_CBCOND, HWCAP_CRC32): New defines. 1073 10742012-04-12 David S. Miller <davem@davemloft.net> 1075 1076 * sparc.h: Define '=' as generating R_SPARC_WDISP10. 1077 10782012-03-10 Edmar Wienskoski <edmar@freescale.com> 1079 1080 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR. 1081 10822012-02-27 Alan Modra <amodra@gmail.com> 1083 1084 * crx.h (cst4_map): Update declaration. 1085 10862012-02-25 Walter Lee <walt@tilera.com> 1087 1088 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS, 1089 TILEGX_OPC_LD_TLS. 1090 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS, 1091 TILEPRO_OPC_LW_TLS_SN. 1092 10932012-02-08 H.J. Lu <hongjiu.lu@intel.com> 1094 1095 * i386.h (XACQUIRE_PREFIX_OPCODE): New. 1096 (XRELEASE_PREFIX_OPCODE): Likewise. 1097 10982011-12-08 Andrew Pinski <apinski@cavium.com> 1099 Adam Nemet <anemet@caviumnetworks.com> 1100 1101 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2. 1102 (INSN_OCTEON2): New macro. 1103 (CPU_OCTEON2): New macro. 1104 (OPCODE_IS_MEMBER): Add Octeon2. 1105 11062011-11-29 Andrew Pinski <apinski@cavium.com> 1107 1108 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP. 1109 (INSN_OCTEONP): New macro. 1110 (CPU_OCTEONP): New macro. 1111 (OPCODE_IS_MEMBER): Add Octeon+. 1112 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values. 1113 11142011-11-01 DJ Delorie <dj@redhat.com> 1115 1116 * rl78.h: New file. 1117 11182011-10-24 Maciej W. Rozycki <macro@codesourcery.com> 1119 1120 * mips.h: Fix a typo in description. 1121 11222011-09-21 David S. Miller <davem@davemloft.net> 1123 1124 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int. 1125 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, 1126 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, 1127 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits. 1128 11292011-08-09 Chao-ying Fu <fu@mips.com> 1130 Maciej W. Rozycki <macro@codesourcery.com> 1131 1132 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. 1133 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. 1134 (INSN_ASE_MASK): Add the MCU bit. 1135 (INSN_MCU): New macro. 1136 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values. 1137 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros. 1138 11392011-08-09 Maciej W. Rozycki <macro@codesourcery.com> 1140 1141 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros. 1142 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise. 1143 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise. 1144 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise. 1145 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise. 1146 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise. 1147 (INSN2_READ_GPR_MMN): Likewise. 1148 (INSN2_READ_FPR_D): Change the bit used. 1149 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise. 1150 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise. 1151 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise. 1152 (INSN2_COND_BRANCH): Likewise. 1153 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros. 1154 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise. 1155 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise. 1156 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise. 1157 (INSN2_MOD_GPR_MN): Likewise. 1158 11592011-08-05 David S. Miller <davem@davemloft.net> 1160 1161 * sparc.h: Document new format codes '4', '5', and '('. 1162 (OPF_LOW4, RS3): New macros. 1163 11642011-08-03 Maciej W. Rozycki <macro@codesourcery.com> 1165 1166 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the 1167 order of flags documented. 1168 11692011-07-29 Maciej W. Rozycki <macro@codesourcery.com> 1170 1171 * mips.h: Clarify the description of microMIPS instruction 1172 manipulation macros. 1173 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros. 1174 11752011-07-24 Chao-ying Fu <fu@mips.com> 1176 Maciej W. Rozycki <macro@codesourcery.com> 1177 1178 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros. 1179 (OP_MASK_STYPE, OP_SH_STYPE): Likewise. 1180 (OP_MASK_CODE10, OP_SH_CODE10): Likewise. 1181 (OP_MASK_TRAP, OP_SH_TRAP): Likewise. 1182 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise. 1183 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise. 1184 (OP_MASK_RS3, OP_SH_RS3): Likewise. 1185 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise. 1186 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise. 1187 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise. 1188 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise. 1189 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise. 1190 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise. 1191 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise. 1192 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise. 1193 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise. 1194 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise. 1195 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise. 1196 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise. 1197 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise. 1198 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise. 1199 (INSN_WRITE_GPR_S): New macro. 1200 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise. 1201 (INSN2_READ_FPR_D): Likewise. 1202 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise. 1203 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise. 1204 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise. 1205 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise. 1206 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise. 1207 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise. 1208 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise. 1209 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise. 1210 (CPU_MICROMIPS): New macro. 1211 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values. 1212 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise. 1213 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise. 1214 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise. 1215 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise. 1216 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise. 1217 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise. 1218 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise. 1219 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise. 1220 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise. 1221 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise. 1222 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise. 1223 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise. 1224 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros. 1225 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise. 1226 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise. 1227 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise. 1228 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise. 1229 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise. 1230 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise. 1231 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise. 1232 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise. 1233 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise. 1234 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise. 1235 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise. 1236 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise. 1237 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise. 1238 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise. 1239 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise. 1240 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise. 1241 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise. 1242 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise. 1243 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise. 1244 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise. 1245 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise. 1246 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise. 1247 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise. 1248 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise. 1249 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise. 1250 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise. 1251 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise. 1252 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise. 1253 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise. 1254 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise. 1255 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise. 1256 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise. 1257 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise. 1258 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise. 1259 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise. 1260 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise. 1261 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise. 1262 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise. 1263 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise. 1264 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise. 1265 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise. 1266 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise. 1267 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise. 1268 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise. 1269 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise. 1270 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise. 1271 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise. 1272 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise. 1273 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise. 1274 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise. 1275 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise. 1276 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise. 1277 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise. 1278 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise. 1279 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise. 1280 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise. 1281 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise. 1282 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise. 1283 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise. 1284 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise. 1285 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise. 1286 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise. 1287 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise. 1288 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise. 1289 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise. 1290 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise. 1291 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise. 1292 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise. 1293 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise. 1294 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise. 1295 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise. 1296 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise. 1297 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise. 1298 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise. 1299 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. 1300 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise. 1301 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. 1302 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. 1303 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. 1304 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. 1305 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. 1306 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise. 1307 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. 1308 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise. 1309 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise. 1310 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise. 1311 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise. 1312 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise. 1313 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise. 1314 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise. 1315 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise. 1316 (micromips_opcodes): New declaration. 1317 (bfd_micromips_num_opcodes): Likewise. 1318 13192011-07-24 Maciej W. Rozycki <macro@codesourcery.com> 1320 1321 * mips.h (INSN_TRAP): Rename to... 1322 (INSN_NO_DELAY_SLOT): ... this. 1323 (INSN_SYNC): Remove macro. 1324 13252011-07-01 Eric B. Weddington <eric.weddington@atmel.com> 1326 1327 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually 1328 a duplicate of AVR_ISA_SPM. 1329 13302011-07-01 Nick Clifton <nickc@redhat.com> 1331 1332 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX. 1333 13342011-06-18 Robin Getz <robin.getz@analog.com> 1335 1336 * bfin.h (is_macmod_signed): New func 1337 13382011-06-18 Mike Frysinger <vapier@gentoo.org> 1339 1340 * bfin.h (is_macmod_pmove): Add missing space before func args. 1341 (is_macmod_hmove): Likewise. 1342 13432011-06-13 Walter Lee <walt@tilera.com> 1344 1345 * tilegx.h: New file. 1346 * tilepro.h: New file. 1347 13482011-05-31 Paul Brook <paul@codesourcery.com> 1349 1350 * arm.h (ARM_ARCH_V7R_IDIV): Define. 1351 13522011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 1353 1354 * s390.h: Replace S390_OPERAND_REG_EVEN with 1355 S390_OPERAND_REG_PAIR. 1356 13572011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 1358 1359 * s390.h: Add S390_OPCODE_REG_EVEN flag. 1360 13612011-04-18 Julian Brown <julian@codesourcery.com> 1362 1363 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask. 1364 13652011-04-11 Dan McDonald <dan@wellkeeper.com> 1366 1367 PR gas/12296 1368 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS. 1369 13702011-03-22 Eric B. Weddington <eric.weddington@atmel.com> 1371 1372 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA): 1373 New instruction set flags. 1374 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA. 1375 13762011-02-28 Maciej W. Rozycki <macro@codesourcery.com> 1377 1378 * mips.h (M_PREF_AB): New enum value. 1379 13802011-02-12 Mike Frysinger <vapier@gentoo.org> 1381 1382 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH, 1383 M_IU): Define. 1384 (is_macmod_pmove, is_macmod_hmove): New functions. 1385 13862011-02-11 Mike Frysinger <vapier@gentoo.org> 1387 1388 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection. 1389 13902011-02-04 Bernd Schmidt <bernds@codesourcery.com> 1391 1392 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP. 1393 * tic6x.h (TIC6X_INSN_ATOMIC): Remove. 1394 13952010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 1396 1397 PR gas/11395 1398 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit 1399 "bb" entries. 1400 14012010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 1402 1403 PR gas/11395 1404 * hppa.h: Clear "d" bit in "add" and "sub" patterns. 1405 14062010-12-18 Richard Sandiford <rdsandiford@googlemail.com> 1407 1408 * mips.h: Update commentary after last commit. 1409 14102010-12-18 Mingjie Xing <mingjie.xing@gmail.com> 1411 1412 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C) 1413 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z) 1414 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define. 1415 14162010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 1417 1418 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU. 1419 14202010-11-23 Richard Sandiford <rdsandiford@googlemail.com> 1421 1422 * mips.h: Fix previous commit. 1423 14242010-11-23 Maciej W. Rozycki <macro@linux-mips.org> 1425 1426 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A. 1427 (INSN_LOONGSON_3A): Clear bit 31. 1428 14292010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 1430 1431 PR gas/12198 1432 * arm.h (ARM_AEXT_V6M_ONLY): New define. 1433 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY. 1434 (ARM_ARCH_V6M_ONLY): New define. 1435 14362010-11-11 Mingming Sun <mingm.sun@gmail.com> 1437 1438 * mips.h (INSN_LOONGSON_3A): Defined. 1439 (CPU_LOONGSON_3A): Defined. 1440 (OPCODE_IS_MEMBER): Add LOONGSON_3A. 1441 14422010-10-09 Matt Rice <ratmice@gmail.com> 1443 1444 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_. 1445 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise. 1446 14472010-09-29 Bernd Schmidt <bernds@codesourcery.com> 1448 1449 * tic6x-control-registers.h (tscl): Now read_write. 1450 14512010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 1452 1453 * s390.h: Add S390_OPCODE_Z196 to enum s390_opcode_cpu_val. 1454 14552010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 1456 1457 * arm.h (ARM_EXT_VIRT): New define. 1458 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename... 1459 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization 1460 Extensions. 1461 14622010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 1463 1464 * arm.h (ARM_AEXT_ADIV): New define. 1465 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise. 1466 14672010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 1468 1469 * arm.h (ARM_EXT_OS): New define. 1470 (ARM_AEXT_V6SM): Likewise. 1471 (ARM_ARCH_V6SM): Likewise. 1472 14732010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 1474 1475 * arm.h (ARM_EXT_MP): Add. 1476 (ARM_ARCH_V7A_MP): Likewise. 1477 14782010-09-22 Mike Frysinger <vapier@gentoo.org> 1479 1480 * bfin.h: Declare pseudoChr structs/defines. 1481 14822010-09-21 Mike Frysinger <vapier@gentoo.org> 1483 1484 * bfin.h: Strip trailing whitespace. 1485 14862009-09-04 Jie Zhang <jie.zhang@analog.com> 1487 1488 * bfin.h (PseudoDbg_Assert): Add bits_grp and mask_grp. 1489 (PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask): Define. 1490 (PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, 1491 PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask): 1492 Adjust accordingly. 1493 (init_PseudoDbg_Assert): Add PseudoDbg_Assert_grp_bits and 1494 PseudoDbg_Assert_grp_mask. 1495 14962010-07-29 DJ Delorie <dj@redhat.com> 1497 1498 * rx.h (RX_Operand_Type): Add TwoReg. 1499 (RX_Opcode_ID): Remove ediv and ediv2. 1500 15012010-07-27 DJ Delorie <dj@redhat.com> 1502 1503 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics. 1504 15052010-07-23 Naveen.H.S <naveen.S@kpitcummins.com> 1506 Ina Pandit <ina.pandit@kpitcummins.com> 1507 1508 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION, 1509 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and 1510 PROCESSOR_V850E2_ALL. 1511 Remove PROCESSOR_V850EA support. 1512 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC, 1513 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI, 1514 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED, 1515 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP, 1516 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and 1517 V850_OPERAND_PERCENT. 1518 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and 1519 V850_NOT_R0. 1520 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP 1521 and V850E_PUSH_POP 1522 15232010-07-06 Maciej W. Rozycki <macro@codesourcery.com> 1524 1525 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro. 1526 (MIPS16_INSN_BRANCH): Rename to... 1527 (MIPS16_INSN_COND_BRANCH): ... this. 1528 15292010-07-03 Alan Modra <amodra@gmail.com> 1530 1531 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete. 1532 Renumber other PPC_OPCODE defines. 1533 15342010-07-03 Alan Modra <amodra@gmail.com> 1535 1536 * ppc.h (PPC_OPCODE_COMMON): Expand comment. 1537 15382010-06-29 Alan Modra <amodra@gmail.com> 1539 1540 * maxq.h: Delete file. 1541 15422010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de> 1543 1544 * ppc.h (PPC_OPCODE_E500): Define. 1545 15462010-05-26 Catherine Moore <clm@codesourcery.com> 1547 1548 * mips.h (INSN_MIPS16): Remove. 1549 15502010-04-21 Joseph Myers <joseph@codesourcery.com> 1551 1552 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask. 1553 15542010-04-15 Nick Clifton <nickc@redhat.com> 1555 1556 * alpha.h: Update copyright notice to use GPLv3. 1557 * arc.h: Likewise. 1558 * arm.h: Likewise. 1559 * avr.h: Likewise. 1560 * bfin.h: Likewise. 1561 * cgen.h: Likewise. 1562 * convex.h: Likewise. 1563 * cr16.h: Likewise. 1564 * cris.h: Likewise. 1565 * crx.h: Likewise. 1566 * d10v.h: Likewise. 1567 * d30v.h: Likewise. 1568 * dlx.h: Likewise. 1569 * h8300.h: Likewise. 1570 * hppa.h: Likewise. 1571 * i370.h: Likewise. 1572 * i386.h: Likewise. 1573 * i860.h: Likewise. 1574 * i960.h: Likewise. 1575 * ia64.h: Likewise. 1576 * m68hc11.h: Likewise. 1577 * m68k.h: Likewise. 1578 * m88k.h: Likewise. 1579 * maxq.h: Likewise. 1580 * mips.h: Likewise. 1581 * mmix.h: Likewise. 1582 * mn10200.h: Likewise. 1583 * mn10300.h: Likewise. 1584 * msp430.h: Likewise. 1585 * np1.h: Likewise. 1586 * ns32k.h: Likewise. 1587 * or32.h: Likewise. 1588 * pdp11.h: Likewise. 1589 * pj.h: Likewise. 1590 * pn.h: Likewise. 1591 * ppc.h: Likewise. 1592 * pyr.h: Likewise. 1593 * rx.h: Likewise. 1594 * s390.h: Likewise. 1595 * score-datadep.h: Likewise. 1596 * score-inst.h: Likewise. 1597 * sparc.h: Likewise. 1598 * spu-insns.h: Likewise. 1599 * spu.h: Likewise. 1600 * tic30.h: Likewise. 1601 * tic4x.h: Likewise. 1602 * tic54x.h: Likewise. 1603 * tic80.h: Likewise. 1604 * v850.h: Likewise. 1605 * vax.h: Likewise. 1606 16072010-03-25 Joseph Myers <joseph@codesourcery.com> 1608 1609 * tic6x-control-registers.h, tic6x-insn-formats.h, 1610 tic6x-opcode-table.h, tic6x.h: New. 1611 16122010-02-25 Wu Zhangjin <wuzhangjin@gmail.com> 1613 1614 * mips.h: (LOONGSON2F_NOP_INSN): New macro. 1615 16162010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com> 1617 1618 * ppc.h (PPC_OPCODE_TITAN): Define. 1619 16202010-01-14 H.J. Lu <hongjiu.lu@intel.com> 1621 1622 * ia64.h (ia64_find_opcode): Remove argument name. 1623 (ia64_find_next_opcode): Likewise. 1624 (ia64_dis_opcode): Likewise. 1625 (ia64_free_opcode): Likewise. 1626 (ia64_find_dependency): Likewise. 1627 16282009-11-22 Doug Evans <dje@sebabeach.org> 1629 1630 * cgen.h: Include bfd_stdint.h. 1631 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types. 1632 16332009-11-18 Paul Brook <paul@codesourcery.com> 1634 1635 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define. 1636 16372009-11-17 Paul Brook <paul@codesourcery.com> 1638 Daniel Jacobowitz <dan@codesourcery.com> 1639 1640 * arm.h (ARM_EXT_V6_DSP): Define. 1641 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP. 1642 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define. 1643 16442009-11-04 DJ Delorie <dj@redhat.com> 1645 1646 * rx.h (rx_decode_opcode) (mvtipl): Add. 1647 (mvtcp, mvfcp, opecp): Remove. 1648 16492009-11-02 Paul Brook <paul@codesourcery.com> 1650 1651 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA, 1652 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define. 1653 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD, 1654 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16, 1655 FPU_ARCH_NEON_VFP_V4): Define. 1656 16572009-10-23 Doug Evans <dje@sebabeach.org> 1658 1659 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h. 1660 * cgen.h: Update. Improve multi-inclusion macro name. 1661 16622009-10-02 Peter Bergner <bergner@vnet.ibm.com> 1663 1664 * ppc.h (PPC_OPCODE_476): Define. 1665 16662009-10-01 Peter Bergner <bergner@vnet.ibm.com> 1667 1668 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2. 1669 16702009-09-29 DJ Delorie <dj@redhat.com> 1671 1672 * rx.h: New file. 1673 16742009-09-22 Peter Bergner <bergner@vnet.ibm.com> 1675 1676 * ppc.h (ppc_cpu_t): Typedef to uint64_t. 1677 16782009-09-21 Ben Elliston <bje@au.ibm.com> 1679 1680 * ppc.h (PPC_OPCODE_PPCA2): New. 1681 16822009-09-05 Martin Thuresson <martin@mtme.org> 1683 1684 * ia64.h (struct ia64_operand): Renamed member class to op_class. 1685 16862009-08-29 Martin Thuresson <martin@mtme.org> 1687 1688 * tic30.h (template): Rename type template to 1689 insn_template. Updated code to use new name. 1690 * tic54x.h (template): Rename type template to 1691 insn_template. 1692 16932009-08-20 Nick Hudson <nick.hudson@gmx.co.uk> 1694 1695 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT. 1696 16972009-06-11 Anthony Green <green@moxielogic.com> 1698 1699 * moxie.h (MOXIE_F3_PCREL): Define. 1700 (moxie_form3_opc_info): Grow. 1701 17022009-06-06 Anthony Green <green@moxielogic.com> 1703 1704 * moxie.h (MOXIE_F1_M): Define. 1705 17062009-04-15 Anthony Green <green@moxielogic.com> 1707 1708 * moxie.h: Created. 1709 17102009-04-06 DJ Delorie <dj@redhat.com> 1711 1712 * h8300.h: Add relaxation attributes to MOVA opcodes. 1713 17142009-03-10 Alan Modra <amodra@bigpond.net.au> 1715 1716 * ppc.h (ppc_parse_cpu): Declare. 1717 17182009-03-02 Qinwei <qinwei@sunnorth.com.cn> 1719 1720 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5 1721 and _IMM11 for mbitclr and mbitset. 1722 * score-datadep.h: Update dependency information. 1723 17242009-02-26 Peter Bergner <bergner@vnet.ibm.com> 1725 1726 * ppc.h (PPC_OPCODE_POWER7): New. 1727 17282009-02-06 Doug Evans <dje@google.com> 1729 1730 * i386.h: Add comment regarding sse* insns and prefixes. 1731 17322009-02-03 Sandip Matte <sandip@rmicorp.com> 1733 1734 * mips.h (INSN_XLR): Define. 1735 (INSN_CHIP_MASK): Update. 1736 (CPU_XLR): Define. 1737 (OPCODE_IS_MEMBER): Update. 1738 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define. 1739 17402009-01-28 Doug Evans <dje@google.com> 1741 1742 * i386.h: Add multiple inclusion protection. 1743 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM) 1744 (EDI_REG_NUM): New macros. 1745 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros. 1746 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros. 1747 (REX_PREFIX_P): New macro. 1748 17492009-01-09 Peter Bergner <bergner@vnet.ibm.com> 1750 1751 * ppc.h (struct powerpc_opcode): New field "deprecated". 1752 (PPC_OPCODE_NOPOWER4): Delete. 1753 17542008-11-28 Joshua Kinard <kumba@gentoo.org> 1755 1756 * mips.h: Define CPU_R14000, CPU_R16000. 1757 (OPCODE_IS_MEMBER): Include R14000, R16000 in test. 1758 17592008-11-18 Catherine Moore <clm@codesourcery.com> 1760 1761 * arm.h (FPU_NEON_FP16): New. 1762 (FPU_ARCH_NEON_FP16): New. 1763 17642008-11-06 Chao-ying Fu <fu@mips.com> 1765 1766 * mips.h: Doucument '1' for 5-bit sync type. 1767 17682008-08-28 H.J. Lu <hongjiu.lu@intel.com> 1769 1770 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update 1771 IA64_RS_CR. 1772 17732008-08-08 Anatoly Sokolov <aesok@post.ru> 1774 1775 * avr.h (AVR_ISA_TINY3, AVR_ISA_ALL, AVR_ISA_USB162): Remove. 1776 (AVR_ISA_AVR3): Redefine. 1777 (AVR_ISA_AVR1, AVR_ISA_AVR2, AVR_ISA_AVR31, AVR_ISA_AVR35, 1778 AVR_ISA_AVR3_ALL, AVR_ISA_AVR4, AVR_ISA_AVR5, AVR_ISA_AVR51, 1779 AVR_ISA_AVR6): Define. 1780 17812008-08-01 Peter Bergner <bergner@vnet.ibm.com> 1782 1783 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New. 1784 17852008-07-30 Michael J. Eager <eager@eagercon.com> 1786 1787 * ppc.h (PPC_OPCODE_405): Define. 1788 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define. 1789 17902008-06-13 Peter Bergner <bergner@vnet.ibm.com> 1791 1792 * ppc.h (ppc_cpu_t): New typedef. 1793 (struct powerpc_opcode <flags>): Use it. 1794 (struct powerpc_operand <insert, extract>): Likewise. 1795 (struct powerpc_macro <flags>): Likewise. 1796 17972008-06-12 Adam Nemet <anemet@caviumnetworks.com> 1798 1799 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S. 1800 Update comment before MIPS16 field descriptors to mention MIPS16. 1801 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for 1802 BBIT. 1803 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1): 1804 New bit masks and shift counts for cins and exts. 1805 1806 * mips.h: Document new field descriptors +Q. 1807 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI. 1808 18092008-04-28 Adam Nemet <anemet@caviumnetworks.com> 1810 1811 * mips.h (INSN_MACRO): Move it up to the pinfo macros. 1812 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros. 1813 18142008-04-14 Edmar Wienskoski <edmar@freescale.com> 1815 1816 * ppc.h: (PPC_OPCODE_E500MC): New. 1817 18182008-04-03 H.J. Lu <hongjiu.lu@intel.com> 1819 1820 * i386.h (MAX_OPERANDS): Set to 5. 1821 (MAX_MNEM_SIZE): Changed to 20. 1822 18232008-03-28 Eric B. Weddington <eric.weddington@atmel.com> 1824 1825 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167. 1826 18272008-03-09 Paul Brook <paul@codesourcery.com> 1828 1829 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define. 1830 18312008-03-04 Paul Brook <paul@codesourcery.com> 1832 1833 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define. 1834 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags. 1835 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define. 1836 18372008-02-27 Denis Vlasenko <vda.linux@googlemail.com> 1838 Nick Clifton <nickc@redhat.com> 1839 1840 PR 3134 1841 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction 1842 with a 32-bit displacement but without the top bit of the 4th byte 1843 set. 1844 18452008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com> 1846 1847 * cr16.h (cr16_num_optab): Declared. 1848 18492008-02-14 Hakan Ardo <hakan@debian.org> 1850 1851 PR gas/2626 1852 * avr.h (AVR_ISA_2xxe): Define. 1853 18542008-02-04 Adam Nemet <anemet@caviumnetworks.com> 1855 1856 * mips.h: Update copyright. 1857 (INSN_CHIP_MASK): New macro. 1858 (INSN_OCTEON): New macro. 1859 (CPU_OCTEON): New macro. 1860 (OPCODE_IS_MEMBER): Handle Octeon instructions. 1861 18622008-01-23 Eric B. Weddington <eric.weddington@atmel.com> 1863 1864 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401. 1865 18662008-01-03 Eric B. Weddington <eric.weddington@atmel.com> 1867 1868 * avr.h (AVR_ISA_USB162): Add new opcode set. 1869 (AVR_ISA_AVR3): Likewise. 1870 18712007-11-29 Mark Shinwell <shinwell@codesourcery.com> 1872 1873 * mips.h (INSN_LOONGSON_2E): New. 1874 (INSN_LOONGSON_2F): New. 1875 (CPU_LOONGSON_2E): New. 1876 (CPU_LOONGSON_2F): New. 1877 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags. 1878 18792007-11-29 Mark Shinwell <shinwell@codesourcery.com> 1880 1881 * mips.h (INSN_ISA*): Redefine certain values as an 1882 enumeration. Update comments. 1883 (mips_isa_table): New. 1884 (ISA_MIPS*): Redefine to match enumeration. 1885 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA* 1886 values. 1887 18882007-08-08 Ben Elliston <bje@au.ibm.com> 1889 1890 * ppc.h (PPC_OPCODE_PPCPS): New. 1891 18922007-07-03 Nathan Sidwell <nathan@codesourcery.com> 1893 1894 * m68k.h: Document j K & E. 1895 18962007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com> 1897 1898 * cr16.h: New file for CR16 target. 1899 19002007-05-02 Alan Modra <amodra@bigpond.net.au> 1901 1902 * ppc.h (PPC_OPERAND_PLUS1): Update comment. 1903 19042007-04-23 Nathan Sidwell <nathan@codesourcery.com> 1905 1906 * m68k.h (mcfisa_c): New. 1907 (mcfusp, mcf_mask): Adjust. 1908 19092007-04-20 Alan Modra <amodra@bigpond.net.au> 1910 1911 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm". 1912 (num_powerpc_operands): Declare. 1913 (PPC_OPERAND_SIGNED et al): Redefine as hex. 1914 (PPC_OPERAND_PLUS1): Define. 1915 19162007-03-21 H.J. Lu <hongjiu.lu@intel.com> 1917 1918 * i386.h (REX_MODE64): Renamed to ... 1919 (REX_W): This. 1920 (REX_EXTX): Renamed to ... 1921 (REX_R): This. 1922 (REX_EXTY): Renamed to ... 1923 (REX_X): This. 1924 (REX_EXTZ): Renamed to ... 1925 (REX_B): This. 1926 19272007-03-15 H.J. Lu <hongjiu.lu@intel.com> 1928 1929 * i386.h: Add entries from config/tc-i386.h and move tables 1930 to opcodes/i386-opc.h. 1931 19322007-03-13 H.J. Lu <hongjiu.lu@intel.com> 1933 1934 * i386.h (FloatDR): Removed. 1935 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR. 1936 19372007-03-01 Alan Modra <amodra@bigpond.net.au> 1938 1939 * spu-insns.h: Add soma double-float insns. 1940 19412007-02-20 Thiemo Seufer <ths@mips.com> 1942 Chao-Ying Fu <fu@mips.com> 1943 1944 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. 1945 (INSN_DSPR2): Add flag for DSP R2 instructions. 1946 (M_BALIGN): New macro. 1947 19482007-02-14 Alan Modra <amodra@bigpond.net.au> 1949 1950 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm 1951 and Seg3ShortFrom with Shortform. 1952 19532007-02-11 H.J. Lu <hongjiu.lu@intel.com> 1954 1955 PR gas/4027 1956 * i386.h (i386_optab): Put the real "test" before the pseudo 1957 one. 1958 19592007-01-08 Kazu Hirata <kazu@codesourcery.com> 1960 1961 * m68k.h (m68010up): OR fido_a. 1962 19632006-12-25 Kazu Hirata <kazu@codesourcery.com> 1964 1965 * m68k.h (fido_a): New. 1966 19672006-12-24 Kazu Hirata <kazu@codesourcery.com> 1968 1969 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a, 1970 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined 1971 values. 1972 19732006-11-08 H.J. Lu <hongjiu.lu@intel.com> 1974 1975 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3. 1976 19772006-10-31 Mei Ligang <ligang@sunnorth.com.cn> 1978 1979 * score-inst.h (enum score_insn_type): Add Insn_internal. 1980 19812006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> 1982 Yukishige Shibata <shibata@rd.scei.sony.co.jp> 1983 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> 1984 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> 1985 Alan Modra <amodra@bigpond.net.au> 1986 1987 * spu-insns.h: New file. 1988 * spu.h: New file. 1989 19902006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> 1991 1992 * ppc.h (PPC_OPCODE_CELL): Define. 1993 19942006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> 1995 1996 * i386.h : Modify opcode to support for the change in POPCNT opcode 1997 in amdfam10 architecture. 1998 19992006-09-28 H.J. Lu <hongjiu.lu@intel.com> 2000 2001 * i386.h: Replace CpuMNI with CpuSSSE3. 2002 20032006-09-26 Mark Shinwell <shinwell@codesourcery.com> 2004 Joseph Myers <joseph@codesourcery.com> 2005 Ian Lance Taylor <ian@wasabisystems.com> 2006 Ben Elliston <bje@wasabisystems.com> 2007 2008 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. 2009 20102006-09-17 Mei Ligang <ligang@sunnorth.com.cn> 2011 2012 * score-datadep.h: New file. 2013 * score-inst.h: New file. 2014 20152006-07-14 H.J. Lu <hongjiu.lu@intel.com> 2016 2017 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps, 2018 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu, 2019 movdq2q and movq2dq. 2020 20212006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> 2022 Michael Meissner <michael.meissner@amd.com> 2023 2024 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions). 2025 20262006-06-12 H.J. Lu <hongjiu.lu@intel.com> 2027 2028 * i386.h (i386_optab): Add "nop" with memory reference. 2029 20302006-06-12 H.J. Lu <hongjiu.lu@intel.com> 2031 2032 * i386.h (i386_optab): Update comment for 64bit NOP. 2033 20342006-06-06 Ben Elliston <bje@au.ibm.com> 2035 Anton Blanchard <anton@samba.org> 2036 2037 * ppc.h (PPC_OPCODE_POWER6): Define. 2038 Adjust whitespace. 2039 20402006-06-05 Thiemo Seufer <ths@mips.com> 2041 2042 * mips.h: Improve description of MT flags. 2043 20442006-05-25 Richard Sandiford <richard@codesourcery.com> 2045 2046 * m68k.h (mcf_mask): Define. 2047 20482006-05-05 Thiemo Seufer <ths@mips.com> 2049 David Ung <davidu@mips.com> 2050 2051 * mips.h (enum): Add macro M_CACHE_AB. 2052 20532006-05-04 Thiemo Seufer <ths@mips.com> 2054 Nigel Stephens <nigel@mips.com> 2055 David Ung <davidu@mips.com> 2056 2057 * mips.h: Add INSN_SMARTMIPS define. 2058 20592006-04-30 Thiemo Seufer <ths@mips.com> 2060 David Ung <davidu@mips.com> 2061 2062 * mips.h: Defines udi bits and masks. Add description of 2063 characters which may appear in the args field of udi 2064 instructions. 2065 20662006-04-26 Thiemo Seufer <ths@networkno.de> 2067 2068 * mips.h: Improve comments describing the bitfield instruction 2069 fields. 2070 20712006-04-26 Julian Brown <julian@codesourcery.com> 2072 2073 * arm.h (FPU_VFP_EXT_V3): Define constant. 2074 (FPU_NEON_EXT_V1): Likewise. 2075 (FPU_VFP_HARD): Update. 2076 (FPU_VFP_V3): Define macro. 2077 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros. 2078 20792006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> 2080 2081 * avr.h (AVR_ISA_PWMx): New. 2082 20832006-03-28 Nathan Sidwell <nathan@codesourcery.com> 2084 2085 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, 2086 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, 2087 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, 2088 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, 2089 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove. 2090 20912006-03-10 Paul Brook <paul@codesourcery.com> 2092 2093 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions. 2094 20952006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2096 2097 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come 2098 first. Correct mask of bb "B" opcode. 2099 21002006-02-27 H.J. Lu <hongjiu.lu@intel.com> 2101 2102 * i386.h (i386_optab): Support Intel Merom New Instructions. 2103 21042006-02-24 Paul Brook <paul@codesourcery.com> 2105 2106 * arm.h: Add V7 feature bits. 2107 21082006-02-23 H.J. Lu <hongjiu.lu@intel.com> 2109 2110 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. 2111 21122006-01-31 Paul Brook <paul@codesourcery.com> 2113 Richard Earnshaw <rearnsha@arm.com> 2114 2115 * arm.h: Use ARM_CPU_FEATURE. 2116 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. 2117 (arm_feature_set): Change to a structure. 2118 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, 2119 ARM_FEATURE): New macros. 2120 21212005-12-07 Hans-Peter Nilsson <hp@axis.com> 2122 2123 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS) 2124 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros. 2125 (ADD_PC_INCR_OPCODE): Don't define. 2126 21272005-12-06 H.J. Lu <hongjiu.lu@intel.com> 2128 2129 PR gas/1874 2130 * i386.h (i386_optab): Add 64bit support for monitor and mwait. 2131 21322005-11-14 David Ung <davidu@mips.com> 2133 2134 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore 2135 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for 2136 save/restore encoding of the args field. 2137 21382005-10-28 Dave Brolley <brolley@redhat.com> 2139 2140 Contribute the following changes: 2141 2005-02-16 Dave Brolley <brolley@redhat.com> 2142 2143 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename 2144 cgen_isa_mask_* to cgen_bitset_*. 2145 * cgen.h: Likewise. 2146 2147 2003-10-21 Richard Sandiford <rsandifo@redhat.com> 2148 2149 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition. 2150 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned". 2151 (CGEN_CPU_TABLE): Make isas a ponter. 2152 2153 2003-09-29 Dave Brolley <brolley@redhat.com> 2154 2155 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef. 2156 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto. 2157 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs. 2158 2159 2002-12-13 Dave Brolley <brolley@redhat.com> 2160 2161 * cgen.h (symcat.h): #include it. 2162 (cgen-bitset.h): #include it. 2163 (CGEN_ATTR_VALUE_TYPE): Now a union. 2164 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h. 2165 (CGEN_ATTR_ENTRY): 'value' now unsigned. 2166 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*). 2167 * cgen-bitset.h: New file. 2168 21692005-09-30 Catherine Moore <clm@cm00re.com> 2170 2171 * bfin.h: New file. 2172 21732005-10-24 Jan Beulich <jbeulich@novell.com> 2174 2175 * ia64.h (enum ia64_opnd): Move memory operand out of set of 2176 indirect operands. 2177 21782005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2179 2180 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes. 2181 Add FLAG_STRICT to pa10 ftest opcode. 2182 21832005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2184 2185 * hppa.h (pa_opcodes): Remove lha entries. 2186 21872005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2188 2189 * hppa.h (FLAG_STRICT): Revise comment. 2190 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants 2191 before corresponding pa11 opcodes. Add strict pa10 register-immediate 2192 entries for "fdc". 2193 21942005-09-30 Catherine Moore <clm@cm00re.com> 2195 2196 * bfin.h: New file. 2197 21982005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2199 2200 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries. 2201 22022005-09-06 Chao-ying Fu <fu@mips.com> 2203 2204 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, 2205 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New 2206 define. 2207 Document !, $, *, &, g, +t, +T operand formats for MT instructions. 2208 (INSN_ASE_MASK): Update to include INSN_MT. 2209 (INSN_MT): New define for MT ASE. 2210 22112005-08-25 Chao-ying Fu <fu@mips.com> 2212 2213 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, 2214 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, 2215 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, 2216 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, 2217 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. 2218 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP 2219 instructions. 2220 (INSN_DSP): New define for DSP ASE. 2221 22222005-08-18 Alan Modra <amodra@bigpond.net.au> 2223 2224 * a29k.h: Delete. 2225 22262005-08-15 Daniel Jacobowitz <dan@codesourcery.com> 2227 2228 * ppc.h (PPC_OPCODE_E300): Define. 2229 22302005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com> 2231 2232 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. 2233 22342005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2235 2236 PR gas/336 2237 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb 2238 and pitlb. 2239 22402005-07-27 Jan Beulich <jbeulich@novell.com> 2241 2242 * i386.h (i386_optab): Add comment to movd. Use LongMem for all 2243 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. 2244 Add movq-s as 64-bit variants of movd-s. 2245 22462005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2247 2248 * hppa.h: Fix punctuation in comment. 2249 2250 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for 2251 implicit space-register addressing. Set space-register bits on opcodes 2252 using implicit space-register addressing. Add various missing pa20 2253 long-immediate opcodes. Remove various opcodes using implicit 3-bit 2254 space-register addressing. Use "fE" instead of "fe" in various 2255 fstw opcodes. 2256 22572005-07-18 Jan Beulich <jbeulich@novell.com> 2258 2259 * i386.h (i386_optab): Operands of aam and aad are unsigned. 2260 22612007-07-15 H.J. Lu <hongjiu.lu@intel.com> 2262 2263 * i386.h (i386_optab): Support Intel VMX Instructions. 2264 22652005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2266 2267 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. 2268 22692005-07-05 Jan Beulich <jbeulich@novell.com> 2270 2271 * i386.h (i386_optab): Add new insns. 2272 22732005-07-01 Nick Clifton <nickc@redhat.com> 2274 2275 * sparc.h: Add typedefs to structure declarations. 2276 22772005-06-20 H.J. Lu <hongjiu.lu@intel.com> 2278 2279 PR 1013 2280 * i386.h (i386_optab): Update comments for 64bit addressing on 2281 mov. Allow 64bit addressing for mov and movq. 2282 22832005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2284 2285 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, 2286 respectively, in various floating-point load and store patterns. 2287 22882005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 2289 2290 * hppa.h (FLAG_STRICT): Correct comment. 2291 (pa_opcodes): Update load and store entries to allow both PA 1.X and 2292 PA 2.0 mneumonics when equivalent. Entries with cache control 2293 completers now require PA 1.1. Adjust whitespace. 2294 22952005-05-19 Anton Blanchard <anton@samba.org> 2296 2297 * ppc.h (PPC_OPCODE_POWER5): Define. 2298 22992005-05-10 Nick Clifton <nickc@redhat.com> 2300 2301 * Update the address and phone number of the FSF organization in 2302 the GPL notices in the following files: 2303 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, 2304 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, 2305 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, 2306 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, 2307 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, 2308 tic54x.h, tic80.h, v850.h, vax.h 2309 23102005-05-09 Jan Beulich <jbeulich@novell.com> 2311 2312 * i386.h (i386_optab): Add ht and hnt. 2313 23142005-04-18 Mark Kettenis <kettenis@gnu.org> 2315 2316 * i386.h: Insert hyphens into selected VIA PadLock extensions. 2317 Add xcrypt-ctr. Provide aliases without hyphens. 2318 23192005-04-13 H.J. Lu <hongjiu.lu@intel.com> 2320 2321 Moved from ../ChangeLog 2322 2323 2005-04-12 Paul Brook <paul@codesourcery.com> 2324 * m88k.h: Rename psr macros to avoid conflicts. 2325 2326 2005-03-12 Zack Weinberg <zack@codesourcery.com> 2327 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. 2328 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, 2329 and ARM_ARCH_V6ZKT2. 2330 2331 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> 2332 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. 2333 Remove redundant instruction types. 2334 (struct argument): X_op - new field. 2335 (struct cst4_entry): Remove. 2336 (no_op_insn): Declare. 2337 2338 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> 2339 * crx.h (enum argtype): Rename types, remove unused types. 2340 2341 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> 2342 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. 2343 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. 2344 (enum operand_type): Rearrange operands, edit comments. 2345 replace us<N> with ui<N> for unsigned immediate. 2346 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped 2347 displacements (respectively). 2348 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. 2349 (instruction type): Add NO_TYPE_INS. 2350 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. 2351 (operand_entry): New field - 'flags'. 2352 (operand flags): New. 2353 2354 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> 2355 * crx.h (operand_type): Remove redundant types i3, i4, 2356 i5, i8, i12. 2357 Add new unsigned immediate types us3, us4, us5, us16. 2358 23592005-04-12 Mark Kettenis <kettenis@gnu.org> 2360 2361 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and 2362 adjust them accordingly. 2363 23642005-04-01 Jan Beulich <jbeulich@novell.com> 2365 2366 * i386.h (i386_optab): Add rdtscp. 2367 23682005-03-29 H.J. Lu <hongjiu.lu@intel.com> 2369 2370 * i386.h (i386_optab): Don't allow the `l' suffix for moving 2371 between memory and segment register. Allow movq for moving between 2372 general-purpose register and segment register. 2373 23742005-02-09 Jan Beulich <jbeulich@novell.com> 2375 2376 PR gas/707 2377 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and 2378 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and 2379 fnstsw. 2380 23812006-02-07 Nathan Sidwell <nathan@codesourcery.com> 2382 2383 * m68k.h (m68008, m68ec030, m68882): Remove. 2384 (m68k_mask): New. 2385 (cpu_m68k, cpu_cf): New. 2386 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, 2387 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. 2388 23892005-01-25 Alexandre Oliva <aoliva@redhat.com> 2390 2391 2004-11-10 Alexandre Oliva <aoliva@redhat.com> 2392 * cgen.h (enum cgen_parse_operand_type): Add 2393 CGEN_PARSE_OPERAND_SYMBOLIC. 2394 23952005-01-21 Fred Fish <fnf@specifixinc.com> 2396 2397 * mips.h: Change INSN_ALIAS to INSN2_ALIAS. 2398 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. 2399 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. 2400 24012005-01-19 Fred Fish <fnf@specifixinc.com> 2402 2403 * mips.h (struct mips_opcode): Add new pinfo2 member. 2404 (INSN_ALIAS): New define for opcode table entries that are 2405 specific instances of another entry, such as 'move' for an 'or' 2406 with a zero operand. 2407 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. 2408 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. 2409 24102004-12-09 Ian Lance Taylor <ian@wasabisystems.com> 2411 2412 * mips.h (CPU_RM9000): Define. 2413 (OPCODE_IS_MEMBER): Handle CPU_RM9000. 2414 24152004-11-25 Jan Beulich <jbeulich@novell.com> 2416 2417 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves 2418 to/from test registers are illegal in 64-bit mode. Add missing 2419 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix 2420 (previously one had to explicitly encode a rex64 prefix). Re-enable 2421 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings 2422 support it there. Add cmpxchg16b as per Intel's 64-bit documentation. 2423 24242004-11-23 Jan Beulich <jbeulich@novell.com> 2425 2426 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are 2427 available only with SSE2. Change the MMX additions introduced by SSE 2428 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A 2429 instructions by their now designated identifier (since combining i686 2430 and 3DNow! does not really imply 3DNow!A). 2431 24322004-11-19 Alan Modra <amodra@bigpond.net.au> 2433 2434 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, 2435 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. 2436 24372004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> 2438 Vineet Sharma <vineets@noida.hcltech.com> 2439 2440 * maxq.h: New file: Disassembly information for the maxq port. 2441 24422004-11-05 H.J. Lu <hongjiu.lu@intel.com> 2443 2444 * i386.h (i386_optab): Put back "movzb". 2445 24462004-11-04 Hans-Peter Nilsson <hp@axis.com> 2447 2448 * cris.h (enum cris_insn_version_usage): Tweak formatting and 2449 comments. Remove member cris_ver_sim. Add members 2450 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, 2451 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. 2452 (struct cris_support_reg, struct cris_cond15): New types. 2453 (cris_conds15): Declare. 2454 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) 2455 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) 2456 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. 2457 (NOP_Z_BITS): Define in terms of NOP_OPCODE. 2458 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and 2459 SIZE_FIELD_UNSIGNED. 2460 24612004-11-04 Jan Beulich <jbeulich@novell.com> 2462 2463 * i386.h (sldx_Suf): Remove. 2464 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. 2465 (q_FP): Define, implying no REX64. 2466 (x_FP, sl_FP): Imply FloatMF. 2467 (i386_optab): Split reg and mem forms of moving from segment registers 2468 so that the memory forms can ignore the 16-/32-bit operand size 2469 distinction. Adjust a few others for Intel mode. Remove *FP uses from 2470 all non-floating-point instructions. Unite 32- and 64-bit forms of 2471 movsx, movzx, and movd. Adjust floating point operations for the above 2472 changes to the *FP macros. Add DefaultSize to floating point control 2473 insns operating on larger memory ranges. Remove left over comments 2474 hinting at certain insns being Intel-syntax ones where the ones 2475 actually meant are already gone. 2476 24772004-10-07 Tomer Levi <Tomer.Levi@nsc.com> 2478 2479 * crx.h: Add COPS_REG_INS - Coprocessor Special register 2480 instruction type. 2481 24822004-09-30 Paul Brook <paul@codesourcery.com> 2483 2484 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. 2485 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. 2486 24872004-09-11 Theodore A. Roth <troth@openavr.org> 2488 2489 * avr.h: Add support for 2490 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. 2491 24922004-09-09 Segher Boessenkool <segher@kernel.crashing.org> 2493 2494 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. 2495 24962004-08-24 Dmitry Diky <diwil@spec.ru> 2497 2498 * msp430.h (msp430_opc): Add new instructions. 2499 (msp430_rcodes): Declare new instructions. 2500 (msp430_hcodes): Likewise.. 2501 25022004-08-13 Nick Clifton <nickc@redhat.com> 2503 2504 PR/301 2505 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX 2506 processors. 2507 25082004-08-30 Michal Ludvig <mludvig@suse.cz> 2509 2510 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. 2511 25122004-07-22 H.J. Lu <hongjiu.lu@intel.com> 2513 2514 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. 2515 25162004-07-21 Jan Beulich <jbeulich@novell.com> 2517 2518 * i386.h: Adjust instruction descriptions to better match the 2519 specification. 2520 25212004-07-16 Richard Earnshaw <rearnsha@arm.com> 2522 2523 * arm.h: Remove all old content. Replace with architecture defines 2524 from gas/config/tc-arm.c. 2525 25262004-07-09 Andreas Schwab <schwab@suse.de> 2527 2528 * m68k.h: Fix comment. 2529 25302004-07-07 Tomer Levi <Tomer.Levi@nsc.com> 2531 2532 * crx.h: New file. 2533 25342004-06-24 Alan Modra <amodra@bigpond.net.au> 2535 2536 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. 2537 25382004-05-24 Peter Barada <peter@the-baradas.com> 2539 2540 * m68k.h: Add 'size' to m68k_opcode. 2541 25422004-05-05 Peter Barada <peter@the-baradas.com> 2543 2544 * m68k.h: Switch from ColdFire chip name to core variant. 2545 25462004-04-22 Peter Barada <peter@the-baradas.com> 2547 2548 * m68k.h: Add mcfmac/mcfemac definitions. Update operand 2549 descriptions for new EMAC cases. 2550 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly 2551 handle Motorola MAC syntax. 2552 Allow disassembly of ColdFire V4e object files. 2553 25542004-03-16 Alan Modra <amodra@bigpond.net.au> 2555 2556 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. 2557 25582004-03-12 Jakub Jelinek <jakub@redhat.com> 2559 2560 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. 2561 25622004-03-12 Michal Ludvig <mludvig@suse.cz> 2563 2564 * i386.h (i386_optab): Added xstore as an alias for xstorerng. 2565 25662004-03-12 Michal Ludvig <mludvig@suse.cz> 2567 2568 * i386.h (i386_optab): Added xstore/xcrypt insns. 2569 25702004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> 2571 2572 * h8300.h (32bit ldc/stc): Add relaxing support. 2573 25742004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> 2575 2576 * h8300.h (BITOP): Pass MEMRELAX flag. 2577 25782004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> 2579 2580 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 2581 except for the H8S. 2582 2583For older changes see ChangeLog-9103 2584 2585Copyright (C) 2004-2015 Free Software Foundation, Inc. 2586 2587Copying and distribution of this file, with or without modification, 2588are permitted in any medium without royalty provided the copyright 2589notice and this notice are preserved. 2590 2591Local Variables: 2592mode: change-log 2593left-margin: 8 2594fill-column: 74 2595version-control: never 2596End: 2597