1	.text
2
3stuff:
4	.ent stuff
5	/* Integer instructions.  */
6
7	mul	$4,$5,$6
8	mulu	$4,$5,$6
9	mulhi	$4,$5,$6
10	mulhiu	$4,$5,$6
11	muls	$4,$5,$6
12	mulsu	$4,$5,$6
13	mulshi	$4,$5,$6
14	mulshiu	$4,$5,$6
15	macc	$4,$5,$6
16	maccu	$4,$5,$6
17	macchi	$4,$5,$6
18	macchiu	$4,$5,$6
19	msac	$4,$5,$6
20	msacu	$4,$5,$6
21	msachi	$4,$5,$6
22	msachiu	$4,$5,$6
23
24	ror	$4,$5,25
25	rorv	$4,$5,$6
26	dror	$4,$5,25
27	dror	$4,$5,57	/* Should expand to dror32 $4,$5,25.  */
28	dror32	$4,$5,25
29	drorv	$4,$5,$6
30
31
32	/* Prefetch instructions.  */
33        # We don't test pref because currently the disassembler will
34        # disassemble it as lwc3.  lwc3 is correct for mips1 to mips3,
35        # while pref is correct for mips4.  Unfortunately, the
36        # disassembler does not know which architecture it is
37        # disassembling for.
38        # pref  4,0($4)
39
40        prefx   4,$4($5)
41
42	/* Debug instructions.  */
43
44	dbreak
45	dret
46	mfdr	$3,$3
47	mtdr	$3,$3
48
49	/* Coprocessor 0 instructions, minus standard ISA 3 ones.
50	   That leaves just the performance monitoring registers.  */
51
52	mfpc	$4,1
53	mfps	$4,1
54	mtpc	$4,1
55	mtps	$4,1
56
57	/* Miscellaneous instructions.  */
58
59	wait
60	wait	0		# disassembles without code
61	wait	0x56789
62
63	ssnop
64
65	clo	$3,$4
66	dclo	$3,$4
67	clz	$3,$4
68	dclz    $3,$4
69
70	luxc1	$f0,$4($2)
71	suxc1   $f2,$4($2)
72
73	tlbp
74	tlbr
75
76	/* Align to 16-byte boundary.  */
77	nop
78	nop
79	nop
80	.end stuff
81