1#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
2#name: MIPS MIPS32r2 non-fp instructions
3#as: -32
4#source: mips32r2.s
5
6# Check MIPS32 Release 2 (mips32r2) *non-fp* instruction assembly
7
8.*: +file format .*mips.*
9
10Disassembly of section .text:
110+0000 <[^>]*> 000000c0 	ehb
120+0004 <[^>]*> 7ca43980 	ext	\$4,\$5,0x6,0x8
130+0008 <[^>]*> 7ca46984 	ins	\$4,\$5,0x6,0x8
140+000c <[^>]*> 0100fc09 	jalr.hb	\$8
150+0010 <[^>]*> 0120a409 	jalr.hb	\$20,\$9
160+0014 <[^>]*> 01000409 	jr.hb	\$8
170+0018 <[^>]*> 7c0a003b 	rdhwr	\$10,\$0
180+001c <[^>]*> 7c0b083b 	rdhwr	\$11,\$1
190+0020 <[^>]*> 7c0c103b 	rdhwr	\$12,\$2
200+0024 <[^>]*> 7c0d183b 	rdhwr	\$13,\$3
210+0028 <[^>]*> 7c0e203b 	rdhwr	\$14,\$4
220+002c <[^>]*> 7c0f283b 	rdhwr	\$15,\$5
230+0030 <[^>]*> 002acf02 	ror	\$25,\$10,0x1c
240+0034 <[^>]*> 002ac902 	ror	\$25,\$10,0x4
250+0038 <[^>]*> 0004c823 	negu	\$25,\$4
260+003c <[^>]*> 032ac846 	rorv	\$25,\$10,\$25
270+0040 <[^>]*> 008ac846 	rorv	\$25,\$10,\$4
280+0044 <[^>]*> 008ac846 	rorv	\$25,\$10,\$4
290+0048 <[^>]*> 7c073c20 	seb	\$7,\$7
300+004c <[^>]*> 7c0a4420 	seb	\$8,\$10
310+0050 <[^>]*> 7c073e20 	seh	\$7,\$7
320+0054 <[^>]*> 7c0a4620 	seh	\$8,\$10
330+0058 <[^>]*> 055f5555 	synci	21845\(\$10\)
340+005c <[^>]*> 7c0738a0 	wsbh	\$7,\$7
350+0060 <[^>]*> 7c0a40a0 	wsbh	\$8,\$10
360+0064 <[^>]*> 41606000 	di
370+0068 <[^>]*> 41606000 	di
380+006c <[^>]*> 416a6000 	di	\$10
390+0070 <[^>]*> 41606020 	ei
400+0074 <[^>]*> 41606020 	ei
410+0078 <[^>]*> 416a6020 	ei	\$10
420+007c <[^>]*> 41595000 	rdpgpr	\$10,\$25
430+0080 <[^>]*> 41d95000 	wrpgpr	\$10,\$25
440+0084 <[^>]*> 00000140 	pause
45	...
46