1/* m68k-parse.h -- header file for m68k assembler
2   Copyright (C) 1987-2017 Free Software Foundation, Inc.
3
4   This file is part of GAS, the GNU Assembler.
5
6   GAS is free software; you can redistribute it and/or modify
7   it under the terms of the GNU General Public License as published by
8   the Free Software Foundation; either version 3, or (at your option)
9   any later version.
10
11   GAS is distributed in the hope that it will be useful,
12   but WITHOUT ANY WARRANTY; without even the implied warranty of
13   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14   GNU General Public License for more details.
15
16   You should have received a copy of the GNU General Public License
17   along with GAS; see the file COPYING.  If not, write to the Free
18   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19   02110-1301, USA.  */
20
21#ifndef M68K_PARSE_H
22#define M68K_PARSE_H
23
24/* This header file defines things which are shared between the
25   operand parser in m68k.y and the m68k assembler proper in
26   tc-m68k.c.  */
27
28/* The various m68k registers.  */
29
30/* DATA and ADDR have to be contiguous, so that reg-DATA gives
31   0-7==data reg, 8-15==addr reg for operands that take both types.
32
33   We don't use forms like "ADDR0 = ADDR" here because this file is
34   likely to be used on an Apollo, and the broken Apollo compiler
35   gives an `undefined variable' error if we do that, according to
36   troy@cbme.unsw.edu.au.  */
37
38#define DATA DATA0
39#define ADDR ADDR0
40#define SP ADDR7
41#define BAD BAD0
42#define BAC BAC0
43
44enum m68k_register
45{
46  DATA0 = 1,			/*   1- 8 == data registers 0-7 */
47  DATA1,
48  DATA2,
49  DATA3,
50  DATA4,
51  DATA5,
52  DATA6,
53  DATA7,
54
55  ADDR0,
56  ADDR1,
57  ADDR2,
58  ADDR3,
59  ADDR4,
60  ADDR5,
61  ADDR6,
62  ADDR7,
63
64  FP0,				/* Eight FP registers */
65  FP1,
66  FP2,
67  FP3,
68  FP4,
69  FP5,
70  FP6,
71  FP7,
72
73  COP0,				/* Co-processor #0-#7 */
74  COP1,
75  COP2,
76  COP3,
77  COP4,
78  COP5,
79  COP6,
80  COP7,
81
82  PC,				/* Program counter */
83  ZPC,				/* Hack for Program space, but 0 addressing */
84  SR,				/* Status Reg */
85  CCR,				/* Condition code Reg */
86  ACC,				/* Accumulator Reg0 (EMAC or ACC on MAC).  */
87  ACC1,				/* Accumulator Reg 1 (EMAC).  */
88  ACC2,				/* Accumulator Reg 2 (EMAC).  */
89  ACC3,				/* Accumulator Reg 3 (EMAC).  */
90  ACCEXT01,			/* Accumulator extension 0&1 (EMAC).  */
91  ACCEXT23,			/* Accumulator extension 2&3 (EMAC).  */
92  MACSR,			/* MAC Status Reg */
93  MASK,				/* Modulus Reg */
94
95  /* These have to be grouped together for the movec instruction to work.  */
96  USP,				/*  User Stack Pointer */
97  ISP,				/*  Interrupt stack pointer */
98  SFC,
99  DFC,
100  CACR,
101  VBR,
102  CAAR,
103  CPUCR,
104  MSP,
105  ITT0,
106  ITT1,
107  DTT0,
108  DTT1,
109  MMUSR,
110  TC,
111  SRP,
112  URP,
113  BUSCR,			/* 68060 added these.  */
114  PCR,
115  ROMBAR,			/* mcf5200 added these.  */
116  RAMBAR_ALT,			/* Some CF chips have RAMBAR using
117				   RAMBAR0's number */
118  RAMBAR0,
119  RAMBAR1,
120  MMUBAR,			/* mcfv4e added these.  */
121  ROMBAR0,			/* mcfv4e added these.  */
122  ROMBAR1,			/* mcfv4e added these.  */
123  MPCR, EDRAMBAR, SECMBAR,	/* mcfv4e added these.  */
124  PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these.  */
125  PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these.  */
126  PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these.  */
127  MBAR0, MBAR1,			/* mcfv4e added these.  */
128  ACR0, ACR1, ACR2, ACR3,       /* mcf5200 added these.  */
129  ACR4, ACR5, ACR6, ACR7,	/* mcf54418 added these.  */
130  FLASHBAR, RAMBAR,  		/* mcf528x added these.  */
131  MBAR2,  		        /* mcf5249 added this.  */
132  MBAR,
133  RGPIOBAR,			/* mcf54418 added this.  */
134  ASID,				/* m5475.  */
135  CAC,  		        /* fido added this.  */
136  MBO,
137#define last_movec_reg MBO
138  /* End of movec ordering constraints.  */
139
140  FPI,
141  FPS,
142  FPC,
143
144  DRP,				/* 68851 or 68030 MMU regs */
145  CRP,
146  CAL,
147  VAL,
148  SCC,
149  AC,
150  BAD0,
151  BAD1,
152  BAD2,
153  BAD3,
154  BAD4,
155  BAD5,
156  BAD6,
157  BAD7,
158  BAC0,
159  BAC1,
160  BAC2,
161  BAC3,
162  BAC4,
163  BAC5,
164  BAC6,
165  BAC7,
166  PSR,				/* aka MMUSR on 68030 (but not MMUSR on 68040)
167				   and ACUSR on 68ec030 */
168  PCSR,
169
170  IC,				/* instruction cache token */
171  DC,				/* data cache token */
172  NC,				/* no cache token */
173  BC,				/* both caches token */
174
175  TT0,				/* 68030 access control unit regs */
176  TT1,
177
178  ZDATA0,			/* suppressed data registers.  */
179  ZDATA1,
180  ZDATA2,
181  ZDATA3,
182  ZDATA4,
183  ZDATA5,
184  ZDATA6,
185  ZDATA7,
186
187  ZADDR0,			/* suppressed address registers.  */
188  ZADDR1,
189  ZADDR2,
190  ZADDR3,
191  ZADDR4,
192  ZADDR5,
193  ZADDR6,
194  ZADDR7,
195
196  /* Upper and lower half of data and address registers.  Order *must*
197     be DATAxL, ADDRxL, DATAxU, ADDRxU.  */
198  DATA0L,			/* lower half of data registers */
199  DATA1L,
200  DATA2L,
201  DATA3L,
202  DATA4L,
203  DATA5L,
204  DATA6L,
205  DATA7L,
206
207  ADDR0L,			/* lower half of address registers */
208  ADDR1L,
209  ADDR2L,
210  ADDR3L,
211  ADDR4L,
212  ADDR5L,
213  ADDR6L,
214  ADDR7L,
215
216  DATA0U,			/* upper half of data registers */
217  DATA1U,
218  DATA2U,
219  DATA3U,
220  DATA4U,
221  DATA5U,
222  DATA6U,
223  DATA7U,
224
225  ADDR0U,			/* upper half of address registers */
226  ADDR1U,
227  ADDR2U,
228  ADDR3U,
229  ADDR4U,
230  ADDR5U,
231  ADDR6U,
232  ADDR7U,
233};
234
235/* Size information.  */
236
237enum m68k_size
238{
239  /* Unspecified.  */
240  SIZE_UNSPEC,
241
242  /* Byte.  */
243  SIZE_BYTE,
244
245  /* Word (2 bytes).  */
246  SIZE_WORD,
247
248  /* Longword (4 bytes).  */
249  SIZE_LONG
250};
251
252/* The structure used to hold information about an index register.  */
253
254struct m68k_indexreg
255{
256  /* The index register itself.  */
257  enum m68k_register reg;
258
259  /* The size to use.  */
260  enum m68k_size size;
261
262  /* The value to scale by.  */
263  int scale;
264};
265
266#ifdef OBJ_ELF
267/* The type of a PIC expression.  */
268
269enum pic_relocation
270{
271  pic_none,			/* not pic */
272  pic_plt_pcrel,		/* @PLTPC */
273  pic_got_pcrel,		/* @GOTPC */
274  pic_plt_off,			/* @PLT */
275  pic_got_off,			/* @GOT */
276  pic_tls_gd,			/* @TLSGD */
277  pic_tls_ldm,			/* @TLSLDM */
278  pic_tls_ldo,			/* @TLSLDO */
279  pic_tls_ie,			/* @TLSIE */
280  pic_tls_le			/* @TLSLE */
281};
282#endif
283
284/* The structure used to hold information about an expression.  */
285
286struct m68k_exp
287{
288  /* The size to use.  */
289  enum m68k_size size;
290
291#ifdef OBJ_ELF
292  /* The type of pic relocation if any.  */
293  enum pic_relocation pic_reloc;
294#endif
295
296  /* The expression itself.  */
297  expressionS exp;
298};
299
300/* The operand modes.  */
301
302enum m68k_operand_type
303{
304  IMMED = 1,
305  ABSL,
306  DREG,
307  AREG,
308  FPREG,
309  CONTROL,
310  AINDR,
311  AINC,
312  ADEC,
313  DISP,
314  BASE,
315  POST,
316  PRE,
317  LSH,  /* MAC/EMAC scalefactor '<<'.  */
318  RSH,  /* MAC/EMAC scalefactor '>>'.  */
319  REGLST
320};
321
322/* The structure used to hold a parsed operand.  */
323
324struct m68k_op
325{
326  /* The type of operand.  */
327  enum m68k_operand_type mode;
328
329  /* The main register.  */
330  enum m68k_register reg;
331
332  /* The register mask for mode REGLST.  */
333  unsigned long mask;
334
335  /* An error message.  */
336  const char *error;
337
338  /* The index register.  */
339  struct m68k_indexreg index;
340
341  /* The displacement.  */
342  struct m68k_exp disp;
343
344  /* The outer displacement.  */
345  struct m68k_exp odisp;
346
347  /* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing).  */
348  int trailing_ampersand;
349};
350
351#endif /* ! defined (M68K_PARSE_H) */
352
353/* The parsing function.  */
354
355extern int m68k_ip_op (char *, struct m68k_op *);
356
357/* Whether register prefixes are optional.  */
358extern int flag_reg_prefix_optional;
359