1// Copyright 2017 The Fuchsia Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#pragma once 6 7// clang-format off 8 9#include <hw/reg.h> 10 11#define DWC3_READ32(a) readl(a) 12#define DWC3_WRITE32(a, v) writel(v, a) 13#define DWC3_READ64(a) readll(a) 14#define DWC3_WRITE64(a, v) writell(v, a) 15 16#define DWC3_MASK(start, count) (((1 << (count)) - 1) << (start)) 17#define DWC3_GET_BITS32(src, start, count) ((DWC3_READ32(src) & DWC3_MASK(start, count)) >> (start)) 18#define DWC3_SET_BITS32(dest, start, count, value) \ 19 DWC3_WRITE32(dest, (DWC3_READ32(dest) & ~DWC3_MASK(start, count)) | \ 20 (((value) << (start)) & DWC3_MASK(start, count))) 21 22// XHCI register offsets 23#define CAPLENGTH 0x0000 // Host Controller Operational Registers 24#define CAPLENGTH_HCIVERSION_START 16 25#define CAPLENGTH_HCIVERSION_BITS 16 26#define CAPLENGTH_CAPLENGTH_START 0 27#define CAPLENGTH_CAPLENGTH_BITS 8 28 29#define HCSPARAMS1 0x0004 // Structural Parameters 1 Register 30#define HCSPARAMS1_MAXPORTS_START 24 31#define HCSPARAMS1_MAXPORTS_BITS 8 32#define HCSPARAMS1_MAXINTRS_START 8 33#define HCSPARAMS1_MAXINTRS_BITS 11 34#define HCSPARAMS1_MAXSLOTS_START 0 35#define HCSPARAMS1_MAXSLOTS_BITS 8 36 37#define HCSPARAMS2 0x0008 // Structural Parameters 2 Register 38#define HCSPARAMS2_MAXSCRATCHPADBUFS_START 27 39#define HCSPARAMS2_MAXSCRATCHPADBUFS_BITS 5 40#define HCSPARAMS2_SPR (1 << 26) 41#define HCSPARAMS2_MAXSCRATCHPADBUFS_HI_START 21 42#define HCSPARAMS2_MAXSCRATCHPADBUFS_HI_BITS 5 43#define HCSPARAMS2_ERSTMAX_START 4 44#define HCSPARAMS2_ERSTMAX_BITS 4 45#define HCSPARAMS2_IST_START 0 46#define HCSPARAMS2_IST_BITS 4 47 48#define HCSPARAMS3 0x000c // Structural Parameters 3 Register 49#define HCSPARAMS3_U2_DEVICE_EXIT_LAT_START 16 50#define HCSPARAMS3_U2_DEVICE_EXIT_LAT_BITS 16 51#define HCSPARAMS3_U1_DEVICE_EXIT_LAT_START 0 52#define HCSPARAMS3_U1_DEVICE_EXIT_LAT_BITS 8 53 54#define HCCPARAMS1 0x0010 // Capability Parameters 1 Register 55#define HCCPARAMS1_XECP_START 16 56#define HCCPARAMS1_XECP_BITS 16 57#define HCCPARAMS1_MAXPSASIZE_START 12 58#define HCCPARAMS1_MAXPSASIZE_BITS 4 59#define HCCPARAMS1_CFC (1 << 11) 60#define HCCPARAMS1_SEC (1 << 10) 61#define HCCPARAMS1_SPC (1 << 9) 62#define HCCPARAMS1_PAE (1 << 8) 63#define HCCPARAMS1_NSS (1 << 7) 64#define HCCPARAMS1_LTC (1 << 6) 65#define HCCPARAMS1_LHRC (1 << 5) 66#define HCCPARAMS1_PIND (1 << 4) 67#define HCCPARAMS1_PPC (1 << 3) 68#define HCCPARAMS1_CSZ (1 << 2) 69#define HCCPARAMS1_BNC (1 << 1) 70#define HCCPARAMS1_AC64 (1 << 0) 71 72#define DBOFF 0x0014 // Doorbell Offset Register 73#define RTSOFF 0x0018 // Runtime Register Space Offset Register 74 75#define HCCPARAMS2 0x001c // Host Controller Capability Parameters 2 76#define HCCPARAMS2_ETC (1 << 6) 77#define HCCPARAMS2_CIC (1 << 5) 78#define HCCPARAMS2_LEC (1 << 4) 79#define HCCPARAMS2_CTC (1 << 3) 80#define HCCPARAMS2_FSC (1 << 2) 81#define HCCPARAMS2_CMC (1 << 1) 82#define HCCPARAMS2_U3C (1 << 0) 83 84// Global register offsets 85#define GSBUSCFG0 0xc100 // Global SoC Bus Configuration Register 0 86#define GSBUSCFG1 0xc104 // Global SoC Bus Configuration Register 1 87#define GTXTHRCFG 0xc108 // Global Tx Threshold Control Register 88#define GRXTHRCFG 0xc10c // Global Rx Threshold Control Register 89 90#define GCTL 0xc110 // Global Core Control Register 91#define GCTL_PWRDNSCALE(n) (((n) & 0x1fff) << 19) 92#define GCTL_PWRDNSCALE_START 19 93#define GCTL_PWRDNSCALE_BITS 13 94#define GCTL_MASTERFILTBYPASS (1 << 18) 95#define GCTL_BYPSSETADDR (1 << 17) 96#define GCTL_U2RSTECN (1 << 16) 97#define GCTL_FRMSCLDWN_START 14 98#define GCTL_FRMSCLDWN_BITS 2 99#define GCTL_PRTCAPDIR_START 12 100#define GCTL_PRTCAPDIR_BITS 2 101#define GCTL_PRTCAPDIR_HOST (1 << GCTL_PRTCAPDIR_START) 102#define GCTL_PRTCAPDIR_DEVICE (2 << GCTL_PRTCAPDIR_START) 103#define GCTL_PRTCAPDIR_OTG (3 << GCTL_PRTCAPDIR_START) 104#define GCTL_PRTCAPDIR_MASK (3 << GCTL_PRTCAPDIR_START) 105#define GCTL_CORESOFTRESET (1 << 11) 106#define GCTL_U1_U2_TIMER_SCALE (1 << 9) 107#define GCTL_DEBUGATTACH (1 << 8) 108#define GCTL_SCALEDOWN_START 4 109#define GCTL_SCALEDOWN_BITS 2 110#define GCTL_DISSCRAMBLE (1 << 3) 111#define GCTL_U2EXIT_LFPS (1 << 2) 112#define GCTL_GBL_HIBERNATION_EN (1 << 1) 113#define GCTL_DSBLCLKGTNG (1 << 0) 114 115#define GPMSTS 0xc114 // Global Power Management Status Register 116#define GSTS 0xc118 // Global Status Register 117#define GSTS_CBELT_START 18 118#define GSTS_CBELT_BITS 4 119#define GSTS_CBELT(s) (((s) >> GSTS_CBELT_START) & ((1 << GSTS_CBELT_START) - 1)) 120#define GSTS_SSIC_IP (1 << 11) 121#define GSTS_OTG_IP (1 << 10) 122#define GSTS_BC_IP (1 << 9) 123#define GSTS_ADP_IP (1 << 8) 124#define GSTS_HOST_IP (1 << 7) 125#define GSTS_DEVICE_IP (1 << 6) 126#define GSTS_CSR_TIMEOUT (1 << 5) 127#define GSTS_BUSERRADDRVLD (1 << 4) 128#define GSTS_CURMOD_START 0 129#define GSTS_CURMOD_BITS 2 130#define GSTS_CURMOD(s) (((s) >> GSTS_CURMOD_START) & ((1 << GSTS_CURMOD_BITS) - 1)) 131 132 133 134#define GUCTL1 0xc11c // Global User Control Register 1 135#define USB31_IP_NAME 0xc120 // IP NAME REGISTER 136#define GGPIO 0xc124 // Global General Purpose Input/Output Register 137#define GUID 0xc128 // Global User ID Register 138#define GUCTL 0xc12c // Global User Control Register 139#define GBUSERRADDR 0xc130 // Global Soc Bus Error Address Register 140#define GBUSERRADDRLO 0xc130 // Global Soc Bus Error Address Register - Low 141#define GBUSERRADDRHI 0xc134 // Global Soc Bus Error Address Register - High 142#define GPRTBIMAP 0xc138 // Global SS Port to Bus Instance Mapping Register - Low 143#define GPRTBIMAPHI 0xc13c // Global SS Port to Bus Instance Mapping Register - High 144 145#define GHWPARAMS0 0xc140 // Global Hardware Parameters Register 0 146#define GHWPARAMS0_AWIDTH_START 24 147#define GHWPARAMS0_AWIDTH_BITS 8 148#define GHWPARAMS0_AWIDTH(p) (((p) >> GHWPARAMS0_AWIDTH_START) & \ 149 ((1 << GHWPARAMS0_AWIDTH_BITS) - 1)) 150#define GHWPARAMS0_SDWIDTH_START 16 151#define GHWPARAMS0_SDWIDTH_BITS 8 152#define GHWPARAMS0_SDWIDTH(p) (((p) >> GHWPARAMS0_SDWIDTH_START) & \ 153 ((1 << GHWPARAMS0_SDWIDTH_BITS) - 1)) 154#define GHWPARAMS0_MDWIDTH_START 8 155#define GHWPARAMS0_MDWIDTH_BITS 8 156#define GHWPARAMS0_MDWIDTH(p) (((p) >> GHWPARAMS0_MDWIDTH_START) & \ 157 ((1 << GHWPARAMS0_MDWIDTH_BITS) - 1)) 158#define GHWPARAMS0_SBUS_TYPE_START 6 159#define GHWPARAMS0_SBUS_TYPE_BITS 2 160#define GHWPARAMS0_SBUS_TYPE(p) (((p) >> GHWPARAMS0_SBUS_TYPE_START) & \ 161 ((1 << GHWPARAMS0_SBUS_TYPE_BITS) - 1)) 162#define GHWPARAMS0_MBUS_TYPE_START 3 163#define GHWPARAMS0_MBUS_TYPE_BITS 3 164#define GHWPARAMS0_MBUS_TYPE(p) (((p) >> GHWPARAMS0_MBUS_TYPE_START) & \ 165 ((1 << GHWPARAMS0_MBUS_TYPE_BITS) - 1)) 166#define GHWPARAMS0_MODE_START 0 167#define GHWPARAMS0_MODE_BITS 3 168#define GHWPARAMS0_MODE(p) (((p) >> GHWPARAMS0_MODE_START) & \ 169 ((1 << GHWPARAMS0_MODE_BITS) - 1)) 170 171#define GHWPARAMS1 0xc144 // Global Hardware Parameters Register 1 172#define GHWPARAMS2 0xc148 // Global Hardware Parameters Register 2 173#define GHWPARAMS3 0xc14c // Global Hardware Parameters Register 3 174#define GHWPARAMS4 0xc150 // Global Hardware Parameters Register 4 175#define GHWPARAMS5 0xc154 // Global Hardware Parameters Register 5 176#define GHWPARAMS6 0xc158 // Global Hardware Parameters Register 6 177#define GHWPARAMS7 0xc15c // Global Hardware Parameters Register 7 178#define GDBGFIFOSPACE 0xc160 // Global Debug Queue/FIFO Space Available Register 179#define GBMUCTL 0xc164 // Global BMU Control Register 180#define GDBGBMU 0xc16c // Global Debug BMU Register 181#define GDBGLSPMUX_HST 0xc170 // Global Debug LSP MUX Register in host mode 182#define GDBGLSPMUX_DEV 0xc170 // Global Debug LSP MUX Register 183#define GDBGLSP 0xc174 // Global Debug LSP Register 184#define GDBGEPINFO0 0xc178 // Global Debug Endpoint Information Register 0 185#define GDBGEPINFO1 0xc17c // Global Debug Endpoint Information Register 1 186#define GPRTBIMAP_HS 0xc180 // Global High-Speed Port to Bus Instance Mapping Register 187#define GPRTBIMAP_HSLO 0xc180 // Global High-Speed Port to Bus Instance Mapping Register - Low 188#define GPRTBIMAP_HSHI 0xc184 // Global High-Speed Port to Bus Instance Mapping Register - High 189#define GPRTBIMAP_FS 0xc188 // Global Full/Low-Speed Port to Bus Instance Mapping Register 190#define GPRTBIMAP_FSLO 0xc188 // Global Full/Low-Speed Port to Bus Instance Mapping Register - Low 191#define GPRTBIMAP_FSHI 0xc18c // Global Full/Low-Speed Port to Bus Instance Mapping Register - High 192#define GHMSOCBWOR 0xc190 // Global Host Mode SoC Bandwidth Override Register 193#define GERRINJCTL_1 0xc194 // Global Error Injection 1 Control Register 194#define GERRINJCTL_2 0xc194 // Global Error Injection 2 Control Register 195#define USB31_VER_NUMBER 0xc1a0 // USB31 IP VERSION NUMBER 196#define USB31_VER_TYPE 0xc1a4 // USB31 IP VERSION TYPE 197#define GSYSBLKWINCTRL 0xc1b0 // System Bus Blocking Window Control 198//#defineGUSB3RMMICTL(n) varies 199#define GUSB2PHYCFG(n) (0xc200 + 4 * (n)) // Global USB2 PHY Configuration Register 200#define GUSB2PHYCFG_PHYSOFTRST (1 << 31) 201#define GUSB2PHYCFG_ULPI_LPM_WITH_OPMODE_CHK (1 << 29) 202#define GUSB2PHYCFG_HSIC_CON_WIDTH_ADJ(n) (((n) & 0x3) << 27) 203#define GUSB2PHYCFG_INV_SEL_HSIC (1 << 26) 204#define GUSB2PHYCFG_LSTRD(n) (((n) & 0x7) << 22) 205#define GUSB2PHYCFG_LSIPD(n) (((n) & 0x7) << 19) 206#define GUSB2PHYCFG_ULPIEXTVBUSINDICATOR (1 << 18) 207#define GUSB2PHYCFG_ULPIEXTVBUSDRV (1 << 17) 208#define GUSB2PHYCFG_ULPIAUTORES (1 << 15) 209#define GUSB2PHYCFG_USBTRDTIM(n) (((n) & 0xf) << 10) 210#define GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10) 211#define GUSB2PHYCFG_XCVRDLY (1 << 9) 212#define GUSB2PHYCFG_ENBLSLPM (1 << 8) 213#define GUSB2PHYCFG_PHYSEL (1 << 7) 214#define GUSB2PHYCFG_SUSPENDUSB20 (1 << 6) 215#define GUSB2PHYCFG_FSINTF (1 << 5) 216#define GUSB2PHYCFG_ULPI_UTMI_SEL (1 << 4) 217#define GUSB2PHYCFG_PHYIF (1 << 3) 218#define GUSB2PHYCFG_TOUTCAL(n) (((n) & 0x7) << 0) 219 220#define GUSB2I2CCTL(n) (0xc240 + 4 * (n)) // Reserved Register 221#define GUSB2PHYACC_UTMI(n) (0xc280 + 4 * (n)) // Global USB 2.0 UTMI PHY Vendor Control Register 222#define GUSB2PHYACC_ULPI(n) (0xc280 + 4 * (n)) // Global USB 2.0 UTMI PHY Vendor Control Register 223 224#define GUSB3PIPECTL(n) (0xc2c0 + 4 * (n)) // Global USB 3.1 PIPE Control Register 225#define GUSB3PIPECTL_PHY_SOFT_RST (1 << 31) // USB3 PHY Soft Reset 226#define GUSB3PIPECTL_HST_PRT_CMPL (1 << 30) 227#define GUSB3PIPECTL_DIS_RX_DET_P3 (1 << 28) 228#define GUSB3PIPECTL_UX_EXIT_IN_PX (1 << 27) 229#define GUSB3PIPECTL_PING_ENHANCE_EN (1 << 26) 230#define GUSB3PIPECTL_U1U2_EXIT_FAIL_TO_RECOV (1 << 25) 231#define GUSB3PIPECTL_REQUEST_P1P2P3 (1 << 24) 232#define GUSB3PIPECTL_START_RX_DET_U3_RX_DET (1 << 23) 233#define GUSB3PIPECTL_DIS_RX_DET_U3_RX_DET (1 << 22) 234#define GUSB3PIPECTL_DELAY_P1P2P3(n) (((n) & 0x7) << 19) 235#define GUSB3PIPECTL_DELAYP1TRANS (1 << 18) 236#define GUSB3PIPECTL_SUSPENDENABLE (1 << 17) 237#define GUSB3PIPECTL_DATWIDTH(n) (((n) & 0x3) << 15) 238#define GUSB3PIPECTL_ABORT_RX_DET_IN_U2 (1 << 14) 239#define GUSB3PIPECTL_SKIP_RX_DET (1 << 13) 240#define GUSB3PIPECTL_LFPS_P0_ALGN (1 << 12) 241#define GUSB3PIPECTL_P3P2_TRAN_OK (1 << 11) 242#define GUSB3PIPECTL_P3_EX_SIG_P3 (1 << 10) 243#define GUSB3PIPECTL_LFPSFILTER (1 << 9) 244#define GUSB3PIPECTL_RX_DETECT_TO_POLLING_LFPS_CONTROL (1 << 8) 245#define GUSB3PIPECTL_SSIC_EN (1 << 7) 246#define GUSB3PIPECTL_TX_SWING (1 << 6) 247#define GUSB3PIPECTL_TX_MARGIN(n) (((n) & 0x7) << 3) 248#define GUSB3PIPECTL_SS_TX_DE_EMPHASIS(n) (((n) & 0x3) << 1) 249#define GUSB3PIPECTL_ELASTIC_BUFFER_MODE (1 << 0) 250 251#define GTXFIFOSIZ(n) (0xc300 + 0x7c * (n)) // Global Transmit FIFO Size Register 252#define GRXFIFOSIZ(n) (0xc380 + 0x7c * (n)) // Global Receive FIFO Size Register 253#define GEVNTADR(n) (0xc400 + 0x10 * (n)) // Global Event Buffer Address Register 254#define GEVNTADRLO(n) (0xc400 + 0x10 * (n)) // Global Event Buffer Address Register - Low 255#define GEVNTADRHI(n) (0xc404 + 0x10 * (n)) // Global Event Buffer Address Register - High 256 257#define GEVNTSIZ(n) (0xc408 + 0x10 * (n)) // Global Event Buffer Size Register 258#define GEVNTSIZ_EVNTINTRPTMASK (1 << 31) // Event Interrupt Mask 259 260#define GEVNTCOUNT(n) (0xc40c + 0x10 * (n)) // Global Event Buffer Size Register 261#define GEVNTCOUNT_EVNT_HANDLER_BUSY (1 << 31) // Event Handler Busy 262#define GEVNTCOUNT_EVNTCOUNT_MASK 0xffff // Mask for Event Count 263 264#define GHWPARAMS8 0xc600 // Global Hardware Parameters Register 8 265#define GSMACCTL 0xc604 // Global SMAC CONTROL REGISTER 266#define GUCTL2 0xc608 // Global User Control Register 2 267#define GUCTL3 0xc60c // Global User Control Register 3 268#define GTXFIFOPRIDEV 0xc610 // Global Device TXFIFO DMA Priority Register 269#define GTXFIFOPRIHST 0xc618 // Global Host TXFIFO DMA Priority Register 270#define GRXFIFOPRIHST 0xc61c // Global Host RXFIFO DMA Priority Register 271#define GFIFOPRIDBC 0xc620 // Global Host Debug Capability DMA Priority Register 272#define GDMAHLRATIO 0xc624 // Global Host FIFO DMA High-Low Priority Ratio Register 273#define GOSTDDMA_ASYNC 0xc628 // Global Number of Async Outstanding DMA Register 274#define GOSTDDMA_PRD 0xc62c // Global Number of Periodic Outstanding DMA Register 275#define GFLADJ 0xc630 // Global Frame Length Adjustment Register 276#define GUSB2RHBCTL(n) (0xc640 + 4 * (n)) // Global USB2 PHY Configuration Register 277 278// Device mode register offsets 279#define DCFG 0xc700 // Device Configuration Register 280#define DCFG_STOP_ON_DISCONNECT (1 << 24) 281#define DCFG_IGN_STRM_PP (1 << 23) 282#define DCFG_LPMCAP (1 << 22) 283#define DCFG_NUMP_START 17 284#define DCFG_NUMP_BITS 5 285#define DCFG_INTRNUM_START 12 286#define DCFG_INTRNUM_BITS 5 287#define DCFG_DEVADDR_START 3 288#define DCFG_DEVADDR_BITS 7 289#define DCFG_DEVSPD_START 0 290#define DCFG_DEVSPD_BITS 3 291#define DCFG_DEVSPD_HIGH 0 292#define DCFG_DEVSPD_FULL 1 293#define DCFG_DEVSPD_LOW 2 294#define DCFG_DEVSPD_SUPER 4 295 296#define DCTL 0xc704 // Device Control Register 297#define DCTL_RUN_STOP (1 << 31) 298#define DCTL_CSFTRST (1 << 30) 299#define DCFG_HIRDTHRES_START 24 300#define DCFG_HIRDTHRES_BITS 5 301#define DCFG_LPM_NYET_THRES_START 20 302#define DCFG_LPM_NYET_THRES_BITS 4 303#define DCTL_KEEP_CONNECT (1 << 19) 304#define DCTL_L1_HIBERNATION_EN (1 << 18) 305#define DCTL_CRS (1 << 17) 306#define DCTL_CSS (1 << 16) 307#define DCTL_INITU2ENA (1 << 12) 308#define DCTL_ACCEPTU2ENA (1 << 11) 309#define DCTL_INITU1ENA (1 << 10) 310#define DCTL_ACCEPTU1ENA (1 << 9) 311#define DCTL_ACCEPTU1ENA (1 << 9) 312#define DCFG_ULSTCHNGREQ_START 5 313#define DCFG_ULSTCHNGREQ_BITS 4 314#define DCFG_TSTCTL_START 1 315#define DCFG_TSTCTL_BITS 4 316 317#define DEVTEN 0xc708 // Device Event Enable Register 318#define DEVTEN_LDMEVTEN (1 << 15) 319#define DEVTEN_L1WKUPEVTEN (1 << 14) 320#define DEVTEN_STOP_ON_DISCONNECT_EN (1 << 13) 321#define DEVTEN_VENDEVTSTRCVDEN (1 << 12) 322#define DEVTEN_ERRTICERREVTEN (1 << 9) 323#define DEVTEN_L1SUSPEN (1 << 8) 324#define DEVTEN_SOFTEVTEN (1 << 7) 325#define DEVTEN_U3_L2_SUSP_EN (1 << 6) 326#define DEVTEN_HIBERNATION_REQ_EVT_EN (1 << 5) 327#define DEVTEN_WKUPEVTEN (1 << 4) 328#define DEVTEN_ULSTCNGEN (1 << 3) 329#define DEVTEN_CONNECTDONEEVTEN (1 << 2) 330#define DEVTEN_USBRSTEVTEN (1 << 1) 331#define DEVTEN_DISSCONNEVTEN (1 << 0) 332 333#define DSTS 0xc70c // Device Status Register 334#define DSTS_DCNRD (1 << 29) 335#define DSTS_SRE (1 << 28) 336#define DSTS_RSS (1 << 25) 337#define DSTS_SSS (1 << 24) 338#define DSTS_COREIDLE (1 << 23) 339#define DSTS_DEVCTRLHLT (1 << 22) 340#define DSTS_USBLNKST_START 18 341#define DSTS_USBLNKST_BITS 4 342#define DSTS_USBLNKST(s) (((s) >> DSTS_USBLNKST_START) & \ 343 ((1 << DSTS_USBLNKST_BITS) - 1)) 344#define DSTS_RXFIFOEMPTY (1 << 17) 345#define DSTS_SOFFN_START 3 346#define DSTS_SOFFN_BITS 14 347#define DSTS_SOFFN(s) (((s) >> DSTS_SOFFN_START) & \ 348 ((1 << DSTS_SOFFN_BITS) - 1)) 349#define DSTS_CONNECTSPD_START 0 350#define DSTS_CONNECTSPD_BITS 3 351#define DSTS_CONNECTSPD(s) (((s) >> DSTS_CONNECTSPD_START) & \ 352 ((1 << DSTS_CONNECTSPD_BITS) - 1)) 353 354// DSTS link state in SS node 355#define DSTS_USBLNKST_U0 0x0 356#define DSTS_USBLNKST_U1 0x1 357#define DSTS_USBLNKST_U2 0x2 358#define DSTS_USBLNKST_U3 0x3 359#define DSTS_USBLNKST_ESS_DIS 0x4 360#define DSTS_USBLNKST_RX_DET 0x5 361#define DSTS_USBLNKST_ESS_INACT 0x6 362#define DSTS_USBLNKST_POLL 0x7 363#define DSTS_USBLNKST_RECOV 0x8 364#define DSTS_USBLNKST_HRESET 0x9 365#define DSTS_USBLNKST_CMPLY 0xa 366#define DSTS_USBLNKST_LPBK 0xb 367#define DSTS_USBLNKST_RESUME_RESET 0xf 368 369// DSTS link state in HS/FS/LS node 370#define DSTS_USBLNKST_ON 0x0 371#define DSTS_USBLNKST_SLEEP 0x2 372#define DSTS_USBLNKST_SUSPEND 0x3 373#define DSTS_USBLNKST_DISCONNECTED 0x4 374#define DSTS_USBLNKST_EARLY_SUSPEND 0x5 375#define DSTS_USBLNKST_RESET 0xe 376#define DSTS_USBLNKST_RESUME 0xf 377 378// DSTS connection speed 379#define DSTS_CONNECTSPD_HIGH 0 380#define DSTS_CONNECTSPD_FULL 1 381#define DSTS_CONNECTSPD_SUPER 4 382#define DSTS_CONNECTSPD_ENHANCED_SUPER 5 383 384#define DGCMDPAR 0xc710 // Device Generic Command Parameter Register 385 386#define DGCMD 0xc714 // Device Generic Command Register 387#define DGCMD_CMDSTATUS_START 12 388#define DGCMD_CMDSTATUS_BITS 4 389#define DGCMD_CMDACT (1 << 10) 390#define DGCMD_CMDIOC (1 << 8) 391#define DGCMD_CMDTYP_START 0 392#define DGCMD_CMDTYP_BITS 8 393 394#define DALEPENA 0xc720 // Device Active USB Endpoint Enable Register 395#define DLDMENA 0xc724 // Device LDM Request Control Register 396 397#define DEPCMDPAR2(n) (0xc800 + 0x10 * (n)) // Endpoint-n Command Parameter 2 Register 398#define DEPCMDPAR1(n) (0xc804 + 0x10 * (n)) // Endpoint-n Command Parameter 1 Register 399#define DEPCMDPAR0(n) (0xc808 + 0x10 * (n)) // Endpoint-n Command Parameter 0 Register 400 401#define DEPCMD(n) (0xc80c + 0x10 * (n)) // Endpoint-n Command Parameter 0 Register 402#define DEPCMD_COMMANDPARAM_START 16 // Command Parameters 403#define DEPCMD_COMMANDPARAM_BITS 16 404#define DEPCMD_CMDSTATUS_START 12 // Command Completion Status 405#define DEPCMD_CMDSTATUS_BITS 4 406#define DEPCMD_HIPRI_FORCERM (1 << 11) // HighPriority/ForceRM 407#define DEPCMD_CMDACT (1 << 10) // Command Active 408#define DEPCMD_CMDIOC (1 << 8) // Command Interrupt on Complete 409#define DEPCMD_CMDTYP(n) (((n) & 0xf) >> 0) 410 411// Command Types for DEPCMD 412#define DEPCFG 1 // Set Endpoint Configuration 413#define DEPXFERCFG 2 // Set Endpoint Transfer Resource Configuration 414#define DEPGETSTATE 3 // Get EndpointState 415#define DEPSSTALL 4 // Set Stall 416#define DEPCSTALL 5 // Clear Stall 417#define DEPSTRTXFER 6 // Start Transfer 418#define DEPUPDXFER 7 // Update Transfer 419#define DEPENDXFER 8 // End Transfer 420#define DEPSTARTCFG 9 // Start New Configuration 421 422#define DEPCMD_RESOURCE_INDEX(n) (((n) & 0x7f) << 16) 423 424// DEPCFG Params 0 425#define DEPCFG_ACTION_INITIALIZE (0 << 30) 426#define DEPCFG_ACTION_RESTORE (1 << 30) 427#define DEPCFG_ACTION_MODIFY (2 << 30) 428#define DEPCFG_BURST_SIZE(n) ((((n) - 1) & 0xf) << 22) 429#define DEPCFG_FIFO_NUM(n) (((n) & 0x1f) << 17) 430#define DEPCFG_INTERNAL_RETRY (1 << 15) 431#define DEPCFG_MAX_PACKET_SIZE(n) (((n) & 0x7ff) << 3) 432#define DEPCFG_EP_TYPE(n) (((n) & 0x3) << 1) 433 434// DEPCFG Params 1 435#define DEPCFG_FIFO_BASED (1 << 31) 436#define DEPCFG_EP_NUMBER(n) (((n) & 0x1f) << 25) 437#define DEPCFG_STREAM_CAPABLE (1 << 24) 438#define DEPCFG_INTERVAL(n) (((n) & 0xff) << 16) 439#define DEPCFG_EBC (1 << 15) // External Buffer Control 440#define DEPCFG_EBC_NO_WRITE_BACK (1 << 14) // Don't write back HWO bit to the TRB descriptor 441#define DEPCFG_STREAM_EVT_EN (1 << 13) 442#define DEPCFG_XFER_NOT_READY_EN (1 << 10) 443#define DEPCFG_XFER_IN_PROGRESS_EN (1 << 9) 444#define DEPCFG_XFER_COMPLETE_EN (1 << 8) 445#define DEPCFG_INTR_NUM(n) (((n) & 0x1f) << 0) 446 447// DEPXFERCFG Params 0 448#define DEPXFERCFG_NUM_XFER_RES(n) (((n) & 0xff) << 0) 449 450#define DEV_IMOD(n) (0xca00 + 4 * (n)) // Device Interrupt Moderation Register 451 452// OTG and Battery Charger register offsets 453#define OCFG 0xcc00 // OTG Configuration Register 454#define OCFG_DISPRTPWRCUTOFF (1 << 5) 455#define OCFG_OTGHIBDISMASK (1 << 4) 456#define OCFG_OTGSFTRSTMSK (1 << 3) 457#define OCFG_HNPCAP (1 << 1) 458#define OCFG_SRPCAP (1 << 0) 459 460#define OCTL 0xcc04 // OTG Control Register 461#define OCTL_OTG3_GOERR (1 << 7) 462#define OCTL_PERIMODE (1 << 6) 463#define OCTL_PRTPWRCTL (1 << 5) 464#define OCTL_HNPREQ (1 << 4) 465#define OCTL_SESREQ (1 << 3) 466#define OCTL_TERMSELDLPULSE (1 << 2) 467#define OCTL_DEVSETHNPEN (1 << 1) 468#define OCTL_HSTSETHNPEN (1 << 0) 469 470#define OEVT 0xcc08 // OTG Event Register 471#define OEVT_DEVICEMOD (1 << 31) 472#define OEVT_OTGXHCIRUNSTPSETEVNT (1 << 27) 473#define OEVT_OTGDEVRUNSTPSETEVNT (1 << 26) 474#define OEVT_OTGHIBENTRYEVNT (1 << 25) 475#define OEVT_OTGCONIDSTSCHNGEVNT (1 << 24) 476#define OEVT_HRRCONFNOTIFEVNT (1 << 23) 477#define OEVT_HRRINITNOTIFEVNT (1 << 22) 478#define OEVT_OTGADEVIDLEEVNT (1 << 21) 479#define OEVT_OTGADEVBHOSTENDEVNT (1 << 20) 480#define OEVT_OTGADEVHOSTEVNT (1 << 19) 481#define OEVT_OTGADEVHNPCHNGEVNT (1 << 18) 482#define OEVT_OTGADEVSRPDETEVNT (1 << 17) 483#define OEVT_OTGADEVSESSENDDETEVNT (1 << 16) 484#define OEVT_OTGBDEVBHOSTENDEVNT (1 << 11) 485#define OEVT_OTGBDEVHNPCHNGEVNT (1 << 10) 486#define OEVT_OTGBDEVSESSVLDDETEVNT (1 << 9) 487#define OEVT_OTGBDEVVBUSCHNGEVNT (1 << 8) 488 489#define OEVTEN 0xcc0c // OTG Event Enable Register 490 491#define OSTS 0xcc10 // OTG Status Register 492#define OSTS_OTGSTATE_START 8 493#define OSTS_OTGSTATE_BITS 4 494#define OSTS_PERIPHERALSTATE (1 << 4) 495#define OSTS_XHCIPRTPOWER (1 << 3) 496#define OSTS_BSESVLD (1 << 2) 497#define OSTS_ASESVLD (1 << 1) 498#define OSTS_CONIDSTS (1 << 0) 499 500#define BCFG 0xcc30 // BC Configuration Register 501#define BCFG_IDDIG_SEL (1 << 1) // IDDIG Select 502#define BCFG_CHIRP_EN (1 << 0) // Chirp Enable 503 504#define BCEVT 0xcc38 // BC Event Register 505#define BCEVT_MV_CHNG_EVNT (1 << 24) // Multi-Valued Input Changed Event 506#define BCEVT_MULT_VAL_ID_BC(e) ((e) & 0x1f) // Multi-Valued ID Pin 507 508#define BCEVTEN 0xcc3c // BC Event Enable Register 509#define BCEVTEN_CHNG_EVNT_ENA (1 << 24) // Multi-Valued Input Changed Event Enable 510 511// Link register offsets 512#define LU1LFPSRXTIM(n) (0xd000 + 0x80 * (n)) // U1_LFPS_RX_TIMER_REG 513#define LU1LFPSTXTIM(n) (0xd004 + 0x80 * (n)) // U1 LFPS TX TIMER REGISTER 514#define LU2LFPSRXTIM(n) (0xd008 + 0x80 * (n)) // U1 LFPS RX TIMER REGISTER 515#define LU2LFPSTXTIM(n) (0xd00c + 0x80 * (n)) // U2 LFPS TX TIMER REG REGISTER 516#define LU3LFPSRXTIM(n) (0xd010 + 0x80 * (n)) // U3 LFPS RX TIMER REGS REGISTER 517#define LU3LFPSTXTIM(n) (0xd014 + 0x80 * (n)) // U3 LFPS TX TIMER REGS REGISTER 518#define LPINGLFPSTIM(n) (0xd018 + 0x80 * (n)) // PING LFPS TIMER REGISTER 519#define LPOLLLFPSTXTIM(n) (0xd01c + 0x80 * (n)) // POLL LFPS TX TIMER REGISTER 520#define LSKIPFREQ(n) (0xd020 + 0x80 * (n)) // SKIP FREQUENCY REGISTER 521#define LLUCTL(n) (0xd024 + 0x80 * (n)) // TX TS1 COUNT REGISTER 522#define LPTMDPDELAY(n) (0xd028 + 0x80 * (n)) // PTM DATAPATH DELAY REGISTER 523#define LSCDTIM1(n) (0xd02c + 0x80 * (n)) // SCD TIMER 1 REGISTER 524#define LSCDTIM2(n) (0xd030 + 0x80 * (n)) // SCD TIMER 2 REGISTER 525#define LSCDTIM3(n) (0xd034 + 0x80 * (n)) // SCD TIMER 3 REGISTER 526#define LSCDTIM4(n) (0xd038 + 0x80 * (n)) // SCD TIMER 4 REGISTER 527#define LLPBMTIM1(n) (0xd03c + 0x80 * (n)) // LPBM TIMER 1 REGISTER 528#define LLPBMTIM2(n) (0xd040 + 0x80 * (n)) // LPBM TIMER 2 REGISTER 529#define LLPBMTXTIM(n) (0xd044 + 0x80 * (n)) // LPBM TX TIMER REGISTER 530#define LLINKERRINJ(n) (0xd048 + 0x80 * (n)) // LINK ERROR TYPE INJECT REGISTER 531#define LLINKERRINJEN(n) (0xd04c + 0x80 * (n)) // LINK ERROR INJECT ENABLE REGISTER 532#define GDBGLTSSM(n) (0xd050 + 0x80 * (n)) // Global Debug LTSSM Register 533#define GDBGLNMCC(n) (0xd054 + 0x80 * (n)) // Global Debug LNMCC Register 534#define LLINKDBGCTRL(n) (0xd058 + 0x80 * (n)) // LINK DEBUG CONTROL REGISTER 535#define LLINKDBGCNTTRIG(n) (0xd05c + 0x80 * (n)) // LINK DEBUG COUNT TRIGGER REGISTER 536#define LCSR_TX_DEEMPH(n) (0xd060 + 0x80 * (n)) // LCSR_TX_DEEMPH REGISTER 537#define LCSR_TX_DEEMPH_1(n) (0xd064 + 0x80 * (n)) // LCSR_TX_DEEMPH_1 REGISTER 538#define LCSR_TX_DEEMPH_2(n) (0xd068 + 0x80 * (n)) // LCSR_TX_DEEMPH_2 REGISTER 539#define LCSR_TX_DEEMPH_3(n) (0xd06c + 0x80 * (n)) // LCSR_TX_DEEMPH_3 REGISTER 540#define LCSRPTMDEBUG1(n) (0xd070 + 0x80 * (n)) // LCSRPTMDEBUG1 REGISTER 541#define LCSRPTMDEBUG2(n) (0xd074 + 0x80 * (n)) // LCSRPTMDELAY2 REGISTER 542