1// Copyright 2017 The Fuchsia Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#pragma once 6 7// Display Related Registers 8#define S912_PRESET_BASE 0xC1104000 9#define S912_PRESET_LENGTH 0x1000 10#define S912_CBUS_REG_BASE 0xC8834000 11#define S912_CBUS_REG_LENGTH 0x1000 12#define S912_DMC_REG_BASE 0xC8838000 13#define S912_DMC_REG_LENGTH 0x1000 14#define S912_HDMITX_BASE 0xC883A000 15#define S912_HDMITX_LENGTH 0x2000 16#define S912_HIU_BASE 0xC883C000 17#define S912_HIU_LENGTH 0x2000 18#define S912_MALI_BASE 0xD00C0000 19#define S912_MALI_LENGTH 0x40000 20#define S912_VPU_BASE 0xD0100000 21#define S912_VPU_LENGTH 0x40000 22#define S912_HDMITX_SEC_BASE 0xDA83A000 23#define S912_HDMITX_SEC_LENGTH 0x2000 24 25#define S912_AOBUS_BASE 0xc8100000 26#define S912_AOBUS_LENGTH 0x100000 27 28#define S912_GPIO_BASE 0xc8834400 29#define S912_GPIO_LENGTH 0x1C00 30#define S912_GPIO_A0_BASE 0xc8100000 31#define S912_GPIO_AO_LENGTH 0x1000 32#define S912_GPIO_INTERRUPT_BASE 0xC1100000 33#define S912_GPIO_INTERRUPT_LENGTH 0x10000 34 35#define S912_I2C_A_BASE 0xc1108500 36#define S912_I2C_A_LENGTH 0x20 37#define S912_I2C_B_BASE 0xc11087c0 38#define S912_I2C_B_LENGTH 0x20 39#define S912_I2C_C_BASE 0xc11087e0 40#define S912_I2C_C_LENGTH 0x20 41#define S912_I2C_D_BASE 0xc1108d20 42#define S912_I2C_D_LENGTH 0x20 43 44#define S912_USB0_BASE 0xc9000000 45#define S912_USB0_LENGTH 0x100000 46#define S912_USB1_BASE 0xc9100000 47#define S912_USB1_LENGTH 0x100000 48 49#define S912_USB_PHY_BASE 0xd0078000 50#define S912_USB_PHY_LENGTH 0x1000 51 52#define S912_UART_A_BASE 0xc11084c0 53#define S912_UART_A_LENGTH 0x18 54#define S912_UART_AO_B_BASE 0xc81004e0 55#define S912_UART_AO_B_LENGTH 0x18 56 57#define S912_DOS_BASE 0xc8820000 58#define S912_DOS_LENGTH 0x10000 59 60#define S912_HIU_MAILBOX_BASE 0xc883C400 61#define S912_HIU_MAILBOX_LENGTH 0x1000 62 63#define S912_MAILBOX_PAYLOAD_BASE 0xc8013000 64#define S912_MAILBOX_PAYLOAD_LENGTH 0x1000 65 66#define S912_FULL_CBUS_BASE 0xC1100000 67#define S912_FULL_CBUS_LENGTH 0x100000 68 69// IRQs 70#define S912_VIU1_VSYNC_IRQ 35 71#define S912_ETH_GMAC_IRQ 40 72#define S912_M_I2C_0_IRQ 53 73#define S912_DEMUX_IRQ 55 74#define S912_UART_A_IRQ 58 75#define S912_USBH_IRQ 62 76#define S912_USBD_IRQ 63 77#define S912_PARSER_IRQ 64 78#define S912_M_I2C_3_IRQ 71 79#define S912_DOS_MBOX_0_IRQ 75 80#define S912_DOS_MBOX_1_IRQ 76 81#define S912_DOS_MBOX_2_IRQ 77 82#define S912_GPIO_IRQ_0 96 83#define S912_GPIO_IRQ_1 97 84#define S912_GPIO_IRQ_2 98 85#define S912_GPIO_IRQ_3 99 86#define S912_GPIO_IRQ_4 100 87#define S912_GPIO_IRQ_5 101 88#define S912_GPIO_IRQ_6 102 89#define S912_GPIO_IRQ_7 103 90#define S912_MALI_IRQ_GP 192 91#define S912_MALI_IRQ_GPMMU 193 92#define S912_MALI_IRQ_PP 194 93#define S912_UART_AO_B_IRQ 229 94#define S912_A0_GPIO_IRQ_0 232 95#define S912_A0_GPIO_IRQ_1 233 96#define S912_MBOX_IRQ_RECEIV0 240 97#define S912_MBOX_IRQ_RECEIV1 241 98#define S912_MBOX_IRQ_RECEIV2 242 99#define S912_MBOX_IRQ_SEND3 243 100#define S912_MBOX_IRQ_SEND4 244 101#define S912_MBOX_IRQ_SEND5 245 102#define S912_M_I2C_1_IRQ 246 103#define S912_M_I2C_2_IRQ 247 104 105// DMC registers 106#define DMC_REG_BASE 0xc8838000 107 108#define PERIPHS_REG_BASE (0xc8834000) 109#define PERIPHS_REG_SIZE (0x2000) 110//Offsets of peripheral control registers 111#define PER_ETH_REG0 (0x400 + (0x50 << 2)) 112#define PER_ETH_REG1 (0x400 + (0x51 << 2)) 113#define PER_ETH_REG2 (0x400 + (0x56 << 2)) 114#define PER_ETH_REG3 (0x400 + (0x57 << 2)) 115#define PER_ETH_REG4 (0x400 + (0x58 << 2)) 116 117 118#define HHI_REG_BASE (0xc883c000) 119#define HHI_REG_SIZE (0x2000) 120//Offsets of HHI registers 121#define HHI_SCR (0x0B << 2) 122#define HHI_TIMEOUT_VALUE (0x0F << 2) 123#define HHI_GP0_PLL_CNTL (0x10 << 2) 124#define HHI_GP0_PLL_CNTL2 (0x11 << 2) 125#define HHI_GP0_PLL_CNTL3 (0x12 << 2) 126#define HHI_GP0_PLL_CNTL4 (0x13 << 2) 127#define HHI_GP0_PLL_CNTL5 (0x14 << 2) 128#define HHI_GP0_PLL_STS (0x15 << 2) 129#define HHI_GP0_PLL_CNTL1 (0x16 << 2) 130#define HHI_XTAL_DIVN_CNTL (0x2F << 2) 131#define HHI_GCLK2_MPEG0 (0x30 << 2) 132#define HHI_GCLK2_MPEG1 (0x31 << 2) 133#define HHI_GCLK2_MPEG2 (0x32 << 2) 134#define HHI_GCLK2_OTHER (0x34 << 2) 135#define HHI_GCLK2_AO (0x35 << 2) 136#define HHI_TIMER90K (0x3B << 2) 137#define HHI_MEM_PD_REG0 (0x40 << 2) 138#define HHI_VPU_MEM_PD_REG0 (0x41 << 2) 139#define HHI_VPU_MEM_PD_REG1 (0x42 << 2) 140#define HHI_VIID_CLK_DIV (0x4A << 2) 141#define HHI_VIID_CLK_CNTL (0x4B << 2) 142#define HHI_GCLK_MPEG0 (0x50 << 2) 143#define HHI_GCLK_MPEG1 (0x51 << 2) 144#define HHI_GCLK_MPEG2 (0x52 << 2) 145#define HHI_GCLK_OTHER (0x54 << 2) 146#define HHI_GCLK_AO (0x55 << 2) 147#define HHI_SYS_CPU_CLK_CNTL1 (0x57 << 2) 148#define HHI_SYS_CPU_RESET_CNTL (0x58 << 2) 149#define HHI_VID_CLK_DIV (0x59 << 2) 150#define HHI_MPEG_CLK_CNTL (0x5D << 2) 151#define HHI_AUD_CLK_CNTL (0x5E << 2) 152#define HHI_VID_CLK_CNTL (0x5F << 2) 153#define HHI_AUD_CLK_CNTL2 (0x64 << 2) 154#define HHI_VID_CLK_CNTL2 (0x65 << 2) 155#define HHI_SYS_CPU_CLK_CNTL0 (0x67 << 2) 156#define HHI_VID_PLL_CLK_DIV (0x68 << 2) 157#define HHI_AUD_CLK_CNTL3 (0x69 << 2) 158#define HHI_MALI_CLK_CNTL (0x6C << 2) 159#define HHI_VPU_CLK_CNTL (0x6F << 2) 160#define HHI_HDMI_CLK_CNTL (0x73 << 2) 161#define HHI_VDEC_CLK_CNTL (0x78 << 2) 162#define HHI_VDEC2_CLK_CNTL (0x79 << 2) 163#define HHI_VDEC3_CLK_CNTL (0x7a << 2) 164#define HHI_VDEC4_CLK_CNTL (0x7b << 2) 165#define HHI_HDCP22_CLK_CNTL (0x7c << 2) 166#define HHI_VAPBCLK_CNTL (0x7d << 2) 167#define HHI_VPU_CLKB_CNTL (0x83 << 2) 168#define HHI_USB_CLK_CNTL (0x88 << 2) 169#define HHI_32K_CLK_CNTL (0x89 << 2) 170#define HHI_GEN_CLK_CNTL (0x8A << 2) 171#define HHI_PCM_CLK_CNTL (0x96 << 2) 172#define HHI_NAND_CLK_CNTL (0x97 << 2) 173#define HHI_SD_EMMC_CLK_CNTL (0x99 << 2) 174#define HHI_MPLL_CNTL (0xA0 << 2) 175#define HHI_MPLL_CNTL2 (0xA1 << 2) 176#define HHI_MPLL_CNTL3 (0xA2 << 2) 177#define HHI_MPLL_CNTL4 (0xA3 << 2) 178#define HHI_MPLL_CNTL5 (0xA4 << 2) 179#define HHI_MPLL_CNTL6 (0xA5 << 2) 180#define HHI_MPLL_CNTL7 (0xA6 << 2) 181#define HHI_MPLL_CNTL8 (0xA7 << 2) 182#define HHI_MPLL_CNTL9 (0xA8 << 2) 183#define HHI_MPLL_CNTL10 (0xA9 << 2) 184#define HHI_MPLL3_CNTL0 (0xB8 << 2) 185#define HHI_MPLL3_CNTL1 (0xB9 << 2) 186#define HHI_VDAC_CNTL0 (0xBD << 2) 187#define HHI_VDAC_CNTL1 (0xBE << 2) 188#define HHI_SYS_PLL_CNTL1 (0xBF << 2) 189#define HHI_SYS_PLL_CNTL (0xC0 << 2) 190#define HHI_SYS_PLL_CNTL2 (0xC1 << 2) 191#define HHI_SYS_PLL_CNTL3 (0xC2 << 2) 192#define HHI_SYS_PLL_CNTL4 (0xC3 << 2) 193#define HHI_SYS_PLL_CNTL5 (0xC4 << 2) 194#define HHI_SYS_PLL_STS (0xC5 << 2) 195#define HHI_DPLL_TOP_I (0xC6 << 2) 196#define HHI_DPLL_TOP2_I (0xC7 << 2) 197#define HHI_HDMI_PLL_CNTL (0xC8 << 2) 198#define HHI_HDMI_PLL_CNTL1 (0xC9 << 2) 199#define HHI_HDMI_PLL_CNTL2 (0xCA << 2) 200#define HHI_HDMI_PLL_CNTL3 (0xCB << 2) 201#define HHI_HDMI_PLL_CNTL4 (0xCC << 2) 202#define HHI_HDMI_PLL_CNTL5 (0xCD << 2) 203#define HHI_HDMI_PLL_STS (0xCE << 2) 204#define HHI_HDMI_PHY_CNTL0 (0xE8 << 2) 205#define HHI_HDMI_PHY_CNTL1 (0xE9 << 2) 206#define HHI_HDMI_PHY_CNTL2 (0xEA << 2) 207#define HHI_HDMI_PHY_CNTL3 (0xEB << 2) 208#define HHI_HDMI_PHY_CNTL4 (0xEC << 2) 209#define HHI_HDMI_PHY_STATUS (0xED << 2) 210#define HHI_VID_LOCK_CLK_CNTL (0xF2 << 2) 211#define HHI_BT656_CLK_CNTL (0xF5 << 2) 212#define HHI_SAR_CLK_CNTL (0xF6 << 2) 213 214#define ETH_MAC_REG_BASE (0xc9410000) 215#define ETH_MAC_REG_SIZE (0x00010000) 216 217#define DMC_CAV_LUT_DATAL (0x12 << 2) 218#define DMC_CAV_LUT_DATAH (0x13 << 2) 219#define DC_CAV_LUT_ADDR (0x14 << 2) 220 221#define DC_CAV_LUT_ADDR_INDEX_MASK 0x7 222#define DC_CAV_LUT_ADDR_RD_EN (1 << 8) 223#define DC_CAV_LUT_ADDR_WR_EN (2 << 8) 224// Alternate Functions for Ethernet 225#define S912_ETH_MDIO S912_GPIOZ(0) 226#define S912_ETH_MDIO_FN 1 227#define S912_ETH_MDC S912_GPIOZ(1) 228#define S912_ETH_MDC_FN 1 229 230#define S912_ETH_RGMII_RX_CLK S912_GPIOZ(2) 231#define S912_ETH_RGMII_RX_CLK_FN 1 232#define S912_ETH_RX_DV S912_GPIOZ(3) 233#define S912_ETH_RX_DV_FN 1 234#define S912_ETH_RXD0 S912_GPIOZ(4) 235#define S912_ETH_RXD0_FN 1 236#define S912_ETH_RXD1 S912_GPIOZ(5) 237#define S912_ETH_RXD1_FN 1 238#define S912_ETH_RXD2 S912_GPIOZ(6) 239#define S912_ETH_RXD2_FN 1 240#define S912_ETH_RXD3 S912_GPIOZ(7) 241#define S912_ETH_RXD3_FN 1 242 243#define S912_ETH_RGMII_TX_CLK S912_GPIOZ(8) 244#define S912_ETH_RGMII_TX_CLK_FN 1 245#define S912_ETH_TX_EN S912_GPIOZ(9) 246#define S912_ETH_TX_EN_FN 1 247#define S912_ETH_TXD0 S912_GPIOZ(10) 248#define S912_ETH_TXD0_FN 1 249#define S912_ETH_TXD1 S912_GPIOZ(11) 250#define S912_ETH_TXD1_FN 1 251#define S912_ETH_TXD2 S912_GPIOZ(12) 252#define S912_ETH_TXD2_FN 1 253#define S912_ETH_TXD3 S912_GPIOZ(13) 254#define S912_ETH_TXD3_FN 1 255 256// Alternate Functions for I2C 257#define S912_I2C_SDA_A S912_GPIODV(24) 258#define S912_I2C_SDA_A_FN 2 259#define S912_I2C_SCK_A S912_GPIODV(25) 260#define S912_I2C_SCK_A_FN 2 261 262#define S912_I2C_SDA_B S912_GPIODV(26) 263#define S912_I2C_SDA_B_FN 2 264#define S912_I2C_SCK_B S912_GPIODV(27) 265#define S912_I2C_SCK_B_FN 2 266 267#define S912_I2C_SDA_C S912_GPIODV(28) 268#define S912_I2C_SDA_C_FN 2 269#define S912_I2C_SCK_C S912_GPIODV(29) 270#define S912_I2C_SCK_C_FN 2 271 272#define S912_I2C_SDA_D S912_GPIOX(10) 273#define S912_I2C_SDA_D_FN 3 274#define S912_I2C_SCK_D S912_GPIOX(11) 275#define S912_I2C_SCK_D_FN 3 276 277#define S912_I2C_SDA_AO S912_GPIOAO(4) 278#define S912_I2C_SDA_AO_FN 2 279#define S912_I2C_SCK_AO S912_GPIOAO(5) 280#define S912_I2C_SCK_AO_FN 2 281 282// Alternate functions for UARTs 283#define S912_UART_TX_A S912_GPIOX(12) 284#define S912_UART_TX_A_FN 1 285#define S912_UART_RX_A S912_GPIOX(13) 286#define S912_UART_RX_A_FN 1 287#define S912_UART_CTS_A S912_GPIOX(14) 288#define S912_UART_CTS_A_FN 1 289#define S912_UART_RTS_A S912_GPIOX(15) 290#define S912_UART_RTS_A_FN 1 291 292#define S912_UART_TX_B S912_GPIODV(24) 293#define S912_UART_TX_B_FN 2 294#define S912_UART_RX_B S912_GPIODV(25) 295#define S912_UART_RX_B_FN 2 296#define S912_UART_CTS_B S912_GPIODV(26) 297#define S912_UART_CTS_B_FN 2 298#define S912_UART_RTS_B S912_GPIODV(27) 299#define S912_UART_RTS_B_FN 2 300 301#define S912_UART_TX_C S912_GPIOX(8) 302#define S912_UART_TX_C_FN 2 303#define S912_UART_RX_C S912_GPIOX(9) 304#define S912_UART_RX_C_FN 2 305#define S912_UART_CTS_C S912_GPIOX(10) 306#define S912_UART_CTS_C_FN 2 307#define S912_UART_RTS_C S912_GPIOX(11) 308#define S912_UART_RTS_C_FN 2 309 310#define S912_UART_TX_AO_A S912_GPIOAO(0) 311#define S912_UART_TX_AO_A_FN 1 312#define S912_UART_RX_AO_A S912_GPIOAO(1) 313#define S912_UART_RX_AO_A_FN 1 314#define S912_UART_CTS_AO_A S912_GPIOAO(2) 315#define S912_UART_CTS_AO_A_FN 1 316#define S912_UART_RTS_AO_A S912_GPIOAO(3) 317#define S912_UART_RTS_AO_A_FN 1 318 319// CTS/RTS cannot be used for UART_AO_B without interfering with UART_AO_A 320#define S912_UART_TX_AO_B S912_GPIOAO(4) 321#define S912_UART_TX_AO_B_FN 1 322#define S912_UART_RX_AO_B S912_GPIOAO(5) 323#define S912_UART_RX_AO_B_FN 1 324 325#define S912_PWM_BASE 0xc1100000 326#define S912_AO_PWM_BASE 0xc8100400 327 328// PWM register offsets 329// These are relative to base address 0xc1100000 and in sizeof(uint32_t) 330#define S912_PWM_PWM_A 0x2154 331#define S912_PWM_PWM_B 0x2155 332#define S912_PWM_MISC_REG_AB 0x2156 333#define S912_DS_A_B 0x2157 334#define S912_PWM_TIME_AB 0x2158 335#define S912_PWM_A2 0x2159 336#define S912_PWM_PWM_C 0x2194 337#define S912_PWM_PWM_D 0x2195 338#define S912_PWM_MISC_REG_CD 0x2196 339#define S912_PWM_DELTA_SIGMA_CD 0x2197 340#define S912_PWM_PWM_E 0x21b0 341#define S912_PWM_PWM_F 0x21b1 342#define S912_PWM_MISC_REG_EF 0x21b2 343#define S912_PWM_DELTA_SIGMA_EF 0x21b3 344#define S912_PWM_TIME_EF 0x21b4 345#define S912_PWM_E2 0x21b5 346 347// These are relative to base address 0xc8100400 and in sizeof(uint32_t) 348#define S912_AO_PWM_PWM_A 0x54 349#define S912_AO_PWM_PWM_B 0x55 350#define S912_AO_PWM_MISC_REG_AB 0x56 351#define S912_AO_PWM_DELTA_SIGMA_AB 0x57 352 353// Alternate Functions for EMMC/NAND 354#define S912_EMMC_NAND_D0 S912_GPIOBOOT(0) 355#define S912_EMMC_NAND_D0_FN 1 356#define S912_EMMC_NAND_D1 S912_GPIOBOOT(1) 357#define S912_EMMC_NAND_D1_FN 1 358#define S912_EMMC_NAND_D2 S912_GPIOBOOT(2) 359#define S912_EMMC_NAND_D2_FN 1 360#define S912_EMMC_NAND_D3 S912_GPIOBOOT(3) 361#define S912_EMMC_NAND_D3_FN 1 362#define S912_EMMC_NAND_D4 S912_GPIOBOOT(4) 363#define S912_EMMC_NAND_D4_FN 1 364#define S912_EMMC_NAND_D5 S912_GPIOBOOT(5) 365#define S912_EMMC_NAND_D5_FN 1 366#define S912_EMMC_NAND_D6 S912_GPIOBOOT(6) 367#define S912_EMMC_NAND_D6_FN 1 368#define S912_EMMC_NAND_D7 S912_GPIOBOOT(7) 369#define S912_EMMC_NAND_D7_FN 1 370#define S912_EMMC_CLK S912_GPIOBOOT(8) 371#define S912_EMMC_CLK_FN 1 372#define S912_EMMC_RST S912_GPIOBOOT(9) 373#define S912_EMMC_RST_FN 1 374#define S912_EMMC_CMD S912_GPIOBOOT(10) 375#define S912_EMMC_CMD_FN 1 376#define S912_EMMC_DS S912_GPIOBOOT(15) 377#define S912_EMMC_DS_FN 1 378 379// Reset register offsets 380#define S912_RESET0_MASK 0x110 381#define S912_RESET2_MASK 0x112 382#define S912_RESET0_LEVEL 0x120 383#define S912_RESET2_LEVEL 0x122 384 385// Audio register blocks 386#define S912_AUDIN_BASE ((uint32_t)0xC110A000) 387#define S912_AUDIN_LEN ((uint32_t)0x1000) 388#define S912_AUDOUT_BASE ((uint32_t)0xC1105400) 389#define S912_AUDOUT_LEN ((uint32_t)0x400) 390 391// Pin defs and alt functions for SPDIF in/out 392#define S912_SPDIF_H4 S912_GPIOH(4) 393#define S912_SPDIF_H4_OUT_FN (1u) 394#define S912_SPDIF_H4_IN_FN (1u) 395#define S912_SPDIF_AO6 S912_GPIOAO(6) 396#define S912_SPDIF_AO6_OUT_FN (3u) 397#define S912_SPDIF_AO9 S912_GPIOAO(9) 398#define S912_SPDIF_AO9_OUT_FN (2u) 399#define S912_SPDIF_Z14 S912_GPIOZ14(14) 400#define S912_SPDIF_Z14_IN_FN (2u) 401