1208599Srdivacky// Copyright 2018 The Fuchsia Authors. All rights reserved. 2208599Srdivacky// Use of this source code is governed by a BSD-style license that can be 3208599Srdivacky// found in the LICENSE file. 4208599Srdivacky 5208599Srdivacky#pragma once 6208599Srdivacky 7208599Srdivacky#define AIU_958_BPF ((uint32_t)(0x00)) 8208599Srdivacky#define AIU_958_BRST ((uint32_t)(0x01)) 9208599Srdivacky#define AIU_958_LENGTH ((uint32_t)(0x02)) 10208599Srdivacky#define AIU_958_PADDSIZE ((uint32_t)(0x03)) 11208599Srdivacky#define AIU_958_MISC ((uint32_t)(0x04)) 12208599Srdivacky#define AIU_958_FORCE_LEFT ((uint32_t)(0x05)) 13208599Srdivacky#define AIU_958_DISCARD_NUM ((uint32_t)(0x06)) 14208599Srdivacky#define AIU_958_DCU_FF_CTRL ((uint32_t)(0x07)) 15208599Srdivacky#define AIU_958_CHSTAT_L0 ((uint32_t)(0x08)) 16208599Srdivacky#define AIU_958_CHSTAT_L1 ((uint32_t)(0x09)) 17208599Srdivacky#define AIU_958_CTRL ((uint32_t)(0x0A)) 18208599Srdivacky#define AIU_958_RPT ((uint32_t)(0x0B)) 19208599Srdivacky#define AIU_I2S_MUTE_SWAP ((uint32_t)(0x0C)) 20208599Srdivacky#define AIU_I2S_SOURCE_DESC ((uint32_t)(0x0D)) 21208599Srdivacky#define AIU_I2S_MED_CTRL ((uint32_t)(0x0E)) 22208599Srdivacky#define AIU_I2S_MED_THRESH ((uint32_t)(0x0F)) 23208599Srdivacky#define AIU_I2S_DAC_CFG ((uint32_t)(0x10)) 24208599Srdivacky#define AIU_I2S_MISC ((uint32_t)(0x12)) 25208599Srdivacky#define AIU_I2S_OUT_CFG ((uint32_t)(0x13)) 26208599Srdivacky#define AIU_RST_SOFT ((uint32_t)(0x15)) 27208599Srdivacky#define AIU_CLK_CTRL ((uint32_t)(0x16)) 28208599Srdivacky#define AIU_MIX_ADCCFG ((uint32_t)(0x17)) 29208599Srdivacky#define AIU_MIX_CTRL ((uint32_t)(0x18)) 30208599Srdivacky#define AIU_CLK_CTRL_MORE ((uint32_t)(0x19)) 31208599Srdivacky#define AIU_958_POP ((uint32_t)(0x1A)) 32208599Srdivacky#define AIU_MIX_GAIN ((uint32_t)(0x1B)) 33208599Srdivacky#define AIU_958_SYNWORD1 ((uint32_t)(0x1C)) 34208599Srdivacky#define AIU_958_SYNWORD2 ((uint32_t)(0x1D)) 35208599Srdivacky#define AIU_958_SYNWORD3 ((uint32_t)(0x1E)) 36208599Srdivacky#define AIU_958_SYNWORD1_MASK ((uint32_t)(0x1F)) 37218893Sdim#define AIU_958_SYNWORD2_MASK ((uint32_t)(0x20)) 38208599Srdivacky#define AIU_958_SYNWORD3_MASK ((uint32_t)(0x21)) 39208599Srdivacky#define AIU_958_FFRDOUT_THD ((uint32_t)(0x22)) 40218893Sdim#define AIU_958_LENGTH_PER_PAUSE ((uint32_t)(0x23)) 41218893Sdim#define AIU_958_PAUSE_NUM ((uint32_t)(0x24)) 42208599Srdivacky#define AIU_958_PAUSE_PAYLOAD ((uint32_t)(0x25)) 43208599Srdivacky#define AIU_958_AUTO_PAUSE ((uint32_t)(0x26)) 44208599Srdivacky#define AIU_958_PAUSE_PD_LENGTH ((uint32_t)(0x27)) 45208599Srdivacky#define AIU_CODEC_DAC_LRCLK_CTRL ((uint32_t)(0x28)) 46208599Srdivacky#define AIU_CODEC_ADC_LRCLK_CTRL ((uint32_t)(0x29)) 47#define AIU_HDMI_CLK_DATA_CTRL ((uint32_t)(0x2a)) 48#define AIU_CODEC_CLK_DATA_CTRL ((uint32_t)(0x2b)) 49#define AIU_958_CHSTAT_R0 ((uint32_t)(0x30)) 50#define AIU_958_CHSTAT_R1 ((uint32_t)(0x31)) 51#define AIU_958_VALID_CTRL ((uint32_t)(0x32)) 52#define AIU_AIFIFO2_CTRL ((uint32_t)(0x40)) 53#define AIU_AIFIFO2_STATUS ((uint32_t)(0x41)) 54#define AIU_AIFIFO2_GBIT ((uint32_t)(0x42)) 55#define AIU_AIFIFO2_CLB ((uint32_t)(0x43)) 56#define AIU_CRC_CTRL ((uint32_t)(0x44)) 57#define AIU_CRC_STATUS ((uint32_t)(0x45)) 58#define AIU_CRC_SHIFT_REG ((uint32_t)(0x46)) 59#define AIU_CRC_IREG ((uint32_t)(0x47)) 60#define AIU_CRC_CAL_REG1 ((uint32_t)(0x48)) 61#define AIU_CRC_CAL_REG0 ((uint32_t)(0x49)) 62#define AIU_CRC_POLY_COEF1 ((uint32_t)(0x4a)) 63#define AIU_CRC_POLY_COEF0 ((uint32_t)(0x4b)) 64#define AIU_CRC_BIT_SIZE1 ((uint32_t)(0x4c)) 65#define AIU_CRC_BIT_SIZE0 ((uint32_t)(0x4d)) 66#define AIU_CRC_BIT_CNT1 ((uint32_t)(0x4e)) 67#define AIU_CRC_BIT_CNT0 ((uint32_t)(0x4f)) 68#define AIU_AMCLK_GATE_HI ((uint32_t)(0x50)) 69#define AIU_AMCLK_GATE_LO ((uint32_t)(0x51)) 70#define AIU_AMCLK_MSR ((uint32_t)(0x52)) 71#define AIU_MEM_I2S_START_PTR ((uint32_t)(0x60)) 72#define AIU_MEM_I2S_RD_PTR ((uint32_t)(0x61)) 73#define AIU_MEM_I2S_END_PTR ((uint32_t)(0x62)) 74#define AIU_MEM_I2S_MASKS ((uint32_t)(0x63)) 75#define AIU_MEM_I2S_CONTROL ((uint32_t)(0x64)) 76#define AIU_MEM_IEC958_START_PTR ((uint32_t)(0x65)) 77#define AIU_MEM_IEC958_RD_PTR ((uint32_t)(0x66)) 78#define AIU_MEM_IEC958_END_PTR ((uint32_t)(0x67)) 79#define AIU_MEM_IEC958_MASKS ((uint32_t)(0x68)) 80#define AIU_MEM_IEC958_CONTROL ((uint32_t)(0x69)) 81#define AIU_MEM_AIFIFO2_START_PTR ((uint32_t)(0x6a)) 82#define AIU_MEM_AIFIFO2_CURR_PTR ((uint32_t)(0x6b)) 83#define AIU_MEM_AIFIFO2_END_PTR ((uint32_t)(0x6c)) 84#define AIU_MEM_AIFIFO2_BYTES_AVAIL ((uint32_t)(0x6d)) 85#define AIU_MEM_AIFIFO2_CONTROL ((uint32_t)(0x6e)) 86#define AIU_MEM_AIFIFO2_MAN_WP ((uint32_t)(0x6f)) 87#define AIU_MEM_AIFIFO2_MAN_RP ((uint32_t)(0x70)) 88#define AIU_MEM_AIFIFO2_LEVEL ((uint32_t)(0x71)) 89#define AIU_MEM_AIFIFO2_BUF_CNTL ((uint32_t)(0x72)) 90#define AIU_MEM_I2S_MAN_WP ((uint32_t)(0x73)) 91#define AIU_MEM_I2S_MAN_RP ((uint32_t)(0x74)) 92#define AIU_MEM_I2S_LEVEL ((uint32_t)(0x75)) 93#define AIU_MEM_I2S_BUF_CNTL ((uint32_t)(0x76)) 94#define AIU_MEM_I2S_BUF_WRAP_COUNT ((uint32_t)(0x77)) 95#define AIU_MEM_I2S_MEM_CTL ((uint32_t)(0x78)) 96#define AIU_MEM_IEC958_MEM_CTL ((uint32_t)(0x79)) 97#define AIU_MEM_IEC958_WRAP_COUNT ((uint32_t)(0x7a)) 98#define AIU_MEM_IEC958_IRQ_LEVEL ((uint32_t)(0x7b)) 99#define AIU_MEM_IEC958_MAN_WP ((uint32_t)(0x7c)) 100#define AIU_MEM_IEC958_MAN_RP ((uint32_t)(0x7d)) 101#define AIU_MEM_IEC958_LEVEL ((uint32_t)(0x7e)) 102#define AIU_MEM_IEC958_BUF_CNTL ((uint32_t)(0x7f)) 103#define AIU_AIFIFO_CTRL ((uint32_t)(0x80)) 104#define AIU_AIFIFO_STATUS ((uint32_t)(0x81)) 105#define AIU_AIFIFO_GBIT ((uint32_t)(0x82)) 106#define AIU_AIFIFO_CLB ((uint32_t)(0x83)) 107#define AIU_MEM_AIFIFO_START_PTR ((uint32_t)(0x84)) 108#define AIU_MEM_AIFIFO_CURR_PTR ((uint32_t)(0x85)) 109#define AIU_MEM_AIFIFO_END_PTR ((uint32_t)(0x86)) 110#define AIU_MEM_AIFIFO_BYTES_AVAIL ((uint32_t)(0x87)) 111#define AIU_MEM_AIFIFO_CONTROL ((uint32_t)(0x88)) 112#define AIU_MEM_AIFIFO_MAN_WP ((uint32_t)(0x89)) 113#define AIU_MEM_AIFIFO_MAN_RP ((uint32_t)(0x8a)) 114#define AIU_MEM_AIFIFO_LEVEL ((uint32_t)(0x8b)) 115#define AIU_MEM_AIFIFO_BUF_CNTL ((uint32_t)(0x8c)) 116#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT ((uint32_t)(0x8d)) 117#define AIU_MEM_AIFIFO2_BUF_WRAP_COUNT ((uint32_t)(0x8e)) 118#define AIU_MEM_AIFIFO_MEM_CTL ((uint32_t)(0x8f)) 119#define AIU_AIFIFO_TIME_STAMP_CNTL ((uint32_t)(0x90)) 120#define AIU_AIFIFO_TIME_STAMP_SYNC_0 ((uint32_t)(0x91)) 121#define AIU_AIFIFO_TIME_STAMP_SYNC_1 ((uint32_t)(0x92)) 122#define AIU_AIFIFO_TIME_STAMP_0 ((uint32_t)(0x93)) 123#define AIU_AIFIFO_TIME_STAMP_1 ((uint32_t)(0x94)) 124#define AIU_AIFIFO_TIME_STAMP_2 ((uint32_t)(0x95)) 125#define AIU_AIFIFO_TIME_STAMP_3 ((uint32_t)(0x96)) 126#define AIU_AIFIFO_TIME_STAMP_LENGTH ((uint32_t)(0x97)) 127#define AIU_AIFIFO2_TIME_STAMP_CNTL ((uint32_t)(0x98)) 128#define AIU_AIFIFO2_TIME_STAMP_SYNC_0 ((uint32_t)(0x99)) 129#define AIU_AIFIFO2_TIME_STAMP_SYNC_1 ((uint32_t)(0x9a)) 130#define AIU_AIFIFO2_TIME_STAMP_0 ((uint32_t)(0x9b)) 131#define AIU_AIFIFO2_TIME_STAMP_1 ((uint32_t)(0x9c)) 132#define AIU_AIFIFO2_TIME_STAMP_2 ((uint32_t)(0x9d)) 133#define AIU_AIFIFO2_TIME_STAMP_3 ((uint32_t)(0x9e)) 134#define AIU_AIFIFO2_TIME_STAMP_LENGTH ((uint32_t)(0x9f)) 135#define AIU_IEC958_TIME_STAMP_CNTL ((uint32_t)(0xa0)) 136#define AIU_IEC958_TIME_STAMP_SYNC_0 ((uint32_t)(0xa1)) 137#define AIU_IEC958_TIME_STAMP_SYNC_1 ((uint32_t)(0xa2)) 138#define AIU_IEC958_TIME_STAMP_0 ((uint32_t)(0xa3)) 139#define AIU_IEC958_TIME_STAMP_1 ((uint32_t)(0xa4)) 140#define AIU_IEC958_TIME_STAMP_2 ((uint32_t)(0xa5)) 141#define AIU_IEC958_TIME_STAMP_3 ((uint32_t)(0xa6)) 142#define AIU_IEC958_TIME_STAMP_LENGTH ((uint32_t)(0xa7)) 143#define AIU_MEM_AIFIFO2_MEM_CTL ((uint32_t)(0xa8)) 144#define AIU_I2S_CBUS_DDR_CNTL ((uint32_t)(0xa9)) 145#define AIU_I2S_CBUS_DDR_WDATA ((uint32_t)(0xaa)) 146#define AIU_I2S_CBUS_DDR_ADDR ((uint32_t)(0xab)) 147 148#define AIU_REG_MASK(bits) ((uint32_t)((1u << (bits)) - 1)) 149 150// Bitfield defs for the IEC958 Misc reg (0x04) 151#define AIU_958_MISC_NON_PCM ((uint32_t)(1u << 0)) 152#define AIU_958_MISC_16BIT ((uint32_t)(1u << 1)) 153#define AIU_958_MISC_INVERT_MSB ((uint32_t)(1u << 2)) 154#define AIU_958_MISC_EXTEND_MSB ((uint32_t)(1u << 3)) 155#define AIU_958_MISC_TX_MSB_FIRST ((uint32_t)(1u << 4)) 156#define AIU_958_MISC_16BIT_ALIGN_MASK AIU_REG_MASK(2) 157#define AIU_958_MISC_16BIT_ALIGN_SHIFT ((uint32_t)(5u)) 158#define AIU_958_MISC_32BIT_MODE ((uint32_t)(1u << 7)) 159#define AIU_958_MISC_32BIT_SHIFT_MASK AIU_REG_MASK(3) 160#define AIU_958_MISC_32BIT_SHIFT_SHIFT ((uint32_t)8u) 161#define AIU_958_MISC_BIG_ENDIAN ((uint32_t)(1u << 11)) 162#define AIU_958_MISC_STREAM_USER_DATA ((uint32_t)(1u << 12)) 163#define AIU_958_MISC_FORCE_LR ((uint32_t)(1u << 13)) 164#define AIU_958_MISC_PCM_SAMP_CTRL_MASK AIU_REG_MASK(2) 165#define AIU_958_MISC_PCM_SAMP_CTRL_SHIFT ((uint32_t)14u) 166 167// Constants for the Misc alignment field. 168// RIGHT: 16 bit samples are transmitted as (00000000b | Sample) 169// CENTER: 16 bit samples are transmitted as (0000b | Sample | 0000b) 170// LEFT: 16 bit samples are transmitted as (Sample | 00000000b) 171#define AIU_958_MISC_16BIT_ALIGN_RIGHT ((uint32_t)0x00) 172#define AIU_958_MISC_16BIT_ALIGN_CENTER ((uint32_t)0x01) 173#define AIU_958_MISC_16BIT_ALIGN_LEFT ((uint32_t)0x02) 174 175// Constants for the Misc PCM sample control field. 176#define AIU_958_MISC_PCM_SAMP_CTRL_NO_SAMPLE ((uint32_t)0x00) 177#define AIU_958_MISC_PCM_SAMP_CTRL_UP ((uint32_t)0x01) 178#define AIU_958_MISC_PCM_SAMP_CTRL_DOWN ((uint32_t)0x02) 179#define AIU_958_MISC_PCM_SAMP_CTRL_DOWN_DROP ((uint32_t)0x03) 180 181// Bitfield defs for the IEC958 FIFO control reg (0x07) 182#define AIU_958_DCU_FF_CTRL_ENB ((uint32_t)(1u << 0)) 183#define AIU_958_DCU_FF_CTRL_AUTO_DISABLE ((uint32_t)(1u << 1)) 184#define AIU_958_DCU_FF_CTRL_IRQ_MODE_MASK AIU_REG_MASK(2u) 185#define AIU_958_DCU_FF_CTRL_IRQ_MODE_SHIFT ((uint32_t)2u) 186#define AIU_958_DCU_FF_CTRL_SYNC_HEAD_SEEK_ENB ((uint32_t)(1u << 4)) 187#define AIU_958_DCU_FF_CTRL_BYTE_SEEK_ENB ((uint32_t)(1u << 5)) 188#define AIU_958_DCU_FF_CTRL_CONT_SEEK ((uint32_t)(1u << 6)) 189#define AIU_958_DCU_FF_CTRL_8BIT ((uint32_t)(1u << 7)) 190#define AIU_958_DCU_FF_CTRL_FIFO_CNT_MASK AIU_REG_MASK(8u) 191#define AIU_958_DCU_FF_CTRL_FIFO_CNT_SHIFT ((uint32_t)8u) 192 193// Bitfield defs for the IEC958 control reg (0x0A) 194#define AIU_958_CTRL_HOLD_INTERFACE ((uint32_t)(1u << 0)) 195#define AIU_958_CTRL_SWAP_CHAN_MASK AIU_REG_MASK(2u) 196#define AIU_958_CTRL_SWAP_CHAN_SHIFT ((uint32_t)1u) 197#define AIU_958_CTRL_MUTE_RIGHT ((uint32_t)(1u << 3)) 198#define AIU_958_CTRL_MUTE_LEFT ((uint32_t)(1u << 4)) 199#define AIU_958_CTRL_MUTE_CONSTANT_MASK AIU_REG_MASK(3u) 200#define AIU_958_CTRL_MUTE_CONSTANT_SHIFT ((uint32_t)5u) 201#define AIU_958_CTRL_FUB_MASK AIU_REG_MASK(2u) 202#define AIU_958_CTRL_FUB_SHIFT ((uint32_t)8u) 203 204// Constants for the MUTE_CONSTANT field of the 958_CTRL register 205// ZERO: 0x000000 206// 24BIT_UZERO: 0x800000 207// 20BIT_UZERO: 0x080000 208// 16BIT_UZERO: 0x008000 209// 24BIT_ONE: 0x000001 210// 20BIT_ONE: 0x000010 211// 16BIT_ONE: 0x000100 212#define AIU_958_CTRL_MC_ZERO ((uint32_t)0u) 213#define AIU_958_CTRL_MC_24BIT_UZERO ((uint32_t)1u) 214#define AIU_958_CTRL_MC_20BIT_UZERO ((uint32_t)2u) 215#define AIU_958_CTRL_MC_16BIT_UZERO ((uint32_t)3u) 216#define AIU_958_CTRL_MC_24BIT_ONE ((uint32_t)4u) 217#define AIU_958_CTRL_MC_20BIT_ONE ((uint32_t)5u) 218#define AIU_958_CTRL_MC_16BIT_ONE ((uint32_t)6u) 219 220// Constants for the FIFO underrun behavior (FUB) field of the 958_CTRL register 221// ZERO : fill with 0x000000 222// MUTE_CONSTANT : fill with the selected mute constant 223// REPEAT_LAST : repeat the last LR frame 224#define AIU_958_CTRL_FUB_ZERO ((uint32_t)0u) 225#define AIU_958_CTRL_FUB_MUTE_CONSTANT ((uint32_t)1u) 226#define AIU_958_CTRL_FUB_REPEAT_LAST ((uint32_t)2u) 227 228// Bitfield defs for RST_SOFT (0x15) 229#define AIU_RS_I2S_FAST_DOMAIN ((uint32_t)(1u << 0)) 230#define AIU_RS_I2S_SLOW_DOMAIN ((uint32_t)(1u << 1)) 231#define AIU_RS_958_FAST_DOMAIN ((uint32_t)(1u << 2)) 232#define AIU_RS_958_SLOW_DOMAIN ((uint32_t)(1u << 3)) 233 234// Bitfield defs for CLK_CTRL (0x16) 235#define AIU_CLK_CTRL_ENB_I2S_DIV ((uint32_t)(1u << 0)) 236#define AIU_CLK_CTRL_ENB_958_DIV ((uint32_t)(1u << 1)) 237#define AIU_CLK_CTRL_I2S_DIV_MASK AIU_REG_MASK(2u) 238#define AIU_CLK_CTRL_I2S_DIV_SHIFT ((uint32_t)2u) 239#define AIU_CLK_CTRL_958_DIV_MASK AIU_REG_MASK(2u) 240#define AIU_CLK_CTRL_958_DIV_SHIFT ((uint32_t)4u) 241#define AIU_CLK_CTRL_INV_AO_CLK ((uint32_t)(1u << 6)) 242#define AIU_CLK_CTRL_INV_ALR_CLK ((uint32_t)(1u << 7)) 243#define AIU_CLK_CTRL_ALR_SKEW_MASK AIU_REG_MASK(2u) 244#define AIU_CLK_CTRL_ALR_SKEW_SHIFT ((uint32_t)8u) 245#define AIU_CLK_CTRL_CLK_SOURCE_SEL ((uint32_t)(1u << 10)) 246#define AIU_CLK_CTRL_AMCLK_OUT_DIV ((uint32_t)(1u << 11)) 247#define AIU_CLK_CTRL_958_DIV_MORE ((uint32_t)(1u << 12)) 248#define AIU_CLK_CTRL_958_DIV_MORE ((uint32_t)(1u << 12)) 249#define AIU_CLK_CTRL_PA_ADDR_SEL_MASK AIU_REG_MASK(2u) 250#define AIU_CLK_CTRL_PA_ADDR_SEL_SHIFT ((uint32_t)13u) 251#define AIU_CLK_CTRL_ENB_DDR_ARB ((uint32_t)(1u << 15)) 252 253// Constants for the ALR Clk skew field 254// SAME_TIME: ALR clk transitions as the MSB is sent 255// BEFORE: ALR clk transitions 1 cycle before the MSB is sent 256// AFTER: ALR clk transitions 1 cycle after the MSB is sent 257#define AIU_CLK_CTRL_ALR_SKEW_SAME_TIME ((uint32_t)0x00) 258#define AIU_CLK_CTRL_ALR_SKEW_BEFORE ((uint32_t)0x01) 259#define AIU_CLK_CTRL_ALR_SKEW_AFTER ((uint32_t)0x02) 260 261// Constants for the Parser-A Addr Select field 262#define AIU_CLK_CTRL_PAAS_AFIFO2 ((uint32_t)0x00) 263#define AIU_CLK_CTRL_PAAS_IEC958 ((uint32_t)0x01) 264#define AIU_CLK_CTRL_PAAS_AFIFO ((uint32_t)0x02) 265#define AIU_CLK_CTRL_PAAS_I2S ((uint32_t)0x03) 266 267// Bitfield defs for the Valid register (0x32) 268#define AIU_958_VCTRL_VBIT ((uint32_t)(1u << 0)) 269#define AIU_958_VCTRL_SEND_VBIT ((uint32_t)(1u << 1)) 270 271// Bitfield defs for the IEC958 Masks reg (0x68) 272#define AIU_MEM_IEC958_MASKS_CHAN_RD_MASK AIU_REG_MASK(8) 273#define AIU_MEM_IEC958_MASKS_CHAN_RD_SHIFT ((uint32_t)0u) 274#define AIU_MEM_IEC958_MASKS_CHAN_MEM_MASK AIU_REG_MASK(8) 275#define AIU_MEM_IEC958_MASKS_CHAN_MEM_SHIFT ((uint32_t)8u) 276 277// Bitfield defs for the IEC958 Mem Control reg (0x69) 278#define AIU_958_MCTRL_INIT ((uint32_t)(1u << 0)) 279#define AIU_958_MCTRL_FILL_ENB ((uint32_t)(1u << 1)) 280#define AIU_958_MCTRL_EMPTY_ENB ((uint32_t)(1u << 2)) 281#define AIU_958_MCTRL_ENDIAN_MASK AIU_REG_MASK(3) 282#define AIU_958_MCTRL_ENDIAN_SHIFT ((uint32_t)3u) 283#define AIU_958_MCTRL_RD_DDR ((uint32_t)(1u << 6)) 284#define AIU_958_MCTRL_16BIT_MODE ((uint32_t)(1u << 7)) 285#define AIU_958_MCTRL_LINEAR_RAW ((uint32_t)(1u << 8)) 286#define AIU_958_MCTRL_ENDIAN_JIC ((uint32_t)(1u << 9)) 287#define AIU_958_MCTRL_FETCHING_DDR ((uint32_t)(1u << 10)) 288#define AIU_958_MCTRL_FIFO_HAS_DATA ((uint32_t)(1u << 11)) 289#define AIU_958_MCTRL_USE_LEVEL ((uint32_t)(1u << 12)) 290#define AIU_958_MCTRL_SIM_ENB ((uint32_t)(1u << 13)) 291#define AIU_958_MCTRL_RD_DATA_BASE_BEGIN_MASK AIU_REG_MASK(4) 292#define AIU_958_MCTRL_RD_DATA_BASE_BEGIN_SHIFT ((uint32_t)24u) 293#define AIU_958_MCTRL_CH_ALWAYS_8 ((uint32_t)(1u << 30)) 294#define AIU_958_MCTRL_A_URGENT ((uint32_t)(1u << 31)) 295 296// Bitfield defs for the IEC958 Buf Control reg (0x7f) 297#define AIU_958_BCTRL_LEVEL_HOLD_MASK AIU_REG_MASK(16) 298#define AIU_958_BCTRL_LEVEL_HOLD_SHIFT ((uint32_t)0u) 299#define AIU_958_BCTRL_A_ID_MASK AIU_REG_MASK(6) 300#define AIU_958_BCTRL_A_ID_SHIFT ((uint32_t)16u) 301#define AIU_958_BCTRL_A_BRST_NUM_MASK AIU_REG_MASK(6) 302#define AIU_958_BCTRL_A_BRST_NUM_SHIFT ((uint32_t)22u) 303 304// Flags that can be set in the low 32 bits a SPDIF channel status word. Note, 305// these do not have anything specific to do with AmLogic audio units, but it is 306// as good a place as any to put some definitions. 307// 308// See 309// https://en.wikipedia.org/wiki/S/PDIF 310// http://www.av-iq.com/avcat/images/documents/pdfs/digaudiochannelstatusbits.pdf 311// http://www.minidisc.org/spdif_c_channel.html 312// https://hackaday.io/project/24911-propeller-spdif-receiver/details 313// For some publicly available details about the meaning of these bits 314// 315#define SPDIF_CS_SPDIF_CONSUMER ((uint32_t)(0u << 0)) 316#define SPDIF_CS_AES_PRO ((uint32_t)(1u << 0)) 317#define SPDIF_CS_AUD_DATA_PCM ((uint32_t)(0u << 1)) 318#define SPDIF_CS_AUD_DATA_NON_PCM ((uint32_t)(1u << 1)) 319#define SPDIF_CS_COPY_DENIED ((uint32_t)(0u << 2)) 320#define SPDIF_CS_COPY_PERMITTED ((uint32_t)(1u << 2)) 321#define SPDIF_CS_NO_PRE_EMPHASIS ((uint32_t)(0u << 3)) 322#define SPDIF_CS_PRE_EMPHASIS ((uint32_t)(1u << 3)) 323#define SPDIF_CS_CHAN_MODE_0 ((uint32_t)(0u << 6)) 324#define SPDIF_CS_CCODE(g, c) ((uint32_t)(((g & 0x7) << 8) | ((c & 0xf) << 11))) 325#define SPDIF_CS_L_BIT ((uint32_t)(1u << 15)) 326#define SPDIF_CS_SRC_NUM(N) ((uint32_t)((N & 0xf) << 16)) 327#define SPDIF_CS_CHAN_NUM(N) ((uint32_t)((N & 0xf) << 20)) 328#define SPDIF_CS_SAMP_FREQ_IGNORE ((uint32_t)(0x1 << 24)) 329#define SPDIF_CS_SAMP_FREQ_22_05K ((uint32_t)(0x4 << 24)) 330#define SPDIF_CS_SAMP_FREQ_44_1K ((uint32_t)(0x0 << 24)) 331#define SPDIF_CS_SAMP_FREQ_88_2K ((uint32_t)(0x8 << 24)) 332#define SPDIF_CS_SAMP_FREQ_176_4K ((uint32_t)(0xC << 24)) 333#define SPDIF_CS_SAMP_FREQ_24K ((uint32_t)(0x6 << 24)) 334#define SPDIF_CS_SAMP_FREQ_32K ((uint32_t)(0x3 << 24)) 335#define SPDIF_CS_SAMP_FREQ_48K ((uint32_t)(0x2 << 24)) 336#define SPDIF_CS_SAMP_FREQ_96K ((uint32_t)(0xA << 24)) 337#define SPDIF_CS_SAMP_FREQ_192K ((uint32_t)(0xE << 24)) 338#define SPDIF_CS_CLK_ACC_100PPM ((uint32_t)(0 << 28)) 339#define SPDIF_CS_CLK_ACC_VARIABLE ((uint32_t)(1 << 28)) 340#define SPDIF_CS_CLK_ACC_50PPM ((uint32_t)(2 << 28)) 341 342#define SPDIF_CS_CCODE_GENERAL SPDIF_CS_CCODE(0, 0) 343#define SPDIF_CS_CCODE_SOLID_STATE_RECORDER SPDIF_CS_CCODE(0, 1) 344#define SPDIF_CS_CCODE_EXPERIMENTAL SPDIF_CS_CCODE(0, 8) 345 346#define SPDIF_CS_CCODE_CD SPDIF_CS_CCODE(1, 0) 347#define SPDIF_CS_CCODE_LASERDISC SPDIF_CS_CCODE(1, 1) 348#define SPDIF_CS_CCODE_MINIDISC SPDIF_CS_CCODE(1, 3) 349#define SPDIF_CS_CCODE_DVD SPDIF_CS_CCODE(1, 9) 350 351#define SPDIF_CS_CCODE_PCM_CODEC SPDIF_CS_CCODE(2, 0) 352#define SPDIF_CS_CCODE_DIGITAL_SAMPLER SPDIF_CS_CCODE(2, 2) 353#define SPDIF_CS_CCODE_DIGITAL_MIXER SPDIF_CS_CCODE(2, 3) 354#define SPDIF_CS_CCODE_DIGITAL_PROCESSOR SPDIF_CS_CCODE(2, 4) 355#define SPDIF_CS_CCODE_SAMPLE_RATE_CONVERTER SPDIF_CS_CCODE(2, 5) 356 357#define SPDIF_CS_CCODE_DAT SPDIF_CS_CCODE(3, 0) 358#define SPDIF_CS_CCODE_DCC SPDIF_CS_CCODE(3, 1) 359#define SPDIF_CS_CCODE_VCR SPDIF_CS_CCODE(3, 8) 360 361#define SPDIF_CS_CCODE_DBR_JAPAN SPDIF_CS_CCODE(4, 0) 362#define SPDIF_CS_CCODE_SW_DELIVERY_INTF SPDIF_CS_CCODE(4, 1) 363#define SPDIF_CS_CCODE_DBR_USA SPDIF_CS_CCODE(4, 8) 364#define SPDIF_CS_CCODE_DBR_EUROPE SPDIF_CS_CCODE(4, 12) 365 366#define SPDIF_CS_CCODE_SYNTHESIZER SPDIF_CS_CCODE(5, 0) 367#define SPDIF_CS_CCODE_MICROPHONE SPDIF_CS_CCODE(5, 1) 368 369#define SPDIF_CS_CCODE_A2D_CONVERTER SPDIF_CS_CCODE(6, 0) 370#define SPDIF_CS_CCODE_A2D_CONVERTER_WITH_SCMS SPDIF_CS_CCODE(6, 2) 371 372