1// Copyright 2018 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5typedef enum axg_clk_gate_idx {
6    // MPEG0 Reg Clocks
7    CLK_AXG_DDR = 0,
8    CLK_AXG_AUDIO_LOCKER,
9    CLK_AXG_MIPI_DSI_HOST,
10    CLK_AXG_ISA,
11    CLK_AXG_PL301,
12    CLK_AXG_PERIPHS,
13    CLK_AXG_SPICC_0,
14    CLK_AXG_I2C,
15    CLK_AXG_RNG0,
16    CLK_AXG_UART0,
17    CLK_AXG_MIPI_DSI_PHY,
18    CLK_AXG_SPICC_1,
19    CLK_AXG_PCIE_A,
20    CLK_AXG_PCIE_B,
21    CLK_AXG_HIU_REG,
22    CLK_AXG_ASSIST_MISC,
23    CLK_AXG_EMMC_B,
24    CLK_AXG_EMMC_C,
25    CLK_AXG_DMA,
26    CLK_AXG_SPI,
27
28    // MPEG1 Reg Clocks
29    CLK_AXG_AUDIO,
30    CLK_AXG_ETH_CORE,
31    CLK_AXG_UART1,
32    CLK_AXG_G2D,
33    CLK_AXG_USB0,
34    CLK_AXG_USB1,
35    CLK_AXG_RESET,
36    CLK_AXG_USB_GENERAL,
37    CLK_AXG_AHB_ARB0,
38    CLK_AXG_EFUSE,
39    CLK_AXG_BOOT_ROM,
40
41    // MPEG2 Reg Clocks
42    CLK_AXG_AHB_DATA_BUS,
43    CLK_AXG_AHB_CTRL_BUS,
44    CLK_AXG_USB1_TO_DDR,
45    CLK_AXG_USB0_TO_DDR,
46    CLK_AXG_MMC_PCLK,
47    CLK_AXG_VPU_INTR,
48    CLK_AXG_SEC_AHB_AHB3_BRIDGE,
49    CLK_AXG_GIC,
50
51    // AO Domain Clocks
52    CLK_AXG_AO_MEDIA_CPU,
53    CLK_AXG_AO_AHB_SRAM,
54    CLK_AXG_AO_AHB_BUS,
55    CLK_AXG_AO_IFACE,
56    CLK_AXG_AO_I2C,
57
58    // Etc...
59    CLK_AXG_CLK81,
60    CLK_CML0_EN,
61
62    // NB: This must be the last entry
63    CLK_AXG_COUNT,
64} axg_clk_gate_idx_t;
65