1// Copyright 2018 The Fuchsia Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#define AML_NAME "aml-nand" 6 7#define P_NAND_CMD (0x00) 8#define P_NAND_CFG (0x04) 9#define P_NAND_DADR (0x08) 10#define P_NAND_IADR (0x0c) 11#define P_NAND_BUF (0x10) 12#define P_NAND_INFO (0x14) 13#define P_NAND_DC (0x18) 14#define P_NAND_ADR (0x1c) 15#define P_NAND_DL (0x20) 16#define P_NAND_DH (0x24) 17#define P_NAND_CADR (0x28) 18#define P_NAND_SADR (0x2c) 19#define P_NAND_PINS (0x30) 20#define P_NAND_VER (0x38) 21 22#define AML_CMD_DRD (0x8<<14) 23#define AML_CMD_IDLE (0xc<<14) 24#define AML_CMD_DWR (0x4<<14) 25#define AML_CMD_CLE (0x5<<14) 26#define AML_CMD_ALE (0x6<<14) 27#define AML_CMD_ADL ((0<<16) | (3<<20)) 28#define AML_CMD_ADH ((1<<16) | (3<<20)) 29#define AML_CMD_AIL ((2<<16) | (3<<20)) 30#define AML_CMD_AIH ((3<<16) | (3<<20)) 31#define AML_CMD_SEED ((8<<16) | (3<<20)) 32#define AML_CMD_M2N ((0<<17) | (2<<20)) 33#define AML_CMD_N2M ((1<<17) | (2<<20)) 34#define AML_CMD_RB (1<<20) 35#define AML_CMD_IO6 ((0xb<<10)|(1<<18)) 36 37#define NAND_TWB_TIME_CYCLE 10 38 39#define CMDRWGEN(cmd_dir, ran, bch, short, pagesize, pages) \ 40 ((cmd_dir) | (ran) << 19 | (bch) << 14 | \ 41 (short) << 13 | ((pagesize)&0x7f) << 6 | ((pages)&0x3f)) 42 43#define GENCMDDADDRL(adl, addr) \ 44 ((adl) | ((addr) & 0xffff)) 45#define GENCMDDADDRH(adh, addr) \ 46 ((adh) | (((addr) >> 16) & 0xffff)) 47 48#define GENCMDIADDRL(ail, addr) \ 49 ((ail) | ((addr) & 0xffff)) 50#define GENCMDIADDRH(aih, addr) \ 51 ((aih) | (((addr) >> 16) & 0xffff)) 52 53#define RB_STA(x) (1<<(26+x)) 54 55#define AML_ECC_UNCORRECTABLE_CNT 0x3f 56 57#define ECC_CHECK_RETURN_FF (-1) 58 59#define DMA_BUSY_TIMEOUT 0x100000 60 61#define CMD_FINISH_TIMEOUT_MS 1000 62 63#define MAX_CE_NUM 2 64 65#define RAN_ENABLE 1 66 67#define CLK_ALWAYS_ON (0x01 << 28) 68#define AML_CLK_CYCLE 6 69 70/* nand flash controller delay 3 ns */ 71#define AML_DEFAULT_DELAY 3000 72 73#define MAX_ECC_INDEX 10 74 75enum { 76 AML_ECC_NONE = 0, 77 /* bch8 with ecc page size of 512B */ 78 AML_ECC_BCH8, 79 /* bch8 with ecc page size of 1024B */ 80 AML_ECC_BCH8_1K, 81 AML_ECC_BCH24_1K, 82 AML_ECC_BCH30_1K, 83 AML_ECC_BCH40_1K, 84 AML_ECC_BCH50_1K, 85 AML_ECC_BCH60_1K, 86 87 /* 88 * Short mode is special only for page 0 when inplement booting 89 * from nand. it means that using a small size(384B/8=48B) of ecc page 90 * with a fixed ecc mode. rom code use short mode to read page0 for 91 * getting nand parameter such as ecc, scramber and so on. 92 * For gxl serial, first page adopt short mode and 60bit ecc; for axg 93 * serial, adopt short mode and 8bit ecc. 94 */ 95 AML_ECC_BCH_SHORT, 96}; 97 98#define AML_WRITE_PAGE_TIMEOUT 2 99#define AML_ERASE_BLOCK_TIMEOUT 400 100 101