1// Copyright 2018 The Fuchsia Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#pragma once 6 7__BEGIN_CDECLS 8 9// clang-format off 10 11//PDM control registers 12#define PDM_CTRL (0x00 << 2) 13#define PDM_HCIC_CTRL1 (0x01 << 2) 14#define PDM_HCIC_CTRL2 (0x02 << 2) 15#define PDM_F1_CTRL (0x03 << 2) 16#define PDM_F2_CTRL (0x04 << 2) 17#define PDM_F3_CTRL (0x05 << 2) 18#define PDM_HPF_CTRL (0x06 << 2) 19#define PDM_CHAN_CTRL (0x07 << 2) 20#define PDM_CHAN_CTRL1 (0x08 << 2) 21#define PDM_COEFF_ADDR (0x09 << 2) 22#define PDM_COEFF_DATA (0x0a << 2) 23#define PDM_CLKG_CTRL (0x0b << 2) 24#define PDM_STS (0x0c << 2) 25 26 27//Clock control registers 28#define EE_AUDIO_MCLK_ENA (1 << 31) 29 30#define EE_AUDIO_CLK_GATE_EN 0x0000 31#define EE_AUDIO_MCLK_A_CTRL 0x0004 32#define EE_AUDIO_MCLK_B_CTRL 0x0008 33#define EE_AUDIO_MCLK_C_CTRL 0x000C 34#define EE_AUDIO_MCLK_D_CTRL 0x0010 35#define EE_AUDIO_MCLK_E_CTRL 0x0014 36#define EE_AUDIO_MCLK_F_CTRL 0x0018 37 38#define EE_AUDIO_MST_A_SCLK_CTRL0 0x0040 39#define EE_AUDIO_MST_A_SCLK_CTRL1 0x0044 40#define EE_AUDIO_MST_B_SCLK_CTRL0 0x0048 41#define EE_AUDIO_MST_B_SCLK_CTRL1 0x004C 42#define EE_AUDIO_MST_C_SCLK_CTRL0 0x0050 43#define EE_AUDIO_MST_C_SCLK_CTRL1 0x0054 44#define EE_AUDIO_MST_D_SCLK_CTRL0 0x0058 45#define EE_AUDIO_MST_D_SCLK_CTRL1 0x005C 46#define EE_AUDIO_MST_E_SCLK_CTRL0 0x0060 47#define EE_AUDIO_MST_E_SCLK_CTRL1 0x0064 48#define EE_AUDIO_MST_F_SCLK_CTRL0 0x0068 49#define EE_AUDIO_MST_F_SCLK_CTRL1 0x006c 50 51#define EE_AUDIO_CLK_TDMOUT_A_CTL 0x0090 52#define EE_AUDIO_CLK_TDMOUT_B_CTL 0x0094 53#define EE_AUDIO_CLK_TDMOUT_C_CTL 0x0098 54 55#define EE_AUDIO_CLK_PDMIN_CTRL0 0x00ac 56#define EE_AUDIO_CLK_PDMIN_CTRL1 0x00b0 57 58//TODDR control reg blocks and offsets 59#define TODDR_CTRL0_OFFS (0x00) 60#define TODDR_CTRL1_OFFS (0x04) 61#define TODDR_START_ADDR_OFFS (0x08) 62#define TODDR_FINISH_ADDR_OFFS (0x0c) 63#define TODDR_INT_ADDR_OFFS (0x10) 64#define TODDR_STATUS1_OFFS (0x14) 65#define TODDR_STATUS2_OFFS (0x18) 66#define TODDR_START_ADDRB_OFFS (0x1c) 67#define TODDR_FINISH_ADDRB_OFFS (0x20) 68#define TODDR_INIT_ADDR_OFFS (0x24) 69 70 71//FRDDR control reg blocks and offsets 72#define FRDDR_CTRL0_OFFS (0x00) 73#define FRDDR_CTRL1_OFFS (0x04) 74#define FRDDR_START_ADDR_OFFS (0x08) 75#define FRDDR_FINISH_ADDR_OFFS (0x0c) 76#define FRDDR_INT_ADDR_OFFS (0x10) 77#define FRDDR_STATUS1_OFFS (0x14) 78#define FRDDR_STATUS2_OFFS (0x18) 79 80#define EE_AUDIO_TODDR_A_CTRL0 (0x40 << 2) 81#define EE_AUDIO_TODDR_B_CTRL0 (0x50 << 2) 82#define EE_AUDIO_TODDR_C_CTRL0 (0x60 << 2) 83#define EE_AUDIO_FRDDR_A_CTRL0 (0x70 << 2) 84#define EE_AUDIO_FRDDR_B_CTRL0 (0x80 << 2) 85#define EE_AUDIO_FRDDR_C_CTRL0 (0x90 << 2) 86 87#define EE_AUDIO_ARB_CTRL (0xa0 << 2) 88 89//TDMOUT control regs (common to three seperate units) 90#define TDMOUT_CTRL0_OFFS (0x00) 91#define TDMOUT_CTRL1_OFFS (0x04) 92#define TDMOUT_SWAP_OFFS (0x08) 93#define TDMOUT_MASK0_OFFS (0x0c) 94#define TDMOUT_MASK1_OFFS (0x10) 95#define TDMOUT_MASK2_OFFS (0x14) 96#define TDMOUT_MASK3_OFFS (0x18) 97#define TDMOUT_STAT_OFFS (0x1c) 98#define TDMOUT_GAIN0_OFFS (0x20) 99#define TDMOUT_GAIN1_OFFS (0x24) 100#define TDMOUT_MUTE_VAL_OFFS (0x28) 101#define TDMOUT_MUTE0_OFFS (0x2c) 102#define TDMOUT_MUTE1_OFFS (0x30) 103#define TDMOUT_MUTE2_OFFS (0x34) 104#define TDMOUT_MUTE3_OFFS (0x38) 105#define TDMOUT_MASK_VAL_OFFS (0x3c) 106 107#define EE_AUDIO_TDMOUT_A_CTRL0 (0x140 << 2) 108#define EE_AUDIO_TDMOUT_B_CTRL0 (0x150 << 2) 109#define EE_AUDIO_TDMOUT_C_CTRL0 (0x160 << 2) 110 111 112//Audio clock gating masks 113#define EE_AUDIO_CLK_GATE_ARB (1 << 0) 114#define EE_AUDIO_CLK_GATE_PDM (1 << 1) 115#define EE_AUDIO_CLK_GATE_TDMINA (1 << 2) 116#define EE_AUDIO_CLK_GATE_TDMINB (1 << 3) 117#define EE_AUDIO_CLK_GATE_TDMINC (1 << 4) 118#define EE_AUDIO_CLK_GATE_TDMOUTA (1 << 6) 119#define EE_AUDIO_CLK_GATE_TDMOUTB (1 << 7) 120#define EE_AUDIO_CLK_GATE_TDMOUTC (1 << 8) 121#define EE_AUDIO_CLK_GATE_FRDDRA (1 << 9) 122#define EE_AUDIO_CLK_GATE_FRDDRB (1 << 10) 123#define EE_AUDIO_CLK_GATE_FRDDRC (1 << 11) 124#define EE_AUDIO_CLK_GATE_TODDRA (1 << 12) 125#define EE_AUDIO_CLK_GATE_TODDRB (1 << 13) 126#define EE_AUDIO_CLK_GATE_TODDRC (1 << 14) 127 128 129 130typedef enum { 131 MP0_PLL = 0, 132 MP1_PLL = 1, 133 MP2_PLL = 2, 134 MP3_PLL = 3, 135 HIFI_PLL = 4, 136 FCLK_DIV3 = 5, 137 FCLK_DIV4 = 6, 138 GP0_PLL = 7 139} ee_audio_mclk_src_t; 140 141typedef enum { 142 MCLK_A = 0, 143 MCLK_B, 144 MCLK_C, 145 MCLK_D, 146 MCLK_E, 147 MCLK_F 148} aml_tdm_mclk_t; 149 150typedef enum { 151 TDM_OUT_A = 0, 152 TDM_OUT_B, 153 TDM_OUT_C 154} aml_tdm_out_t; 155 156typedef enum { 157 FRDDR_A = 0, 158 FRDDR_B, 159 FRDDR_C 160} aml_frddr_t; 161 162typedef enum { 163 TODDR_A = 0, 164 TODDR_B, 165 TODDR_C 166} aml_toddr_t; 167 168// clang-format on 169__END_CDECLS 170