1// Copyright 2016 The Fuchsia Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#pragma once 6 7// See: PCI/PCI-X Family of Gigabit Ethernet Controllers 8// Software Developer's Manual 9// 317453006EN.PDF 10// Revision 4.0 11 12#define IE_CTRL 0x0000 // Device Control 13#define IE_STATUS 0x0008 // Device Status 14#define IE_CTRL_EXT 0x0018 // Extended Device Control 15#define IE_MDIC 0x0020 // MDI control (PHY access) 16#define IE_TXCW 0x0178 // TX Config Word 17#define IE_RXCW 0x0180 // RX Config Word 18#define IE_ICR 0x00c0 // Interrupt Cause Read 19#define IE_ICS 0x00c8 // Interrupt Cause Set 20#define IE_IMS 0x00d0 // Interrupt Mask Set / Read 21#define IE_IMC 0x00d8 // Interrupt Mask Clear 22 23#define IE_RCTL 0x0100 // Receive Control 24#define IE_RDBAL 0x2800 // RX Descriptor Base Low 25#define IE_RDBAH 0x2804 // RX Descriptor Base High 26#define IE_RDLEN 0x2808 // RX Descriptor Length 27#define IE_RDH 0x2810 // RX Descriptor Head 28#define IE_RDT 0x2818 // RX Descriptor Tail 29#define IE_RDTR 0x3820 // RX Delay Timer 30 31#define IE_TCTL 0x0400 // Transmit Control 32#define IE_TIPG 0x0410 // TX IPG 33#define IE_TDBAL 0x3800 // TX Descriptor Base Low 34#define IE_TDBAH 0x3804 // TX Descriptor Base High 35#define IE_TDLEN 0x3808 // TX Descriptor Length 36#define IE_TDH 0x3810 // TX Descriptor Head 37#define IE_TDT 0x3818 // TX Descriptor Tail 38#define IE_TIDV 0x3820 // TX Interrupt Delay Value 39 40#define IE_TXDMAC 0x3000 // TX DMA Control 41#define IE_TXDCTL 0x3828 // TX Descriptor Control 42#define IE_RXDCTL 0x2828 // RX Descriptor Control 43 44#define IE_RXCSUM 0x5000 // RX Checksum Control 45#define IE_MTA(n) (0x5200 + ((n) * 4)) // RX Multicast Table Array [0:127] 46#define IE_RAL(n) (0x5400 + ((n) * 8)) // RX Address Low 47#define IE_RAH(n) (0x5404 + ((n) * 8)) // RX Address High 48 49 50#define IE_CTRL_FD (1u << 0) // Full Duplex 51#define IE_CTRL_LRST (1u << 3) // Link Reset (Halt TX and RX) 52#define IE_CTRL_ASDE (1u << 5) // Auto Speed Detect Enable 53#define IE_CTRL_SLU (1u << 6) // Set Link Up (ignored in ASDE mode) 54#define IE_CTRL_ILOS (1u << 7) // Invert Loss-of-Signal 55#define IE_CTRL_SPEED (3u << 8) 56#define IE_CTRL_10M (0u << 8) 57#define IE_CTRL_100M (1u << 8) 58#define IE_CTRL_1000M (2u << 8) 59#define IE_CTRL_FRCSPD (1u << 11) // Force Speed 60#define IE_CTRL_RST (1u << 26) // Device Reset (self-clearing after >1us) 61#define IE_CTRL_VME (1u << 30) // VLAN Mode Enable 62#define IE_CTRL_PHY_RST (1u << 31) // PHY Reset 63 64#define IE_STATUS_FD (1u << 0) // Full Duplex 65#define IE_STATUS_LU (1u << 1) // Link Up 66#define IE_STATUS_TXOFF (1u << 4) 67#define IE_STATUS_TBIMODE (1u << 5) 68#define IE_STATUS_SPEED (3u << 6) 69#define IE_STATUS_10M (0u << 6) 70#define IE_STATUS_100M (1u << 6) 71#define IE_STATUS_1000M (2u << 6) 72 73#define IE_MDIC_GET_DATA(val) ((val) & 0xffff) 74#define IE_MDIC_PUT_DATA(val) ((val) & 0xffff) 75#define IE_MDIC_GET_REGADD(val) (((val) >> 16) & 0x1f) 76#define IE_MDIC_PUT_REGADD(val) (((val) & 0x1f) << 16) 77#define IE_MDIC_GET_PHYADD(val) (((val) >> 21) & 0x1f) 78#define IE_MDIC_PUT_PHYADD(val) (((val) & 0x1f) << 21) 79#define IE_MDIC_OP_WRITE (1u << 26) 80#define IE_MDIC_OP_READ (2u << 26) 81#define IE_MDIC_R (1u << 28) // Ready 82#define IE_MDIC_I (1u << 29) // Interrupt enable 83#define IE_MDIC_E (1u << 30) // Error 84 85#define IE_INT_TXDW (1u << 0) // TX Descriptor Written Back 86#define IE_INT_TXQE (1u << 1) // TX Queue Empty 87#define IE_INT_LSC (1u << 2) // Link Status Change 88#define IE_INT_RXSEQ (1u << 3) // RX Sequence Error 89#define IE_INT_RXDMT0 (1u << 4) // RX Descriptor Min Threshold 90#define IE_INT_RXO (1u << 6) // RX FIFO Overrun 91#define IE_INT_RXT0 (1u << 7) // RX Timer 92#define IE_INT_MDAC (1u << 9) // MDIO Access Complete 93#define IE_INT_PHYINT (1u << 12 // PHY Interrupt 94 95#define IE_RCTL_RST (1u << 0) // RX Reset* 96#define IE_RCTL_EN (1u << 1) // RX Enable 97#define IE_RCTL_SBP (1u << 2) // Store Bad Packates 98#define IE_RCTL_UPE (1u << 3) // Unicast Promisc Enable 99#define IE_RCTL_MPE (1u << 4) // Multicast Promisc Enable 100#define IE_RCTL_LPE (1u << 5) // Long Packet RX Enable (>1522 bytes) 101#define IE_RCTL_LBM (3u << 6) // PHY/EXT Loopback 102#define IE_RCTL_RDMTS2 (0u << 8) // RX Desc Min Thres 1/2 RDLEN 103#define IE_RCTL_RDMTS4 (1u << 8) // RX Desc Min Thres 1/4 RDLEN 104#define IE_RCTL_RDMTS8 (2u << 8) // RX Desc Min Thres 1/8 RDLEN 105#define IE_RCTL_MO36 (0u << 12) // Multicast Filter Offset 36..47 106#define IE_RCTL_MO35 (1u << 12) // Multicast Filter Offset 35..46 107#define IE_RCTL_MO34 (2u << 12) // Multicast Filter Offset 34..45 108#define IE_RCTL_MO32 (3u << 12) // Multicast Filter Offset 32..43 109#define IE_RCTL_BAM (1u << 15) // RX Broadcast Packets Enable 110#define IE_RCTL_BSIZE2048 (0u << 16) // RX Buffer 2048 * (BSEX * 16) 111#define IE_RCTL_BSIZE1024 (1u << 16) // RX Buffer 1024 * (BSEX * 16) 112#define IE_RCTL_BSIZE512 (2u << 16) // RX Buffer 512 * (BSEX * 16) 113#define IE_RCTL_BSIZE256 (3u << 16) // RX Buffer 256 * (BSEX * 16) 114#define IE_RCTL_DPF (1u << 22) // Discard Pause Frames 115#define IE_RCTL_PMCF (1u << 23) // Pass MAC Control Frames 116#define IE_RCTL_BSEX (1u << 25) // Buffer Size Extension (x16) 117#define IE_RCTL_SECRC (1u << 26) // Strip CRC Field 118 119#define IE_TCTL_RESERVED ((1u << 2) | (1u << 23) | (0xfu << 25) | (1u << 31)) 120#define IE_TCTL_RST (1u << 0) // TX Reset? 121#define IE_TCTL_EN (1u << 1) // TX Enable 122#define IE_TCTL_PSP (1u << 3) // Pad Short Packets (to 64b) 123#define IE_TCTL_CT(n) ((n) << 4) // Collision Threshold (rec 15) 124#define IE_TCTL_COLD_HD (0x200u << 12) // Collision Distance Half Duplex 125#define IE_TCTL_COLD_FD (0x40u << 12) // Collision Distance Full Duplex 126#define IE_TCTL_SWXOFF (1u << 22) // XOFF TX (self-clearing) 127 128 129typedef struct ie_rxd { 130 uint64_t addr; 131 uint64_t info; 132} ie_rxd_t; 133 134#define IE_RXD_RXE (1ull << 47) // RX Data Error 135#define IE_RXD_IPE (1ull << 46) // IP Checksum Error 136#define IE_RXD_TCPE (1ull << 45) // TCP/UDP Checksum Error 137#define IE_RXD_CXE (1ull << 44) // Carrier Extension Error 138#define IE_RXD_SEQ (1ull << 42) // Sequence Error 139#define IE_RXD_SE (1ull << 41) // Symbol Error 140#define IE_RXD_CE (1ull << 40) // CRC Error or Alignment Error 141 142#define IE_RXD_PIF (1ull << 39) // Passed Inexact Filter 143#define IE_RXD_IPCS (1ull << 38) // IP Checksum Calculated 144#define IE_RXD_TCPCS (1ull << 37) // TCP Checksum Calculated 145#define IE_RXD_VP (1ull << 35) // 802.1Q / Matched VET 146#define IE_RXD_IXSM (1ull << 34) // Ignore IPCS and TCPCS bits 147#define IE_RXD_EOP (1ull << 33) // End of Packet (last desc) 148#define IE_RXD_DONE (1ull << 32) // Descriptor Done (hw is done) 149 150#define IE_RXD_CHK(n) (((n) >> 16) & 0xffff) 151#define IE_RXD_LEN(n) ((n) & 0xffff) 152 153#define IE_RXDCTL_PTHRESH(n) (((uint32_t)(n) & 0x1f) << 0) 154#define IE_RXDCTL_HTHRESH(n) (((uint32_t)(n) & 0x1f) << 8) 155#define IE_RXDCTL_WTHRESH(n) (((uint32_t)(n) & 0x1f) << 16) 156#define IE_RXDCTL_GRAN (1u << 24) 157#define IE_RXDCTL_ENABLE (1u << 25) 158 159typedef struct ie_txd { 160 uint64_t addr; 161 uint64_t info; 162} ie_txd_t; 163 164#define IE_TXD_TU (1ull << 35) // TX Underrun 165#define IE_TXD_LC (1ull << 34) // Late Collision 166#define IE_TXD_EC (1ull << 33) // Excess Collisions 167#define IE_TXD_DONE (1ull << 32) // Descriptor Done 168 169#define IE_TXD_IDE (1ull << 31) // Interrupt Delay Enable 170#define IE_TXD_VLE (1ull << 30) // VLAN Packet Enable 171#define IE_TXD_DEXT (1ull << 29) // Extension 172#define IE_TXD_RPS (1ull << 28) // Report Packet Send 173#define IE_TXD_RS (1ull << 27) // Report Status 174#define IE_TXD_IC (1ull << 26) // Insert Checksum 175#define IE_TXD_IFCS (1ull << 25) // Insert FCS/CRC 176#define IE_TXD_EOP (1ull << 24) // End Of Packet 177 178#define IE_TXD_CSS(n) ((((uint64_t)(n)) & 0xff) << 40) 179#define IE_TXD_CSO(n) ((((uint64_t)(n)) & 0xff) << 16) 180#define IE_TXD_LEN(n) (((uint64_t)(n)) & 0xffff) 181 182#define IE_TXDCTL_WTHRESH(n) (((uint32_t)(n) & 0x1f) << 16) 183#define IE_TXDCTL_GRAN (1u << 24) 184#define IE_TXDCTL_ENABLE (1u << 25) 185 186#define IE_MAX_PHY_ADDR 0x1f 187 188// PHY registers 189 190// PHY Control Register 191#define IE_PHY_PCTRL (0x00) 192#define IE_PHY_PCTRL_MASK ((1u << 6) | (1u << 13)) 193#define IE_PHY_PCTRL_SPEED_1000 ((1u << 6) | (0u << 13)) 194#define IE_PHY_PCTRL_SPEED_100 ((0u << 6) | (1u << 13)) 195#define IE_PHY_PCTRL_SPEED_10 ((0u << 6) | (0u << 13)) 196#define IE_PHY_PCTRL_EN_COLL_TEST (1u << 7) 197#define IE_PHY_PCTRL_FULL_DUPLEX (1u << 8) 198#define IE_PHY_PCTRL_RESTART_AUTONEG (1u << 9) 199#define IE_PHY_PCTRL_ISOLATE (1u << 10) 200#define IE_PHY_PCTRL_POWER_DOWN (1u << 11) 201#define IE_PHY_PCTRL_EN_AUTONEG (1u << 12) 202#define IE_PHY_PCTRL_EN_LOOPBACK (1u << 14) 203#define IE_PHY_PCTRL_RESET (1u << 15) 204 205// PHY Identifier Register (LSB) 206#define IE_PHY_PID (0x02) 207 208// I211 registers 209// Reference: Intel�� Ethernet Controller I211 Datasheet 210// June 2018 211// Revision Number: 3.3 212// Order No. 333017-006 213// 214// https://www.intel.com/content/www/us/en/embedded/products/networking/ethernet-controller-i210-i211-family-documentation.html 215// https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/i211-ethernet-controller-datasheet.pdf?asset=9567 216 217#define IE_IAM 0x00e0 // Interrupt Acknowledge Auto Mask Register 218#define IE_EEC 0x12010 // EEPROM/Flash Control 219 220#define IE_TCTL_BST(n) (((n) & 0x3ff) << 12) // Back-Off Slot Time. This value determines 221 // the back-off slot time value in byte time. 222#define IE_STATUS_PF_RST_DONE (1u << 21) // When set, indicates that software reset 223 // (CTRL.RST) or device reset (CTRL.DEV_RST) 224 // has completed and the software device 225 // driver can begin initialization process. 226#define IE_INT_RXDW (1u << 7) // Receiver Descriptor Write Back. Set when 227 // the I211 writes back an Rx descriptor to 228 // memory. 229#define IE_EEC_AUTO_RD (1u << 9) 230