1// Copyright 2017 The Fuchsia Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style license that can be 3// found in the LICENSE file. 4 5#pragma once 6 7#include <ddk/device.h> 8#include <ddk/io-buffer.h> 9#include <ddk/protocol/platform-device.h> 10#include <zircon/listnode.h> 11#include <zircon/types.h> 12#include <threads.h> 13#include "dsi.h" 14 15#define ADV7533_REG_CHIP_REVISION 0x00 16#define ADV7533_REG_POWER 0x41 17#define ADV7533_REG_STATUS 0x42 18#define ADV7533_REG_EDID_I2C_ADDR 0x43 19#define ADV7533_REG_PACKET_ENABLE1 0x44 20#define ADV7533_REG_PACKET_I2C_ADDR 0x45 21#define ADV7533_REG_INT0_ENABLE 0x94 22#define ADV7533_REG_INT1_ENABLE 0x95 23#define ADV7533_REG_INT0 0x96 24#define ADV7533_REG_INT1 0x96 25#define ADV7533_REG_HDCP_HDMI_CFG 0xaf 26#define ADV7533_REG_EDID_SEGMENT 0xc4 27#define ADV7533_REG_DDC_STATUS 0xc8 28#define ADV7533_REG_EDID_READ_CTRL 0xc9 29#define ADV7533_REG_POWER2 0xd6 30#define ADV7533_REG_CEC_I2C_ADDR 0xe1 31#define ADV7533_REG_CEC_CTRL 0xe2 32#define ADV7533_REG_CHIP_ID_HIGH 0xf5 33#define ADV7533_REG_CHIP_ID_LOW 0xf6 34 35#define EDID_I2C_ADDR (0x3B << 1) 36#define PACKET_I2C_ADDR (0x34 << 1) 37#define CEC_I2C_ADDR (0x38 << 1) 38 39/* ADV7533_REG_POWER Bit Definitions */ 40#define REG_POWER_PWR_UP (0x10) 41#define REG_POWER_PWR_DWN (0x50) 42 43/* ADV7533_REG_STATUS Bit Definitions */ 44#define REG_STATUS_HPD_DET (1 << 6) 45#define REG_STATUS_MON_SNS_DET (1 << 5) 46 47 48/* ADV7533_REG_PACKET_ENABLE1 Bit Definitions */ 49#define PACKET_ENABLE_DISABLE (0x0) 50 51/* ADV7533_REG_INT_ENABLE Bit Definitions */ 52#define REG_INT0_ENABLE_HPD (1 << 7) 53#define REG_INT0_ENABLE_EDID_RDY (1 << 2) 54#define REG_INT1_ENABLE_DDC_ERR (1 << 7) 55 56/* ADV7533_REG_INT0 Bit Definitions */ 57#define REG_INT0_HPD (1 << 7) 58 59/* ADV7533_REG_POWER2 Bit Definitions */ 60#define REG_POWER2_HPD_ALWAYS_HIGH (0xC0) 61 62/* ADV7533_REG_DDC_STATUS Bit Definition */ 63#define REG_DDC_STATUS_EDID_READY (0x2) 64 65/* ADV7533_REG_HDCP_HDMI_CFG Bit Definition */ 66#define REG_HDCP_HDMI_CFG_AVI_MODE (0 << 1) 67#define REG_HDCP_HDMI_CFG_HDMI_MODE (1 << 1) 68#define REG_HDCP_HDMI_CFG_DEFAULT (0x14) 69#define REG_HDCP_HDMI_CFG_ENB_HDMI (REG_HDCP_HDMI_CFG_DEFAULT | \ 70 REG_HDCP_HDMI_CFG_HDMI_MODE) 71#define REG_HDCP_HDMI_CFG_ENB_AVI (REG_HDCP_HDMI_CFG_DEFAULT | \ 72 REG_HDCP_HDMI_CFG_AVI_MODE) 73 74static void adv7533_mainchn_write(dsi_t* dsi, uint8_t d1, uint8_t d2); 75static void adv7533_mainchn_read(dsi_t* dsi, uint8_t d1, uint8_t len); 76static void adv7533_cecchn_write(dsi_t* dsi, uint8_t d1, uint8_t d2); 77static void adv7533_edidchn_read(dsi_t* dsi, uint8_t d1, uint8_t len); 78zx_status_t adv7533_init(dsi_t* dsi); 79void hdmi_init(dsi_t* dsi); 80uint8_t* adv7533_get_edid_buffer(void);