1// Copyright 2018 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#pragma once
6
7#include "aml-clk-blocks.h"
8#include <soc/aml-meson/g12a-clk.h>
9
10// TODO(braval): Use common bitfield header (ZX-2526) when available for
11//               macros used below to avoid duplication.
12#define BIT(pos) (1U << (pos))
13#define MSR_CLK_SRC_MASK 0x7f
14#define MSR_VAL_MASK 0x000FFFFF
15#define MSR_CLK_SRC_SHIFT 20
16#define MSR_ENABLE BIT(16)
17#define MSR_CONT BIT(17) // continuous measurement.
18#define MSR_INTR BIT(18) // interrupts.
19#define MSR_RUN BIT(19)
20#define MSR_BUSY BIT(31)
21
22#define G12A_HHI_SYS_CPU_CLK_CNTL1 (0x57 << 2)
23#define G12A_HHI_TS_CLK_CNTL (0x64 << 2)
24
25// NOTE: This list only contains the clocks in use currently and
26//       not all avaialbe clocks.
27static meson_clk_gate_t g12a_clk_gates[] = {
28    // SYS CPU Clock gates.
29    {.reg = G12A_HHI_SYS_CPU_CLK_CNTL1, .bit = 24}, // CLK_SYS_PLL_DIV16
30    {.reg = G12A_HHI_SYS_CPU_CLK_CNTL1, .bit = 1},  // CLK_SYS_CPU_CLK_DIV16
31};
32
33static_assert(CLK_G12A_COUNT == countof(g12a_clk_gates),
34              "g12a_clk_gates[] and g12a_clk_gate_idx_t count mismatch");
35
36static meson_clk_msr_t g12_clk_msr = {
37    .reg0_offset = (0x1 << 2),
38    .reg2_offset = (0x3 << 2),
39};
40
41// This clock table is meant only for CLK-MEASURE
42// Indexes here, correspond to actual clk mux
43// values written to measure respective clk.
44static const char* const g12a_clk_table[] = {
45    "am_ring_osc_clk_out_ee[0]", //  0
46    "am_ring_osc_clk_out_ee[1]", //  1
47    "am_ring_osc_clk_out_ee[2]", //  2
48    "sys_cpu_ring_osc_clk[0]",   //  3
49    "gp0_pll_clk",               //  4
50    "1'b0",                      //  5
51    "cts_enci_clk",              //  6
52    "clk81",                     //  7
53    "cts_encp_clk",              //  8
54    "cts_encl_clk",              //  9
55    "cts_vdac_clk",              // 10
56    "mac_eth_tx_clk",            // 11
57    "hifi_pll_clk",              // 12
58    "mod_tcon_clko",             // 13
59    "cts_FEC_CLK_0",             // 14
60    "cts_FEC_CLK_1",             // 15
61    "cts_FEC_CLK_2",             // 16
62    "sys_pll_div16",             // 17
63    "sys_cpu_clk_div16",         // 18
64    "lcd_an_clk_ph2",            // 19
65    "rtc_osc_clk_out",           // 20
66    "lcd_an_clk_ph3",            // 21
67    "mac_eth_phy_ref_clk",       // 22
68    "mpll_clk_50m",              // 23
69    "cts_eth_clk125Mhz",         // 24
70    "cts_eth_clk_rmii",          // 25
71    "sc_clk_int",                // 26
72    "co_clkin_to_mac",           // 27
73    "cts_sar_adc_clk",           // 28
74    "pcie_clk_inp",              // 29
75    "pcie_clk_inn",              // 30
76    "mpll_clk_test_out",         // 31
77    "cts_vdec_clk",              // 32
78    "sys_cpu_ring_osc_clk[1]",   // 33
79    "eth_mppll_50m_ckout",       // 34
80    "cts_mali_clk",              // 35
81    "cts_hdmi_tx_pixel_clk",     // 36
82    "cts_cdac_clk_c",            // 37
83    "cts_vdin_meas_clk",         // 38
84    "cts_bt656_clk0",            // 39
85    "1'b0",                      // 40
86    "mac_eth_rx_clk_rmii",       // 41
87    "mp0_clk_out",               // 42
88    "fclk_div5",                 // 43
89    "cts_pwm_B_clk",             // 44
90    "cts_pwm_A_clk",             // 45
91    "cts_vpu_clk",               // 46
92    "ddr_dpll_pt_clk",           // 47
93    "mp1_clk_out",               // 48
94    "mp2_clk_out",               // 49
95    "mp3_clk_out",               // 50
96    "cts_sd_emmc_clk_C",         // 51
97    "cts_sd_emmc_clk_B",         // 52
98    "cts_sd_emmc_clk_A",         // 53
99    "cts_vpu_clkc",              // 54
100    "vid_pll_div_clk_out",       // 55
101    "cts_wave420l_aclk",         // 56
102    "cts_wave420l_cclk",         // 57
103    "cts_wave420l_bclk",         // 58
104    "cts_hcodec_clk",            // 59
105    "1'b0",                      // 60
106    "gpio_clk_msr",              // 61
107    "cts_hevcb_clk",             // 62
108    "cts_dsi_meas_clk",          // 63
109    "cts_spicc_1_clk",           // 64
110    "cts_spicc_0_clk",           // 65
111    "cts_vid_lock_clk",          // 66
112    "cts_dsi_phy_clk",           // 67
113    "cts_hdcp22_esmclk",         // 68
114    "cts_hdcp22_skpclk",         // 69
115    "cts_pwm_F_clk",             // 70
116    "cts_pwm_E_clk",             // 71
117    "cts_pwm_D_clk",             // 72
118    "cts_pwm_C_clk",             // 73
119    "1'b0",                      // 74
120    "cts_hevcf_clk",             // 75
121    "1'b0",                      // 76
122    "rng_ring_osc_clk[0]",       // 77
123    "rng_ring_osc_clk[1]",       // 78
124    "rng_ring_osc_clk[2]",       // 79
125    "rng_ring_osc_clk[3]",       // 80
126    "cts_vapbclk",               // 81
127    "cts_ge2d_clk",              // 82
128    "co_rx_clk",                 // 83
129    "co_tx_clk",                 // 84
130    "1'b0",                      // 85
131    "1'b0",                      // 86
132    "1'b0",                      // 87
133    "1'b0",                      // 88
134    "HDMI_CLK_TODIG",            // 89
135    "cts_hdmitx_sys_clk",        // 90
136    "1'b0",                      // 91
137    "1'b0",                      // 92
138    "1'b0",                      // 93
139    "eth_phy_rxclk",             // 94
140    "eth_phy_plltxclk",          // 95
141    "cts_vpu_clkb",              // 96
142    "cts_vpu_clkb_tmp",          // 97
143    "cts_ts_clk",                // 98
144    "am_ring_osc_clk_out_ee[3]", // 99
145    "am_ring_osc_clk_out_ee[4]", // 100
146    "am_ring_osc_clk_out_ee[5]", // 101
147    "am_ring_osc_clk_out_ee[6]", // 102
148    "am_ring_osc_clk_out_ee[7]", // 103
149    "am_ring_osc_clk_out_ee[8]", // 104
150    "am_ring_osc_clk_out_ee[9]", // 105
151    "ephy_test_clk",             // 106
152    "au_dac_clk_g128x",          // 107
153    "c_alocker_in_clk",          // 108
154    "c_alocker_out_clk",         // 109
155    "audio_tdmout_c_sclk",       // 110
156    "audio_tdmout_b_sclk",       // 111
157    "audio_tdmout_a_sclk",       // 112
158    "audio_tdmin_lb_sclk",       // 113
159    "audio_tdmin_c_sclk",        // 114
160    "audio_tdmin_b_sclk",        // 115
161    "audio_tdmin_a_sclk",        // 116
162    "audio_resample_clk",        // 117
163    "audio_pdm_sysclk",          // 118
164    "audio_spdifout_b_mst_clk",  // 119
165    "audio_spdifout_mst_clk",    // 120
166    "audio_spdifin_mst_clk",     // 121
167    "mod_audio_pdm_dclk_o",      // 122
168};
169