1// Copyright 2018 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#pragma once
6
7typedef struct imx_sdhci_regs {
8    uint32_t ds_addr;                       // 0x00
9    uint32_t blk_att;                       // 0x04
10    uint32_t cmd_arg;                       // 0x08
11    uint32_t cmd_xfr_typ;                   // 0x0C
12    uint32_t cmd_rsp0;                      // 0x10
13    uint32_t cmd_rsp1;                      // 0x14
14    uint32_t cmd_rsp2;                      // 0x18
15    uint32_t cmd_rsp3;                      // 0x1C
16    uint32_t data_buff_acc_port;            // 0x20
17    uint32_t pres_state;                    // 0x24
18    uint32_t prot_ctrl;                     // 0x28
19    uint32_t sys_ctrl;                      // 0x2C
20    uint32_t int_status;                    // 0x30
21    uint32_t int_status_en;                 // 0x34
22    uint32_t int_signal_en;                 // 0x38
23    uint32_t autocmd12_err_status;          // 0x3C
24    uint32_t host_ctrl_cap;                 // 0x40
25    uint32_t wtmk_lvl;                      // 0x44
26    uint32_t mix_ctrl;                      // 0x48
27    uint8_t rsv1[4];                        // xxxxxxxx
28    uint32_t force_event;                   // 0x50
29    uint32_t adma_err_status;               // 0x54
30    uint32_t adma_sys_addr;                 // 0x58
31    uint8_t rsv2[4];                        // xxxxxxxx
32    uint32_t dll_ctrl;                      // 0x60
33    uint32_t dll_status;                    // 0x64
34    uint32_t clk_tune_ctrl_status;          // 0x68
35    uint8_t rsv3[4];                        // xxxxxxxx
36    uint32_t strobe_dll_ctrl;               // 0x70
37    uint32_t strobe_dll_status;             // 0x74
38    uint8_t rsv4[72];                       // xxxxxxxx
39    uint32_t vend_spec;                     // 0xC0
40    uint32_t mmc_boot;                      // 0xC4
41    uint32_t vend_spec2;                    // 0xC8
42    uint32_t tuning_ctrl;                   // 0xCC
43} __PACKED imx_sdhci_regs_t;
44
45
46#define IMX_SDHC_DS_ADDR(x)                         (x << 2)
47
48#define IMX_SDHC_BLK_ATT_BLKSIZE(x)                 ( x & 0x1FFF)
49#define IMX_SDHC_BLK_ATT_BLKCNT(x)                  ((x & 0xFFFF) << 16)
50
51
52#define IMX_SDHC_CMD_XFER_TYPE_CMDINX(x)            ((x & 0x3f) << 24)
53#define IMX_SDHC_CMD_XFER_TYPE_CMDTYP_ABORT         (3 << 22)
54#define IMX_SDHC_CMD_XFER_TYPE_CMDTYP_RESUME        (2 << 22)
55#define IMX_SDHC_CMD_XFER_TYPE_CMDTYP_SUSPEND       (1 << 22)
56#define IMX_SDHC_CMD_XFER_TYPE_CMDTYP_NORM          (0 << 22)
57#define IMX_SDHC_CMD_XFER_TYPE_DPSEL                (1 << 21)
58#define IMX_SDHC_CMD_XFER_TYPE_CICEN                (1 << 20)
59#define IMX_SDHC_CMD_XFER_TYPE_CCCEN                (1 << 19)
60#define IMX_SDHC_CMD_XFER_TYPE_RSP_TYPE_48_BSY      (3 << 16)
61#define IMX_SDHC_CMD_XFER_TYPE_RSP_TYPE_48          (2 << 16)
62#define IMX_SDHC_CMD_XFER_TYPE_RSP_TYPE_136         (1 << 16)
63#define IMX_SDHC_CMD_XFER_TYPE_RSP_TYPE_NO_RESP     (0 << 16)
64#define IMX_SDHC_CMD_XFER_TYPE_CMD_MASK             (0xFFFF << 16)
65
66#define IMX_SDHC_PRES_STATE_DLSL(x)                 (x << 24)
67#define IMX_SDHC_PRES_STATE_CLSL                    (1 << 23)
68#define IMX_SDHC_PRES_STATE_WPSPL                   (1 << 19)
69#define IMX_SDHC_PRES_STATE_CDPL                    (1 << 18)
70#define IMX_SDHC_PRES_STATE_CINST                   (1 << 16)
71#define IMX_SDHC_PRES_STATE_TSCD                    (1 << 15)
72#define IMX_SDHC_PRES_STATE_RTR                     (1 << 12)
73#define IMX_SDHC_PRES_STATE_BREN                    (1 << 11)
74#define IMX_SDHC_PRES_STATE_BWEN                    (1 << 10)
75#define IMX_SDHC_PRES_STATE_RTA                     (1 << 9)
76#define IMX_SDHC_PRES_STATE_WTA                     (1 << 8)
77#define IMX_SDHC_PRES_STATE_SDOFF                   (1 << 7)
78#define IMX_SDHC_PRES_STATE_PEROFF                  (1 << 6)
79#define IMX_SDHC_PRES_STATE_HCKOFF                  (1 << 5)
80#define IMX_SDHC_PRES_STATE_IPGOFF                  (1 << 4)
81#define IMX_SDHC_PRES_STATE_SDSTB                   (1 << 3)
82#define IMX_SDHC_PRES_STATE_DLA                     (1 << 2)
83#define IMX_SDHC_PRES_STATE_CDIHB                   (1 << 1)
84#define IMX_SDHC_PRES_STATE_CIHB                    (1 << 0)
85
86
87#define IMX_SDHC_PROT_CTRL_DMASEL_MASK              (3 << 8)
88#define IMX_SDHC_PROT_CTRL_DMASEL_ADMA2             (2 << 8)
89#define IMX_SDHC_PROT_CTRL_DMASEL_ADMA1             (1 << 8)
90#define IMX_SDHC_PROT_CTRL_DMASEL_NODMA             (0 << 8)
91#define IMX_SDHC_PROT_CTRL_CDSS                     (1 << 7)
92#define IMX_SDHC_PROT_CTRL_CDTL                     (1 << 6)
93#define IMX_SDHC_PROT_CTRL_INIT                     (1 << 5)
94#define IMX_SDHC_PROT_CTRL_DTW_MASK                 (3 << 1)
95#define IMX_SDHC_PROT_CTRL_DTW_8                    (2 << 1)
96#define IMX_SDHC_PROT_CTRL_DTW_4                    (1 << 1)
97#define IMX_SDHC_PROT_CTRL_DTW_1                    (0 << 1)
98
99#define IMX_SDHC_SYS_CTRL_RSTT                      (1 << 28)
100#define IMX_SDHC_SYS_CTRL_INTA                      (1 << 27)
101#define IMX_SDHC_SYS_CTRL_RSTD                      (1 << 26)
102#define IMX_SDHC_SYS_CTRL_RSTC                      (1 << 25)
103#define IMX_SDHC_SYS_CTRL_RSTA                      (1 << 24)
104#define IMX_SDHC_SYS_CTRL_DTOCV_MASK                (0xf << 16)
105#define IMX_SDHC_SYS_CTRL_DTOCV(x)                  (x << 16)
106#define IMX_SDHC_SYS_CTRL_SDCLKFS(x)                ((x & 0xFF) << 8)
107#define IMX_SDHC_SYS_CTRL_DVS(x)                    ((x & 0xF) << 4)
108
109// Undocumented sysctl bits (clock related)
110#define IMX_SDHC_SYS_CTRL_CLOCK_MASK                (0x0000fff0)
111#define IMX_SDHC_SYS_CTRL_PREDIV_SHIFT              (8)
112#define IMX_SDHC_SYS_CTRL_DIVIDER_SHIFT             (4)
113#define IMX_SDHC_SYS_CTRL_CLOCK_PEREN               (1 << 2)
114#define IMX_SDHC_SYS_CTRL_CLOCK_HCKEN               (1 << 1)
115#define IMX_SDHC_SYS_CTRL_CLOCK_IPGEN               (1 << 0)
116
117#define IMX_SDHC_INT_STAT_DMAE                      (1 << 28)
118#define IMX_SDHC_INT_STAT_TNE                       (1 << 26)
119#define IMX_SDHC_INT_STAT_AC12E                     (1 << 24)
120#define IMX_SDHC_INT_STAT_DEBE                      (1 << 22)
121#define IMX_SDHC_INT_STAT_DCE                       (1 << 21)
122#define IMX_SDHC_INT_STAT_DTOE                      (1 << 20)
123#define IMX_SDHC_INT_STAT_CIE                       (1 << 19)
124#define IMX_SDHC_INT_STAT_CEBE                      (1 << 18)
125#define IMX_SDHC_INT_STAT_CCE                       (1 << 17)
126#define IMX_SDHC_INT_STAT_CTOE                      (1 << 16)
127#define IMX_SDHC_INT_STAT_TP                        (1 << 14)
128#define IMX_SDHC_INT_STAT_RTE                       (1 << 12)
129#define IMX_SDHC_INT_STAT_CINT                      (1 << 8)
130#define IMX_SDHC_INT_STAT_CRM                       (1 << 7)
131#define IMX_SDHC_INT_STAT_CINS                      (1 << 6)
132#define IMX_SDHC_INT_STAT_BRR                       (1 << 5)
133#define IMX_SDHC_INT_STAT_BWR                       (1 << 4)
134#define IMX_SDHC_INT_STAT_DINT                      (1 << 3)
135#define IMX_SDHC_INT_STAT_BGE                       (1 << 2)
136#define IMX_SDHC_INT_STAT_TC                        (1 << 1)
137#define IMX_SDHC_INT_STAT_CC                        (1 << 0)
138
139#define IMX_SDHC_INT_EN_DMAEN                       (1 << 28)
140#define IMX_SDHC_INT_EN_TNE                         (1 << 26)
141#define IMX_SDHC_INT_EN_AC12E                       (1 << 24)
142#define IMX_SDHC_INT_EN_DEBE                        (1 << 22)
143#define IMX_SDHC_INT_EN_DCE                         (1 << 21)
144#define IMX_SDHC_INT_EN_DTOE                        (1 << 20)
145#define IMX_SDHC_INT_EN_CIE                         (1 << 19)
146#define IMX_SDHC_INT_EN_CEBE                        (1 << 18)
147#define IMX_SDHC_INT_EN_CCE                         (1 << 17)
148#define IMX_SDHC_INT_EN_CTOE                        (1 << 16)
149#define IMX_SDHC_INT_EN_TP                          (1 << 14)
150#define IMX_SDHC_INT_EN_RTE                         (1 << 12)
151#define IMX_SDHC_INT_EN_CINT                        (1 << 8)
152#define IMX_SDHC_INT_EN_CRM                         (1 << 7)
153#define IMX_SDHC_INT_EN_CINS                        (1 << 6)
154#define IMX_SDHC_INT_EN_BRR                         (1 << 5)
155#define IMX_SDHC_INT_EN_BWR                         (1 << 4)
156#define IMX_SDHC_INT_EN_DINT                        (1 << 3)
157#define IMX_SDHC_INT_EN_BGE                         (1 << 2)
158#define IMX_SDHC_INT_EN_TC                          (1 << 1)
159#define IMX_SDHC_INT_EN_CC                          (1 << 0)
160
161#define IMX_SDHC_INT_SIG_DMAEN                     (1 << 28)
162#define IMX_SDHC_INT_SIG_TNE                       (1 << 26)
163#define IMX_SDHC_INT_SIG_AC12E                     (1 << 24)
164#define IMX_SDHC_INT_SIG_DEBE                      (1 << 22)
165#define IMX_SDHC_INT_SIG_DCE                       (1 << 21)
166#define IMX_SDHC_INT_SIG_DTOE                      (1 << 20)
167#define IMX_SDHC_INT_SIG_CIE                       (1 << 19)
168#define IMX_SDHC_INT_SIG_CEBE                      (1 << 18)
169#define IMX_SDHC_INT_SIG_CCE                       (1 << 17)
170#define IMX_SDHC_INT_SIG_CTOE                      (1 << 16)
171#define IMX_SDHC_INT_SIG_TP                        (1 << 14)
172#define IMX_SDHC_INT_SIG_RTE                       (1 << 12)
173#define IMX_SDHC_INT_SIG_CINT                      (1 << 8)
174#define IMX_SDHC_INT_SIG_CRM                       (1 << 7)
175#define IMX_SDHC_INT_SIG_CINS                      (1 << 6)
176#define IMX_SDHC_INT_SIG_BRR                       (1 << 5)
177#define IMX_SDHC_INT_SIG_BWR                       (1 << 4)
178#define IMX_SDHC_INT_SIG_DINT                      (1 << 3)
179#define IMX_SDHC_INT_SIG_BGE                       (1 << 2)
180#define IMX_SDHC_INT_SIG_TC                        (1 << 1)
181#define IMX_SDHC_INT_SIG_CC                        (1 << 0)
182
183#define IMX_SDHC_HOST_CTRL_CAP_VS18                 (1 << 26)
184#define IMX_SDHC_HOST_CTRL_CAP_VS30                 (1 << 25)
185#define IMX_SDHC_HOST_CTRL_CAP_VS33                 (1 << 24)
186#define IMX_SDHC_HOST_CTRL_CAP_SRS                  (1 << 23)
187#define IMX_SDHC_HOST_CTRL_CAP_DMAS                 (1 << 22)
188#define IMX_SDHC_HOST_CTRL_CAP_HSS                  (1 << 21)
189#define IMX_SDHC_HOST_CTRL_CAP_ADMAS                (1 << 20)
190
191#define IMX_SDHC_MIX_CTRL_HS400                     (1 << 26)
192#define IMX_SDHC_MIX_CTRL_FBCLK_SEL                 (1 << 25)
193#define IMX_SDHC_MIX_CTRL_AUTO_TUNE                 (1 << 24)
194#define IMX_SDHC_MIX_CTRL_SMP_CLK_SEL               (1 << 23)
195#define IMX_SDHC_MIX_CTRL_EXE_TUNE                  (1 << 22)
196#define IMX_SDHC_MIX_CTRL_AC23EN                    (1 << 7)
197#define IMX_SDHC_MIX_CTRL_NIBBLE_POS                (1 << 6)
198#define IMX_SDHC_MIX_CTRL_MSBSEL                    (1 << 5)
199#define IMX_SDHC_MIX_CTRL_DTDSEL                    (1 << 4)
200#define IMX_SDHC_MIX_CTRL_DDR_EN                    (1 << 3)
201#define IMX_SDHC_MIX_CTRL_AC12EN                    (1 << 2)
202#define IMX_SDHC_MIX_CTRL_BCEN                      (1 << 1)
203#define IMX_SDHC_MIX_CTRL_DMAEN                     (1 << 0)
204#define IMX_SDHC_MIX_CTRL_CMD_MASK                  (0xb6 << 0)
205
206#define IMX_SDHC_VEND_SPEC_CARD_CLK_SOFT_EN         (1 << 14)
207#define IMX_SDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN       (1 << 13)
208#define IMX_SDHC_VEND_SPEC_HCLK_SOFT_EN             (1 << 12)
209#define IMX_SDHC_VEND_SPEC_IPG_CLK_SOFT_EN          (1 << 11)
210#define IMX_SDHC_VEND_SPEC_FRC_SDCLK_ON             (1 << 8)
211#define IMX_SDHC_VEND_SPEC_INIT                     (0x20007809)
212
213#define IMX_SDHC_AUTOCMD12_ERRSTS_SMP_CLK_SEL       (1 << 23)
214#define IMX_SDHC_AUTOCMD12_ERRSTS_EXE_TUNING        (1 << 22)
215
216#define IMX_SDHC_DLLCTRL_SLV_DLY_TARGET             (0x5 << 3)
217#define IMX_SDHC_DLLCTRL_RESET                      (1 << 1)
218#define IMX_SDHC_DLLCTRL_ENABLE                     (1 << 0)
219
220#define IMX_SDHC_DLLSTS_REF_LOCK                    (1 << 1)
221#define IMX_SDHC_DLLSTS_SLV_LOCK                    (1 << 0)
222
223#define IMX_SDHC_TUNING_CTRL_START_TAP_MASK         (0xFF << 0)
224#define IMX_SDHC_TUNING_CTRL_START_TAP(x)           (x << 0)
225#define IMX_SDHC_TUNING_CTRL_STEP_MASK              (0x7 << 16)
226#define IMX_SDHC_TUNING_CTRL_STEP(x)                (x << 16)
227#define IMX_SDHC_TUNING_CTRL_STD_TUN_EN             (1 << 24)