1/*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/param.h> 31 32#include "diag.h" 33 34#include "ah.h" 35#include "ah_internal.h" 36#include "ar5211/ar5211reg.h" 37#include "ar5211/ar5211phy.h" 38 39#include "dumpregs.h" 40 41static struct dumpreg ar5211regs[] = { 42 DEFBASICfmt(AR_CR, "CR", AR_CR_BITS), 43 DEFBASIC(AR_RXDP, "RXDP"), 44 DEFBASICfmt(AR_CFG, "CFG", AR_CFG_BITS), 45 DEFBASICfmt(AR_IER, "IER", AR_IER_BITS), 46 DEFBASIC(AR_RTSD0, "RTSD0"), 47 DEFBASIC(AR_RTSD1, "RTSD1"), 48 DEFBASICfmt(AR_TXCFG, "TXCFG", AR_TXCFG_BITS), 49 DEFBASIC(AR_RXCFG, "RXCFG"), 50 DEFBASIC(AR5211_JUMBO_LAST, "JLAST"), 51 DEFBASIC(AR_MIBC, "MIBC"), 52 DEFBASIC(AR_TOPS, "TOPS"), 53 DEFBASIC(AR_RXNPTO, "RXNPTO"), 54 DEFBASIC(AR_TXNPTO, "TXNPTO"), 55 DEFBASIC(AR_RFGTO, "RFGTO"), 56 DEFBASIC(AR_RFCNT, "RFCNT"), 57 DEFBASIC(AR_MACMISC, "MISC"), 58 DEFVOID(AR5311_QDCLKGATE, "AR5311_QDCLKGATE"), 59 60 DEFINT(AR_ISR, "ISR"), 61 DEFINT(AR_ISR_S0, "ISR_S0"), 62 DEFINT(AR_ISR_S1, "ISR_S1"), 63 DEFINT(AR_ISR_S2, "ISR_S2"), 64 DEFINT(AR_ISR_S3, "ISR_S3"), 65 DEFINT(AR_ISR_S4, "ISR_S4"), 66 DEFINT(AR_IMR, "IMR"), 67 DEFINT(AR_IMR_S0, "IMR_S0"), 68 DEFINT(AR_IMR_S1, "IMR_S1"), 69 DEFINT(AR_IMR_S2, "IMR_S2"), 70 DEFINT(AR_IMR_S3, "IMR_S3"), 71 DEFINT(AR_IMR_S4, "IMR_S4"), 72 /* NB: don't read the RAC so we don't affect operation */ 73 DEFVOID(AR_ISR_RAC, "ISR_RAC"), 74 DEFINT(AR_ISR_S0_S, "ISR_S0_S"), 75 DEFINT(AR_ISR_S1_S, "ISR_S1_S"), 76 DEFINT(AR_ISR_S2_S, "ISR_S2_S"), 77 DEFINT(AR_ISR_S3_S, "ISR_S3_S"), 78 DEFINT(AR_ISR_S4_S, "ISR_S4_S"), 79 80 DEFQCU(AR_Q0_TXDP, "Q0_TXDP"), 81 DEFQCU(AR_Q1_TXDP, "Q1_TXDP"), 82 DEFQCU(AR_Q2_TXDP, "Q2_TXDP"), 83 DEFQCU(AR_Q3_TXDP, "Q3_TXDP"), 84 DEFQCU(AR_Q4_TXDP, "Q4_TXDP"), 85 DEFQCU(AR_Q5_TXDP, "Q5_TXDP"), 86 DEFQCU(AR_Q6_TXDP, "Q6_TXDP"), 87 DEFQCU(AR_Q7_TXDP, "Q7_TXDP"), 88 DEFQCU(AR_Q8_TXDP, "Q8_TXDP"), 89 DEFQCU(AR_Q9_TXDP, "Q9_TXDP"), 90 91 DEFQCU(AR_Q_TXE, "Q_TXE"), 92 DEFQCU(AR_Q_TXD, "Q_TXD"), 93 94 DEFQCU(AR_Q0_CBRCFG, "Q0_CBR"), 95 DEFQCU(AR_Q1_CBRCFG, "Q1_CBR"), 96 DEFQCU(AR_Q2_CBRCFG, "Q2_CBR"), 97 DEFQCU(AR_Q3_CBRCFG, "Q3_CBR"), 98 DEFQCU(AR_Q4_CBRCFG, "Q4_CBR"), 99 DEFQCU(AR_Q5_CBRCFG, "Q5_CBR"), 100 DEFQCU(AR_Q6_CBRCFG, "Q6_CBR"), 101 DEFQCU(AR_Q7_CBRCFG, "Q7_CBR"), 102 DEFQCU(AR_Q8_CBRCFG, "Q8_CBR"), 103 DEFQCU(AR_Q9_CBRCFG, "Q9_CBR"), 104 105 DEFQCU(AR_Q0_RDYTIMECFG, "Q0_RDYT"), 106 DEFQCU(AR_Q1_RDYTIMECFG, "Q1_RDYT"), 107 DEFQCU(AR_Q2_RDYTIMECFG, "Q2_RDYT"), 108 DEFQCU(AR_Q3_RDYTIMECFG, "Q3_RDYT"), 109 DEFQCU(AR_Q4_RDYTIMECFG, "Q4_RDYT"), 110 DEFQCU(AR_Q5_RDYTIMECFG, "Q5_RDYT"), 111 DEFQCU(AR_Q6_RDYTIMECFG, "Q6_RDYT"), 112 DEFQCU(AR_Q7_RDYTIMECFG, "Q7_RDYT"), 113 DEFQCU(AR_Q8_RDYTIMECFG, "Q8_RDYT"), 114 DEFQCU(AR_Q9_RDYTIMECFG, "Q9_RDYT"), 115 116 DEFQCU(AR_Q_ONESHOTARM_SC, "Q_ONESHOTARM_SC"), 117 DEFQCU(AR_Q_ONESHOTARM_CC, "Q_ONESHOTARM_CC"), 118 119 DEFQCU(AR_Q0_MISC, "Q0_MISC"), 120 DEFQCU(AR_Q1_MISC, "Q1_MISC"), 121 DEFQCU(AR_Q2_MISC, "Q2_MISC"), 122 DEFQCU(AR_Q3_MISC, "Q3_MISC"), 123 DEFQCU(AR_Q4_MISC, "Q4_MISC"), 124 DEFQCU(AR_Q5_MISC, "Q5_MISC"), 125 DEFQCU(AR_Q6_MISC, "Q6_MISC"), 126 DEFQCU(AR_Q7_MISC, "Q7_MISC"), 127 DEFQCU(AR_Q8_MISC, "Q8_MISC"), 128 DEFQCU(AR_Q9_MISC, "Q9_MISC"), 129 130 DEFQCU(AR_Q0_STS, "Q0_STS"), 131 DEFQCU(AR_Q1_STS, "Q1_STS"), 132 DEFQCU(AR_Q2_STS, "Q2_STS"), 133 DEFQCU(AR_Q3_STS, "Q3_STS"), 134 DEFQCU(AR_Q4_STS, "Q4_STS"), 135 DEFQCU(AR_Q5_STS, "Q5_STS"), 136 DEFQCU(AR_Q6_STS, "Q6_STS"), 137 DEFQCU(AR_Q7_STS, "Q7_STS"), 138 DEFQCU(AR_Q8_STS, "Q8_STS"), 139 DEFQCU(AR_Q9_STS, "Q9_STS"), 140 141 DEFQCU(AR_Q_RDYTIMESHDN, "Q_RDYTIMSHD"), 142 143 DEFQCU(AR_D0_QCUMASK, "D0_MASK"), 144 DEFQCU(AR_D1_QCUMASK, "D1_MASK"), 145 DEFQCU(AR_D2_QCUMASK, "D2_MASK"), 146 DEFQCU(AR_D3_QCUMASK, "D3_MASK"), 147 DEFQCU(AR_D4_QCUMASK, "D4_MASK"), 148 DEFQCU(AR_D5_QCUMASK, "D5_MASK"), 149 DEFQCU(AR_D6_QCUMASK, "D6_MASK"), 150 DEFQCU(AR_D7_QCUMASK, "D7_MASK"), 151 DEFQCU(AR_D8_QCUMASK, "D8_MASK"), 152 DEFQCU(AR_D9_QCUMASK, "D9_MASK"), 153 154 DEFDCU(AR_D0_LCL_IFS, "D0_IFS"), 155 DEFDCU(AR_D1_LCL_IFS, "D1_IFS"), 156 DEFDCU(AR_D2_LCL_IFS, "D2_IFS"), 157 DEFDCU(AR_D3_LCL_IFS, "D3_IFS"), 158 DEFDCU(AR_D4_LCL_IFS, "D4_IFS"), 159 DEFDCU(AR_D5_LCL_IFS, "D5_IFS"), 160 DEFDCU(AR_D6_LCL_IFS, "D6_IFS"), 161 DEFDCU(AR_D7_LCL_IFS, "D7_IFS"), 162 DEFDCU(AR_D8_LCL_IFS, "D8_IFS"), 163 DEFDCU(AR_D9_LCL_IFS, "D9_IFS"), 164 165 DEFDCU(AR_D0_RETRY_LIMIT, "D0_RTRY"), 166 DEFDCU(AR_D1_RETRY_LIMIT, "D1_RTRY"), 167 DEFDCU(AR_D2_RETRY_LIMIT, "D2_RTRY"), 168 DEFDCU(AR_D3_RETRY_LIMIT, "D3_RTRY"), 169 DEFDCU(AR_D4_RETRY_LIMIT, "D4_RTRY"), 170 DEFDCU(AR_D5_RETRY_LIMIT, "D5_RTRY"), 171 DEFDCU(AR_D6_RETRY_LIMIT, "D6_RTRY"), 172 DEFDCU(AR_D7_RETRY_LIMIT, "D7_RTRY"), 173 DEFDCU(AR_D8_RETRY_LIMIT, "D8_RTRY"), 174 DEFDCU(AR_D9_RETRY_LIMIT, "D9_RTRY"), 175 176 DEFDCU(AR_D0_CHNTIME, "D0_CHNT"), 177 DEFDCU(AR_D1_CHNTIME, "D1_CHNT"), 178 DEFDCU(AR_D2_CHNTIME, "D2_CHNT"), 179 DEFDCU(AR_D3_CHNTIME, "D3_CHNT"), 180 DEFDCU(AR_D4_CHNTIME, "D4_CHNT"), 181 DEFDCU(AR_D5_CHNTIME, "D5_CHNT"), 182 DEFDCU(AR_D6_CHNTIME, "D6_CHNT"), 183 DEFDCU(AR_D7_CHNTIME, "D7_CHNT"), 184 DEFDCU(AR_D8_CHNTIME, "D8_CHNT"), 185 DEFDCU(AR_D9_CHNTIME, "D9_CHNT"), 186 187 DEFDCU(AR_D0_MISC, "D0_MISC"), 188 DEFDCU(AR_D1_MISC, "D1_MISC"), 189 DEFDCU(AR_D2_MISC, "D2_MISC"), 190 DEFDCU(AR_D3_MISC, "D3_MISC"), 191 DEFDCU(AR_D4_MISC, "D4_MISC"), 192 DEFDCU(AR_D5_MISC, "D5_MISC"), 193 DEFDCU(AR_D6_MISC, "D6_MISC"), 194 DEFDCU(AR_D7_MISC, "D7_MISC"), 195 DEFDCU(AR_D8_MISC, "D8_MISC"), 196 DEFDCU(AR_D9_MISC, "D9_MISC"), 197 198 DEFDCU(AR_D0_SEQNUM, "D0_SEQ"), 199 DEFDCU(AR_D1_SEQNUM, "D1_SEQ"), 200 DEFDCU(AR_D2_SEQNUM, "D2_SEQ"), 201 DEFDCU(AR_D3_SEQNUM, "D3_SEQ"), 202 DEFDCU(AR_D4_SEQNUM, "D4_SEQ"), 203 DEFDCU(AR_D5_SEQNUM, "D5_SEQ"), 204 DEFDCU(AR_D6_SEQNUM, "D6_SEQ"), 205 DEFDCU(AR_D7_SEQNUM, "D7_SEQ"), 206 DEFDCU(AR_D8_SEQNUM, "D8_SEQ"), 207 DEFDCU(AR_D9_SEQNUM, "D9_SEQ"), 208 209 DEFBASIC(AR_D_GBL_IFS_SIFS, "D_SIFS"), 210 DEFBASIC(AR_D_GBL_IFS_SLOT, "D_SLOT"), 211 DEFBASIC(AR_D_GBL_IFS_EIFS, "D_EIFS"), 212 DEFBASIC(AR_D_GBL_IFS_MISC, "D_MISC"), 213 DEFBASIC(AR_D_FPCTL, "D_FPCTL"), 214 DEFBASIC(AR_D_TXPSE, "D_TXPSE"), 215 DEFVOID(AR_D_TXBLK_CMD, "D_CMD"), 216#if 0 217 DEFVOID(AR_D_TXBLK_DATA, "D_DATA"), 218#endif 219 DEFVOID(AR_D_TXBLK_CLR, "D_CLR"), 220 DEFVOID(AR_D_TXBLK_SET, "D_SET"), 221 DEFBASICfmt(AR_RC, "RC", AR_RC_BITS), 222 DEFBASICfmt(AR_SCR, "SCR", AR_SCR_BITS), 223 DEFBASICfmt(AR_INTPEND, "INTPEND", AR_INTPEND_BITS), 224 DEFBASIC(AR_SFR, "SFR"), 225 DEFBASICfmt(AR_PCICFG, "PCICFG", AR_PCICFG_BITS), 226 DEFBASIC(AR_GPIOCR, "GPIOCR"), 227 DEFBASIC(AR_GPIODO, "GPIODO"), 228 DEFBASIC(AR_GPIODI, "GPIODI"), 229 DEFBASIC(AR_SREV, "SREV"), 230 DEFVOID(AR_EEPROM_ADDR, "EEADDR"), 231 DEFVOID(AR_EEPROM_DATA, "EEDATA"), 232 DEFVOID(AR_EEPROM_CMD, "EECMD"), 233 DEFVOID(AR_EEPROM_STS, "EESTS"), 234 DEFVOID(AR_EEPROM_CFG, "EECFG"), 235 DEFBASIC(AR_STA_ID0, "STA_ID0"), 236 DEFBASICfmt(AR_STA_ID1, "STA_ID1", AR_STA_ID1_BITS), 237 DEFBASIC(AR_BSS_ID0, "BSS_ID0"), 238 DEFBASIC(AR_BSS_ID1, "BSS_ID1"), 239 DEFBASIC(AR_SLOT_TIME, "SLOTTIME"), 240 DEFBASIC(AR_TIME_OUT, "TIME_OUT"), 241 DEFBASIC(AR_RSSI_THR, "RSSI_THR"), 242 DEFBASIC(AR_USEC, "USEC"), 243 DEFBASICfmt(AR_BEACON, "BEACON", AR_BEACON_BITS), 244 DEFBASIC(AR_CFP_PERIOD, "CFP_PER"), 245 DEFBASIC(AR_TIMER0, "TIMER0"), 246 DEFBASIC(AR_TIMER1, "TIMER1"), 247 DEFBASIC(AR_TIMER2, "TIMER2"), 248 DEFBASIC(AR_TIMER3, "TIMER3"), 249 DEFBASIC(AR_CFP_DUR, "CFP_DUR"), 250 DEFBASICfmt(AR_RX_FILTER, "RXFILTER", AR_RX_FILTER_BITS), 251 DEFBASIC(AR_MCAST_FIL0, "MCAST_0"), 252 DEFBASIC(AR_MCAST_FIL1, "MCAST_1"), 253 DEFBASICfmt(AR_DIAG_SW, "DIAG_SW", AR_DIAG_SW_BITS), 254 DEFBASIC(AR_TSF_L32, "TSF_L32"), 255 DEFBASIC(AR_TSF_U32, "TSF_U32"), 256 DEFBASIC(AR_TST_ADDAC, "TST_ADAC"), 257 DEFBASIC(AR_DEF_ANTENNA, "DEF_ANT"), 258 259 DEFBASIC(AR_LAST_TSTP, "LAST_TST"), 260 DEFBASIC(AR_NAV, "NAV"), 261 DEFBASIC(AR_RTS_OK, "RTS_OK"), 262 DEFBASIC(AR_RTS_FAIL, "RTS_FAIL"), 263 DEFBASIC(AR_ACK_FAIL, "ACK_FAIL"), 264 DEFBASIC(AR_FCS_FAIL, "FCS_FAIL"), 265 DEFBASIC(AR_BEACON_CNT, "BEAC_CNT"), 266 267 DEFVOID(AR_PHY_TURBO, "PHY_TURBO"), 268 DEFVOID(AR_PHY_CHIP_ID, "PHY_CHIP_ID"), 269 DEFVOID(AR_PHY_ACTIVE, "PHY_ACTIVE"), 270 DEFVOID(AR_PHY_AGC_CONTROL, "PHY_AGC_CONTROL"), 271 DEFVOID(AR_PHY_PLL_CTL, "PHY_PLL_CTL"), 272 DEFVOID(AR_PHY_RX_DELAY, "PHY_RX_DELAY"), 273 DEFVOID(AR_PHY_TIMING_CTRL4,"PHY_TIMING_CTRL4"), 274 DEFVOID(AR_PHY_RADAR_0, "PHY_RADAR_0"), 275 DEFVOID(AR_PHY_IQCAL_RES_PWR_MEAS_I,"PHY_IQCAL_RES_PWR_MEAS_I"), 276 DEFVOID(AR_PHY_IQCAL_RES_PWR_MEAS_Q,"PHY_IQCAL_RES_PWR_MEAS_Q"), 277 DEFVOID(AR_PHY_IQCAL_RES_IQ_CORR_MEAS,"PHY_IQCAL_RES_IQ_CORR_MEAS"), 278 DEFVOID(AR_PHY_CURRENT_RSSI,"PHY_CURRENT_RSSI"), 279 DEFVOID(AR5211_PHY_MODE, "PHY_MODE"), 280}; 281 282static __constructor void 283ar5211_ctor(void) 284{ 285#define MAC5211 SREV(2,0), SREV(4,5) 286 register_regs(ar5211regs, nitems(ar5211regs), MAC5211, PHYANY); 287 register_keycache(128, MAC5211, PHYANY); 288 289 register_range(0x9800, 0x987c, DUMP_BASEBAND, MAC5211, PHYANY); 290 register_range(0x9900, 0x995c, DUMP_BASEBAND, MAC5211, PHYANY); 291 register_range(0x9c00, 0x9c1c, DUMP_BASEBAND, MAC5211, PHYANY); 292} 293