1/*- 2 * Copyright (c) 1995 Bruce D. Evans. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the author nor the names of contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#ifndef _X86_X86_VAR_H_ 31#define _X86_X86_VAR_H_ 32 33/* 34 * Miscellaneous machine-dependent declarations. 35 */ 36 37extern long Maxmem; 38extern u_int basemem; 39extern u_int cpu_exthigh; 40extern u_int cpu_feature; 41extern u_int cpu_feature2; 42extern u_int amd_feature; 43extern u_int amd_feature2; 44extern u_int amd_rascap; 45extern u_int amd_pminfo; 46extern u_int amd_extended_feature_extensions; 47extern u_int via_feature_rng; 48extern u_int via_feature_xcrypt; 49extern u_int cpu_clflush_line_size; 50extern u_int cpu_stdext_feature; 51extern u_int cpu_stdext_feature2; 52extern u_int cpu_stdext_feature3; 53extern uint64_t cpu_ia32_arch_caps; 54extern u_int cpu_high; 55extern u_int cpu_id; 56extern u_int cpu_max_ext_state_size; 57extern u_int cpu_mxcsr_mask; 58extern u_int cpu_procinfo; 59extern u_int cpu_procinfo2; 60extern u_int cpu_procinfo3; 61extern char cpu_vendor[]; 62extern char cpu_model[]; 63extern u_int cpu_vendor_id; 64extern u_int cpu_mon_mwait_flags; 65extern u_int cpu_mon_min_size; 66extern u_int cpu_mon_max_size; 67extern u_int cpu_maxphyaddr; 68extern u_int cpu_power_eax; 69extern u_int cpu_power_ebx; 70extern u_int cpu_power_ecx; 71extern u_int cpu_power_edx; 72extern u_int hv_base; 73extern u_int hv_high; 74extern char hv_vendor[]; 75extern char kstack[]; 76extern char sigcode[]; 77extern int szsigcode; 78extern int workaround_erratum383; 79extern int _udatasel; 80extern int _ucodesel; 81extern int _ucode32sel; 82extern int _ufssel; 83extern int _ugssel; 84extern int use_xsave; 85extern uint64_t xsave_mask; 86extern u_int max_apic_id; 87extern int i386_read_exec; 88extern int pti; 89extern int hw_ibrs_ibpb_active; 90extern int hw_mds_disable; 91extern int hw_ssb_active; 92extern int x86_taa_enable; 93extern int cpu_flush_rsb_ctxsw; 94extern int x86_rngds_mitg_enable; 95extern int zenbleed_enable; 96extern int cpu_amdc1e_bug; 97extern char bootmethod[16]; 98 99struct pcb; 100struct thread; 101struct reg; 102struct fpreg; 103struct dbreg; 104struct dumperinfo; 105struct trapframe; 106struct minidumpstate; 107 108/* 109 * The interface type of the interrupt handler entry point cannot be 110 * expressed in C. Use simplest non-variadic function type as an 111 * approximation. 112 */ 113typedef void alias_for_inthand_t(void); 114 115bool acpi_get_fadt_bootflags(uint16_t *flagsp); 116void *alloc_fpusave(int flags); 117u_int cpu_auxmsr(void); 118vm_paddr_t cpu_getmaxphyaddr(void); 119bool cpu_mwait_usable(void); 120void cpu_probe_amdc1e(void); 121void cpu_setregs(void); 122int dbreg_set_watchpoint(vm_offset_t addr, vm_size_t size, int access); 123int dbreg_clr_watchpoint(vm_offset_t addr, vm_size_t size); 124void dbreg_list_watchpoints(void); 125void x86_clear_dbregs(struct pcb *pcb); 126bool disable_wp(void); 127void restore_wp(bool old_wp); 128void finishidentcpu(void); 129void identify_cpu1(void); 130void identify_cpu2(void); 131void identify_cpu_ext_features(void); 132void identify_cpu_fixup_bsp(void); 133void identify_hypervisor(void); 134void initializecpu(void); 135void initializecpucache(void); 136bool fix_cpuid(void); 137void fillw(int /*u_short*/ pat, void *base, size_t cnt); 138int isa_nmi(int cd); 139void handle_ibrs_entry(void); 140void handle_ibrs_exit(void); 141void hw_ibrs_recalculate(bool all_cpus); 142void hw_mds_recalculate(void); 143void hw_ssb_recalculate(bool all_cpus); 144void x86_taa_recalculate(void); 145void x86_rngds_mitg_recalculate(bool all_cpus); 146void zenbleed_sanitize_enable(void); 147void zenbleed_check_and_apply(bool all_cpus); 148void nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame); 149void nmi_call_kdb_smp(u_int type, struct trapframe *frame); 150void nmi_handle_intr(u_int type, struct trapframe *frame); 151void pagecopy(void *from, void *to); 152void printcpuinfo(void); 153int pti_get_default(void); 154int user_dbreg_trap(register_t dr6); 155int cpu_minidumpsys(struct dumperinfo *, const struct minidumpstate *); 156struct pcb *get_pcb_td(struct thread *td); 157void x86_set_fork_retval(struct thread *td); 158uint64_t rdtsc_ordered(void); 159 160/* 161 * MSR ops for x86_msr_op() 162 */ 163#define MSR_OP_ANDNOT 0x00000001 164#define MSR_OP_OR 0x00000002 165#define MSR_OP_WRITE 0x00000003 166#define MSR_OP_READ 0x00000004 167 168/* 169 * Where and which execution mode 170 */ 171#define MSR_OP_LOCAL 0x10000000 172#define MSR_OP_SCHED_ALL 0x20000000 173#define MSR_OP_SCHED_ONE 0x30000000 174#define MSR_OP_RENDEZVOUS_ALL 0x40000000 175#define MSR_OP_RENDEZVOUS_ONE 0x50000000 176#define MSR_OP_CPUID(id) ((id) << 8) 177 178void x86_msr_op(u_int msr, u_int op, uint64_t arg1, uint64_t *res); 179 180#if defined(__i386__) && defined(INVARIANTS) 181void trap_check_kstack(void); 182#else 183#define trap_check_kstack() 184#endif 185 186#endif 187