1/*-
2 * Copyright (c) 2015-2024 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35/*
36 * RISC-V Timer
37 */
38
39#include "opt_platform.h"
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/bus.h>
44#include <sys/kernel.h>
45#include <sys/module.h>
46#include <sys/rman.h>
47#include <sys/timeet.h>
48#include <sys/timetc.h>
49#include <sys/vdso.h>
50#include <sys/watchdog.h>
51
52#include <machine/cpufunc.h>
53#include <machine/intr.h>
54#include <machine/md_var.h>
55#include <machine/sbi.h>
56
57#include <dev/ofw/ofw_bus.h>
58#include <dev/ofw/openfirm.h>
59
60struct riscv_timer_softc {
61	struct resource		*irq_res;
62	void			*ih;
63	uint32_t		clkfreq;
64	struct eventtimer	et;
65};
66static struct riscv_timer_softc *riscv_timer_sc = NULL;
67
68static timecounter_get_t riscv_timer_tc_get_timecount;
69static timecounter_fill_vdso_timehands_t riscv_timer_tc_fill_vdso_timehands;
70
71static struct timecounter riscv_timer_timecount = {
72	.tc_name           = "RISC-V Timecounter",
73	.tc_get_timecount  = riscv_timer_tc_get_timecount,
74	.tc_poll_pps       = NULL,
75	.tc_counter_mask   = ~0u,
76	.tc_frequency      = 0,
77	.tc_quality        = 1000,
78	.tc_fill_vdso_timehands = riscv_timer_tc_fill_vdso_timehands,
79};
80
81static inline uint64_t
82get_timecount(void)
83{
84
85	return (rdtime());
86}
87
88static inline void
89set_timecmp(uint64_t timecmp)
90{
91
92	if (has_sstc)
93		csr_write(stimecmp, timecmp);
94	else
95		sbi_set_timer(timecmp);
96}
97
98static u_int
99riscv_timer_tc_get_timecount(struct timecounter *tc __unused)
100{
101
102	return (get_timecount());
103}
104
105static uint32_t
106riscv_timer_tc_fill_vdso_timehands(struct vdso_timehands *vdso_th,
107    struct timecounter *tc)
108{
109	vdso_th->th_algo = VDSO_TH_ALGO_RISCV_RDTIME;
110	bzero(vdso_th->th_res, sizeof(vdso_th->th_res));
111	return (1);
112}
113
114static int
115riscv_timer_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
116{
117	uint64_t counts;
118
119	if (first != 0) {
120		counts = ((uint32_t)et->et_frequency * first) >> 32;
121		set_timecmp(get_timecount() + counts);
122
123		return (0);
124	}
125
126	return (EINVAL);
127}
128
129static int
130riscv_timer_et_stop(struct eventtimer *et)
131{
132
133	/* Disable timer interrupts. */
134	csr_clear(sie, SIE_STIE);
135
136	return (0);
137}
138
139static int
140riscv_timer_intr(void *arg)
141{
142	struct riscv_timer_softc *sc;
143
144	sc = (struct riscv_timer_softc *)arg;
145
146	if (has_sstc)
147		csr_write(stimecmp, -1UL);
148	else
149		csr_clear(sip, SIP_STIP);
150
151	if (sc->et.et_active)
152		sc->et.et_event_cb(&sc->et, sc->et.et_arg);
153
154	return (FILTER_HANDLED);
155}
156
157static int
158riscv_timer_get_timebase(device_t dev, uint32_t *freq)
159{
160	phandle_t node;
161	int len;
162
163	node = OF_finddevice("/cpus");
164	if (node == -1) {
165		if (bootverbose)
166			device_printf(dev, "Can't find cpus node.\n");
167		return (ENXIO);
168	}
169
170	len = OF_getproplen(node, "timebase-frequency");
171	if (len != 4) {
172		if (bootverbose)
173			device_printf(dev,
174			    "Can't find timebase-frequency property.\n");
175		return (ENXIO);
176	}
177
178	OF_getencprop(node, "timebase-frequency", freq, len);
179
180	return (0);
181}
182
183static int
184riscv_timer_probe(device_t dev)
185{
186
187	device_set_desc(dev, "RISC-V Timer");
188
189	return (BUS_PROBE_DEFAULT);
190}
191
192static int
193riscv_timer_attach(device_t dev)
194{
195	struct riscv_timer_softc *sc;
196	int irq, rid, error;
197	phandle_t iparent;
198	pcell_t cell;
199
200	sc = device_get_softc(dev);
201	if (riscv_timer_sc != NULL)
202		return (ENXIO);
203
204	if (device_get_unit(dev) != 0)
205		return (ENXIO);
206
207	if (riscv_timer_get_timebase(dev, &sc->clkfreq) != 0) {
208		device_printf(dev, "No clock frequency specified\n");
209		return (ENXIO);
210	}
211
212	riscv_timer_sc = sc;
213
214	iparent = OF_xref_from_node(ofw_bus_get_node(intr_irq_root_dev));
215	cell = IRQ_TIMER_SUPERVISOR;
216	irq = ofw_bus_map_intr(dev, iparent, 1, &cell);
217	error = bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1);
218	if (error != 0) {
219		device_printf(dev, "Unable to register IRQ resource\n");
220		return (ENXIO);
221	}
222
223	rid = 0;
224	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
225	    RF_ACTIVE);
226	if (sc->irq_res == NULL) {
227		device_printf(dev, "Unable to alloc IRQ resource\n");
228		return (ENXIO);
229	}
230
231	/* Setup IRQs handler */
232	error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK,
233	    riscv_timer_intr, NULL, sc, &sc->ih);
234	if (error != 0) {
235		device_printf(dev, "Unable to setup IRQ resource\n");
236		return (ENXIO);
237	}
238
239	riscv_timer_timecount.tc_frequency = sc->clkfreq;
240	riscv_timer_timecount.tc_priv = sc;
241	tc_init(&riscv_timer_timecount);
242
243	sc->et.et_name = "RISC-V Eventtimer";
244	sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
245	sc->et.et_quality = 1000;
246
247	sc->et.et_frequency = sc->clkfreq;
248	sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
249	sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
250	sc->et.et_start = riscv_timer_et_start;
251	sc->et.et_stop = riscv_timer_et_stop;
252	sc->et.et_priv = sc;
253	et_register(&sc->et);
254
255	set_cputicker(get_timecount, sc->clkfreq, false);
256
257	return (0);
258}
259
260static device_method_t riscv_timer_methods[] = {
261	DEVMETHOD(device_probe,		riscv_timer_probe),
262	DEVMETHOD(device_attach,	riscv_timer_attach),
263	{ 0, 0 }
264};
265
266static driver_t riscv_timer_driver = {
267	"timer",
268	riscv_timer_methods,
269	sizeof(struct riscv_timer_softc),
270};
271
272EARLY_DRIVER_MODULE(timer, nexus, riscv_timer_driver, 0, 0,
273    BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
274
275void
276DELAY(int usec)
277{
278	int64_t counts, counts_per_usec;
279	uint64_t first, last;
280
281	/*
282	 * Check the timers are setup, if not just
283	 * use a for loop for the meantime
284	 */
285	if (riscv_timer_sc == NULL) {
286		for (; usec > 0; usec--)
287			for (counts = 200; counts > 0; counts--)
288				/*
289				 * Prevent the compiler from optimizing
290				 * out the loop
291				 */
292				cpufunc_nullop();
293		return;
294	}
295	TSENTER();
296
297	/* Get the number of times to count */
298	counts_per_usec = ((riscv_timer_timecount.tc_frequency / 1000000) + 1);
299
300	/*
301	 * Clamp the timeout at a maximum value (about 32 seconds with
302	 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
303	 * near that length of time and if they are, they should be hung
304	 * out to dry.
305	 */
306	if (usec >= (0x80000000U / counts_per_usec))
307		counts = (0x80000000U / counts_per_usec) - 1;
308	else
309		counts = usec * counts_per_usec;
310
311	first = get_timecount();
312
313	while (counts > 0) {
314		last = get_timecount();
315		counts -= (int64_t)(last - first);
316		first = last;
317	}
318	TSEXIT();
319}
320