1/*- 2 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 4 * Copyright (c) 2015-2016 Justin Hibbits <jhibbits@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* ATA register defines */ 30 31#define ATA_FEATURE 1 /* (W) feature */ 32#define ATA_F_DMA 0x01 /* enable DMA */ 33#define ATA_F_OVL 0x02 /* enable overlap */ 34 35#define ATA_COUNT 2 /* (W) sector count */ 36 37#define ATA_SECTOR 3 /* (RW) sector # */ 38#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 39#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 40#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 41#define ATA_D_LBA 0x40 /* use LBA addressing */ 42#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 43 44#define ATA_COMMAND 7 /* (W) command */ 45 46#define ATA_ERROR 8 /* (R) error */ 47#define ATA_E_ILI 0x01 /* illegal length */ 48#define ATA_E_NM 0x02 /* no media */ 49#define ATA_E_ABORT 0x04 /* command aborted */ 50#define ATA_E_MCR 0x08 /* media change request */ 51#define ATA_E_IDNF 0x10 /* ID not found */ 52#define ATA_E_MC 0x20 /* media changed */ 53#define ATA_E_UNC 0x40 /* uncorrectable data */ 54#define ATA_E_ICRC 0x80 /* UDMA crc error */ 55#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 56 57#define ATA_IREASON 9 /* (R) interrupt reason */ 58#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 59#define ATA_I_IN 0x02 /* read (1) | write (0) */ 60#define ATA_I_RELEASE 0x04 /* released bus (1) */ 61#define ATA_I_TAGMASK 0xf8 /* tag mask */ 62 63#define ATA_STATUS 10 /* (R) status */ 64#define ATA_ALTSTAT 11 /* (R) alternate status */ 65#define ATA_S_ERROR 0x01 /* error */ 66#define ATA_S_INDEX 0x02 /* index */ 67#define ATA_S_CORR 0x04 /* data corrected */ 68#define ATA_S_DRQ 0x08 /* data request */ 69#define ATA_S_DSC 0x10 /* drive seek completed */ 70#define ATA_S_SERVICE 0x10 /* drive needs service */ 71#define ATA_S_DWF 0x20 /* drive write fault */ 72#define ATA_S_DMA 0x20 /* DMA ready */ 73#define ATA_S_READY 0x40 /* drive ready */ 74#define ATA_S_BUSY 0x80 /* busy */ 75 76#define ATA_CONTROL 12 /* (W) control */ 77#define ATA_A_IDS 0x02 /* disable interrupts */ 78#define ATA_A_RESET 0x04 /* RESET controller */ 79#define ATA_A_4BIT 0x08 /* 4 head bits */ 80#define ATA_A_HOB 0x80 /* High Order Byte enable */ 81 82/* SATA register defines */ 83#define ATA_SSTATUS 13 84#define ATA_SS_DET_MASK 0x0000000f 85#define ATA_SS_DET_NO_DEVICE 0x00000000 86#define ATA_SS_DET_DEV_PRESENT 0x00000001 87#define ATA_SS_DET_PHY_ONLINE 0x00000003 88#define ATA_SS_DET_PHY_OFFLINE 0x00000004 89 90#define ATA_SS_SPD_MASK 0x000000f0 91#define ATA_SS_SPD_NO_SPEED 0x00000000 92#define ATA_SS_SPD_GEN1 0x00000010 93#define ATA_SS_SPD_GEN2 0x00000020 94#define ATA_SS_SPD_GEN3 0x00000030 95 96#define ATA_SS_IPM_MASK 0x00000f00 97#define ATA_SS_IPM_NO_DEVICE 0x00000000 98#define ATA_SS_IPM_ACTIVE 0x00000100 99#define ATA_SS_IPM_PARTIAL 0x00000200 100#define ATA_SS_IPM_SLUMBER 0x00000600 101#define ATA_SS_IPM_DEVSLEEP 0x00000800 102 103#define ATA_SERROR 14 104#define ATA_SE_DATA_CORRECTED 0x00000001 105#define ATA_SE_COMM_CORRECTED 0x00000002 106#define ATA_SE_DATA_ERR 0x00000100 107#define ATA_SE_COMM_ERR 0x00000200 108#define ATA_SE_PROT_ERR 0x00000400 109#define ATA_SE_HOST_ERR 0x00000800 110#define ATA_SE_PHY_CHANGED 0x00010000 111#define ATA_SE_PHY_IERROR 0x00020000 112#define ATA_SE_COMM_WAKE 0x00040000 113#define ATA_SE_DECODE_ERR 0x00080000 114#define ATA_SE_PARITY_ERR 0x00100000 115#define ATA_SE_CRC_ERR 0x00200000 116#define ATA_SE_HANDSHAKE_ERR 0x00400000 117#define ATA_SE_LINKSEQ_ERR 0x00800000 118#define ATA_SE_TRANSPORT_ERR 0x01000000 119#define ATA_SE_UNKNOWN_FIS 0x02000000 120#define ATA_SE_EXCHANGED 0x04000000 121 122#define ATA_SCONTROL 15 123#define ATA_SC_DET_MASK 0x0000000f 124#define ATA_SC_DET_IDLE 0x00000000 125#define ATA_SC_DET_RESET 0x00000001 126#define ATA_SC_DET_DISABLE 0x00000004 127 128#define ATA_SC_SPD_MASK 0x000000f0 129#define ATA_SC_SPD_NO_SPEED 0x00000000 130#define ATA_SC_SPD_SPEED_GEN1 0x00000010 131#define ATA_SC_SPD_SPEED_GEN2 0x00000020 132#define ATA_SC_SPD_SPEED_GEN3 0x00000030 133 134#define ATA_SC_IPM_MASK 0x00000f00 135#define ATA_SC_IPM_NONE 0x00000000 136#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 137#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 138#define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400 139