1/*- 2 * Copyright (C) 2006-2012 Semihalf 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 19 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 21 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 23 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25/*- 26 * Copyright (C) 2001 Benno Rice 27 * All rights reserved. 28 * 29 * Redistribution and use in source and binary forms, with or without 30 * modification, are permitted provided that the following conditions 31 * are met: 32 * 1. Redistributions of source code must retain the above copyright 33 * notice, this list of conditions and the following disclaimer. 34 * 2. Redistributions in binary form must reproduce the above copyright 35 * notice, this list of conditions and the following disclaimer in the 36 * documentation and/or other materials provided with the distribution. 37 * 38 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 39 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 40 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 41 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 43 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 44 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 45 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 46 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 47 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $ 49 */ 50/*- 51 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 52 * Copyright (C) 1995, 1996 TooLs GmbH. 53 * All rights reserved. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 3. All advertising materials mentioning features or use of this software 64 * must display the following acknowledgement: 65 * This product includes software developed by TooLs GmbH. 66 * 4. The name of TooLs GmbH may not be used to endorse or promote products 67 * derived from this software without specific prior written permission. 68 * 69 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 73 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 74 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 75 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 76 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 77 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 78 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81#include <sys/cdefs.h> 82#include "opt_ddb.h" 83#include "opt_hwpmc_hooks.h" 84#include "opt_kstack_pages.h" 85#include "opt_platform.h" 86 87#include <sys/types.h> 88#include <sys/param.h> 89#include <sys/proc.h> 90#include <sys/systm.h> 91#include <sys/time.h> 92#include <sys/bio.h> 93#include <sys/buf.h> 94#include <sys/bus.h> 95#include <sys/cons.h> 96#include <sys/cpu.h> 97#include <sys/kdb.h> 98#include <sys/kernel.h> 99#include <sys/lock.h> 100#include <sys/mutex.h> 101#include <sys/rwlock.h> 102#include <sys/sysctl.h> 103#include <sys/exec.h> 104#include <sys/ktr.h> 105#include <sys/syscallsubr.h> 106#include <sys/sysproto.h> 107#include <sys/signalvar.h> 108#include <sys/sysent.h> 109#include <sys/imgact.h> 110#include <sys/msgbuf.h> 111#include <sys/ptrace.h> 112 113#include <vm/vm.h> 114#include <vm/pmap.h> 115#include <vm/vm_extern.h> 116#include <vm/vm_page.h> 117#include <vm/vm_object.h> 118#include <vm/vm_pager.h> 119 120#include <machine/cpu.h> 121#include <machine/kdb.h> 122#include <machine/vmparam.h> 123#include <machine/spr.h> 124#include <machine/hid.h> 125#include <machine/psl.h> 126#include <machine/trap.h> 127#include <machine/md_var.h> 128#include <machine/mmuvar.h> 129#include <machine/sigframe.h> 130#include <machine/machdep.h> 131#include <machine/metadata.h> 132#include <machine/platform.h> 133 134#include <sys/linker.h> 135#include <sys/reboot.h> 136 137#include <contrib/libfdt/libfdt.h> 138#include <dev/fdt/fdt_common.h> 139#include <dev/ofw/openfirm.h> 140 141#ifdef DDB 142#include <ddb/ddb.h> 143#endif 144 145#ifdef DEBUG 146#define debugf(fmt, args...) printf(fmt, ##args) 147#else 148#define debugf(fmt, args...) 149#endif 150 151extern unsigned char _etext[]; 152extern unsigned char _edata[]; 153extern unsigned char __bss_start[]; 154extern unsigned char __sbss_start[]; 155extern unsigned char __sbss_end[]; 156extern unsigned char _end[]; 157extern vm_offset_t __endkernel; 158extern vm_paddr_t kernload; 159 160/* 161 * Bootinfo is passed to us by legacy loaders. Save the address of the 162 * structure to handle backward compatibility. 163 */ 164uint32_t *bootinfo; 165 166void print_kernel_section_addr(void); 167void print_kenv(void); 168uintptr_t booke_init(u_long, u_long); 169void ivor_setup(void); 170 171extern void *interrupt_vector_base; 172extern void *int_critical_input; 173extern void *int_machine_check; 174extern void *int_data_storage; 175extern void *int_instr_storage; 176extern void *int_external_input; 177extern void *int_alignment; 178extern void *int_fpu; 179extern void *int_program; 180extern void *int_syscall; 181extern void *int_decrementer; 182extern void *int_fixed_interval_timer; 183extern void *int_watchdog; 184extern void *int_data_tlb_error; 185extern void *int_inst_tlb_error; 186extern void *int_debug; 187extern void *int_debug_ed; 188extern void *int_vec; 189extern void *int_vecast; 190#ifdef __SPE__ 191extern void *int_spe_fpdata; 192extern void *int_spe_fpround; 193#endif 194#ifdef HWPMC_HOOKS 195extern void *int_performance_counter; 196#endif 197 198#define SET_TRAP(ivor, handler) \ 199 KASSERT(((uintptr_t)(&handler) & ~0xffffUL) == \ 200 ((uintptr_t)(&interrupt_vector_base) & ~0xffffUL), \ 201 ("Handler " #handler " too far from interrupt vector base")); \ 202 mtspr(ivor, (uintptr_t)(&handler) & 0xffffUL); 203 204uintptr_t powerpc_init(vm_offset_t fdt, vm_offset_t, vm_offset_t, void *mdp, 205 uint32_t mdp_cookie); 206void booke_cpu_init(void); 207 208void 209booke_cpu_init(void) 210{ 211 212 cpu_features |= PPC_FEATURE_BOOKE; 213 214 psl_kernset = PSL_CE | PSL_ME | PSL_EE; 215#ifdef __powerpc64__ 216 psl_kernset |= PSL_CM; 217#endif 218 psl_userset = psl_kernset | PSL_PR; 219#ifdef __powerpc64__ 220 psl_userset32 = psl_userset & ~PSL_CM; 221#endif 222 /* 223 * Zeroed bits in this variable signify that the value of the bit 224 * in its position is allowed to vary between userspace contexts. 225 * 226 * All other bits are required to be identical for every userspace 227 * context. The actual *value* of the bit is determined by 228 * psl_userset and/or psl_userset32, and is not allowed to change. 229 * 230 * Remember to update this set when implementing support for 231 * *conditionally* enabling a processor facility. Failing to do 232 * this will cause swapcontext() in userspace to break when a 233 * process uses a conditionally-enabled facility. 234 * 235 * When *unconditionally* implementing support for a processor 236 * facility, update psl_userset / psl_userset32 instead. 237 * 238 * See the access control check in set_mcontext(). 239 */ 240 psl_userstatic = ~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1); 241 242 pmap_mmu_install(MMU_TYPE_BOOKE, BUS_PROBE_GENERIC); 243} 244 245void 246ivor_setup(void) 247{ 248 249 mtspr(SPR_IVPR, ((uintptr_t)&interrupt_vector_base) & ~0xffffUL); 250 251 SET_TRAP(SPR_IVOR0, int_critical_input); 252 SET_TRAP(SPR_IVOR1, int_machine_check); 253 SET_TRAP(SPR_IVOR2, int_data_storage); 254 SET_TRAP(SPR_IVOR3, int_instr_storage); 255 SET_TRAP(SPR_IVOR4, int_external_input); 256 SET_TRAP(SPR_IVOR5, int_alignment); 257 SET_TRAP(SPR_IVOR6, int_program); 258 SET_TRAP(SPR_IVOR8, int_syscall); 259 SET_TRAP(SPR_IVOR10, int_decrementer); 260 SET_TRAP(SPR_IVOR11, int_fixed_interval_timer); 261 SET_TRAP(SPR_IVOR12, int_watchdog); 262 SET_TRAP(SPR_IVOR13, int_data_tlb_error); 263 SET_TRAP(SPR_IVOR14, int_inst_tlb_error); 264 SET_TRAP(SPR_IVOR15, int_debug); 265#ifdef HWPMC_HOOKS 266 SET_TRAP(SPR_IVOR35, int_performance_counter); 267#endif 268 switch ((mfpvr() >> 16) & 0xffff) { 269 case FSL_E6500: 270 SET_TRAP(SPR_IVOR32, int_vec); 271 SET_TRAP(SPR_IVOR33, int_vecast); 272 /* FALLTHROUGH */ 273 case FSL_E500mc: 274 case FSL_E5500: 275 SET_TRAP(SPR_IVOR7, int_fpu); 276 SET_TRAP(SPR_IVOR15, int_debug_ed); 277 break; 278 case FSL_E500v1: 279 case FSL_E500v2: 280 SET_TRAP(SPR_IVOR32, int_vec); 281#ifdef __SPE__ 282 SET_TRAP(SPR_IVOR33, int_spe_fpdata); 283 SET_TRAP(SPR_IVOR34, int_spe_fpround); 284#endif 285 break; 286 } 287 288#ifdef __powerpc64__ 289 /* Set 64-bit interrupt mode. */ 290 mtspr(SPR_EPCR, mfspr(SPR_EPCR) | EPCR_ICM); 291#endif 292} 293 294static int 295booke_check_for_fdt(uint32_t arg1, vm_offset_t *dtbp) 296{ 297 void *ptr; 298 int fdt_size; 299 300 if (arg1 % 8 != 0) 301 return (-1); 302 303 ptr = (void *)pmap_early_io_map(arg1, PAGE_SIZE); 304 if (fdt_check_header(ptr) != 0) 305 return (-1); 306 307 /* 308 * Read FDT total size from the header of FDT. 309 * This for sure hits within first page which is 310 * already mapped. 311 */ 312 fdt_size = fdt_totalsize((void *)ptr); 313 314 /* 315 * Ok, arg1 points to FDT, so we need to map it in. 316 * First, unmap this page and then map FDT again with full size 317 */ 318 pmap_early_io_unmap((vm_offset_t)ptr, PAGE_SIZE); 319 ptr = (void *)pmap_early_io_map(arg1, fdt_size); 320 *dtbp = (vm_offset_t)ptr; 321 322 return (0); 323} 324 325uintptr_t 326booke_init(u_long arg1, u_long arg2) 327{ 328 uintptr_t ret; 329 void *mdp; 330 vm_offset_t dtbp, end; 331 332 end = (uintptr_t)_end; 333 dtbp = (vm_offset_t)NULL; 334 335 /* Set up TLB initially */ 336 bootinfo = NULL; 337 bzero(__sbss_start, __sbss_end - __sbss_start); 338 bzero(__bss_start, _end - __bss_start); 339 tlb1_init(); 340 341 /* 342 * Handle the various ways we can get loaded and started: 343 * - FreeBSD's loader passes the pointer to the metadata 344 * in arg1, with arg2 undefined. arg1 has a value that's 345 * relative to the kernel's link address (i.e. larger 346 * than 0xc0000000). 347 * - Juniper's loader passes the metadata pointer in arg2 348 * and sets arg1 to zero. This is to signal that the 349 * loader maps the kernel and starts it at its link 350 * address (unlike the FreeBSD loader). 351 * - U-Boot passes the standard argc and argv parameters 352 * in arg1 and arg2 (resp). arg1 is between 1 and some 353 * relatively small number, such as 64K. arg2 is the 354 * physical address of the argv vector. 355 * - ePAPR loaders pass an FDT blob in r3 (arg1) and the magic hex 356 * string 0x45504150 ('EPAP') in r6 (which has been lost by now). 357 * r4 (arg2) is supposed to be set to zero, but is not always. 358 */ 359 360 if (arg1 == 0) /* Juniper loader */ 361 mdp = (void *)arg2; 362 else if (booke_check_for_fdt(arg1, &dtbp) == 0) { /* ePAPR */ 363 end = roundup(end, 8); 364 memmove((void *)end, (void *)dtbp, fdt_totalsize((void *)dtbp)); 365 dtbp = end; 366 end += fdt_totalsize((void *)dtbp); 367 __endkernel = end; 368 mdp = NULL; 369 } else if (arg1 > (uintptr_t)kernload) /* FreeBSD loader */ 370 mdp = (void *)arg1; 371 else /* U-Boot */ 372 mdp = NULL; 373 374 /* Default to 32 byte cache line size. */ 375 switch ((mfpvr()) >> 16) { 376 case FSL_E500mc: 377 case FSL_E5500: 378 case FSL_E6500: 379 cacheline_size = 64; 380 break; 381 } 382 383 /* 384 * Last element is a magic cookie that indicates that the metadata 385 * pointer is meaningful. 386 */ 387 ret = powerpc_init(dtbp, 0, 0, mdp, (mdp == NULL) ? 0 : 0xfb5d104d); 388 389 /* Enable caches */ 390 booke_enable_l1_cache(); 391 booke_enable_l2_cache(); 392 393 booke_enable_bpred(); 394 395 return (ret); 396} 397 398#define RES_GRANULE cacheline_size 399extern uintptr_t tlb0_miss_locks[]; 400 401/* Initialise a struct pcpu. */ 402void 403cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz) 404{ 405 406 pcpu->pc_booke.tid_next = TID_MIN; 407 408#ifdef SMP 409 uintptr_t *ptr; 410 int words_per_gran = RES_GRANULE / sizeof(uintptr_t); 411 412 ptr = &tlb0_miss_locks[cpuid * words_per_gran]; 413 pcpu->pc_booke.tlb_lock = ptr; 414 *ptr = TLB_UNLOCKED; 415 *(ptr + 1) = 0; /* recurse counter */ 416#endif 417} 418 419/* Shutdown the CPU as much as possible. */ 420void 421cpu_halt(void) 422{ 423 424 mtmsr(mfmsr() & ~(PSL_CE | PSL_EE | PSL_ME | PSL_DE)); 425 while (1) 426 ; 427} 428 429int 430ptrace_single_step(struct thread *td) 431{ 432 struct trapframe *tf; 433 434 tf = td->td_frame; 435 tf->srr1 |= PSL_DE; 436 tf->cpu.booke.dbcr0 |= (DBCR0_IDM | DBCR0_IC); 437 return (0); 438} 439 440int 441ptrace_clear_single_step(struct thread *td) 442{ 443 struct trapframe *tf; 444 445 tf = td->td_frame; 446 tf->srr1 &= ~PSL_DE; 447 tf->cpu.booke.dbcr0 &= ~(DBCR0_IDM | DBCR0_IC); 448 return (0); 449} 450 451void 452kdb_cpu_clear_singlestep(void) 453{ 454 register_t r; 455 456 r = mfspr(SPR_DBCR0); 457 mtspr(SPR_DBCR0, r & ~DBCR0_IC); 458 kdb_frame->srr1 &= ~PSL_DE; 459} 460 461void 462kdb_cpu_set_singlestep(void) 463{ 464 register_t r; 465 466 r = mfspr(SPR_DBCR0); 467 mtspr(SPR_DBCR0, r | DBCR0_IC | DBCR0_IDM); 468 kdb_frame->srr1 |= PSL_DE; 469} 470