1/*
2 * Copyright (C) 2015 Cavium Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 */
27
28#ifndef NIC_REG_H
29#define NIC_REG_H
30
31#define	NIC_PF_REG_COUNT			29573
32#define	NIC_VF_REG_COUNT			249
33
34/* Physical function register offsets */
35#define	NIC_PF_CFG				(0x0000)
36#define	NIC_PF_STATUS				(0x0010)
37#define	NIC_PF_INTR_TIMER_CFG			(0x0030)
38#define	NIC_PF_BIST_STATUS			(0x0040)
39#define	NIC_PF_SOFT_RESET			(0x0050)
40#define	NIC_PF_TCP_TIMER			(0x0060)
41#define	NIC_PF_BP_CFG				(0x0080)
42#define	NIC_PF_RRM_CFG				(0x0088)
43#define	NIC_PF_CQM_CF				(0x00A0)
44#define	NIC_PF_CNM_CF				(0x00A8)
45#define	NIC_PF_CNM_STATUS			(0x00B0)
46#define	NIC_PF_CQ_AVG_CFG			(0x00C0)
47#define	NIC_PF_RRM_AVG_CFG			(0x00C8)
48#define	NIC_PF_INTF_0_1_SEND_CFG		(0x0200)
49#define	NIC_PF_INTF_0_1_BP_CFG			(0x0208)
50#define	NIC_PF_INTF_0_1_BP_DIS_0_1		(0x0210)
51#define	NIC_PF_INTF_0_1_BP_SW_0_1		(0x0220)
52#define	NIC_PF_RBDR_BP_STATE_0_3		(0x0240)
53#define	NIC_PF_MAILBOX_INT			(0x0410)
54#define	NIC_PF_MAILBOX_INT_W1S			(0x0430)
55#define	NIC_PF_MAILBOX_ENA_W1C			(0x0450)
56#define	NIC_PF_MAILBOX_ENA_W1S			(0x0470)
57#define	NIC_PF_RX_ETYPE_0_7			(0x0500)
58#define	NIC_PF_PKIND_0_15_CFG			(0x0600)
59#define	NIC_PF_ECC0_FLIP0			(0x1000)
60#define	NIC_PF_ECC1_FLIP0			(0x1008)
61#define	NIC_PF_ECC2_FLIP0			(0x1010)
62#define	NIC_PF_ECC3_FLIP0			(0x1018)
63#define	NIC_PF_ECC0_FLIP1			(0x1080)
64#define	NIC_PF_ECC1_FLIP1			(0x1088)
65#define	NIC_PF_ECC2_FLIP1			(0x1090)
66#define	NIC_PF_ECC3_FLIP1			(0x1098)
67#define	NIC_PF_ECC0_CDIS			(0x1100)
68#define	NIC_PF_ECC1_CDIS			(0x1108)
69#define	NIC_PF_ECC2_CDIS			(0x1110)
70#define	NIC_PF_ECC3_CDIS			(0x1118)
71#define	NIC_PF_BIST0_STATUS			(0x1280)
72#define	NIC_PF_BIST1_STATUS			(0x1288)
73#define	NIC_PF_BIST2_STATUS			(0x1290)
74#define	NIC_PF_BIST3_STATUS			(0x1298)
75#define	NIC_PF_ECC0_SBE_INT			(0x2000)
76#define	NIC_PF_ECC0_SBE_INT_W1S			(0x2008)
77#define	NIC_PF_ECC0_SBE_ENA_W1C			(0x2010)
78#define	NIC_PF_ECC0_SBE_ENA_W1S			(0x2018)
79#define	NIC_PF_ECC0_DBE_INT			(0x2100)
80#define	NIC_PF_ECC0_DBE_INT_W1S			(0x2108)
81#define	NIC_PF_ECC0_DBE_ENA_W1C			(0x2110)
82#define	NIC_PF_ECC0_DBE_ENA_W1S			(0x2118)
83#define	NIC_PF_ECC1_SBE_INT			(0x2200)
84#define	NIC_PF_ECC1_SBE_INT_W1S			(0x2208)
85#define	NIC_PF_ECC1_SBE_ENA_W1C			(0x2210)
86#define	NIC_PF_ECC1_SBE_ENA_W1S			(0x2218)
87#define	NIC_PF_ECC1_DBE_INT			(0x2300)
88#define	NIC_PF_ECC1_DBE_INT_W1S			(0x2308)
89#define	NIC_PF_ECC1_DBE_ENA_W1C			(0x2310)
90#define	NIC_PF_ECC1_DBE_ENA_W1S			(0x2318)
91#define	NIC_PF_ECC2_SBE_INT			(0x2400)
92#define	NIC_PF_ECC2_SBE_INT_W1S			(0x2408)
93#define	NIC_PF_ECC2_SBE_ENA_W1C			(0x2410)
94#define	NIC_PF_ECC2_SBE_ENA_W1S			(0x2418)
95#define	NIC_PF_ECC2_DBE_INT			(0x2500)
96#define	NIC_PF_ECC2_DBE_INT_W1S			(0x2508)
97#define	NIC_PF_ECC2_DBE_ENA_W1C			(0x2510)
98#define	NIC_PF_ECC2_DBE_ENA_W1S			(0x2518)
99#define	NIC_PF_ECC3_SBE_INT			(0x2600)
100#define	NIC_PF_ECC3_SBE_INT_W1S			(0x2608)
101#define	NIC_PF_ECC3_SBE_ENA_W1C			(0x2610)
102#define	NIC_PF_ECC3_SBE_ENA_W1S			(0x2618)
103#define	NIC_PF_ECC3_DBE_INT			(0x2700)
104#define	NIC_PF_ECC3_DBE_INT_W1S			(0x2708)
105#define	NIC_PF_ECC3_DBE_ENA_W1C			(0x2710)
106#define	NIC_PF_ECC3_DBE_ENA_W1S			(0x2718)
107#define	NIC_PF_CPI_0_2047_CFG			(0x200000)
108#define	NIC_PF_MPI_0_2047_CFG			(0x210000)
109#define	NIC_PF_RSSI_0_4097_RQ			(0x220000)
110#define	NIC_PF_LMAC_0_7_CFG			(0x240000)
111#define	NIC_PF_LMAC_0_7_SW_XOFF			(0x242000)
112#define	NIC_PF_LMAC_0_7_CREDIT			(0x244000)
113#define	NIC_PF_CHAN_0_255_TX_CFG		(0x400000)
114#define	NIC_PF_CHAN_0_255_RX_CFG		(0x420000)
115#define	NIC_PF_CHAN_0_255_SW_XOFF		(0x440000)
116#define	NIC_PF_CHAN_0_255_CREDIT		(0x460000)
117#define	NIC_PF_CHAN_0_255_RX_BP_CFG		(0x480000)
118#define	NIC_PF_SW_SYNC_RX			(0x490000)
119#define	NIC_PF_SW_SYNC_RX_DONE			(0x490008)
120#define	NIC_PF_TL2_0_63_CFG			(0x500000)
121#define	NIC_PF_TL2_0_63_PRI			(0x520000)
122#define	NIC_PF_TL2_0_63_SH_STATUS		(0x580000)
123#define	NIC_PF_TL3A_0_63_CFG			(0x5F0000)
124#define	NIC_PF_TL3_0_255_CFG			(0x600000)
125#define	NIC_PF_TL3_0_255_CHAN			(0x620000)
126#define	NIC_PF_TL3_0_255_PIR			(0x640000)
127#define	NIC_PF_TL3_0_255_SW_XOFF		(0x660000)
128#define	NIC_PF_TL3_0_255_CNM_RATE		(0x680000)
129#define	NIC_PF_TL3_0_255_SH_STATUS		(0x6A0000)
130#define	NIC_PF_TL4A_0_255_CFG			(0x6F0000)
131#define	NIC_PF_TL4_0_1023_CFG			(0x800000)
132#define	NIC_PF_TL4_0_1023_SW_XOFF		(0x820000)
133#define	NIC_PF_TL4_0_1023_SH_STATUS		(0x840000)
134#define	NIC_PF_TL4A_0_1023_CNM_RATE		(0x880000)
135#define	NIC_PF_TL4A_0_1023_CNM_STATUS		(0x8A0000)
136#define	NIC_PF_VF_0_127_MAILBOX_0_1		(0x20002030)
137#define	NIC_PF_VNIC_0_127_TX_STAT_0_4		(0x20004000)
138#define	NIC_PF_VNIC_0_127_RX_STAT_0_13		(0x20004100)
139#define	NIC_PF_QSET_0_127_LOCK_0_15		(0x20006000)
140#define	NIC_PF_QSET_0_127_CFG			(0x20010000)
141#define	NIC_PF_QSET_0_127_RQ_0_7_CFG		(0x20010400)
142#define	NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG	(0x20010420)
143#define	NIC_PF_QSET_0_127_RQ_0_7_BP_CFG		(0x20010500)
144#define	NIC_PF_QSET_0_127_RQ_0_7_STAT_0_1	(0x20010600)
145#define	NIC_PF_QSET_0_127_SQ_0_7_CFG		(0x20010C00)
146#define	NIC_PF_QSET_0_127_SQ_0_7_CFG2		(0x20010C08)
147#define	NIC_PF_QSET_0_127_SQ_0_7_STAT_0_1	(0x20010D00)
148
149#define	NIC_PF_MSIX_VEC_0_18_ADDR		(0x000000)
150#define	NIC_PF_MSIX_VEC_0_CTL			(0x000008)
151#define	NIC_PF_MSIX_PBA_0			(0x0F0000)
152
153/* Virtual function register offsets */
154#define	NIC_VNIC_CFG				(0x000020)
155#define	NIC_VF_PF_MAILBOX_0_1			(0x000130)
156#define	NIC_VF_INT				(0x000200)
157#define	NIC_VF_INT_W1S				(0x000220)
158#define	NIC_VF_ENA_W1C				(0x000240)
159#define	NIC_VF_ENA_W1S				(0x000260)
160
161#define	NIC_VNIC_RSS_CFG			(0x0020E0)
162#define	NIC_VNIC_RSS_KEY_0_4			(0x002200)
163#define	NIC_VNIC_TX_STAT_0_4			(0x004000)
164#define	NIC_VNIC_RX_STAT_0_13			(0x004100)
165#define	NIC_QSET_RQ_GEN_CFG			(0x010010)
166
167#define	NIC_QSET_CQ_0_7_CFG			(0x010400)
168#define	NIC_QSET_CQ_0_7_CFG2			(0x010408)
169#define	NIC_QSET_CQ_0_7_THRESH			(0x010410)
170#define	NIC_QSET_CQ_0_7_BASE			(0x010420)
171#define	NIC_QSET_CQ_0_7_HEAD			(0x010428)
172#define	NIC_QSET_CQ_0_7_TAIL			(0x010430)
173#define	NIC_QSET_CQ_0_7_DOOR			(0x010438)
174#define	NIC_QSET_CQ_0_7_STATUS			(0x010440)
175#define	NIC_QSET_CQ_0_7_STATUS2			(0x010448)
176#define	NIC_QSET_CQ_0_7_DEBUG			(0x010450)
177
178#define	NIC_QSET_RQ_0_7_CFG			(0x010600)
179#define	NIC_QSET_RQ_0_7_STAT_0_1		(0x010700)
180
181#define	NIC_QSET_SQ_0_7_CFG			(0x010800)
182#define	NIC_QSET_SQ_0_7_THRESH			(0x010810)
183#define	NIC_QSET_SQ_0_7_BASE			(0x010820)
184#define	NIC_QSET_SQ_0_7_HEAD			(0x010828)
185#define	NIC_QSET_SQ_0_7_TAIL			(0x010830)
186#define	NIC_QSET_SQ_0_7_DOOR			(0x010838)
187#define	NIC_QSET_SQ_0_7_STATUS			(0x010840)
188#define	NIC_QSET_SQ_0_7_DEBUG			(0x010848)
189#define	NIC_QSET_SQ_0_7_CNM_CHG			(0x010860)
190#define	NIC_QSET_SQ_0_7_STAT_0_1		(0x010900)
191
192#define	NIC_QSET_RBDR_0_1_CFG			(0x010C00)
193#define	NIC_QSET_RBDR_0_1_THRESH		(0x010C10)
194#define	NIC_QSET_RBDR_0_1_BASE			(0x010C20)
195#define	NIC_QSET_RBDR_0_1_HEAD			(0x010C28)
196#define	NIC_QSET_RBDR_0_1_TAIL			(0x010C30)
197#define	NIC_QSET_RBDR_0_1_DOOR			(0x010C38)
198#define	NIC_QSET_RBDR_0_1_STATUS0		(0x010C40)
199#define	NIC_QSET_RBDR_0_1_STATUS1		(0x010C48)
200#define	NIC_QSET_RBDR_0_1_PREFETCH_STATUS	(0x010C50)
201
202#define	NIC_VF_MSIX_VECTOR_0_19_ADDR		(0x000000)
203#define	NIC_VF_MSIX_VECTOR_0_19_CTL		(0x000008)
204#define	NIC_VF_MSIX_PBA				(0x0F0000)
205
206/* Offsets within registers */
207#define	NIC_MSIX_VEC_SHIFT			4
208#define	NIC_Q_NUM_SHIFT				18
209#define	NIC_QS_ID_SHIFT				21
210#define	NIC_VF_NUM_SHIFT			21
211
212/* Port kind configuration register */
213struct pkind_cfg {
214	uint64_t minlen:16;
215	uint64_t maxlen:16;
216	uint64_t reserved_32_32:1;
217	uint64_t lenerr_en:1;
218	uint64_t rx_hdr:3;
219	uint64_t hdr_sl:5;
220	uint64_t reserved_42_63:22;
221};
222
223#endif /* NIC_REG_H */
224