1/*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35#include <sys/cdefs.h> 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#ifdef HAVE_KERNEL_OPTION_HEADERS 84#include "opt_device_polling.h" 85#endif 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/module.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96#include <sys/sysctl.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_var.h> 103#include <net/if_media.h> 104#include <net/if_types.h> 105#include <net/if_vlan_var.h> 106 107#include <net/bpf.h> 108 109#include <machine/bus.h> 110#include <machine/resource.h> 111#include <sys/bus.h> 112#include <sys/rman.h> 113 114#include <dev/mii/mii.h> 115#include <dev/mii/miivar.h> 116 117#include <dev/pci/pcireg.h> 118#include <dev/pci/pcivar.h> 119 120MODULE_DEPEND(vge, pci, 1, 1, 1); 121MODULE_DEPEND(vge, ether, 1, 1, 1); 122MODULE_DEPEND(vge, miibus, 1, 1, 1); 123 124/* "device miibus" required. See GENERIC if you get errors here. */ 125#include "miibus_if.h" 126 127#include <dev/vge/if_vgereg.h> 128#include <dev/vge/if_vgevar.h> 129 130#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 131 132/* Tunables */ 133static int msi_disable = 0; 134TUNABLE_INT("hw.vge.msi_disable", &msi_disable); 135 136/* 137 * The SQE error counter of MIB seems to report bogus value. 138 * Vendor's workaround does not seem to work on PCIe based 139 * controllers. Disable it until we find better workaround. 140 */ 141#undef VGE_ENABLE_SQEERR 142 143/* 144 * Various supported device vendors/types and their names. 145 */ 146static struct vge_type vge_devs[] = { 147 { VIA_VENDORID, VIA_DEVICEID_61XX, 148 "VIA Networking Velocity Gigabit Ethernet" }, 149 { 0, 0, NULL } 150}; 151 152static int vge_attach(device_t); 153static int vge_detach(device_t); 154static int vge_probe(device_t); 155static int vge_resume(device_t); 156static int vge_shutdown(device_t); 157static int vge_suspend(device_t); 158 159static void vge_cam_clear(struct vge_softc *); 160static int vge_cam_set(struct vge_softc *, uint8_t *); 161static void vge_clrwol(struct vge_softc *); 162static void vge_discard_rxbuf(struct vge_softc *, int); 163static int vge_dma_alloc(struct vge_softc *); 164static void vge_dma_free(struct vge_softc *); 165static void vge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 166#ifdef VGE_EEPROM 167static void vge_eeprom_getword(struct vge_softc *, int, uint16_t *); 168#endif 169static int vge_encap(struct vge_softc *, struct mbuf **); 170#ifndef __NO_STRICT_ALIGNMENT 171static __inline void 172 vge_fixup_rx(struct mbuf *); 173#endif 174static void vge_freebufs(struct vge_softc *); 175static void vge_ifmedia_sts(if_t, struct ifmediareq *); 176static int vge_ifmedia_upd(if_t); 177static int vge_ifmedia_upd_locked(struct vge_softc *); 178static void vge_init(void *); 179static void vge_init_locked(struct vge_softc *); 180static void vge_intr(void *); 181static void vge_intr_holdoff(struct vge_softc *); 182static int vge_ioctl(if_t, u_long, caddr_t); 183static void vge_link_statchg(void *); 184static int vge_miibus_readreg(device_t, int, int); 185static int vge_miibus_writereg(device_t, int, int, int); 186static void vge_miipoll_start(struct vge_softc *); 187static void vge_miipoll_stop(struct vge_softc *); 188static int vge_newbuf(struct vge_softc *, int); 189static void vge_read_eeprom(struct vge_softc *, caddr_t, int, int, int); 190static void vge_reset(struct vge_softc *); 191static int vge_rx_list_init(struct vge_softc *); 192static int vge_rxeof(struct vge_softc *, int); 193static void vge_rxfilter(struct vge_softc *); 194static void vge_setmedia(struct vge_softc *); 195static void vge_setvlan(struct vge_softc *); 196static void vge_setwol(struct vge_softc *); 197static void vge_start(if_t); 198static void vge_start_locked(if_t); 199static void vge_stats_clear(struct vge_softc *); 200static void vge_stats_update(struct vge_softc *); 201static void vge_stop(struct vge_softc *); 202static void vge_sysctl_node(struct vge_softc *); 203static int vge_tx_list_init(struct vge_softc *); 204static void vge_txeof(struct vge_softc *); 205static void vge_watchdog(void *); 206 207static device_method_t vge_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_probe, vge_probe), 210 DEVMETHOD(device_attach, vge_attach), 211 DEVMETHOD(device_detach, vge_detach), 212 DEVMETHOD(device_suspend, vge_suspend), 213 DEVMETHOD(device_resume, vge_resume), 214 DEVMETHOD(device_shutdown, vge_shutdown), 215 216 /* MII interface */ 217 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 218 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 219 220 DEVMETHOD_END 221}; 222 223static driver_t vge_driver = { 224 "vge", 225 vge_methods, 226 sizeof(struct vge_softc) 227}; 228 229DRIVER_MODULE(vge, pci, vge_driver, 0, 0); 230DRIVER_MODULE(miibus, vge, miibus_driver, 0, 0); 231 232#ifdef VGE_EEPROM 233/* 234 * Read a word of data stored in the EEPROM at address 'addr.' 235 */ 236static void 237vge_eeprom_getword(struct vge_softc *sc, int addr, uint16_t *dest) 238{ 239 int i; 240 uint16_t word = 0; 241 242 /* 243 * Enter EEPROM embedded programming mode. In order to 244 * access the EEPROM at all, we first have to set the 245 * EELOAD bit in the CHIPCFG2 register. 246 */ 247 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 248 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 249 250 /* Select the address of the word we want to read */ 251 CSR_WRITE_1(sc, VGE_EEADDR, addr); 252 253 /* Issue read command */ 254 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 255 256 /* Wait for the done bit to be set. */ 257 for (i = 0; i < VGE_TIMEOUT; i++) { 258 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 259 break; 260 } 261 262 if (i == VGE_TIMEOUT) { 263 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 264 *dest = 0; 265 return; 266 } 267 268 /* Read the result */ 269 word = CSR_READ_2(sc, VGE_EERDDAT); 270 271 /* Turn off EEPROM access mode. */ 272 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 273 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 274 275 *dest = word; 276} 277#endif 278 279/* 280 * Read a sequence of words from the EEPROM. 281 */ 282static void 283vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, int swap) 284{ 285 int i; 286#ifdef VGE_EEPROM 287 uint16_t word = 0, *ptr; 288 289 for (i = 0; i < cnt; i++) { 290 vge_eeprom_getword(sc, off + i, &word); 291 ptr = (uint16_t *)(dest + (i * 2)); 292 if (swap) 293 *ptr = ntohs(word); 294 else 295 *ptr = word; 296 } 297#else 298 for (i = 0; i < ETHER_ADDR_LEN; i++) 299 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 300#endif 301} 302 303static void 304vge_miipoll_stop(struct vge_softc *sc) 305{ 306 int i; 307 308 CSR_WRITE_1(sc, VGE_MIICMD, 0); 309 310 for (i = 0; i < VGE_TIMEOUT; i++) { 311 DELAY(1); 312 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 313 break; 314 } 315 316 if (i == VGE_TIMEOUT) 317 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 318} 319 320static void 321vge_miipoll_start(struct vge_softc *sc) 322{ 323 int i; 324 325 /* First, make sure we're idle. */ 326 327 CSR_WRITE_1(sc, VGE_MIICMD, 0); 328 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 329 330 for (i = 0; i < VGE_TIMEOUT; i++) { 331 DELAY(1); 332 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 333 break; 334 } 335 336 if (i == VGE_TIMEOUT) { 337 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 338 return; 339 } 340 341 /* Now enable auto poll mode. */ 342 343 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 344 345 /* And make sure it started. */ 346 347 for (i = 0; i < VGE_TIMEOUT; i++) { 348 DELAY(1); 349 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 350 break; 351 } 352 353 if (i == VGE_TIMEOUT) 354 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 355} 356 357static int 358vge_miibus_readreg(device_t dev, int phy, int reg) 359{ 360 struct vge_softc *sc; 361 int i; 362 uint16_t rval = 0; 363 364 sc = device_get_softc(dev); 365 366 vge_miipoll_stop(sc); 367 368 /* Specify the register we want to read. */ 369 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 370 371 /* Issue read command. */ 372 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 373 374 /* Wait for the read command bit to self-clear. */ 375 for (i = 0; i < VGE_TIMEOUT; i++) { 376 DELAY(1); 377 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 378 break; 379 } 380 381 if (i == VGE_TIMEOUT) 382 device_printf(sc->vge_dev, "MII read timed out\n"); 383 else 384 rval = CSR_READ_2(sc, VGE_MIIDATA); 385 386 vge_miipoll_start(sc); 387 388 return (rval); 389} 390 391static int 392vge_miibus_writereg(device_t dev, int phy, int reg, int data) 393{ 394 struct vge_softc *sc; 395 int i, rval = 0; 396 397 sc = device_get_softc(dev); 398 399 vge_miipoll_stop(sc); 400 401 /* Specify the register we want to write. */ 402 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 403 404 /* Specify the data we want to write. */ 405 CSR_WRITE_2(sc, VGE_MIIDATA, data); 406 407 /* Issue write command. */ 408 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 409 410 /* Wait for the write command bit to self-clear. */ 411 for (i = 0; i < VGE_TIMEOUT; i++) { 412 DELAY(1); 413 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 414 break; 415 } 416 417 if (i == VGE_TIMEOUT) { 418 device_printf(sc->vge_dev, "MII write timed out\n"); 419 rval = EIO; 420 } 421 422 vge_miipoll_start(sc); 423 424 return (rval); 425} 426 427static void 428vge_cam_clear(struct vge_softc *sc) 429{ 430 int i; 431 432 /* 433 * Turn off all the mask bits. This tells the chip 434 * that none of the entries in the CAM filter are valid. 435 * desired entries will be enabled as we fill the filter in. 436 */ 437 438 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 439 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 440 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 441 for (i = 0; i < 8; i++) 442 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 443 444 /* Clear the VLAN filter too. */ 445 446 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 447 for (i = 0; i < 8; i++) 448 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 449 450 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 451 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 452 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 453 454 sc->vge_camidx = 0; 455} 456 457static int 458vge_cam_set(struct vge_softc *sc, uint8_t *addr) 459{ 460 int i, error = 0; 461 462 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 463 return (ENOSPC); 464 465 /* Select the CAM data page. */ 466 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 467 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 468 469 /* Set the filter entry we want to update and enable writing. */ 470 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 471 472 /* Write the address to the CAM registers */ 473 for (i = 0; i < ETHER_ADDR_LEN; i++) 474 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 475 476 /* Issue a write command. */ 477 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 478 479 /* Wake for it to clear. */ 480 for (i = 0; i < VGE_TIMEOUT; i++) { 481 DELAY(1); 482 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 483 break; 484 } 485 486 if (i == VGE_TIMEOUT) { 487 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 488 error = EIO; 489 goto fail; 490 } 491 492 /* Select the CAM mask page. */ 493 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 494 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 495 496 /* Set the mask bit that enables this filter. */ 497 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 498 1<<(sc->vge_camidx & 7)); 499 500 sc->vge_camidx++; 501 502fail: 503 /* Turn off access to CAM. */ 504 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 505 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 506 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 507 508 return (error); 509} 510 511static void 512vge_setvlan(struct vge_softc *sc) 513{ 514 if_t ifp; 515 uint8_t cfg; 516 517 VGE_LOCK_ASSERT(sc); 518 519 ifp = sc->vge_ifp; 520 cfg = CSR_READ_1(sc, VGE_RXCFG); 521 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 522 cfg |= VGE_VTAG_OPT2; 523 else 524 cfg &= ~VGE_VTAG_OPT2; 525 CSR_WRITE_1(sc, VGE_RXCFG, cfg); 526} 527 528static u_int 529vge_set_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 530{ 531 struct vge_softc *sc = arg; 532 533 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 534 return (0); 535 536 (void )vge_cam_set(sc, LLADDR(sdl)); 537 538 return (1); 539} 540 541static u_int 542vge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 543{ 544 uint32_t h, *hashes = arg; 545 546 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 547 if (h < 32) 548 hashes[0] |= (1 << h); 549 else 550 hashes[1] |= (1 << (h - 32)); 551 552 return (1); 553} 554 555/* 556 * Program the multicast filter. We use the 64-entry CAM filter 557 * for perfect filtering. If there's more than 64 multicast addresses, 558 * we use the hash filter instead. 559 */ 560static void 561vge_rxfilter(struct vge_softc *sc) 562{ 563 if_t ifp; 564 uint32_t hashes[2]; 565 uint8_t rxcfg; 566 567 VGE_LOCK_ASSERT(sc); 568 569 /* First, zot all the multicast entries. */ 570 hashes[0] = 0; 571 hashes[1] = 0; 572 573 rxcfg = CSR_READ_1(sc, VGE_RXCTL); 574 rxcfg &= ~(VGE_RXCTL_RX_MCAST | VGE_RXCTL_RX_BCAST | 575 VGE_RXCTL_RX_PROMISC); 576 /* 577 * Always allow VLAN oversized frames and frames for 578 * this host. 579 */ 580 rxcfg |= VGE_RXCTL_RX_GIANT | VGE_RXCTL_RX_UCAST; 581 582 ifp = sc->vge_ifp; 583 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 584 rxcfg |= VGE_RXCTL_RX_BCAST; 585 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 586 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 587 rxcfg |= VGE_RXCTL_RX_PROMISC; 588 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) { 589 hashes[0] = 0xFFFFFFFF; 590 hashes[1] = 0xFFFFFFFF; 591 } 592 goto done; 593 } 594 595 vge_cam_clear(sc); 596 597 /* Now program new ones */ 598 if_foreach_llmaddr(ifp, vge_set_maddr, sc); 599 600 /* If there were too many addresses, use the hash filter. */ 601 if (sc->vge_camidx == VGE_CAM_MAXADDRS) { 602 vge_cam_clear(sc); 603 if_foreach_llmaddr(ifp, vge_hash_maddr, hashes); 604 } 605 606done: 607 if (hashes[0] != 0 || hashes[1] != 0) 608 rxcfg |= VGE_RXCTL_RX_MCAST; 609 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 610 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 611 CSR_WRITE_1(sc, VGE_RXCTL, rxcfg); 612} 613 614static void 615vge_reset(struct vge_softc *sc) 616{ 617 int i; 618 619 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 620 621 for (i = 0; i < VGE_TIMEOUT; i++) { 622 DELAY(5); 623 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 624 break; 625 } 626 627 if (i == VGE_TIMEOUT) { 628 device_printf(sc->vge_dev, "soft reset timed out\n"); 629 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 630 DELAY(2000); 631 } 632 633 DELAY(5000); 634} 635 636/* 637 * Probe for a VIA gigabit chip. Check the PCI vendor and device 638 * IDs against our list and return a device name if we find a match. 639 */ 640static int 641vge_probe(device_t dev) 642{ 643 struct vge_type *t; 644 645 t = vge_devs; 646 647 while (t->vge_name != NULL) { 648 if ((pci_get_vendor(dev) == t->vge_vid) && 649 (pci_get_device(dev) == t->vge_did)) { 650 device_set_desc(dev, t->vge_name); 651 return (BUS_PROBE_DEFAULT); 652 } 653 t++; 654 } 655 656 return (ENXIO); 657} 658 659/* 660 * Map a single buffer address. 661 */ 662 663struct vge_dmamap_arg { 664 bus_addr_t vge_busaddr; 665}; 666 667static void 668vge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 669{ 670 struct vge_dmamap_arg *ctx; 671 672 if (error != 0) 673 return; 674 675 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 676 677 ctx = (struct vge_dmamap_arg *)arg; 678 ctx->vge_busaddr = segs[0].ds_addr; 679} 680 681static int 682vge_dma_alloc(struct vge_softc *sc) 683{ 684 struct vge_dmamap_arg ctx; 685 struct vge_txdesc *txd; 686 struct vge_rxdesc *rxd; 687 bus_addr_t lowaddr, tx_ring_end, rx_ring_end; 688 int error, i; 689 690 /* 691 * It seems old PCI controllers do not support DAC. DAC 692 * configuration can be enabled by accessing VGE_CHIPCFG3 693 * register but honor EEPROM configuration instead of 694 * blindly overriding DAC configuration. PCIe based 695 * controllers are supposed to support 64bit DMA so enable 696 * 64bit DMA on these controllers. 697 */ 698 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) 699 lowaddr = BUS_SPACE_MAXADDR; 700 else 701 lowaddr = BUS_SPACE_MAXADDR_32BIT; 702 703again: 704 /* Create parent ring tag. */ 705 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 706 1, 0, /* algnmnt, boundary */ 707 lowaddr, /* lowaddr */ 708 BUS_SPACE_MAXADDR, /* highaddr */ 709 NULL, NULL, /* filter, filterarg */ 710 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 711 0, /* nsegments */ 712 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 713 0, /* flags */ 714 NULL, NULL, /* lockfunc, lockarg */ 715 &sc->vge_cdata.vge_ring_tag); 716 if (error != 0) { 717 device_printf(sc->vge_dev, 718 "could not create parent DMA tag.\n"); 719 goto fail; 720 } 721 722 /* Create tag for Tx ring. */ 723 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 724 VGE_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 725 BUS_SPACE_MAXADDR, /* lowaddr */ 726 BUS_SPACE_MAXADDR, /* highaddr */ 727 NULL, NULL, /* filter, filterarg */ 728 VGE_TX_LIST_SZ, /* maxsize */ 729 1, /* nsegments */ 730 VGE_TX_LIST_SZ, /* maxsegsize */ 731 0, /* flags */ 732 NULL, NULL, /* lockfunc, lockarg */ 733 &sc->vge_cdata.vge_tx_ring_tag); 734 if (error != 0) { 735 device_printf(sc->vge_dev, 736 "could not allocate Tx ring DMA tag.\n"); 737 goto fail; 738 } 739 740 /* Create tag for Rx ring. */ 741 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 742 VGE_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 743 BUS_SPACE_MAXADDR, /* lowaddr */ 744 BUS_SPACE_MAXADDR, /* highaddr */ 745 NULL, NULL, /* filter, filterarg */ 746 VGE_RX_LIST_SZ, /* maxsize */ 747 1, /* nsegments */ 748 VGE_RX_LIST_SZ, /* maxsegsize */ 749 0, /* flags */ 750 NULL, NULL, /* lockfunc, lockarg */ 751 &sc->vge_cdata.vge_rx_ring_tag); 752 if (error != 0) { 753 device_printf(sc->vge_dev, 754 "could not allocate Rx ring DMA tag.\n"); 755 goto fail; 756 } 757 758 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 759 error = bus_dmamem_alloc(sc->vge_cdata.vge_tx_ring_tag, 760 (void **)&sc->vge_rdata.vge_tx_ring, 761 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 762 &sc->vge_cdata.vge_tx_ring_map); 763 if (error != 0) { 764 device_printf(sc->vge_dev, 765 "could not allocate DMA'able memory for Tx ring.\n"); 766 goto fail; 767 } 768 769 ctx.vge_busaddr = 0; 770 error = bus_dmamap_load(sc->vge_cdata.vge_tx_ring_tag, 771 sc->vge_cdata.vge_tx_ring_map, sc->vge_rdata.vge_tx_ring, 772 VGE_TX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 773 if (error != 0 || ctx.vge_busaddr == 0) { 774 device_printf(sc->vge_dev, 775 "could not load DMA'able memory for Tx ring.\n"); 776 goto fail; 777 } 778 sc->vge_rdata.vge_tx_ring_paddr = ctx.vge_busaddr; 779 780 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 781 error = bus_dmamem_alloc(sc->vge_cdata.vge_rx_ring_tag, 782 (void **)&sc->vge_rdata.vge_rx_ring, 783 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 784 &sc->vge_cdata.vge_rx_ring_map); 785 if (error != 0) { 786 device_printf(sc->vge_dev, 787 "could not allocate DMA'able memory for Rx ring.\n"); 788 goto fail; 789 } 790 791 ctx.vge_busaddr = 0; 792 error = bus_dmamap_load(sc->vge_cdata.vge_rx_ring_tag, 793 sc->vge_cdata.vge_rx_ring_map, sc->vge_rdata.vge_rx_ring, 794 VGE_RX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 795 if (error != 0 || ctx.vge_busaddr == 0) { 796 device_printf(sc->vge_dev, 797 "could not load DMA'able memory for Rx ring.\n"); 798 goto fail; 799 } 800 sc->vge_rdata.vge_rx_ring_paddr = ctx.vge_busaddr; 801 802 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 803 tx_ring_end = sc->vge_rdata.vge_tx_ring_paddr + VGE_TX_LIST_SZ; 804 rx_ring_end = sc->vge_rdata.vge_rx_ring_paddr + VGE_RX_LIST_SZ; 805 if ((VGE_ADDR_HI(tx_ring_end) != 806 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)) || 807 (VGE_ADDR_HI(rx_ring_end) != 808 VGE_ADDR_HI(sc->vge_rdata.vge_rx_ring_paddr)) || 809 VGE_ADDR_HI(tx_ring_end) != VGE_ADDR_HI(rx_ring_end)) { 810 device_printf(sc->vge_dev, "4GB boundary crossed, " 811 "switching to 32bit DMA address mode.\n"); 812 vge_dma_free(sc); 813 /* Limit DMA address space to 32bit and try again. */ 814 lowaddr = BUS_SPACE_MAXADDR_32BIT; 815 goto again; 816 } 817 818 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) 819 lowaddr = VGE_BUF_DMA_MAXADDR; 820 else 821 lowaddr = BUS_SPACE_MAXADDR_32BIT; 822 /* Create parent buffer tag. */ 823 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 824 1, 0, /* algnmnt, boundary */ 825 lowaddr, /* lowaddr */ 826 BUS_SPACE_MAXADDR, /* highaddr */ 827 NULL, NULL, /* filter, filterarg */ 828 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 829 0, /* nsegments */ 830 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 831 0, /* flags */ 832 NULL, NULL, /* lockfunc, lockarg */ 833 &sc->vge_cdata.vge_buffer_tag); 834 if (error != 0) { 835 device_printf(sc->vge_dev, 836 "could not create parent buffer DMA tag.\n"); 837 goto fail; 838 } 839 840 /* Create tag for Tx buffers. */ 841 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 842 1, 0, /* algnmnt, boundary */ 843 BUS_SPACE_MAXADDR, /* lowaddr */ 844 BUS_SPACE_MAXADDR, /* highaddr */ 845 NULL, NULL, /* filter, filterarg */ 846 MCLBYTES * VGE_MAXTXSEGS, /* maxsize */ 847 VGE_MAXTXSEGS, /* nsegments */ 848 MCLBYTES, /* maxsegsize */ 849 0, /* flags */ 850 NULL, NULL, /* lockfunc, lockarg */ 851 &sc->vge_cdata.vge_tx_tag); 852 if (error != 0) { 853 device_printf(sc->vge_dev, "could not create Tx DMA tag.\n"); 854 goto fail; 855 } 856 857 /* Create tag for Rx buffers. */ 858 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 859 VGE_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 860 BUS_SPACE_MAXADDR, /* lowaddr */ 861 BUS_SPACE_MAXADDR, /* highaddr */ 862 NULL, NULL, /* filter, filterarg */ 863 MCLBYTES, /* maxsize */ 864 1, /* nsegments */ 865 MCLBYTES, /* maxsegsize */ 866 0, /* flags */ 867 NULL, NULL, /* lockfunc, lockarg */ 868 &sc->vge_cdata.vge_rx_tag); 869 if (error != 0) { 870 device_printf(sc->vge_dev, "could not create Rx DMA tag.\n"); 871 goto fail; 872 } 873 874 /* Create DMA maps for Tx buffers. */ 875 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 876 txd = &sc->vge_cdata.vge_txdesc[i]; 877 txd->tx_m = NULL; 878 txd->tx_dmamap = NULL; 879 error = bus_dmamap_create(sc->vge_cdata.vge_tx_tag, 0, 880 &txd->tx_dmamap); 881 if (error != 0) { 882 device_printf(sc->vge_dev, 883 "could not create Tx dmamap.\n"); 884 goto fail; 885 } 886 } 887 /* Create DMA maps for Rx buffers. */ 888 if ((error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 889 &sc->vge_cdata.vge_rx_sparemap)) != 0) { 890 device_printf(sc->vge_dev, 891 "could not create spare Rx dmamap.\n"); 892 goto fail; 893 } 894 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 895 rxd = &sc->vge_cdata.vge_rxdesc[i]; 896 rxd->rx_m = NULL; 897 rxd->rx_dmamap = NULL; 898 error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 899 &rxd->rx_dmamap); 900 if (error != 0) { 901 device_printf(sc->vge_dev, 902 "could not create Rx dmamap.\n"); 903 goto fail; 904 } 905 } 906 907fail: 908 return (error); 909} 910 911static void 912vge_dma_free(struct vge_softc *sc) 913{ 914 struct vge_txdesc *txd; 915 struct vge_rxdesc *rxd; 916 int i; 917 918 /* Tx ring. */ 919 if (sc->vge_cdata.vge_tx_ring_tag != NULL) { 920 if (sc->vge_rdata.vge_tx_ring_paddr) 921 bus_dmamap_unload(sc->vge_cdata.vge_tx_ring_tag, 922 sc->vge_cdata.vge_tx_ring_map); 923 if (sc->vge_rdata.vge_tx_ring) 924 bus_dmamem_free(sc->vge_cdata.vge_tx_ring_tag, 925 sc->vge_rdata.vge_tx_ring, 926 sc->vge_cdata.vge_tx_ring_map); 927 sc->vge_rdata.vge_tx_ring = NULL; 928 sc->vge_rdata.vge_tx_ring_paddr = 0; 929 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_ring_tag); 930 sc->vge_cdata.vge_tx_ring_tag = NULL; 931 } 932 /* Rx ring. */ 933 if (sc->vge_cdata.vge_rx_ring_tag != NULL) { 934 if (sc->vge_rdata.vge_rx_ring_paddr) 935 bus_dmamap_unload(sc->vge_cdata.vge_rx_ring_tag, 936 sc->vge_cdata.vge_rx_ring_map); 937 if (sc->vge_rdata.vge_rx_ring) 938 bus_dmamem_free(sc->vge_cdata.vge_rx_ring_tag, 939 sc->vge_rdata.vge_rx_ring, 940 sc->vge_cdata.vge_rx_ring_map); 941 sc->vge_rdata.vge_rx_ring = NULL; 942 sc->vge_rdata.vge_rx_ring_paddr = 0; 943 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_ring_tag); 944 sc->vge_cdata.vge_rx_ring_tag = NULL; 945 } 946 /* Tx buffers. */ 947 if (sc->vge_cdata.vge_tx_tag != NULL) { 948 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 949 txd = &sc->vge_cdata.vge_txdesc[i]; 950 if (txd->tx_dmamap != NULL) { 951 bus_dmamap_destroy(sc->vge_cdata.vge_tx_tag, 952 txd->tx_dmamap); 953 txd->tx_dmamap = NULL; 954 } 955 } 956 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_tag); 957 sc->vge_cdata.vge_tx_tag = NULL; 958 } 959 /* Rx buffers. */ 960 if (sc->vge_cdata.vge_rx_tag != NULL) { 961 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 962 rxd = &sc->vge_cdata.vge_rxdesc[i]; 963 if (rxd->rx_dmamap != NULL) { 964 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 965 rxd->rx_dmamap); 966 rxd->rx_dmamap = NULL; 967 } 968 } 969 if (sc->vge_cdata.vge_rx_sparemap != NULL) { 970 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 971 sc->vge_cdata.vge_rx_sparemap); 972 sc->vge_cdata.vge_rx_sparemap = NULL; 973 } 974 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_tag); 975 sc->vge_cdata.vge_rx_tag = NULL; 976 } 977 978 if (sc->vge_cdata.vge_buffer_tag != NULL) { 979 bus_dma_tag_destroy(sc->vge_cdata.vge_buffer_tag); 980 sc->vge_cdata.vge_buffer_tag = NULL; 981 } 982 if (sc->vge_cdata.vge_ring_tag != NULL) { 983 bus_dma_tag_destroy(sc->vge_cdata.vge_ring_tag); 984 sc->vge_cdata.vge_ring_tag = NULL; 985 } 986} 987 988/* 989 * Attach the interface. Allocate softc structures, do ifmedia 990 * setup and ethernet/BPF attach. 991 */ 992static int 993vge_attach(device_t dev) 994{ 995 u_char eaddr[ETHER_ADDR_LEN]; 996 struct vge_softc *sc; 997 if_t ifp; 998 int error = 0, cap, i, msic, rid; 999 1000 sc = device_get_softc(dev); 1001 sc->vge_dev = dev; 1002 1003 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1004 MTX_DEF); 1005 callout_init_mtx(&sc->vge_watchdog, &sc->vge_mtx, 0); 1006 1007 /* 1008 * Map control/status registers. 1009 */ 1010 pci_enable_busmaster(dev); 1011 1012 rid = PCIR_BAR(1); 1013 sc->vge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1014 RF_ACTIVE); 1015 1016 if (sc->vge_res == NULL) { 1017 device_printf(dev, "couldn't map ports/memory\n"); 1018 error = ENXIO; 1019 goto fail; 1020 } 1021 1022 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { 1023 sc->vge_flags |= VGE_FLAG_PCIE; 1024 sc->vge_expcap = cap; 1025 } else 1026 sc->vge_flags |= VGE_FLAG_JUMBO; 1027 if (pci_find_cap(dev, PCIY_PMG, &cap) == 0) { 1028 sc->vge_flags |= VGE_FLAG_PMCAP; 1029 sc->vge_pmcap = cap; 1030 } 1031 rid = 0; 1032 msic = pci_msi_count(dev); 1033 if (msi_disable == 0 && msic > 0) { 1034 msic = 1; 1035 if (pci_alloc_msi(dev, &msic) == 0) { 1036 if (msic == 1) { 1037 sc->vge_flags |= VGE_FLAG_MSI; 1038 device_printf(dev, "Using %d MSI message\n", 1039 msic); 1040 rid = 1; 1041 } else 1042 pci_release_msi(dev); 1043 } 1044 } 1045 1046 /* Allocate interrupt */ 1047 sc->vge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1048 ((sc->vge_flags & VGE_FLAG_MSI) ? 0 : RF_SHAREABLE) | RF_ACTIVE); 1049 if (sc->vge_irq == NULL) { 1050 device_printf(dev, "couldn't map interrupt\n"); 1051 error = ENXIO; 1052 goto fail; 1053 } 1054 1055 /* Reset the adapter. */ 1056 vge_reset(sc); 1057 /* Reload EEPROM. */ 1058 CSR_WRITE_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 1059 for (i = 0; i < VGE_TIMEOUT; i++) { 1060 DELAY(5); 1061 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 1062 break; 1063 } 1064 if (i == VGE_TIMEOUT) 1065 device_printf(dev, "EEPROM reload timed out\n"); 1066 /* 1067 * Clear PACPI as EEPROM reload will set the bit. Otherwise 1068 * MAC will receive magic packet which in turn confuses 1069 * controller. 1070 */ 1071 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 1072 1073 /* 1074 * Get station address from the EEPROM. 1075 */ 1076 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 1077 /* 1078 * Save configured PHY address. 1079 * It seems the PHY address of PCIe controllers just 1080 * reflects media jump strapping status so we assume the 1081 * internal PHY address of PCIe controller is at 1. 1082 */ 1083 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) 1084 sc->vge_phyaddr = 1; 1085 else 1086 sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) & 1087 VGE_MIICFG_PHYADDR; 1088 /* Clear WOL and take hardware from powerdown. */ 1089 vge_clrwol(sc); 1090 vge_sysctl_node(sc); 1091 error = vge_dma_alloc(sc); 1092 if (error) 1093 goto fail; 1094 1095 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 1096 if (ifp == NULL) { 1097 device_printf(dev, "can not if_alloc()\n"); 1098 error = ENOSPC; 1099 goto fail; 1100 } 1101 1102 vge_miipoll_start(sc); 1103 /* Do MII setup */ 1104 error = mii_attach(dev, &sc->vge_miibus, ifp, vge_ifmedia_upd, 1105 vge_ifmedia_sts, BMSR_DEFCAPMASK, sc->vge_phyaddr, MII_OFFSET_ANY, 1106 MIIF_DOPAUSE); 1107 if (error != 0) { 1108 device_printf(dev, "attaching PHYs failed\n"); 1109 goto fail; 1110 } 1111 1112 if_setsoftc(ifp, sc); 1113 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1114 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1115 if_setioctlfn(ifp, vge_ioctl); 1116 if_setcapabilities(ifp, IFCAP_VLAN_MTU); 1117 if_setstartfn(ifp, vge_start); 1118 if_sethwassist(ifp, VGE_CSUM_FEATURES); 1119 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 1120 IFCAP_VLAN_HWTAGGING, 0); 1121 if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0) 1122 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0); 1123 if_setcapenable(ifp, if_getcapabilities(ifp)); 1124#ifdef DEVICE_POLLING 1125 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 1126#endif 1127 if_setinitfn(ifp, vge_init); 1128 if_setsendqlen(ifp, VGE_TX_DESC_CNT - 1); 1129 if_setsendqready(ifp); 1130 1131 /* 1132 * Call MI attach routine. 1133 */ 1134 ether_ifattach(ifp, eaddr); 1135 1136 /* Tell the upper layer(s) we support long frames. */ 1137 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1138 1139 /* Hook interrupt last to avoid having to lock softc */ 1140 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1141 NULL, vge_intr, sc, &sc->vge_intrhand); 1142 1143 if (error) { 1144 device_printf(dev, "couldn't set up irq\n"); 1145 ether_ifdetach(ifp); 1146 goto fail; 1147 } 1148 1149fail: 1150 if (error) 1151 vge_detach(dev); 1152 1153 return (error); 1154} 1155 1156/* 1157 * Shutdown hardware and free up resources. This can be called any 1158 * time after the mutex has been initialized. It is called in both 1159 * the error case in attach and the normal detach case so it needs 1160 * to be careful about only freeing resources that have actually been 1161 * allocated. 1162 */ 1163static int 1164vge_detach(device_t dev) 1165{ 1166 struct vge_softc *sc; 1167 if_t ifp; 1168 1169 sc = device_get_softc(dev); 1170 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1171 ifp = sc->vge_ifp; 1172 1173#ifdef DEVICE_POLLING 1174 if (if_getcapenable(ifp) & IFCAP_POLLING) 1175 ether_poll_deregister(ifp); 1176#endif 1177 1178 /* These should only be active if attach succeeded */ 1179 if (device_is_attached(dev)) { 1180 ether_ifdetach(ifp); 1181 VGE_LOCK(sc); 1182 vge_stop(sc); 1183 VGE_UNLOCK(sc); 1184 callout_drain(&sc->vge_watchdog); 1185 } 1186 if (sc->vge_miibus) 1187 device_delete_child(dev, sc->vge_miibus); 1188 bus_generic_detach(dev); 1189 1190 if (sc->vge_intrhand) 1191 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1192 if (sc->vge_irq) 1193 bus_release_resource(dev, SYS_RES_IRQ, 1194 sc->vge_flags & VGE_FLAG_MSI ? 1 : 0, sc->vge_irq); 1195 if (sc->vge_flags & VGE_FLAG_MSI) 1196 pci_release_msi(dev); 1197 if (sc->vge_res) 1198 bus_release_resource(dev, SYS_RES_MEMORY, 1199 PCIR_BAR(1), sc->vge_res); 1200 if (ifp) 1201 if_free(ifp); 1202 1203 vge_dma_free(sc); 1204 mtx_destroy(&sc->vge_mtx); 1205 1206 return (0); 1207} 1208 1209static void 1210vge_discard_rxbuf(struct vge_softc *sc, int prod) 1211{ 1212 struct vge_rxdesc *rxd; 1213 int i; 1214 1215 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1216 rxd->rx_desc->vge_sts = 0; 1217 rxd->rx_desc->vge_ctl = 0; 1218 1219 /* 1220 * Note: the manual fails to document the fact that for 1221 * proper operation, the driver needs to replentish the RX 1222 * DMA ring 4 descriptors at a time (rather than one at a 1223 * time, like most chips). We can allocate the new buffers 1224 * but we should not set the OWN bits until we're ready 1225 * to hand back 4 of them in one shot. 1226 */ 1227 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1228 for (i = VGE_RXCHUNK; i > 0; i--) { 1229 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1230 rxd = rxd->rxd_prev; 1231 } 1232 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1233 } 1234} 1235 1236static int 1237vge_newbuf(struct vge_softc *sc, int prod) 1238{ 1239 struct vge_rxdesc *rxd; 1240 struct mbuf *m; 1241 bus_dma_segment_t segs[1]; 1242 bus_dmamap_t map; 1243 int i, nsegs; 1244 1245 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1246 if (m == NULL) 1247 return (ENOBUFS); 1248 /* 1249 * This is part of an evil trick to deal with strict-alignment 1250 * architectures. The VIA chip requires RX buffers to be aligned 1251 * on 32-bit boundaries, but that will hose strict-alignment 1252 * architectures. To get around this, we leave some empty space 1253 * at the start of each buffer and for non-strict-alignment hosts, 1254 * we copy the buffer back two bytes to achieve word alignment. 1255 * This is slightly more efficient than allocating a new buffer, 1256 * copying the contents, and discarding the old buffer. 1257 */ 1258 m->m_len = m->m_pkthdr.len = MCLBYTES; 1259 m_adj(m, VGE_RX_BUF_ALIGN); 1260 1261 if (bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_rx_tag, 1262 sc->vge_cdata.vge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1263 m_freem(m); 1264 return (ENOBUFS); 1265 } 1266 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1267 1268 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1269 if (rxd->rx_m != NULL) { 1270 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1271 BUS_DMASYNC_POSTREAD); 1272 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap); 1273 } 1274 map = rxd->rx_dmamap; 1275 rxd->rx_dmamap = sc->vge_cdata.vge_rx_sparemap; 1276 sc->vge_cdata.vge_rx_sparemap = map; 1277 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1278 BUS_DMASYNC_PREREAD); 1279 rxd->rx_m = m; 1280 1281 rxd->rx_desc->vge_sts = 0; 1282 rxd->rx_desc->vge_ctl = 0; 1283 rxd->rx_desc->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 1284 rxd->rx_desc->vge_addrhi = htole32(VGE_ADDR_HI(segs[0].ds_addr) | 1285 (VGE_BUFLEN(segs[0].ds_len) << 16) | VGE_RXDESC_I); 1286 1287 /* 1288 * Note: the manual fails to document the fact that for 1289 * proper operation, the driver needs to replenish the RX 1290 * DMA ring 4 descriptors at a time (rather than one at a 1291 * time, like most chips). We can allocate the new buffers 1292 * but we should not set the OWN bits until we're ready 1293 * to hand back 4 of them in one shot. 1294 */ 1295 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1296 for (i = VGE_RXCHUNK; i > 0; i--) { 1297 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1298 rxd = rxd->rxd_prev; 1299 } 1300 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1301 } 1302 1303 return (0); 1304} 1305 1306static int 1307vge_tx_list_init(struct vge_softc *sc) 1308{ 1309 struct vge_ring_data *rd; 1310 struct vge_txdesc *txd; 1311 int i; 1312 1313 VGE_LOCK_ASSERT(sc); 1314 1315 sc->vge_cdata.vge_tx_prodidx = 0; 1316 sc->vge_cdata.vge_tx_considx = 0; 1317 sc->vge_cdata.vge_tx_cnt = 0; 1318 1319 rd = &sc->vge_rdata; 1320 bzero(rd->vge_tx_ring, VGE_TX_LIST_SZ); 1321 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1322 txd = &sc->vge_cdata.vge_txdesc[i]; 1323 txd->tx_m = NULL; 1324 txd->tx_desc = &rd->vge_tx_ring[i]; 1325 } 1326 1327 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1328 sc->vge_cdata.vge_tx_ring_map, 1329 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1330 1331 return (0); 1332} 1333 1334static int 1335vge_rx_list_init(struct vge_softc *sc) 1336{ 1337 struct vge_ring_data *rd; 1338 struct vge_rxdesc *rxd; 1339 int i; 1340 1341 VGE_LOCK_ASSERT(sc); 1342 1343 sc->vge_cdata.vge_rx_prodidx = 0; 1344 sc->vge_cdata.vge_head = NULL; 1345 sc->vge_cdata.vge_tail = NULL; 1346 sc->vge_cdata.vge_rx_commit = 0; 1347 1348 rd = &sc->vge_rdata; 1349 bzero(rd->vge_rx_ring, VGE_RX_LIST_SZ); 1350 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1351 rxd = &sc->vge_cdata.vge_rxdesc[i]; 1352 rxd->rx_m = NULL; 1353 rxd->rx_desc = &rd->vge_rx_ring[i]; 1354 if (i == 0) 1355 rxd->rxd_prev = 1356 &sc->vge_cdata.vge_rxdesc[VGE_RX_DESC_CNT - 1]; 1357 else 1358 rxd->rxd_prev = &sc->vge_cdata.vge_rxdesc[i - 1]; 1359 if (vge_newbuf(sc, i) != 0) 1360 return (ENOBUFS); 1361 } 1362 1363 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1364 sc->vge_cdata.vge_rx_ring_map, 1365 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1366 1367 sc->vge_cdata.vge_rx_commit = 0; 1368 1369 return (0); 1370} 1371 1372static void 1373vge_freebufs(struct vge_softc *sc) 1374{ 1375 struct vge_txdesc *txd; 1376 struct vge_rxdesc *rxd; 1377 if_t ifp; 1378 int i; 1379 1380 VGE_LOCK_ASSERT(sc); 1381 1382 ifp = sc->vge_ifp; 1383 /* 1384 * Free RX and TX mbufs still in the queues. 1385 */ 1386 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1387 rxd = &sc->vge_cdata.vge_rxdesc[i]; 1388 if (rxd->rx_m != NULL) { 1389 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, 1390 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 1391 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, 1392 rxd->rx_dmamap); 1393 m_freem(rxd->rx_m); 1394 rxd->rx_m = NULL; 1395 } 1396 } 1397 1398 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1399 txd = &sc->vge_cdata.vge_txdesc[i]; 1400 if (txd->tx_m != NULL) { 1401 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, 1402 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1403 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, 1404 txd->tx_dmamap); 1405 m_freem(txd->tx_m); 1406 txd->tx_m = NULL; 1407 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1408 } 1409 } 1410} 1411 1412#ifndef __NO_STRICT_ALIGNMENT 1413static __inline void 1414vge_fixup_rx(struct mbuf *m) 1415{ 1416 int i; 1417 uint16_t *src, *dst; 1418 1419 src = mtod(m, uint16_t *); 1420 dst = src - 1; 1421 1422 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1423 *dst++ = *src++; 1424 1425 m->m_data -= ETHER_ALIGN; 1426} 1427#endif 1428 1429/* 1430 * RX handler. We support the reception of jumbo frames that have 1431 * been fragmented across multiple 2K mbuf cluster buffers. 1432 */ 1433static int 1434vge_rxeof(struct vge_softc *sc, int count) 1435{ 1436 struct mbuf *m; 1437 if_t ifp; 1438 int prod, prog, total_len; 1439 struct vge_rxdesc *rxd; 1440 struct vge_rx_desc *cur_rx; 1441 uint32_t rxstat, rxctl; 1442 1443 VGE_LOCK_ASSERT(sc); 1444 1445 ifp = sc->vge_ifp; 1446 1447 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1448 sc->vge_cdata.vge_rx_ring_map, 1449 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1450 1451 prod = sc->vge_cdata.vge_rx_prodidx; 1452 for (prog = 0; count > 0 && 1453 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; 1454 VGE_RX_DESC_INC(prod)) { 1455 cur_rx = &sc->vge_rdata.vge_rx_ring[prod]; 1456 rxstat = le32toh(cur_rx->vge_sts); 1457 if ((rxstat & VGE_RDSTS_OWN) != 0) 1458 break; 1459 count--; 1460 prog++; 1461 rxctl = le32toh(cur_rx->vge_ctl); 1462 total_len = VGE_RXBYTES(rxstat); 1463 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1464 m = rxd->rx_m; 1465 1466 /* 1467 * If the 'start of frame' bit is set, this indicates 1468 * either the first fragment in a multi-fragment receive, 1469 * or an intermediate fragment. Either way, we want to 1470 * accumulate the buffers. 1471 */ 1472 if ((rxstat & VGE_RXPKT_SOF) != 0) { 1473 if (vge_newbuf(sc, prod) != 0) { 1474 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1475 VGE_CHAIN_RESET(sc); 1476 vge_discard_rxbuf(sc, prod); 1477 continue; 1478 } 1479 m->m_len = MCLBYTES - VGE_RX_BUF_ALIGN; 1480 if (sc->vge_cdata.vge_head == NULL) { 1481 sc->vge_cdata.vge_head = m; 1482 sc->vge_cdata.vge_tail = m; 1483 } else { 1484 m->m_flags &= ~M_PKTHDR; 1485 sc->vge_cdata.vge_tail->m_next = m; 1486 sc->vge_cdata.vge_tail = m; 1487 } 1488 continue; 1489 } 1490 1491 /* 1492 * Bad/error frames will have the RXOK bit cleared. 1493 * However, there's one error case we want to allow: 1494 * if a VLAN tagged frame arrives and the chip can't 1495 * match it against the CAM filter, it considers this 1496 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1497 * We don't want to drop the frame though: our VLAN 1498 * filtering is done in software. 1499 * We also want to receive bad-checksummed frames and 1500 * and frames with bad-length. 1501 */ 1502 if ((rxstat & VGE_RDSTS_RXOK) == 0 && 1503 (rxstat & (VGE_RDSTS_VIDM | VGE_RDSTS_RLERR | 1504 VGE_RDSTS_CSUMERR)) == 0) { 1505 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1506 /* 1507 * If this is part of a multi-fragment packet, 1508 * discard all the pieces. 1509 */ 1510 VGE_CHAIN_RESET(sc); 1511 vge_discard_rxbuf(sc, prod); 1512 continue; 1513 } 1514 1515 if (vge_newbuf(sc, prod) != 0) { 1516 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1517 VGE_CHAIN_RESET(sc); 1518 vge_discard_rxbuf(sc, prod); 1519 continue; 1520 } 1521 1522 /* Chain received mbufs. */ 1523 if (sc->vge_cdata.vge_head != NULL) { 1524 m->m_len = total_len % (MCLBYTES - VGE_RX_BUF_ALIGN); 1525 /* 1526 * Special case: if there's 4 bytes or less 1527 * in this buffer, the mbuf can be discarded: 1528 * the last 4 bytes is the CRC, which we don't 1529 * care about anyway. 1530 */ 1531 if (m->m_len <= ETHER_CRC_LEN) { 1532 sc->vge_cdata.vge_tail->m_len -= 1533 (ETHER_CRC_LEN - m->m_len); 1534 m_freem(m); 1535 } else { 1536 m->m_len -= ETHER_CRC_LEN; 1537 m->m_flags &= ~M_PKTHDR; 1538 sc->vge_cdata.vge_tail->m_next = m; 1539 } 1540 m = sc->vge_cdata.vge_head; 1541 m->m_flags |= M_PKTHDR; 1542 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1543 } else { 1544 m->m_flags |= M_PKTHDR; 1545 m->m_pkthdr.len = m->m_len = 1546 (total_len - ETHER_CRC_LEN); 1547 } 1548 1549#ifndef __NO_STRICT_ALIGNMENT 1550 vge_fixup_rx(m); 1551#endif 1552 m->m_pkthdr.rcvif = ifp; 1553 1554 /* Do RX checksumming if enabled */ 1555 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 1556 (rxctl & VGE_RDCTL_FRAG) == 0) { 1557 /* Check IP header checksum */ 1558 if ((rxctl & VGE_RDCTL_IPPKT) != 0) 1559 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1560 if ((rxctl & VGE_RDCTL_IPCSUMOK) != 0) 1561 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1562 1563 /* Check TCP/UDP checksum */ 1564 if (rxctl & (VGE_RDCTL_TCPPKT | VGE_RDCTL_UDPPKT) && 1565 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1566 m->m_pkthdr.csum_flags |= 1567 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1568 m->m_pkthdr.csum_data = 0xffff; 1569 } 1570 } 1571 1572 if ((rxstat & VGE_RDSTS_VTAG) != 0) { 1573 /* 1574 * The 32-bit rxctl register is stored in little-endian. 1575 * However, the 16-bit vlan tag is stored in big-endian, 1576 * so we have to byte swap it. 1577 */ 1578 m->m_pkthdr.ether_vtag = 1579 bswap16(rxctl & VGE_RDCTL_VLANID); 1580 m->m_flags |= M_VLANTAG; 1581 } 1582 1583 VGE_UNLOCK(sc); 1584 if_input(ifp, m); 1585 VGE_LOCK(sc); 1586 sc->vge_cdata.vge_head = NULL; 1587 sc->vge_cdata.vge_tail = NULL; 1588 } 1589 1590 if (prog > 0) { 1591 sc->vge_cdata.vge_rx_prodidx = prod; 1592 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1593 sc->vge_cdata.vge_rx_ring_map, 1594 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1595 /* Update residue counter. */ 1596 if (sc->vge_cdata.vge_rx_commit != 0) { 1597 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, 1598 sc->vge_cdata.vge_rx_commit); 1599 sc->vge_cdata.vge_rx_commit = 0; 1600 } 1601 } 1602 return (prog); 1603} 1604 1605static void 1606vge_txeof(struct vge_softc *sc) 1607{ 1608 if_t ifp; 1609 struct vge_tx_desc *cur_tx; 1610 struct vge_txdesc *txd; 1611 uint32_t txstat; 1612 int cons, prod; 1613 1614 VGE_LOCK_ASSERT(sc); 1615 1616 ifp = sc->vge_ifp; 1617 1618 if (sc->vge_cdata.vge_tx_cnt == 0) 1619 return; 1620 1621 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1622 sc->vge_cdata.vge_tx_ring_map, 1623 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1624 1625 /* 1626 * Go through our tx list and free mbufs for those 1627 * frames that have been transmitted. 1628 */ 1629 cons = sc->vge_cdata.vge_tx_considx; 1630 prod = sc->vge_cdata.vge_tx_prodidx; 1631 for (; cons != prod; VGE_TX_DESC_INC(cons)) { 1632 cur_tx = &sc->vge_rdata.vge_tx_ring[cons]; 1633 txstat = le32toh(cur_tx->vge_sts); 1634 if ((txstat & VGE_TDSTS_OWN) != 0) 1635 break; 1636 sc->vge_cdata.vge_tx_cnt--; 1637 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1638 1639 txd = &sc->vge_cdata.vge_txdesc[cons]; 1640 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1641 BUS_DMASYNC_POSTWRITE); 1642 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap); 1643 1644 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n", 1645 __func__)); 1646 m_freem(txd->tx_m); 1647 txd->tx_m = NULL; 1648 txd->tx_desc->vge_frag[0].vge_addrhi = 0; 1649 } 1650 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1651 sc->vge_cdata.vge_tx_ring_map, 1652 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1653 sc->vge_cdata.vge_tx_considx = cons; 1654 if (sc->vge_cdata.vge_tx_cnt == 0) 1655 sc->vge_timer = 0; 1656} 1657 1658static void 1659vge_link_statchg(void *xsc) 1660{ 1661 struct vge_softc *sc; 1662 if_t ifp; 1663 uint8_t physts; 1664 1665 sc = xsc; 1666 ifp = sc->vge_ifp; 1667 VGE_LOCK_ASSERT(sc); 1668 1669 physts = CSR_READ_1(sc, VGE_PHYSTS0); 1670 if ((physts & VGE_PHYSTS_RESETSTS) == 0) { 1671 if ((physts & VGE_PHYSTS_LINK) == 0) { 1672 sc->vge_flags &= ~VGE_FLAG_LINK; 1673 if_link_state_change(sc->vge_ifp, 1674 LINK_STATE_DOWN); 1675 } else { 1676 sc->vge_flags |= VGE_FLAG_LINK; 1677 if_link_state_change(sc->vge_ifp, 1678 LINK_STATE_UP); 1679 CSR_WRITE_1(sc, VGE_CRC2, VGE_CR2_FDX_TXFLOWCTL_ENABLE | 1680 VGE_CR2_FDX_RXFLOWCTL_ENABLE); 1681 if ((physts & VGE_PHYSTS_FDX) != 0) { 1682 if ((physts & VGE_PHYSTS_TXFLOWCAP) != 0) 1683 CSR_WRITE_1(sc, VGE_CRS2, 1684 VGE_CR2_FDX_TXFLOWCTL_ENABLE); 1685 if ((physts & VGE_PHYSTS_RXFLOWCAP) != 0) 1686 CSR_WRITE_1(sc, VGE_CRS2, 1687 VGE_CR2_FDX_RXFLOWCTL_ENABLE); 1688 } 1689 if (!if_sendq_empty(ifp)) 1690 vge_start_locked(ifp); 1691 } 1692 } 1693 /* 1694 * Restart MII auto-polling because link state change interrupt 1695 * will disable it. 1696 */ 1697 vge_miipoll_start(sc); 1698} 1699 1700#ifdef DEVICE_POLLING 1701static int 1702vge_poll (if_t ifp, enum poll_cmd cmd, int count) 1703{ 1704 struct vge_softc *sc = if_getsoftc(ifp); 1705 int rx_npkts = 0; 1706 1707 VGE_LOCK(sc); 1708 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 1709 goto done; 1710 1711 rx_npkts = vge_rxeof(sc, count); 1712 vge_txeof(sc); 1713 1714 if (!if_sendq_empty(ifp)) 1715 vge_start_locked(ifp); 1716 1717 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1718 uint32_t status; 1719 status = CSR_READ_4(sc, VGE_ISR); 1720 if (status == 0xFFFFFFFF) 1721 goto done; 1722 if (status) 1723 CSR_WRITE_4(sc, VGE_ISR, status); 1724 1725 /* 1726 * XXX check behaviour on receiver stalls. 1727 */ 1728 1729 if (status & VGE_ISR_TXDMA_STALL || 1730 status & VGE_ISR_RXDMA_STALL) { 1731 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1732 vge_init_locked(sc); 1733 } 1734 1735 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1736 vge_rxeof(sc, count); 1737 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1738 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1739 } 1740 } 1741done: 1742 VGE_UNLOCK(sc); 1743 return (rx_npkts); 1744} 1745#endif /* DEVICE_POLLING */ 1746 1747static void 1748vge_intr(void *arg) 1749{ 1750 struct vge_softc *sc; 1751 if_t ifp; 1752 uint32_t status; 1753 1754 sc = arg; 1755 VGE_LOCK(sc); 1756 1757 ifp = sc->vge_ifp; 1758 if ((sc->vge_flags & VGE_FLAG_SUSPENDED) != 0 || 1759 (if_getflags(ifp) & IFF_UP) == 0) { 1760 VGE_UNLOCK(sc); 1761 return; 1762 } 1763 1764#ifdef DEVICE_POLLING 1765 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1766 status = CSR_READ_4(sc, VGE_ISR); 1767 CSR_WRITE_4(sc, VGE_ISR, status); 1768 if (status != 0xFFFFFFFF && (status & VGE_ISR_LINKSTS) != 0) 1769 vge_link_statchg(sc); 1770 VGE_UNLOCK(sc); 1771 return; 1772 } 1773#endif 1774 1775 /* Disable interrupts */ 1776 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1777 status = CSR_READ_4(sc, VGE_ISR); 1778 CSR_WRITE_4(sc, VGE_ISR, status | VGE_ISR_HOLDOFF_RELOAD); 1779 /* If the card has gone away the read returns 0xffff. */ 1780 if (status == 0xFFFFFFFF || (status & VGE_INTRS) == 0) 1781 goto done; 1782 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1783 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1784 vge_rxeof(sc, VGE_RX_DESC_CNT); 1785 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1786 vge_rxeof(sc, VGE_RX_DESC_CNT); 1787 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1788 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1789 } 1790 1791 if (status & (VGE_ISR_TXOK0|VGE_ISR_TXOK_HIPRIO)) 1792 vge_txeof(sc); 1793 1794 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1795 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1796 vge_init_locked(sc); 1797 } 1798 1799 if (status & VGE_ISR_LINKSTS) 1800 vge_link_statchg(sc); 1801 } 1802done: 1803 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1804 /* Re-enable interrupts */ 1805 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1806 1807 if (!if_sendq_empty(ifp)) 1808 vge_start_locked(ifp); 1809 } 1810 VGE_UNLOCK(sc); 1811} 1812 1813static int 1814vge_encap(struct vge_softc *sc, struct mbuf **m_head) 1815{ 1816 struct vge_txdesc *txd; 1817 struct vge_tx_frag *frag; 1818 struct mbuf *m; 1819 bus_dma_segment_t txsegs[VGE_MAXTXSEGS]; 1820 int error, i, nsegs, padlen; 1821 uint32_t cflags; 1822 1823 VGE_LOCK_ASSERT(sc); 1824 1825 M_ASSERTPKTHDR((*m_head)); 1826 1827 /* Argh. This chip does not autopad short frames. */ 1828 if ((*m_head)->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1829 m = *m_head; 1830 padlen = VGE_MIN_FRAMELEN - m->m_pkthdr.len; 1831 if (M_WRITABLE(m) == 0) { 1832 /* Get a writable copy. */ 1833 m = m_dup(*m_head, M_NOWAIT); 1834 m_freem(*m_head); 1835 if (m == NULL) { 1836 *m_head = NULL; 1837 return (ENOBUFS); 1838 } 1839 *m_head = m; 1840 } 1841 if (M_TRAILINGSPACE(m) < padlen) { 1842 m = m_defrag(m, M_NOWAIT); 1843 if (m == NULL) { 1844 m_freem(*m_head); 1845 *m_head = NULL; 1846 return (ENOBUFS); 1847 } 1848 } 1849 /* 1850 * Manually pad short frames, and zero the pad space 1851 * to avoid leaking data. 1852 */ 1853 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1854 m->m_pkthdr.len += padlen; 1855 m->m_len = m->m_pkthdr.len; 1856 *m_head = m; 1857 } 1858 1859 txd = &sc->vge_cdata.vge_txdesc[sc->vge_cdata.vge_tx_prodidx]; 1860 1861 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1862 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1863 if (error == EFBIG) { 1864 m = m_collapse(*m_head, M_NOWAIT, VGE_MAXTXSEGS); 1865 if (m == NULL) { 1866 m_freem(*m_head); 1867 *m_head = NULL; 1868 return (ENOMEM); 1869 } 1870 *m_head = m; 1871 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1872 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1873 if (error != 0) { 1874 m_freem(*m_head); 1875 *m_head = NULL; 1876 return (error); 1877 } 1878 } else if (error != 0) 1879 return (error); 1880 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1881 BUS_DMASYNC_PREWRITE); 1882 1883 m = *m_head; 1884 cflags = 0; 1885 1886 /* Configure checksum offload. */ 1887 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1888 cflags |= VGE_TDCTL_IPCSUM; 1889 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1890 cflags |= VGE_TDCTL_TCPCSUM; 1891 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1892 cflags |= VGE_TDCTL_UDPCSUM; 1893 1894 /* Configure VLAN. */ 1895 if ((m->m_flags & M_VLANTAG) != 0) 1896 cflags |= m->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG; 1897 txd->tx_desc->vge_sts = htole32(m->m_pkthdr.len << 16); 1898 /* 1899 * XXX 1900 * Velocity family seems to support TSO but no information 1901 * for MSS configuration is available. Also the number of 1902 * fragments supported by a descriptor is too small to hold 1903 * entire 64KB TCP/IP segment. Maybe VGE_TD_LS_MOF, 1904 * VGE_TD_LS_SOF and VGE_TD_LS_EOF could be used to build 1905 * longer chain of buffers but no additional information is 1906 * available. 1907 * 1908 * When telling the chip how many segments there are, we 1909 * must use nsegs + 1 instead of just nsegs. Darned if I 1910 * know why. This also means we can't use the last fragment 1911 * field of Tx descriptor. 1912 */ 1913 txd->tx_desc->vge_ctl = htole32(cflags | ((nsegs + 1) << 28) | 1914 VGE_TD_LS_NORM); 1915 for (i = 0; i < nsegs; i++) { 1916 frag = &txd->tx_desc->vge_frag[i]; 1917 frag->vge_addrlo = htole32(VGE_ADDR_LO(txsegs[i].ds_addr)); 1918 frag->vge_addrhi = htole32(VGE_ADDR_HI(txsegs[i].ds_addr) | 1919 (VGE_BUFLEN(txsegs[i].ds_len) << 16)); 1920 } 1921 1922 sc->vge_cdata.vge_tx_cnt++; 1923 VGE_TX_DESC_INC(sc->vge_cdata.vge_tx_prodidx); 1924 1925 /* 1926 * Finally request interrupt and give the first descriptor 1927 * ownership to hardware. 1928 */ 1929 txd->tx_desc->vge_ctl |= htole32(VGE_TDCTL_TIC); 1930 txd->tx_desc->vge_sts |= htole32(VGE_TDSTS_OWN); 1931 txd->tx_m = m; 1932 1933 return (0); 1934} 1935 1936/* 1937 * Main transmit routine. 1938 */ 1939 1940static void 1941vge_start(if_t ifp) 1942{ 1943 struct vge_softc *sc; 1944 1945 sc = if_getsoftc(ifp); 1946 VGE_LOCK(sc); 1947 vge_start_locked(ifp); 1948 VGE_UNLOCK(sc); 1949} 1950 1951static void 1952vge_start_locked(if_t ifp) 1953{ 1954 struct vge_softc *sc; 1955 struct vge_txdesc *txd; 1956 struct mbuf *m_head; 1957 int enq, idx; 1958 1959 sc = if_getsoftc(ifp); 1960 1961 VGE_LOCK_ASSERT(sc); 1962 1963 if ((sc->vge_flags & VGE_FLAG_LINK) == 0 || 1964 (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1965 IFF_DRV_RUNNING) 1966 return; 1967 1968 idx = sc->vge_cdata.vge_tx_prodidx; 1969 VGE_TX_DESC_DEC(idx); 1970 for (enq = 0; !if_sendq_empty(ifp) && 1971 sc->vge_cdata.vge_tx_cnt < VGE_TX_DESC_CNT - 1; ) { 1972 m_head = if_dequeue(ifp); 1973 if (m_head == NULL) 1974 break; 1975 /* 1976 * Pack the data into the transmit ring. If we 1977 * don't have room, set the OACTIVE flag and wait 1978 * for the NIC to drain the ring. 1979 */ 1980 if (vge_encap(sc, &m_head)) { 1981 if (m_head == NULL) 1982 break; 1983 if_sendq_prepend(ifp, m_head); 1984 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1985 break; 1986 } 1987 1988 txd = &sc->vge_cdata.vge_txdesc[idx]; 1989 txd->tx_desc->vge_frag[0].vge_addrhi |= htole32(VGE_TXDESC_Q); 1990 VGE_TX_DESC_INC(idx); 1991 1992 enq++; 1993 /* 1994 * If there's a BPF listener, bounce a copy of this frame 1995 * to him. 1996 */ 1997 ETHER_BPF_MTAP(ifp, m_head); 1998 } 1999 2000 if (enq > 0) { 2001 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 2002 sc->vge_cdata.vge_tx_ring_map, 2003 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2004 /* Issue a transmit command. */ 2005 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 2006 /* 2007 * Set a timeout in case the chip goes out to lunch. 2008 */ 2009 sc->vge_timer = 5; 2010 } 2011} 2012 2013static void 2014vge_init(void *xsc) 2015{ 2016 struct vge_softc *sc = xsc; 2017 2018 VGE_LOCK(sc); 2019 vge_init_locked(sc); 2020 VGE_UNLOCK(sc); 2021} 2022 2023static void 2024vge_init_locked(struct vge_softc *sc) 2025{ 2026 if_t ifp = sc->vge_ifp; 2027 int error, i; 2028 2029 VGE_LOCK_ASSERT(sc); 2030 2031 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2032 return; 2033 2034 /* 2035 * Cancel pending I/O and free all RX/TX buffers. 2036 */ 2037 vge_stop(sc); 2038 vge_reset(sc); 2039 vge_miipoll_start(sc); 2040 2041 /* 2042 * Initialize the RX and TX descriptors and mbufs. 2043 */ 2044 2045 error = vge_rx_list_init(sc); 2046 if (error != 0) { 2047 device_printf(sc->vge_dev, "no memory for Rx buffers.\n"); 2048 return; 2049 } 2050 vge_tx_list_init(sc); 2051 /* Clear MAC statistics. */ 2052 vge_stats_clear(sc); 2053 /* Set our station address */ 2054 for (i = 0; i < ETHER_ADDR_LEN; i++) 2055 CSR_WRITE_1(sc, VGE_PAR0 + i, if_getlladdr(sc->vge_ifp)[i]); 2056 2057 /* 2058 * Set receive FIFO threshold. Also allow transmission and 2059 * reception of VLAN tagged frames. 2060 */ 2061 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 2062 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES); 2063 2064 /* Set DMA burst length */ 2065 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 2066 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 2067 2068 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 2069 2070 /* Set collision backoff algorithm */ 2071 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 2072 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 2073 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 2074 2075 /* Disable LPSEL field in priority resolution */ 2076 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 2077 2078 /* 2079 * Load the addresses of the DMA queues into the chip. 2080 * Note that we only use one transmit queue. 2081 */ 2082 2083 CSR_WRITE_4(sc, VGE_TXDESC_HIADDR, 2084 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)); 2085 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2086 VGE_ADDR_LO(sc->vge_rdata.vge_tx_ring_paddr)); 2087 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2088 2089 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2090 VGE_ADDR_LO(sc->vge_rdata.vge_rx_ring_paddr)); 2091 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2092 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2093 2094 /* Configure interrupt moderation. */ 2095 vge_intr_holdoff(sc); 2096 2097 /* Enable and wake up the RX descriptor queue */ 2098 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2099 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2100 2101 /* Enable the TX descriptor queue */ 2102 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2103 2104 /* Init the cam filter. */ 2105 vge_cam_clear(sc); 2106 2107 /* Set up receiver filter. */ 2108 vge_rxfilter(sc); 2109 vge_setvlan(sc); 2110 2111 /* Initialize pause timer. */ 2112 CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF); 2113 /* 2114 * Initialize flow control parameters. 2115 * TX XON high threshold : 48 2116 * TX pause low threshold : 24 2117 * Disable hald-duplex flow control 2118 */ 2119 CSR_WRITE_1(sc, VGE_CRC2, 0xFF); 2120 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_XON_ENABLE | 0x0B); 2121 2122 /* Enable jumbo frame reception (if desired) */ 2123 2124 /* Start the MAC. */ 2125 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2126 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2127 CSR_WRITE_1(sc, VGE_CRS0, 2128 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2129 2130#ifdef DEVICE_POLLING 2131 /* 2132 * Disable interrupts except link state change if we are polling. 2133 */ 2134 if (if_getcapenable(ifp) & IFCAP_POLLING) { 2135 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS_POLLING); 2136 } else /* otherwise ... */ 2137#endif 2138 { 2139 /* 2140 * Enable interrupts. 2141 */ 2142 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2143 } 2144 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2145 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2146 2147 sc->vge_flags &= ~VGE_FLAG_LINK; 2148 vge_ifmedia_upd_locked(sc); 2149 2150 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2151 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2152 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2153} 2154 2155/* 2156 * Set media options. 2157 */ 2158static int 2159vge_ifmedia_upd(if_t ifp) 2160{ 2161 struct vge_softc *sc; 2162 int error; 2163 2164 sc = if_getsoftc(ifp); 2165 VGE_LOCK(sc); 2166 error = vge_ifmedia_upd_locked(sc); 2167 VGE_UNLOCK(sc); 2168 2169 return (error); 2170} 2171 2172static int 2173vge_ifmedia_upd_locked(struct vge_softc *sc) 2174{ 2175 struct mii_data *mii; 2176 struct mii_softc *miisc; 2177 int error; 2178 2179 mii = device_get_softc(sc->vge_miibus); 2180 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2181 PHY_RESET(miisc); 2182 vge_setmedia(sc); 2183 error = mii_mediachg(mii); 2184 2185 return (error); 2186} 2187 2188/* 2189 * Report current media status. 2190 */ 2191static void 2192vge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2193{ 2194 struct vge_softc *sc; 2195 struct mii_data *mii; 2196 2197 sc = if_getsoftc(ifp); 2198 mii = device_get_softc(sc->vge_miibus); 2199 2200 VGE_LOCK(sc); 2201 if ((if_getflags(ifp) & IFF_UP) == 0) { 2202 VGE_UNLOCK(sc); 2203 return; 2204 } 2205 mii_pollstat(mii); 2206 ifmr->ifm_active = mii->mii_media_active; 2207 ifmr->ifm_status = mii->mii_media_status; 2208 VGE_UNLOCK(sc); 2209} 2210 2211static void 2212vge_setmedia(struct vge_softc *sc) 2213{ 2214 struct mii_data *mii; 2215 struct ifmedia_entry *ife; 2216 2217 mii = device_get_softc(sc->vge_miibus); 2218 ife = mii->mii_media.ifm_cur; 2219 2220 /* 2221 * If the user manually selects a media mode, we need to turn 2222 * on the forced MAC mode bit in the DIAGCTL register. If the 2223 * user happens to choose a full duplex mode, we also need to 2224 * set the 'force full duplex' bit. This applies only to 2225 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2226 * mode is disabled, and in 1000baseT mode, full duplex is 2227 * always implied, so we turn on the forced mode bit but leave 2228 * the FDX bit cleared. 2229 */ 2230 2231 switch (IFM_SUBTYPE(ife->ifm_media)) { 2232 case IFM_AUTO: 2233 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2234 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2235 break; 2236 case IFM_1000_T: 2237 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2238 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2239 break; 2240 case IFM_100_TX: 2241 case IFM_10_T: 2242 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2243 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2244 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2245 } else { 2246 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2247 } 2248 break; 2249 default: 2250 device_printf(sc->vge_dev, "unknown media type: %x\n", 2251 IFM_SUBTYPE(ife->ifm_media)); 2252 break; 2253 } 2254} 2255 2256static int 2257vge_ioctl(if_t ifp, u_long command, caddr_t data) 2258{ 2259 struct vge_softc *sc = if_getsoftc(ifp); 2260 struct ifreq *ifr = (struct ifreq *) data; 2261 struct mii_data *mii; 2262 int error = 0, mask; 2263 2264 switch (command) { 2265 case SIOCSIFMTU: 2266 VGE_LOCK(sc); 2267 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > VGE_JUMBO_MTU) 2268 error = EINVAL; 2269 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 2270 if (ifr->ifr_mtu > ETHERMTU && 2271 (sc->vge_flags & VGE_FLAG_JUMBO) == 0) 2272 error = EINVAL; 2273 else 2274 if_setmtu(ifp, ifr->ifr_mtu); 2275 } 2276 VGE_UNLOCK(sc); 2277 break; 2278 case SIOCSIFFLAGS: 2279 VGE_LOCK(sc); 2280 if ((if_getflags(ifp) & IFF_UP) != 0) { 2281 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 2282 ((if_getflags(ifp) ^ sc->vge_if_flags) & 2283 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2284 vge_rxfilter(sc); 2285 else 2286 vge_init_locked(sc); 2287 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2288 vge_stop(sc); 2289 sc->vge_if_flags = if_getflags(ifp); 2290 VGE_UNLOCK(sc); 2291 break; 2292 case SIOCADDMULTI: 2293 case SIOCDELMULTI: 2294 VGE_LOCK(sc); 2295 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2296 vge_rxfilter(sc); 2297 VGE_UNLOCK(sc); 2298 break; 2299 case SIOCGIFMEDIA: 2300 case SIOCSIFMEDIA: 2301 mii = device_get_softc(sc->vge_miibus); 2302 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2303 break; 2304 case SIOCSIFCAP: 2305 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2306#ifdef DEVICE_POLLING 2307 if (mask & IFCAP_POLLING) { 2308 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2309 error = ether_poll_register(vge_poll, ifp); 2310 if (error) 2311 return (error); 2312 VGE_LOCK(sc); 2313 /* Disable interrupts */ 2314 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS_POLLING); 2315 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2316 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2317 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 2318 VGE_UNLOCK(sc); 2319 } else { 2320 error = ether_poll_deregister(ifp); 2321 /* Enable interrupts. */ 2322 VGE_LOCK(sc); 2323 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2324 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2325 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2326 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 2327 VGE_UNLOCK(sc); 2328 } 2329 } 2330#endif /* DEVICE_POLLING */ 2331 VGE_LOCK(sc); 2332 if ((mask & IFCAP_TXCSUM) != 0 && 2333 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 2334 if_togglecapenable(ifp, IFCAP_TXCSUM); 2335 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 2336 if_sethwassistbits(ifp, VGE_CSUM_FEATURES, 0); 2337 else 2338 if_sethwassistbits(ifp, 0, VGE_CSUM_FEATURES); 2339 } 2340 if ((mask & IFCAP_RXCSUM) != 0 && 2341 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 2342 if_togglecapenable(ifp, IFCAP_RXCSUM); 2343 if ((mask & IFCAP_WOL_UCAST) != 0 && 2344 (if_getcapabilities(ifp) & IFCAP_WOL_UCAST) != 0) 2345 if_togglecapenable(ifp, IFCAP_WOL_UCAST); 2346 if ((mask & IFCAP_WOL_MCAST) != 0 && 2347 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 2348 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 2349 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2350 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 2351 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2352 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2353 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2354 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2355 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2356 (IFCAP_VLAN_HWTAGGING & if_getcapabilities(ifp)) != 0) { 2357 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2358 vge_setvlan(sc); 2359 } 2360 VGE_UNLOCK(sc); 2361 VLAN_CAPABILITIES(ifp); 2362 break; 2363 default: 2364 error = ether_ioctl(ifp, command, data); 2365 break; 2366 } 2367 2368 return (error); 2369} 2370 2371static void 2372vge_watchdog(void *arg) 2373{ 2374 struct vge_softc *sc; 2375 if_t ifp; 2376 2377 sc = arg; 2378 VGE_LOCK_ASSERT(sc); 2379 vge_stats_update(sc); 2380 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2381 if (sc->vge_timer == 0 || --sc->vge_timer > 0) 2382 return; 2383 2384 ifp = sc->vge_ifp; 2385 if_printf(ifp, "watchdog timeout\n"); 2386 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2387 2388 vge_txeof(sc); 2389 vge_rxeof(sc, VGE_RX_DESC_CNT); 2390 2391 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2392 vge_init_locked(sc); 2393} 2394 2395/* 2396 * Stop the adapter and free any mbufs allocated to the 2397 * RX and TX lists. 2398 */ 2399static void 2400vge_stop(struct vge_softc *sc) 2401{ 2402 if_t ifp; 2403 2404 VGE_LOCK_ASSERT(sc); 2405 ifp = sc->vge_ifp; 2406 sc->vge_timer = 0; 2407 callout_stop(&sc->vge_watchdog); 2408 2409 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2410 2411 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2412 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2413 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2414 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2415 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2416 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2417 2418 vge_stats_update(sc); 2419 VGE_CHAIN_RESET(sc); 2420 vge_txeof(sc); 2421 vge_freebufs(sc); 2422} 2423 2424/* 2425 * Device suspend routine. Stop the interface and save some PCI 2426 * settings in case the BIOS doesn't restore them properly on 2427 * resume. 2428 */ 2429static int 2430vge_suspend(device_t dev) 2431{ 2432 struct vge_softc *sc; 2433 2434 sc = device_get_softc(dev); 2435 2436 VGE_LOCK(sc); 2437 vge_stop(sc); 2438 vge_setwol(sc); 2439 sc->vge_flags |= VGE_FLAG_SUSPENDED; 2440 VGE_UNLOCK(sc); 2441 2442 return (0); 2443} 2444 2445/* 2446 * Device resume routine. Restore some PCI settings in case the BIOS 2447 * doesn't, re-enable busmastering, and restart the interface if 2448 * appropriate. 2449 */ 2450static int 2451vge_resume(device_t dev) 2452{ 2453 struct vge_softc *sc; 2454 if_t ifp; 2455 uint16_t pmstat; 2456 2457 sc = device_get_softc(dev); 2458 VGE_LOCK(sc); 2459 if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0) { 2460 /* Disable PME and clear PME status. */ 2461 pmstat = pci_read_config(sc->vge_dev, 2462 sc->vge_pmcap + PCIR_POWER_STATUS, 2); 2463 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2464 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2465 pci_write_config(sc->vge_dev, 2466 sc->vge_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2467 } 2468 } 2469 vge_clrwol(sc); 2470 /* Restart MII auto-polling. */ 2471 vge_miipoll_start(sc); 2472 ifp = sc->vge_ifp; 2473 /* Reinitialize interface if necessary. */ 2474 if ((if_getflags(ifp) & IFF_UP) != 0) { 2475 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2476 vge_init_locked(sc); 2477 } 2478 sc->vge_flags &= ~VGE_FLAG_SUSPENDED; 2479 VGE_UNLOCK(sc); 2480 2481 return (0); 2482} 2483 2484/* 2485 * Stop all chip I/O so that the kernel's probe routines don't 2486 * get confused by errant DMAs when rebooting. 2487 */ 2488static int 2489vge_shutdown(device_t dev) 2490{ 2491 2492 return (vge_suspend(dev)); 2493} 2494 2495#define VGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2496 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2497 2498static void 2499vge_sysctl_node(struct vge_softc *sc) 2500{ 2501 struct sysctl_ctx_list *ctx; 2502 struct sysctl_oid_list *child, *parent; 2503 struct sysctl_oid *tree; 2504 struct vge_hw_stats *stats; 2505 2506 stats = &sc->vge_stats; 2507 ctx = device_get_sysctl_ctx(sc->vge_dev); 2508 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vge_dev)); 2509 2510 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_holdoff", 2511 CTLFLAG_RW, &sc->vge_int_holdoff, 0, "interrupt holdoff"); 2512 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rx_coal_pkt", 2513 CTLFLAG_RW, &sc->vge_rx_coal_pkt, 0, "rx coalescing packet"); 2514 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "tx_coal_pkt", 2515 CTLFLAG_RW, &sc->vge_tx_coal_pkt, 0, "tx coalescing packet"); 2516 2517 /* Pull in device tunables. */ 2518 sc->vge_int_holdoff = VGE_INT_HOLDOFF_DEFAULT; 2519 resource_int_value(device_get_name(sc->vge_dev), 2520 device_get_unit(sc->vge_dev), "int_holdoff", &sc->vge_int_holdoff); 2521 sc->vge_rx_coal_pkt = VGE_RX_COAL_PKT_DEFAULT; 2522 resource_int_value(device_get_name(sc->vge_dev), 2523 device_get_unit(sc->vge_dev), "rx_coal_pkt", &sc->vge_rx_coal_pkt); 2524 sc->vge_tx_coal_pkt = VGE_TX_COAL_PKT_DEFAULT; 2525 resource_int_value(device_get_name(sc->vge_dev), 2526 device_get_unit(sc->vge_dev), "tx_coal_pkt", &sc->vge_tx_coal_pkt); 2527 2528 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 2529 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "VGE statistics"); 2530 parent = SYSCTL_CHILDREN(tree); 2531 2532 /* Rx statistics. */ 2533 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 2534 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX MAC statistics"); 2535 child = SYSCTL_CHILDREN(tree); 2536 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames", 2537 &stats->rx_frames, "frames"); 2538 VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2539 &stats->rx_good_frames, "Good frames"); 2540 VGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 2541 &stats->rx_fifo_oflows, "FIFO overflows"); 2542 VGE_SYSCTL_STAT_ADD32(ctx, child, "runts", 2543 &stats->rx_runts, "Too short frames"); 2544 VGE_SYSCTL_STAT_ADD32(ctx, child, "runts_errs", 2545 &stats->rx_runts_errs, "Too short frames with errors"); 2546 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 2547 &stats->rx_pkts_64, "64 bytes frames"); 2548 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 2549 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 2550 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 2551 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 2552 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 2553 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 2554 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 2555 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 2556 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 2557 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 2558 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 2559 &stats->rx_pkts_1519_max, "1519 to max frames"); 2560 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max_errs", 2561 &stats->rx_pkts_1519_max_errs, "1519 to max frames with error"); 2562 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo", 2563 &stats->rx_jumbos, "Jumbo frames"); 2564 VGE_SYSCTL_STAT_ADD32(ctx, child, "crcerrs", 2565 &stats->rx_crcerrs, "CRC errors"); 2566 VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 2567 &stats->rx_pause_frames, "Pause frames"); 2568 VGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 2569 &stats->rx_alignerrs, "Alignment errors"); 2570 VGE_SYSCTL_STAT_ADD32(ctx, child, "nobufs", 2571 &stats->rx_nobufs, "Frames with no buffer event"); 2572 VGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs", 2573 &stats->rx_symerrs, "Frames with symbol errors"); 2574 VGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 2575 &stats->rx_lenerrs, "Frames with length mismatched"); 2576 2577 /* Tx statistics. */ 2578 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 2579 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX MAC statistics"); 2580 child = SYSCTL_CHILDREN(tree); 2581 VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2582 &stats->tx_good_frames, "Good frames"); 2583 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 2584 &stats->tx_pkts_64, "64 bytes frames"); 2585 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 2586 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 2587 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 2588 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 2589 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 2590 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 2591 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 2592 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 2593 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 2594 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 2595 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo", 2596 &stats->tx_jumbos, "Jumbo frames"); 2597 VGE_SYSCTL_STAT_ADD32(ctx, child, "colls", 2598 &stats->tx_colls, "Collisions"); 2599 VGE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 2600 &stats->tx_latecolls, "Late collisions"); 2601 VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 2602 &stats->tx_pause, "Pause frames"); 2603#ifdef VGE_ENABLE_SQEERR 2604 VGE_SYSCTL_STAT_ADD32(ctx, child, "sqeerrs", 2605 &stats->tx_sqeerrs, "SQE errors"); 2606#endif 2607 /* Clear MAC statistics. */ 2608 vge_stats_clear(sc); 2609} 2610 2611#undef VGE_SYSCTL_STAT_ADD32 2612 2613static void 2614vge_stats_clear(struct vge_softc *sc) 2615{ 2616 int i; 2617 2618 CSR_WRITE_1(sc, VGE_MIBCSR, 2619 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FREEZE); 2620 CSR_WRITE_1(sc, VGE_MIBCSR, 2621 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_CLR); 2622 for (i = VGE_TIMEOUT; i > 0; i--) { 2623 DELAY(1); 2624 if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_CLR) == 0) 2625 break; 2626 } 2627 if (i == 0) 2628 device_printf(sc->vge_dev, "MIB clear timed out!\n"); 2629 CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) & 2630 ~VGE_MIBCSR_FREEZE); 2631} 2632 2633static void 2634vge_stats_update(struct vge_softc *sc) 2635{ 2636 struct vge_hw_stats *stats; 2637 if_t ifp; 2638 uint32_t mib[VGE_MIB_CNT], val; 2639 int i; 2640 2641 VGE_LOCK_ASSERT(sc); 2642 2643 stats = &sc->vge_stats; 2644 ifp = sc->vge_ifp; 2645 2646 CSR_WRITE_1(sc, VGE_MIBCSR, 2647 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FLUSH); 2648 for (i = VGE_TIMEOUT; i > 0; i--) { 2649 DELAY(1); 2650 if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_FLUSH) == 0) 2651 break; 2652 } 2653 if (i == 0) { 2654 device_printf(sc->vge_dev, "MIB counter dump timed out!\n"); 2655 vge_stats_clear(sc); 2656 return; 2657 } 2658 2659 bzero(mib, sizeof(mib)); 2660reset_idx: 2661 /* Set MIB read index to 0. */ 2662 CSR_WRITE_1(sc, VGE_MIBCSR, 2663 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_RINI); 2664 for (i = 0; i < VGE_MIB_CNT; i++) { 2665 val = CSR_READ_4(sc, VGE_MIBDATA); 2666 if (i != VGE_MIB_DATA_IDX(val)) { 2667 /* Reading interrupted. */ 2668 goto reset_idx; 2669 } 2670 mib[i] = val & VGE_MIB_DATA_MASK; 2671 } 2672 2673 /* Rx stats. */ 2674 stats->rx_frames += mib[VGE_MIB_RX_FRAMES]; 2675 stats->rx_good_frames += mib[VGE_MIB_RX_GOOD_FRAMES]; 2676 stats->rx_fifo_oflows += mib[VGE_MIB_RX_FIFO_OVERRUNS]; 2677 stats->rx_runts += mib[VGE_MIB_RX_RUNTS]; 2678 stats->rx_runts_errs += mib[VGE_MIB_RX_RUNTS_ERRS]; 2679 stats->rx_pkts_64 += mib[VGE_MIB_RX_PKTS_64]; 2680 stats->rx_pkts_65_127 += mib[VGE_MIB_RX_PKTS_65_127]; 2681 stats->rx_pkts_128_255 += mib[VGE_MIB_RX_PKTS_128_255]; 2682 stats->rx_pkts_256_511 += mib[VGE_MIB_RX_PKTS_256_511]; 2683 stats->rx_pkts_512_1023 += mib[VGE_MIB_RX_PKTS_512_1023]; 2684 stats->rx_pkts_1024_1518 += mib[VGE_MIB_RX_PKTS_1024_1518]; 2685 stats->rx_pkts_1519_max += mib[VGE_MIB_RX_PKTS_1519_MAX]; 2686 stats->rx_pkts_1519_max_errs += mib[VGE_MIB_RX_PKTS_1519_MAX_ERRS]; 2687 stats->rx_jumbos += mib[VGE_MIB_RX_JUMBOS]; 2688 stats->rx_crcerrs += mib[VGE_MIB_RX_CRCERRS]; 2689 stats->rx_pause_frames += mib[VGE_MIB_RX_PAUSE]; 2690 stats->rx_alignerrs += mib[VGE_MIB_RX_ALIGNERRS]; 2691 stats->rx_nobufs += mib[VGE_MIB_RX_NOBUFS]; 2692 stats->rx_symerrs += mib[VGE_MIB_RX_SYMERRS]; 2693 stats->rx_lenerrs += mib[VGE_MIB_RX_LENERRS]; 2694 2695 /* Tx stats. */ 2696 stats->tx_good_frames += mib[VGE_MIB_TX_GOOD_FRAMES]; 2697 stats->tx_pkts_64 += mib[VGE_MIB_TX_PKTS_64]; 2698 stats->tx_pkts_65_127 += mib[VGE_MIB_TX_PKTS_65_127]; 2699 stats->tx_pkts_128_255 += mib[VGE_MIB_TX_PKTS_128_255]; 2700 stats->tx_pkts_256_511 += mib[VGE_MIB_TX_PKTS_256_511]; 2701 stats->tx_pkts_512_1023 += mib[VGE_MIB_TX_PKTS_512_1023]; 2702 stats->tx_pkts_1024_1518 += mib[VGE_MIB_TX_PKTS_1024_1518]; 2703 stats->tx_jumbos += mib[VGE_MIB_TX_JUMBOS]; 2704 stats->tx_colls += mib[VGE_MIB_TX_COLLS]; 2705 stats->tx_pause += mib[VGE_MIB_TX_PAUSE]; 2706#ifdef VGE_ENABLE_SQEERR 2707 stats->tx_sqeerrs += mib[VGE_MIB_TX_SQEERRS]; 2708#endif 2709 stats->tx_latecolls += mib[VGE_MIB_TX_LATECOLLS]; 2710 2711 /* Update counters in ifnet. */ 2712 if_inc_counter(ifp, IFCOUNTER_OPACKETS, mib[VGE_MIB_TX_GOOD_FRAMES]); 2713 2714 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2715 mib[VGE_MIB_TX_COLLS] + mib[VGE_MIB_TX_LATECOLLS]); 2716 2717 if_inc_counter(ifp, IFCOUNTER_OERRORS, 2718 mib[VGE_MIB_TX_COLLS] + mib[VGE_MIB_TX_LATECOLLS]); 2719 2720 if_inc_counter(ifp, IFCOUNTER_IPACKETS, mib[VGE_MIB_RX_GOOD_FRAMES]); 2721 2722 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2723 mib[VGE_MIB_RX_FIFO_OVERRUNS] + 2724 mib[VGE_MIB_RX_RUNTS] + 2725 mib[VGE_MIB_RX_RUNTS_ERRS] + 2726 mib[VGE_MIB_RX_CRCERRS] + 2727 mib[VGE_MIB_RX_ALIGNERRS] + 2728 mib[VGE_MIB_RX_NOBUFS] + 2729 mib[VGE_MIB_RX_SYMERRS] + 2730 mib[VGE_MIB_RX_LENERRS]); 2731} 2732 2733static void 2734vge_intr_holdoff(struct vge_softc *sc) 2735{ 2736 uint8_t intctl; 2737 2738 VGE_LOCK_ASSERT(sc); 2739 2740 /* 2741 * Set Tx interrupt supression threshold. 2742 * It's possible to use single-shot timer in VGE_CRS1 register 2743 * in Tx path such that driver can remove most of Tx completion 2744 * interrupts. However this requires additional access to 2745 * VGE_CRS1 register to reload the timer in addintion to 2746 * activating Tx kick command. Another downside is we don't know 2747 * what single-shot timer value should be used in advance so 2748 * reclaiming transmitted mbufs could be delayed a lot which in 2749 * turn slows down Tx operation. 2750 */ 2751 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_TXSUPPTHR); 2752 CSR_WRITE_1(sc, VGE_TXSUPPTHR, sc->vge_tx_coal_pkt); 2753 2754 /* Set Rx interrupt suppresion threshold. */ 2755 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2756 CSR_WRITE_1(sc, VGE_RXSUPPTHR, sc->vge_rx_coal_pkt); 2757 2758 intctl = CSR_READ_1(sc, VGE_INTCTL1); 2759 intctl &= ~VGE_INTCTL_SC_RELOAD; 2760 intctl |= VGE_INTCTL_HC_RELOAD; 2761 if (sc->vge_tx_coal_pkt <= 0) 2762 intctl |= VGE_INTCTL_TXINTSUP_DISABLE; 2763 else 2764 intctl &= ~VGE_INTCTL_TXINTSUP_DISABLE; 2765 if (sc->vge_rx_coal_pkt <= 0) 2766 intctl |= VGE_INTCTL_RXINTSUP_DISABLE; 2767 else 2768 intctl &= ~VGE_INTCTL_RXINTSUP_DISABLE; 2769 CSR_WRITE_1(sc, VGE_INTCTL1, intctl); 2770 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_HOLDOFF); 2771 if (sc->vge_int_holdoff > 0) { 2772 /* Set interrupt holdoff timer. */ 2773 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2774 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 2775 VGE_INT_HOLDOFF_USEC(sc->vge_int_holdoff)); 2776 /* Enable holdoff timer. */ 2777 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2778 } 2779} 2780 2781static void 2782vge_setlinkspeed(struct vge_softc *sc) 2783{ 2784 struct mii_data *mii; 2785 int aneg, i; 2786 2787 VGE_LOCK_ASSERT(sc); 2788 2789 mii = device_get_softc(sc->vge_miibus); 2790 mii_pollstat(mii); 2791 aneg = 0; 2792 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2793 (IFM_ACTIVE | IFM_AVALID)) { 2794 switch IFM_SUBTYPE(mii->mii_media_active) { 2795 case IFM_10_T: 2796 case IFM_100_TX: 2797 return; 2798 case IFM_1000_T: 2799 aneg++; 2800 default: 2801 break; 2802 } 2803 } 2804 /* Clear forced MAC speed/duplex configuration. */ 2805 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2806 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2807 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_100T2CR, 0); 2808 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_ANAR, 2809 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2810 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR, 2811 BMCR_AUTOEN | BMCR_STARTNEG); 2812 DELAY(1000); 2813 if (aneg != 0) { 2814 /* Poll link state until vge(4) get a 10/100 link. */ 2815 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2816 mii_pollstat(mii); 2817 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2818 == (IFM_ACTIVE | IFM_AVALID)) { 2819 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2820 case IFM_10_T: 2821 case IFM_100_TX: 2822 return; 2823 default: 2824 break; 2825 } 2826 } 2827 VGE_UNLOCK(sc); 2828 pause("vgelnk", hz); 2829 VGE_LOCK(sc); 2830 } 2831 if (i == MII_ANEGTICKS_GIGE) 2832 device_printf(sc->vge_dev, "establishing link failed, " 2833 "WOL may not work!"); 2834 } 2835 /* 2836 * No link, force MAC to have 100Mbps, full-duplex link. 2837 * This is the last resort and may/may not work. 2838 */ 2839 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2840 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2841} 2842 2843static void 2844vge_setwol(struct vge_softc *sc) 2845{ 2846 if_t ifp; 2847 uint16_t pmstat; 2848 uint8_t val; 2849 2850 VGE_LOCK_ASSERT(sc); 2851 2852 if ((sc->vge_flags & VGE_FLAG_PMCAP) == 0) { 2853 /* No PME capability, PHY power down. */ 2854 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR, 2855 BMCR_PDOWN); 2856 vge_miipoll_stop(sc); 2857 return; 2858 } 2859 2860 ifp = sc->vge_ifp; 2861 2862 /* Clear WOL on pattern match. */ 2863 CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL); 2864 /* Disable WOL on magic/unicast packet. */ 2865 CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F); 2866 CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM | 2867 VGE_WOLCFG_PMEOVR); 2868 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2869 vge_setlinkspeed(sc); 2870 val = 0; 2871 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0) 2872 val |= VGE_WOLCR1_UCAST; 2873 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2874 val |= VGE_WOLCR1_MAGIC; 2875 CSR_WRITE_1(sc, VGE_WOLCR1S, val); 2876 val = 0; 2877 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2878 val |= VGE_WOLCFG_SAM | VGE_WOLCFG_SAB; 2879 CSR_WRITE_1(sc, VGE_WOLCFGS, val | VGE_WOLCFG_PMEOVR); 2880 /* Disable MII auto-polling. */ 2881 vge_miipoll_stop(sc); 2882 } 2883 CSR_SETBIT_1(sc, VGE_DIAGCTL, 2884 VGE_DIAGCTL_MACFORCE | VGE_DIAGCTL_FDXFORCE); 2885 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII); 2886 2887 /* Clear WOL status on pattern match. */ 2888 CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF); 2889 CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF); 2890 2891 val = CSR_READ_1(sc, VGE_PWRSTAT); 2892 val |= VGE_STICKHW_SWPTAG; 2893 CSR_WRITE_1(sc, VGE_PWRSTAT, val); 2894 /* Put hardware into sleep. */ 2895 val = CSR_READ_1(sc, VGE_PWRSTAT); 2896 val |= VGE_STICKHW_DS0 | VGE_STICKHW_DS1; 2897 CSR_WRITE_1(sc, VGE_PWRSTAT, val); 2898 /* Request PME if WOL is requested. */ 2899 pmstat = pci_read_config(sc->vge_dev, sc->vge_pmcap + 2900 PCIR_POWER_STATUS, 2); 2901 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2902 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2903 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2904 pci_write_config(sc->vge_dev, sc->vge_pmcap + PCIR_POWER_STATUS, 2905 pmstat, 2); 2906} 2907 2908static void 2909vge_clrwol(struct vge_softc *sc) 2910{ 2911 uint8_t val; 2912 2913 val = CSR_READ_1(sc, VGE_PWRSTAT); 2914 val &= ~VGE_STICKHW_SWPTAG; 2915 CSR_WRITE_1(sc, VGE_PWRSTAT, val); 2916 /* Disable WOL and clear power state indicator. */ 2917 val = CSR_READ_1(sc, VGE_PWRSTAT); 2918 val &= ~(VGE_STICKHW_DS0 | VGE_STICKHW_DS1); 2919 CSR_WRITE_1(sc, VGE_PWRSTAT, val); 2920 2921 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII); 2922 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2923 2924 /* Clear WOL on pattern match. */ 2925 CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL); 2926 /* Disable WOL on magic/unicast packet. */ 2927 CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F); 2928 CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM | 2929 VGE_WOLCFG_PMEOVR); 2930 /* Clear WOL status on pattern match. */ 2931 CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF); 2932 CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF); 2933} 2934