1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * This file contains the driver for the AVR32 series USB Device 30 * Controller 31 */ 32 33/* 34 * NOTE: When the chip detects BUS-reset it will also reset the 35 * endpoints, Function-address and more. 36 */ 37#ifdef USB_GLOBAL_INCLUDE_FILE 38#include USB_GLOBAL_INCLUDE_FILE 39#else 40#include <sys/stdint.h> 41#include <sys/stddef.h> 42#include <sys/param.h> 43#include <sys/queue.h> 44#include <sys/types.h> 45#include <sys/systm.h> 46#include <sys/kernel.h> 47#include <sys/bus.h> 48#include <sys/module.h> 49#include <sys/lock.h> 50#include <sys/mutex.h> 51#include <sys/condvar.h> 52#include <sys/sysctl.h> 53#include <sys/sx.h> 54#include <sys/unistd.h> 55#include <sys/callout.h> 56#include <sys/malloc.h> 57#include <sys/priv.h> 58 59#include <dev/usb/usb.h> 60#include <dev/usb/usbdi.h> 61 62#define USB_DEBUG_VAR avr32dci_debug 63 64#include <dev/usb/usb_core.h> 65#include <dev/usb/usb_debug.h> 66#include <dev/usb/usb_busdma.h> 67#include <dev/usb/usb_process.h> 68#include <dev/usb/usb_transfer.h> 69#include <dev/usb/usb_device.h> 70#include <dev/usb/usb_hub.h> 71#include <dev/usb/usb_util.h> 72 73#include <dev/usb/usb_controller.h> 74#include <dev/usb/usb_bus.h> 75#endif /* USB_GLOBAL_INCLUDE_FILE */ 76 77#include <dev/usb/controller/avr32dci.h> 78 79#define AVR32_BUS2SC(bus) \ 80 __containerof(bus, struct avr32dci_softc, sc_bus) 81 82#define AVR32_PC2SC(pc) \ 83 AVR32_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 84 85#ifdef USB_DEBUG 86static int avr32dci_debug = 0; 87 88static SYSCTL_NODE(_hw_usb, OID_AUTO, avr32dci, 89 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 90 "USB AVR32 DCI"); 91SYSCTL_INT(_hw_usb_avr32dci, OID_AUTO, debug, CTLFLAG_RWTUN, 92 &avr32dci_debug, 0, "AVR32 DCI debug level"); 93#endif 94 95#define AVR32_INTR_ENDPT 1 96 97/* prototypes */ 98 99static const struct usb_bus_methods avr32dci_bus_methods; 100static const struct usb_pipe_methods avr32dci_device_non_isoc_methods; 101static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods; 102 103static avr32dci_cmd_t avr32dci_setup_rx; 104static avr32dci_cmd_t avr32dci_data_rx; 105static avr32dci_cmd_t avr32dci_data_tx; 106static avr32dci_cmd_t avr32dci_data_tx_sync; 107static void avr32dci_device_done(struct usb_xfer *, usb_error_t); 108static void avr32dci_do_poll(struct usb_bus *); 109static void avr32dci_standard_done(struct usb_xfer *); 110static void avr32dci_root_intr(struct avr32dci_softc *sc); 111 112/* 113 * Here is a list of what the chip supports: 114 */ 115static const struct usb_hw_ep_profile 116 avr32dci_ep_profile[4] = { 117 [0] = { 118 .max_in_frame_size = 64, 119 .max_out_frame_size = 64, 120 .is_simplex = 1, 121 .support_control = 1, 122 }, 123 124 [1] = { 125 .max_in_frame_size = 512, 126 .max_out_frame_size = 512, 127 .is_simplex = 1, 128 .support_bulk = 1, 129 .support_interrupt = 1, 130 .support_isochronous = 1, 131 .support_in = 1, 132 .support_out = 1, 133 }, 134 135 [2] = { 136 .max_in_frame_size = 64, 137 .max_out_frame_size = 64, 138 .is_simplex = 1, 139 .support_bulk = 1, 140 .support_interrupt = 1, 141 .support_in = 1, 142 .support_out = 1, 143 }, 144 145 [3] = { 146 .max_in_frame_size = 1024, 147 .max_out_frame_size = 1024, 148 .is_simplex = 1, 149 .support_bulk = 1, 150 .support_interrupt = 1, 151 .support_isochronous = 1, 152 .support_in = 1, 153 .support_out = 1, 154 }, 155}; 156 157static void 158avr32dci_get_hw_ep_profile(struct usb_device *udev, 159 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 160{ 161 if (ep_addr == 0) 162 *ppf = avr32dci_ep_profile; 163 else if (ep_addr < 3) 164 *ppf = avr32dci_ep_profile + 1; 165 else if (ep_addr < 5) 166 *ppf = avr32dci_ep_profile + 2; 167 else if (ep_addr < 7) 168 *ppf = avr32dci_ep_profile + 3; 169 else 170 *ppf = NULL; 171} 172 173static void 174avr32dci_mod_ctrl(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) 175{ 176 uint32_t temp; 177 178 temp = AVR32_READ_4(sc, AVR32_CTRL); 179 temp |= set; 180 temp &= ~clear; 181 AVR32_WRITE_4(sc, AVR32_CTRL, temp); 182} 183 184static void 185avr32dci_mod_ien(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) 186{ 187 uint32_t temp; 188 189 temp = AVR32_READ_4(sc, AVR32_IEN); 190 temp |= set; 191 temp &= ~clear; 192 AVR32_WRITE_4(sc, AVR32_IEN, temp); 193} 194 195static void 196avr32dci_clocks_on(struct avr32dci_softc *sc) 197{ 198 if (sc->sc_flags.clocks_off && 199 sc->sc_flags.port_powered) { 200 DPRINTFN(5, "\n"); 201 202 /* turn on clocks */ 203 (sc->sc_clocks_on) (&sc->sc_bus); 204 205 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); 206 207 sc->sc_flags.clocks_off = 0; 208 } 209} 210 211static void 212avr32dci_clocks_off(struct avr32dci_softc *sc) 213{ 214 if (!sc->sc_flags.clocks_off) { 215 DPRINTFN(5, "\n"); 216 217 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_EN_USBA); 218 219 /* turn clocks off */ 220 (sc->sc_clocks_off) (&sc->sc_bus); 221 222 sc->sc_flags.clocks_off = 1; 223 } 224} 225 226static void 227avr32dci_pull_up(struct avr32dci_softc *sc) 228{ 229 /* pullup D+, if possible */ 230 231 if (!sc->sc_flags.d_pulled_up && 232 sc->sc_flags.port_powered) { 233 sc->sc_flags.d_pulled_up = 1; 234 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_DETACH); 235 } 236} 237 238static void 239avr32dci_pull_down(struct avr32dci_softc *sc) 240{ 241 /* pulldown D+, if possible */ 242 243 if (sc->sc_flags.d_pulled_up) { 244 sc->sc_flags.d_pulled_up = 0; 245 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); 246 } 247} 248 249static void 250avr32dci_wakeup_peer(struct avr32dci_softc *sc) 251{ 252 if (!sc->sc_flags.status_suspend) { 253 return; 254 } 255 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_REWAKEUP, 0); 256 257 /* wait 8 milliseconds */ 258 /* Wait for reset to complete. */ 259 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 260 261 /* hardware should have cleared RMWKUP bit */ 262} 263 264static void 265avr32dci_set_address(struct avr32dci_softc *sc, uint8_t addr) 266{ 267 DPRINTFN(5, "addr=%d\n", addr); 268 269 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_FADDR_EN | addr, 0); 270} 271 272static uint8_t 273avr32dci_setup_rx(struct avr32dci_td *td) 274{ 275 struct avr32dci_softc *sc; 276 struct usb_device_request req; 277 uint16_t count; 278 uint32_t temp; 279 280 /* get pointer to softc */ 281 sc = AVR32_PC2SC(td->pc); 282 283 /* check endpoint status */ 284 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 285 286 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 287 288 if (!(temp & AVR32_EPTSTA_RX_SETUP)) { 289 goto not_complete; 290 } 291 /* clear did stall */ 292 td->did_stall = 0; 293 /* get the packet byte count */ 294 count = AVR32_EPTSTA_BYTE_COUNT(temp); 295 296 /* verify data length */ 297 if (count != td->remainder) { 298 DPRINTFN(0, "Invalid SETUP packet " 299 "length, %d bytes\n", count); 300 goto not_complete; 301 } 302 if (count != sizeof(req)) { 303 DPRINTFN(0, "Unsupported SETUP packet " 304 "length, %d bytes\n", count); 305 goto not_complete; 306 } 307 /* receive data */ 308 memcpy(&req, sc->physdata, sizeof(req)); 309 310 /* copy data into real buffer */ 311 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 312 313 td->offset = sizeof(req); 314 td->remainder = 0; 315 316 /* sneak peek the set address */ 317 if ((req.bmRequestType == UT_WRITE_DEVICE) && 318 (req.bRequest == UR_SET_ADDRESS)) { 319 sc->sc_dv_addr = req.wValue[0] & 0x7F; 320 /* must write address before ZLP */ 321 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_FADDR_EN | 322 AVR32_CTRL_DEV_ADDR); 323 avr32dci_mod_ctrl(sc, sc->sc_dv_addr, 0); 324 } else { 325 sc->sc_dv_addr = 0xFF; 326 } 327 328 /* clear SETUP packet interrupt */ 329 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); 330 return (0); /* complete */ 331 332not_complete: 333 if (temp & AVR32_EPTSTA_RX_SETUP) { 334 /* clear SETUP packet interrupt */ 335 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); 336 } 337 /* abort any ongoing transfer */ 338 if (!td->did_stall) { 339 DPRINTFN(5, "stalling\n"); 340 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(td->ep_no), 341 AVR32_EPTSTA_FRCESTALL); 342 td->did_stall = 1; 343 } 344 return (1); /* not complete */ 345} 346 347static uint8_t 348avr32dci_data_rx(struct avr32dci_td *td) 349{ 350 struct avr32dci_softc *sc; 351 struct usb_page_search buf_res; 352 uint16_t count; 353 uint32_t temp; 354 uint8_t to; 355 uint8_t got_short; 356 357 to = 4; /* don't loop forever! */ 358 got_short = 0; 359 360 /* get pointer to softc */ 361 sc = AVR32_PC2SC(td->pc); 362 363repeat: 364 /* check if any of the FIFO banks have data */ 365 /* check endpoint status */ 366 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 367 368 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 369 370 if (temp & AVR32_EPTSTA_RX_SETUP) { 371 if (td->remainder == 0) { 372 /* 373 * We are actually complete and have 374 * received the next SETUP 375 */ 376 DPRINTFN(5, "faking complete\n"); 377 return (0); /* complete */ 378 } 379 /* 380 * USB Host Aborted the transfer. 381 */ 382 td->error = 1; 383 return (0); /* complete */ 384 } 385 /* check status */ 386 if (!(temp & AVR32_EPTSTA_RX_BK_RDY)) { 387 /* no data */ 388 goto not_complete; 389 } 390 /* get the packet byte count */ 391 count = AVR32_EPTSTA_BYTE_COUNT(temp); 392 393 /* verify the packet byte count */ 394 if (count != td->max_packet_size) { 395 if (count < td->max_packet_size) { 396 /* we have a short packet */ 397 td->short_pkt = 1; 398 got_short = 1; 399 } else { 400 /* invalid USB packet */ 401 td->error = 1; 402 return (0); /* we are complete */ 403 } 404 } 405 /* verify the packet byte count */ 406 if (count > td->remainder) { 407 /* invalid USB packet */ 408 td->error = 1; 409 return (0); /* we are complete */ 410 } 411 while (count > 0) { 412 usbd_get_page(td->pc, td->offset, &buf_res); 413 414 /* get correct length */ 415 if (buf_res.length > count) { 416 buf_res.length = count; 417 } 418 /* receive data */ 419 memcpy(buf_res.buffer, sc->physdata + 420 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + 421 (td->ep_no << 16) + (td->offset % td->max_packet_size), buf_res.length); 422 /* update counters */ 423 count -= buf_res.length; 424 td->offset += buf_res.length; 425 td->remainder -= buf_res.length; 426 } 427 428 /* clear OUT packet interrupt */ 429 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_BK_RDY); 430 431 /* check if we are complete */ 432 if ((td->remainder == 0) || got_short) { 433 if (td->short_pkt) { 434 /* we are complete */ 435 return (0); 436 } 437 /* else need to receive a zero length packet */ 438 } 439 if (--to) { 440 goto repeat; 441 } 442not_complete: 443 return (1); /* not complete */ 444} 445 446static uint8_t 447avr32dci_data_tx(struct avr32dci_td *td) 448{ 449 struct avr32dci_softc *sc; 450 struct usb_page_search buf_res; 451 uint16_t count; 452 uint8_t to; 453 uint32_t temp; 454 455 to = 4; /* don't loop forever! */ 456 457 /* get pointer to softc */ 458 sc = AVR32_PC2SC(td->pc); 459 460repeat: 461 462 /* check endpoint status */ 463 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 464 465 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 466 467 if (temp & AVR32_EPTSTA_RX_SETUP) { 468 /* 469 * The current transfer was aborted 470 * by the USB Host 471 */ 472 td->error = 1; 473 return (0); /* complete */ 474 } 475 if (temp & AVR32_EPTSTA_TX_PK_RDY) { 476 /* cannot write any data - all banks are busy */ 477 goto not_complete; 478 } 479 count = td->max_packet_size; 480 if (td->remainder < count) { 481 /* we have a short packet */ 482 td->short_pkt = 1; 483 count = td->remainder; 484 } 485 while (count > 0) { 486 usbd_get_page(td->pc, td->offset, &buf_res); 487 488 /* get correct length */ 489 if (buf_res.length > count) { 490 buf_res.length = count; 491 } 492 /* transmit data */ 493 memcpy(sc->physdata + 494 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + 495 (td->ep_no << 16) + (td->offset % td->max_packet_size), 496 buf_res.buffer, buf_res.length); 497 /* update counters */ 498 count -= buf_res.length; 499 td->offset += buf_res.length; 500 td->remainder -= buf_res.length; 501 } 502 503 /* allocate FIFO bank */ 504 AVR32_WRITE_4(sc, AVR32_EPTCTL(td->ep_no), AVR32_EPTCTL_TX_PK_RDY); 505 506 /* check remainder */ 507 if (td->remainder == 0) { 508 if (td->short_pkt) { 509 return (0); /* complete */ 510 } 511 /* else we need to transmit a short packet */ 512 } 513 if (--to) { 514 goto repeat; 515 } 516not_complete: 517 return (1); /* not complete */ 518} 519 520static uint8_t 521avr32dci_data_tx_sync(struct avr32dci_td *td) 522{ 523 struct avr32dci_softc *sc; 524 uint32_t temp; 525 526 /* get pointer to softc */ 527 sc = AVR32_PC2SC(td->pc); 528 529 /* check endpoint status */ 530 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 531 532 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 533 534 if (temp & AVR32_EPTSTA_RX_SETUP) { 535 DPRINTFN(5, "faking complete\n"); 536 /* Race condition */ 537 return (0); /* complete */ 538 } 539 /* 540 * The control endpoint has only got one bank, so if that bank 541 * is free the packet has been transferred! 542 */ 543 if (AVR32_EPTSTA_BUSY_BANK_STA(temp) != 0) { 544 /* cannot write any data - a bank is busy */ 545 goto not_complete; 546 } 547 if (sc->sc_dv_addr != 0xFF) { 548 /* set new address */ 549 avr32dci_set_address(sc, sc->sc_dv_addr); 550 } 551 return (0); /* complete */ 552 553not_complete: 554 return (1); /* not complete */ 555} 556 557static uint8_t 558avr32dci_xfer_do_fifo(struct usb_xfer *xfer) 559{ 560 struct avr32dci_td *td; 561 562 DPRINTFN(9, "\n"); 563 564 td = xfer->td_transfer_cache; 565 while (1) { 566 if ((td->func) (td)) { 567 /* operation in progress */ 568 break; 569 } 570 if (((void *)td) == xfer->td_transfer_last) { 571 goto done; 572 } 573 if (td->error) { 574 goto done; 575 } else if (td->remainder > 0) { 576 /* 577 * We had a short transfer. If there is no alternate 578 * next, stop processing ! 579 */ 580 if (!td->alt_next) { 581 goto done; 582 } 583 } 584 /* 585 * Fetch the next transfer descriptor and transfer 586 * some flags to the next transfer descriptor 587 */ 588 td = td->obj_next; 589 xfer->td_transfer_cache = td; 590 } 591 return (1); /* not complete */ 592 593done: 594 /* compute all actual lengths */ 595 596 avr32dci_standard_done(xfer); 597 return (0); /* complete */ 598} 599 600static void 601avr32dci_interrupt_poll(struct avr32dci_softc *sc) 602{ 603 struct usb_xfer *xfer; 604 605repeat: 606 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 607 if (!avr32dci_xfer_do_fifo(xfer)) { 608 /* queue has been modified */ 609 goto repeat; 610 } 611 } 612} 613 614void 615avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on) 616{ 617 DPRINTFN(5, "vbus = %u\n", is_on); 618 619 if (is_on) { 620 if (!sc->sc_flags.status_vbus) { 621 sc->sc_flags.status_vbus = 1; 622 623 /* complete root HUB interrupt endpoint */ 624 625 avr32dci_root_intr(sc); 626 } 627 } else { 628 if (sc->sc_flags.status_vbus) { 629 sc->sc_flags.status_vbus = 0; 630 sc->sc_flags.status_bus_reset = 0; 631 sc->sc_flags.status_suspend = 0; 632 sc->sc_flags.change_suspend = 0; 633 sc->sc_flags.change_connect = 1; 634 635 /* complete root HUB interrupt endpoint */ 636 637 avr32dci_root_intr(sc); 638 } 639 } 640} 641 642void 643avr32dci_interrupt(struct avr32dci_softc *sc) 644{ 645 uint32_t status; 646 647 USB_BUS_LOCK(&sc->sc_bus); 648 649 /* read interrupt status */ 650 status = AVR32_READ_4(sc, AVR32_INTSTA); 651 652 /* clear all set interrupts */ 653 AVR32_WRITE_4(sc, AVR32_CLRINT, status); 654 655 DPRINTFN(14, "INTSTA=0x%08x\n", status); 656 657 /* check for any bus state change interrupts */ 658 if (status & AVR32_INT_ENDRESET) { 659 DPRINTFN(5, "end of reset\n"); 660 661 /* set correct state */ 662 sc->sc_flags.status_bus_reset = 1; 663 sc->sc_flags.status_suspend = 0; 664 sc->sc_flags.change_suspend = 0; 665 sc->sc_flags.change_connect = 1; 666 667 /* disable resume interrupt */ 668 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 669 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); 670 671 /* complete root HUB interrupt endpoint */ 672 avr32dci_root_intr(sc); 673 } 674 /* 675 * If resume and suspend is set at the same time we interpret 676 * that like RESUME. Resume is set when there is at least 3 677 * milliseconds of inactivity on the USB BUS. 678 */ 679 if (status & AVR32_INT_WAKE_UP) { 680 DPRINTFN(5, "resume interrupt\n"); 681 682 if (sc->sc_flags.status_suspend) { 683 /* update status bits */ 684 sc->sc_flags.status_suspend = 0; 685 sc->sc_flags.change_suspend = 1; 686 687 /* disable resume interrupt */ 688 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 689 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); 690 691 /* complete root HUB interrupt endpoint */ 692 avr32dci_root_intr(sc); 693 } 694 } else if (status & AVR32_INT_DET_SUSPD) { 695 DPRINTFN(5, "suspend interrupt\n"); 696 697 if (!sc->sc_flags.status_suspend) { 698 /* update status bits */ 699 sc->sc_flags.status_suspend = 1; 700 sc->sc_flags.change_suspend = 1; 701 702 /* disable suspend interrupt */ 703 avr32dci_mod_ien(sc, AVR32_INT_WAKE_UP | 704 AVR32_INT_ENDRESET, AVR32_INT_DET_SUSPD); 705 706 /* complete root HUB interrupt endpoint */ 707 avr32dci_root_intr(sc); 708 } 709 } 710 /* check for any endpoint interrupts */ 711 if (status & -AVR32_INT_EPT_INT(0)) { 712 DPRINTFN(5, "real endpoint interrupt\n"); 713 714 avr32dci_interrupt_poll(sc); 715 } 716 USB_BUS_UNLOCK(&sc->sc_bus); 717} 718 719static void 720avr32dci_setup_standard_chain_sub(struct avr32dci_std_temp *temp) 721{ 722 struct avr32dci_td *td; 723 724 /* get current Transfer Descriptor */ 725 td = temp->td_next; 726 temp->td = td; 727 728 /* prepare for next TD */ 729 temp->td_next = td->obj_next; 730 731 /* fill out the Transfer Descriptor */ 732 td->func = temp->func; 733 td->pc = temp->pc; 734 td->offset = temp->offset; 735 td->remainder = temp->len; 736 td->error = 0; 737 td->did_stall = temp->did_stall; 738 td->short_pkt = temp->short_pkt; 739 td->alt_next = temp->setup_alt_next; 740} 741 742static void 743avr32dci_setup_standard_chain(struct usb_xfer *xfer) 744{ 745 struct avr32dci_std_temp temp; 746 struct avr32dci_softc *sc; 747 struct avr32dci_td *td; 748 uint32_t x; 749 uint8_t ep_no; 750 uint8_t need_sync; 751 752 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 753 xfer->address, UE_GET_ADDR(xfer->endpointno), 754 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 755 756 temp.max_frame_size = xfer->max_frame_size; 757 758 td = xfer->td_start[0]; 759 xfer->td_transfer_first = td; 760 xfer->td_transfer_cache = td; 761 762 /* setup temp */ 763 764 temp.pc = NULL; 765 temp.td = NULL; 766 temp.td_next = xfer->td_start[0]; 767 temp.offset = 0; 768 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 769 xfer->flags_int.isochronous_xfr; 770 temp.did_stall = !xfer->flags_int.control_stall; 771 772 sc = AVR32_BUS2SC(xfer->xroot->bus); 773 ep_no = (xfer->endpointno & UE_ADDR); 774 775 /* check if we should prepend a setup message */ 776 777 if (xfer->flags_int.control_xfr) { 778 if (xfer->flags_int.control_hdr) { 779 temp.func = &avr32dci_setup_rx; 780 temp.len = xfer->frlengths[0]; 781 temp.pc = xfer->frbuffers + 0; 782 temp.short_pkt = temp.len ? 1 : 0; 783 /* check for last frame */ 784 if (xfer->nframes == 1) { 785 /* no STATUS stage yet, SETUP is last */ 786 if (xfer->flags_int.control_act) 787 temp.setup_alt_next = 0; 788 } 789 avr32dci_setup_standard_chain_sub(&temp); 790 } 791 x = 1; 792 } else { 793 x = 0; 794 } 795 796 if (x != xfer->nframes) { 797 if (xfer->endpointno & UE_DIR_IN) { 798 temp.func = &avr32dci_data_tx; 799 need_sync = 1; 800 } else { 801 temp.func = &avr32dci_data_rx; 802 need_sync = 0; 803 } 804 805 /* setup "pc" pointer */ 806 temp.pc = xfer->frbuffers + x; 807 } else { 808 need_sync = 0; 809 } 810 while (x != xfer->nframes) { 811 /* DATA0 / DATA1 message */ 812 813 temp.len = xfer->frlengths[x]; 814 815 x++; 816 817 if (x == xfer->nframes) { 818 if (xfer->flags_int.control_xfr) { 819 if (xfer->flags_int.control_act) { 820 temp.setup_alt_next = 0; 821 } 822 } else { 823 temp.setup_alt_next = 0; 824 } 825 } 826 if (temp.len == 0) { 827 /* make sure that we send an USB packet */ 828 829 temp.short_pkt = 0; 830 831 } else { 832 /* regular data transfer */ 833 834 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 835 } 836 837 avr32dci_setup_standard_chain_sub(&temp); 838 839 if (xfer->flags_int.isochronous_xfr) { 840 temp.offset += temp.len; 841 } else { 842 /* get next Page Cache pointer */ 843 temp.pc = xfer->frbuffers + x; 844 } 845 } 846 847 if (xfer->flags_int.control_xfr) { 848 /* always setup a valid "pc" pointer for status and sync */ 849 temp.pc = xfer->frbuffers + 0; 850 temp.len = 0; 851 temp.short_pkt = 0; 852 temp.setup_alt_next = 0; 853 854 /* check if we need to sync */ 855 if (need_sync) { 856 /* we need a SYNC point after TX */ 857 temp.func = &avr32dci_data_tx_sync; 858 avr32dci_setup_standard_chain_sub(&temp); 859 } 860 /* check if we should append a status stage */ 861 if (!xfer->flags_int.control_act) { 862 /* 863 * Send a DATA1 message and invert the current 864 * endpoint direction. 865 */ 866 if (xfer->endpointno & UE_DIR_IN) { 867 temp.func = &avr32dci_data_rx; 868 need_sync = 0; 869 } else { 870 temp.func = &avr32dci_data_tx; 871 need_sync = 1; 872 } 873 874 avr32dci_setup_standard_chain_sub(&temp); 875 if (need_sync) { 876 /* we need a SYNC point after TX */ 877 temp.func = &avr32dci_data_tx_sync; 878 avr32dci_setup_standard_chain_sub(&temp); 879 } 880 } 881 } 882 /* must have at least one frame! */ 883 td = temp.td; 884 xfer->td_transfer_last = td; 885} 886 887static void 888avr32dci_timeout(void *arg) 889{ 890 struct usb_xfer *xfer = arg; 891 892 DPRINTF("xfer=%p\n", xfer); 893 894 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 895 896 /* transfer is transferred */ 897 avr32dci_device_done(xfer, USB_ERR_TIMEOUT); 898} 899 900static void 901avr32dci_start_standard_chain(struct usb_xfer *xfer) 902{ 903 DPRINTFN(9, "\n"); 904 905 /* poll one time - will turn on interrupts */ 906 if (avr32dci_xfer_do_fifo(xfer)) { 907 uint8_t ep_no = xfer->endpointno & UE_ADDR; 908 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 909 910 avr32dci_mod_ien(sc, AVR32_INT_EPT_INT(ep_no), 0); 911 912 /* put transfer on interrupt queue */ 913 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 914 915 /* start timeout, if any */ 916 if (xfer->timeout != 0) { 917 usbd_transfer_timeout_ms(xfer, 918 &avr32dci_timeout, xfer->timeout); 919 } 920 } 921} 922 923static void 924avr32dci_root_intr(struct avr32dci_softc *sc) 925{ 926 DPRINTFN(9, "\n"); 927 928 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 929 930 /* set port bit */ 931 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 932 933 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 934 sizeof(sc->sc_hub_idata)); 935} 936 937static usb_error_t 938avr32dci_standard_done_sub(struct usb_xfer *xfer) 939{ 940 struct avr32dci_td *td; 941 uint32_t len; 942 uint8_t error; 943 944 DPRINTFN(9, "\n"); 945 946 td = xfer->td_transfer_cache; 947 948 do { 949 len = td->remainder; 950 951 if (xfer->aframes != xfer->nframes) { 952 /* 953 * Verify the length and subtract 954 * the remainder from "frlengths[]": 955 */ 956 if (len > xfer->frlengths[xfer->aframes]) { 957 td->error = 1; 958 } else { 959 xfer->frlengths[xfer->aframes] -= len; 960 } 961 } 962 /* Check for transfer error */ 963 if (td->error) { 964 /* the transfer is finished */ 965 error = 1; 966 td = NULL; 967 break; 968 } 969 /* Check for short transfer */ 970 if (len > 0) { 971 if (xfer->flags_int.short_frames_ok || 972 xfer->flags_int.isochronous_xfr) { 973 /* follow alt next */ 974 if (td->alt_next) { 975 td = td->obj_next; 976 } else { 977 td = NULL; 978 } 979 } else { 980 /* the transfer is finished */ 981 td = NULL; 982 } 983 error = 0; 984 break; 985 } 986 td = td->obj_next; 987 988 /* this USB frame is complete */ 989 error = 0; 990 break; 991 992 } while (0); 993 994 /* update transfer cache */ 995 996 xfer->td_transfer_cache = td; 997 998 return (error ? 999 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1000} 1001 1002static void 1003avr32dci_standard_done(struct usb_xfer *xfer) 1004{ 1005 usb_error_t err = 0; 1006 1007 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1008 xfer, xfer->endpoint); 1009 1010 /* reset scanner */ 1011 1012 xfer->td_transfer_cache = xfer->td_transfer_first; 1013 1014 if (xfer->flags_int.control_xfr) { 1015 if (xfer->flags_int.control_hdr) { 1016 err = avr32dci_standard_done_sub(xfer); 1017 } 1018 xfer->aframes = 1; 1019 1020 if (xfer->td_transfer_cache == NULL) { 1021 goto done; 1022 } 1023 } 1024 while (xfer->aframes != xfer->nframes) { 1025 err = avr32dci_standard_done_sub(xfer); 1026 xfer->aframes++; 1027 1028 if (xfer->td_transfer_cache == NULL) { 1029 goto done; 1030 } 1031 } 1032 1033 if (xfer->flags_int.control_xfr && 1034 !xfer->flags_int.control_act) { 1035 err = avr32dci_standard_done_sub(xfer); 1036 } 1037done: 1038 avr32dci_device_done(xfer, err); 1039} 1040 1041/*------------------------------------------------------------------------* 1042 * avr32dci_device_done 1043 * 1044 * NOTE: this function can be called more than one time on the 1045 * same USB transfer! 1046 *------------------------------------------------------------------------*/ 1047static void 1048avr32dci_device_done(struct usb_xfer *xfer, usb_error_t error) 1049{ 1050 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 1051 uint8_t ep_no; 1052 1053 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1054 1055 DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n", 1056 xfer, xfer->endpoint, error); 1057 1058 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1059 ep_no = (xfer->endpointno & UE_ADDR); 1060 1061 /* disable endpoint interrupt */ 1062 avr32dci_mod_ien(sc, 0, AVR32_INT_EPT_INT(ep_no)); 1063 1064 DPRINTFN(15, "disabled interrupts!\n"); 1065 } 1066 /* dequeue transfer and start next transfer */ 1067 usbd_transfer_done(xfer, error); 1068} 1069 1070static void 1071avr32dci_xfer_stall(struct usb_xfer *xfer) 1072{ 1073 avr32dci_device_done(xfer, USB_ERR_STALLED); 1074} 1075 1076static void 1077avr32dci_set_stall(struct usb_device *udev, 1078 struct usb_endpoint *pipe, uint8_t *did_stall) 1079{ 1080 struct avr32dci_softc *sc; 1081 uint8_t ep_no; 1082 1083 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1084 1085 DPRINTFN(5, "pipe=%p\n", pipe); 1086 1087 sc = AVR32_BUS2SC(udev->bus); 1088 /* get endpoint number */ 1089 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1090 /* set stall */ 1091 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1092} 1093 1094static void 1095avr32dci_clear_stall_sub(struct avr32dci_softc *sc, uint8_t ep_no, 1096 uint8_t ep_type, uint8_t ep_dir) 1097{ 1098 const struct usb_hw_ep_profile *pf; 1099 uint32_t temp; 1100 uint32_t epsize; 1101 uint8_t n; 1102 1103 if (ep_type == UE_CONTROL) { 1104 /* clearing stall is not needed */ 1105 return; 1106 } 1107 /* set endpoint reset */ 1108 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(ep_no)); 1109 1110 /* set stall */ 1111 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1112 1113 /* reset data toggle */ 1114 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_TOGGLESQ); 1115 1116 /* clear stall */ 1117 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1118 1119 if (ep_type == UE_BULK) { 1120 temp = AVR32_EPTCFG_TYPE_BULK; 1121 } else if (ep_type == UE_INTERRUPT) { 1122 temp = AVR32_EPTCFG_TYPE_INTR; 1123 } else { 1124 temp = AVR32_EPTCFG_TYPE_ISOC | 1125 AVR32_EPTCFG_NB_TRANS(1); 1126 } 1127 if (ep_dir & UE_DIR_IN) { 1128 temp |= AVR32_EPTCFG_EPDIR_IN; 1129 } 1130 avr32dci_get_hw_ep_profile(NULL, &pf, ep_no); 1131 1132 /* compute endpoint size (use maximum) */ 1133 epsize = pf->max_in_frame_size | pf->max_out_frame_size; 1134 n = 0; 1135 while ((epsize /= 2)) 1136 n++; 1137 temp |= AVR32_EPTCFG_EPSIZE(n); 1138 1139 /* use the maximum number of banks supported */ 1140 if (ep_no < 1) 1141 temp |= AVR32_EPTCFG_NBANK(1); 1142 else if (ep_no < 3) 1143 temp |= AVR32_EPTCFG_NBANK(2); 1144 else 1145 temp |= AVR32_EPTCFG_NBANK(3); 1146 1147 AVR32_WRITE_4(sc, AVR32_EPTCFG(ep_no), temp); 1148 1149 temp = AVR32_READ_4(sc, AVR32_EPTCFG(ep_no)); 1150 1151 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { 1152 device_printf(sc->sc_bus.bdev, "Chip rejected configuration\n"); 1153 } else { 1154 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(ep_no), 1155 AVR32_EPTCTL_EPT_ENABL); 1156 } 1157} 1158 1159static void 1160avr32dci_clear_stall(struct usb_device *udev, struct usb_endpoint *pipe) 1161{ 1162 struct avr32dci_softc *sc; 1163 struct usb_endpoint_descriptor *ed; 1164 1165 DPRINTFN(5, "pipe=%p\n", pipe); 1166 1167 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1168 1169 /* check mode */ 1170 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1171 /* not supported */ 1172 return; 1173 } 1174 /* get softc */ 1175 sc = AVR32_BUS2SC(udev->bus); 1176 1177 /* get endpoint descriptor */ 1178 ed = pipe->edesc; 1179 1180 /* reset endpoint */ 1181 avr32dci_clear_stall_sub(sc, 1182 (ed->bEndpointAddress & UE_ADDR), 1183 (ed->bmAttributes & UE_XFERTYPE), 1184 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1185} 1186 1187usb_error_t 1188avr32dci_init(struct avr32dci_softc *sc) 1189{ 1190 uint8_t n; 1191 1192 DPRINTF("start\n"); 1193 1194 /* set up the bus structure */ 1195 sc->sc_bus.usbrev = USB_REV_1_1; 1196 sc->sc_bus.methods = &avr32dci_bus_methods; 1197 1198 USB_BUS_LOCK(&sc->sc_bus); 1199 1200 /* make sure USB is enabled */ 1201 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); 1202 1203 /* turn on clocks */ 1204 (sc->sc_clocks_on) (&sc->sc_bus); 1205 1206 /* make sure device is re-enumerated */ 1207 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); 1208 1209 /* wait a little for things to stabilise */ 1210 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1211 1212 /* disable interrupts */ 1213 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); 1214 1215 /* enable interrupts */ 1216 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 1217 AVR32_INT_ENDRESET, 0); 1218 1219 /* reset all endpoints */ 1220 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1); 1221 1222 /* disable all endpoints */ 1223 for (n = 0; n != AVR32_EP_MAX; n++) { 1224 /* disable endpoint */ 1225 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); 1226 } 1227 1228 /* turn off clocks */ 1229 1230 avr32dci_clocks_off(sc); 1231 1232 USB_BUS_UNLOCK(&sc->sc_bus); 1233 1234 /* catch any lost interrupts */ 1235 1236 avr32dci_do_poll(&sc->sc_bus); 1237 1238 return (0); /* success */ 1239} 1240 1241void 1242avr32dci_uninit(struct avr32dci_softc *sc) 1243{ 1244 uint8_t n; 1245 1246 USB_BUS_LOCK(&sc->sc_bus); 1247 1248 /* turn on clocks */ 1249 (sc->sc_clocks_on) (&sc->sc_bus); 1250 1251 /* disable interrupts */ 1252 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); 1253 1254 /* reset all endpoints */ 1255 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1); 1256 1257 /* disable all endpoints */ 1258 for (n = 0; n != AVR32_EP_MAX; n++) { 1259 /* disable endpoint */ 1260 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); 1261 } 1262 1263 sc->sc_flags.port_powered = 0; 1264 sc->sc_flags.status_vbus = 0; 1265 sc->sc_flags.status_bus_reset = 0; 1266 sc->sc_flags.status_suspend = 0; 1267 sc->sc_flags.change_suspend = 0; 1268 sc->sc_flags.change_connect = 1; 1269 1270 avr32dci_pull_down(sc); 1271 avr32dci_clocks_off(sc); 1272 1273 USB_BUS_UNLOCK(&sc->sc_bus); 1274} 1275 1276static void 1277avr32dci_suspend(struct avr32dci_softc *sc) 1278{ 1279 /* TODO */ 1280} 1281 1282static void 1283avr32dci_resume(struct avr32dci_softc *sc) 1284{ 1285 /* TODO */ 1286} 1287 1288static void 1289avr32dci_do_poll(struct usb_bus *bus) 1290{ 1291 struct avr32dci_softc *sc = AVR32_BUS2SC(bus); 1292 1293 USB_BUS_LOCK(&sc->sc_bus); 1294 avr32dci_interrupt_poll(sc); 1295 USB_BUS_UNLOCK(&sc->sc_bus); 1296} 1297 1298/*------------------------------------------------------------------------* 1299 * avr32dci bulk support 1300 * avr32dci control support 1301 * avr32dci interrupt support 1302 *------------------------------------------------------------------------*/ 1303static void 1304avr32dci_device_non_isoc_open(struct usb_xfer *xfer) 1305{ 1306 return; 1307} 1308 1309static void 1310avr32dci_device_non_isoc_close(struct usb_xfer *xfer) 1311{ 1312 avr32dci_device_done(xfer, USB_ERR_CANCELLED); 1313} 1314 1315static void 1316avr32dci_device_non_isoc_enter(struct usb_xfer *xfer) 1317{ 1318 return; 1319} 1320 1321static void 1322avr32dci_device_non_isoc_start(struct usb_xfer *xfer) 1323{ 1324 /* setup TDs */ 1325 avr32dci_setup_standard_chain(xfer); 1326 avr32dci_start_standard_chain(xfer); 1327} 1328 1329static const struct usb_pipe_methods avr32dci_device_non_isoc_methods = 1330{ 1331 .open = avr32dci_device_non_isoc_open, 1332 .close = avr32dci_device_non_isoc_close, 1333 .enter = avr32dci_device_non_isoc_enter, 1334 .start = avr32dci_device_non_isoc_start, 1335}; 1336 1337/*------------------------------------------------------------------------* 1338 * avr32dci full speed isochronous support 1339 *------------------------------------------------------------------------*/ 1340static void 1341avr32dci_device_isoc_fs_open(struct usb_xfer *xfer) 1342{ 1343 return; 1344} 1345 1346static void 1347avr32dci_device_isoc_fs_close(struct usb_xfer *xfer) 1348{ 1349 avr32dci_device_done(xfer, USB_ERR_CANCELLED); 1350} 1351 1352static void 1353avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer) 1354{ 1355 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 1356 uint32_t nframes; 1357 uint8_t ep_no; 1358 1359 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1360 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1361 1362 /* get the current frame index */ 1363 ep_no = xfer->endpointno & UE_ADDR; 1364 nframes = (AVR32_READ_4(sc, AVR32_FNUM) / 8); 1365 1366 if (usbd_xfer_get_isochronous_start_frame( 1367 xfer, nframes, 0, 1, AVR32_FRAME_MASK, NULL)) 1368 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1369 1370 /* setup TDs */ 1371 avr32dci_setup_standard_chain(xfer); 1372} 1373 1374static void 1375avr32dci_device_isoc_fs_start(struct usb_xfer *xfer) 1376{ 1377 /* start TD chain */ 1378 avr32dci_start_standard_chain(xfer); 1379} 1380 1381static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods = 1382{ 1383 .open = avr32dci_device_isoc_fs_open, 1384 .close = avr32dci_device_isoc_fs_close, 1385 .enter = avr32dci_device_isoc_fs_enter, 1386 .start = avr32dci_device_isoc_fs_start, 1387}; 1388 1389/*------------------------------------------------------------------------* 1390 * avr32dci root control support 1391 *------------------------------------------------------------------------* 1392 * Simulate a hardware HUB by handling all the necessary requests. 1393 *------------------------------------------------------------------------*/ 1394 1395static const struct usb_device_descriptor avr32dci_devd = { 1396 .bLength = sizeof(struct usb_device_descriptor), 1397 .bDescriptorType = UDESC_DEVICE, 1398 .bcdUSB = {0x00, 0x02}, 1399 .bDeviceClass = UDCLASS_HUB, 1400 .bDeviceSubClass = UDSUBCLASS_HUB, 1401 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1402 .bMaxPacketSize = 64, 1403 .bcdDevice = {0x00, 0x01}, 1404 .iManufacturer = 1, 1405 .iProduct = 2, 1406 .bNumConfigurations = 1, 1407}; 1408 1409static const struct usb_device_qualifier avr32dci_odevd = { 1410 .bLength = sizeof(struct usb_device_qualifier), 1411 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1412 .bcdUSB = {0x00, 0x02}, 1413 .bDeviceClass = UDCLASS_HUB, 1414 .bDeviceSubClass = UDSUBCLASS_HUB, 1415 .bDeviceProtocol = UDPROTO_FSHUB, 1416 .bMaxPacketSize0 = 0, 1417 .bNumConfigurations = 0, 1418}; 1419 1420static const struct avr32dci_config_desc avr32dci_confd = { 1421 .confd = { 1422 .bLength = sizeof(struct usb_config_descriptor), 1423 .bDescriptorType = UDESC_CONFIG, 1424 .wTotalLength[0] = sizeof(avr32dci_confd), 1425 .bNumInterface = 1, 1426 .bConfigurationValue = 1, 1427 .iConfiguration = 0, 1428 .bmAttributes = UC_SELF_POWERED, 1429 .bMaxPower = 0, 1430 }, 1431 .ifcd = { 1432 .bLength = sizeof(struct usb_interface_descriptor), 1433 .bDescriptorType = UDESC_INTERFACE, 1434 .bNumEndpoints = 1, 1435 .bInterfaceClass = UICLASS_HUB, 1436 .bInterfaceSubClass = UISUBCLASS_HUB, 1437 .bInterfaceProtocol = 0, 1438 }, 1439 .endpd = { 1440 .bLength = sizeof(struct usb_endpoint_descriptor), 1441 .bDescriptorType = UDESC_ENDPOINT, 1442 .bEndpointAddress = (UE_DIR_IN | AVR32_INTR_ENDPT), 1443 .bmAttributes = UE_INTERRUPT, 1444 .wMaxPacketSize[0] = 8, 1445 .bInterval = 255, 1446 }, 1447}; 1448#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 1449 1450static const struct usb_hub_descriptor_min avr32dci_hubd = { 1451 .bDescLength = sizeof(avr32dci_hubd), 1452 .bDescriptorType = UDESC_HUB, 1453 .bNbrPorts = 1, 1454 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 1455 .bPwrOn2PwrGood = 50, 1456 .bHubContrCurrent = 0, 1457 .DeviceRemovable = {0}, /* port is removable */ 1458}; 1459 1460#define STRING_VENDOR \ 1461 "A\0V\0R\0003\0002" 1462 1463#define STRING_PRODUCT \ 1464 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" 1465 1466USB_MAKE_STRING_DESC(STRING_VENDOR, avr32dci_vendor); 1467USB_MAKE_STRING_DESC(STRING_PRODUCT, avr32dci_product); 1468 1469static usb_error_t 1470avr32dci_roothub_exec(struct usb_device *udev, 1471 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1472{ 1473 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); 1474 const void *ptr; 1475 uint16_t len; 1476 uint16_t value; 1477 uint16_t index; 1478 uint32_t temp; 1479 usb_error_t err; 1480 1481 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1482 1483 /* buffer reset */ 1484 ptr = (const void *)&sc->sc_hub_temp; 1485 len = 0; 1486 err = 0; 1487 1488 value = UGETW(req->wValue); 1489 index = UGETW(req->wIndex); 1490 1491 /* demultiplex the control request */ 1492 1493 switch (req->bmRequestType) { 1494 case UT_READ_DEVICE: 1495 switch (req->bRequest) { 1496 case UR_GET_DESCRIPTOR: 1497 goto tr_handle_get_descriptor; 1498 case UR_GET_CONFIG: 1499 goto tr_handle_get_config; 1500 case UR_GET_STATUS: 1501 goto tr_handle_get_status; 1502 default: 1503 goto tr_stalled; 1504 } 1505 break; 1506 1507 case UT_WRITE_DEVICE: 1508 switch (req->bRequest) { 1509 case UR_SET_ADDRESS: 1510 goto tr_handle_set_address; 1511 case UR_SET_CONFIG: 1512 goto tr_handle_set_config; 1513 case UR_CLEAR_FEATURE: 1514 goto tr_valid; /* nop */ 1515 case UR_SET_DESCRIPTOR: 1516 goto tr_valid; /* nop */ 1517 case UR_SET_FEATURE: 1518 default: 1519 goto tr_stalled; 1520 } 1521 break; 1522 1523 case UT_WRITE_ENDPOINT: 1524 switch (req->bRequest) { 1525 case UR_CLEAR_FEATURE: 1526 switch (UGETW(req->wValue)) { 1527 case UF_ENDPOINT_HALT: 1528 goto tr_handle_clear_halt; 1529 case UF_DEVICE_REMOTE_WAKEUP: 1530 goto tr_handle_clear_wakeup; 1531 default: 1532 goto tr_stalled; 1533 } 1534 break; 1535 case UR_SET_FEATURE: 1536 switch (UGETW(req->wValue)) { 1537 case UF_ENDPOINT_HALT: 1538 goto tr_handle_set_halt; 1539 case UF_DEVICE_REMOTE_WAKEUP: 1540 goto tr_handle_set_wakeup; 1541 default: 1542 goto tr_stalled; 1543 } 1544 break; 1545 case UR_SYNCH_FRAME: 1546 goto tr_valid; /* nop */ 1547 default: 1548 goto tr_stalled; 1549 } 1550 break; 1551 1552 case UT_READ_ENDPOINT: 1553 switch (req->bRequest) { 1554 case UR_GET_STATUS: 1555 goto tr_handle_get_ep_status; 1556 default: 1557 goto tr_stalled; 1558 } 1559 break; 1560 1561 case UT_WRITE_INTERFACE: 1562 switch (req->bRequest) { 1563 case UR_SET_INTERFACE: 1564 goto tr_handle_set_interface; 1565 case UR_CLEAR_FEATURE: 1566 goto tr_valid; /* nop */ 1567 case UR_SET_FEATURE: 1568 default: 1569 goto tr_stalled; 1570 } 1571 break; 1572 1573 case UT_READ_INTERFACE: 1574 switch (req->bRequest) { 1575 case UR_GET_INTERFACE: 1576 goto tr_handle_get_interface; 1577 case UR_GET_STATUS: 1578 goto tr_handle_get_iface_status; 1579 default: 1580 goto tr_stalled; 1581 } 1582 break; 1583 1584 case UT_WRITE_CLASS_INTERFACE: 1585 case UT_WRITE_VENDOR_INTERFACE: 1586 /* XXX forward */ 1587 break; 1588 1589 case UT_READ_CLASS_INTERFACE: 1590 case UT_READ_VENDOR_INTERFACE: 1591 /* XXX forward */ 1592 break; 1593 1594 case UT_WRITE_CLASS_DEVICE: 1595 switch (req->bRequest) { 1596 case UR_CLEAR_FEATURE: 1597 goto tr_valid; 1598 case UR_SET_DESCRIPTOR: 1599 case UR_SET_FEATURE: 1600 break; 1601 default: 1602 goto tr_stalled; 1603 } 1604 break; 1605 1606 case UT_WRITE_CLASS_OTHER: 1607 switch (req->bRequest) { 1608 case UR_CLEAR_FEATURE: 1609 goto tr_handle_clear_port_feature; 1610 case UR_SET_FEATURE: 1611 goto tr_handle_set_port_feature; 1612 case UR_CLEAR_TT_BUFFER: 1613 case UR_RESET_TT: 1614 case UR_STOP_TT: 1615 goto tr_valid; 1616 1617 default: 1618 goto tr_stalled; 1619 } 1620 break; 1621 1622 case UT_READ_CLASS_OTHER: 1623 switch (req->bRequest) { 1624 case UR_GET_TT_STATE: 1625 goto tr_handle_get_tt_state; 1626 case UR_GET_STATUS: 1627 goto tr_handle_get_port_status; 1628 default: 1629 goto tr_stalled; 1630 } 1631 break; 1632 1633 case UT_READ_CLASS_DEVICE: 1634 switch (req->bRequest) { 1635 case UR_GET_DESCRIPTOR: 1636 goto tr_handle_get_class_descriptor; 1637 case UR_GET_STATUS: 1638 goto tr_handle_get_class_status; 1639 1640 default: 1641 goto tr_stalled; 1642 } 1643 break; 1644 default: 1645 goto tr_stalled; 1646 } 1647 goto tr_valid; 1648 1649tr_handle_get_descriptor: 1650 switch (value >> 8) { 1651 case UDESC_DEVICE: 1652 if (value & 0xff) { 1653 goto tr_stalled; 1654 } 1655 len = sizeof(avr32dci_devd); 1656 ptr = (const void *)&avr32dci_devd; 1657 goto tr_valid; 1658 case UDESC_DEVICE_QUALIFIER: 1659 if (value & 0xff) 1660 goto tr_stalled; 1661 len = sizeof(avr32dci_odevd); 1662 ptr = (const void *)&avr32dci_odevd; 1663 goto tr_valid; 1664 case UDESC_CONFIG: 1665 if (value & 0xff) { 1666 goto tr_stalled; 1667 } 1668 len = sizeof(avr32dci_confd); 1669 ptr = (const void *)&avr32dci_confd; 1670 goto tr_valid; 1671 case UDESC_STRING: 1672 switch (value & 0xff) { 1673 case 0: /* Language table */ 1674 len = sizeof(usb_string_lang_en); 1675 ptr = (const void *)&usb_string_lang_en; 1676 goto tr_valid; 1677 1678 case 1: /* Vendor */ 1679 len = sizeof(avr32dci_vendor); 1680 ptr = (const void *)&avr32dci_vendor; 1681 goto tr_valid; 1682 1683 case 2: /* Product */ 1684 len = sizeof(avr32dci_product); 1685 ptr = (const void *)&avr32dci_product; 1686 goto tr_valid; 1687 default: 1688 break; 1689 } 1690 break; 1691 default: 1692 goto tr_stalled; 1693 } 1694 goto tr_stalled; 1695 1696tr_handle_get_config: 1697 len = 1; 1698 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1699 goto tr_valid; 1700 1701tr_handle_get_status: 1702 len = 2; 1703 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1704 goto tr_valid; 1705 1706tr_handle_set_address: 1707 if (value & 0xFF00) { 1708 goto tr_stalled; 1709 } 1710 sc->sc_rt_addr = value; 1711 goto tr_valid; 1712 1713tr_handle_set_config: 1714 if (value >= 2) { 1715 goto tr_stalled; 1716 } 1717 sc->sc_conf = value; 1718 goto tr_valid; 1719 1720tr_handle_get_interface: 1721 len = 1; 1722 sc->sc_hub_temp.wValue[0] = 0; 1723 goto tr_valid; 1724 1725tr_handle_get_tt_state: 1726tr_handle_get_class_status: 1727tr_handle_get_iface_status: 1728tr_handle_get_ep_status: 1729 len = 2; 1730 USETW(sc->sc_hub_temp.wValue, 0); 1731 goto tr_valid; 1732 1733tr_handle_set_halt: 1734tr_handle_set_interface: 1735tr_handle_set_wakeup: 1736tr_handle_clear_wakeup: 1737tr_handle_clear_halt: 1738 goto tr_valid; 1739 1740tr_handle_clear_port_feature: 1741 if (index != 1) { 1742 goto tr_stalled; 1743 } 1744 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1745 1746 switch (value) { 1747 case UHF_PORT_SUSPEND: 1748 avr32dci_wakeup_peer(sc); 1749 break; 1750 1751 case UHF_PORT_ENABLE: 1752 sc->sc_flags.port_enabled = 0; 1753 break; 1754 1755 case UHF_PORT_TEST: 1756 case UHF_PORT_INDICATOR: 1757 case UHF_C_PORT_ENABLE: 1758 case UHF_C_PORT_OVER_CURRENT: 1759 case UHF_C_PORT_RESET: 1760 /* nops */ 1761 break; 1762 case UHF_PORT_POWER: 1763 sc->sc_flags.port_powered = 0; 1764 avr32dci_pull_down(sc); 1765 avr32dci_clocks_off(sc); 1766 break; 1767 case UHF_C_PORT_CONNECTION: 1768 /* clear connect change flag */ 1769 sc->sc_flags.change_connect = 0; 1770 1771 if (!sc->sc_flags.status_bus_reset) { 1772 /* we are not connected */ 1773 break; 1774 } 1775 /* configure the control endpoint */ 1776 /* set endpoint reset */ 1777 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(0)); 1778 1779 /* set stall */ 1780 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(0), AVR32_EPTSTA_FRCESTALL); 1781 1782 /* reset data toggle */ 1783 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_TOGGLESQ); 1784 1785 /* clear stall */ 1786 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_FRCESTALL); 1787 1788 /* configure */ 1789 AVR32_WRITE_4(sc, AVR32_EPTCFG(0), AVR32_EPTCFG_TYPE_CTRL | 1790 AVR32_EPTCFG_NBANK(1) | AVR32_EPTCFG_EPSIZE(6)); 1791 1792 temp = AVR32_READ_4(sc, AVR32_EPTCFG(0)); 1793 1794 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { 1795 device_printf(sc->sc_bus.bdev, 1796 "Chip rejected configuration\n"); 1797 } else { 1798 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(0), 1799 AVR32_EPTCTL_EPT_ENABL); 1800 } 1801 break; 1802 case UHF_C_PORT_SUSPEND: 1803 sc->sc_flags.change_suspend = 0; 1804 break; 1805 default: 1806 err = USB_ERR_IOERROR; 1807 goto done; 1808 } 1809 goto tr_valid; 1810 1811tr_handle_set_port_feature: 1812 if (index != 1) { 1813 goto tr_stalled; 1814 } 1815 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1816 1817 switch (value) { 1818 case UHF_PORT_ENABLE: 1819 sc->sc_flags.port_enabled = 1; 1820 break; 1821 case UHF_PORT_SUSPEND: 1822 case UHF_PORT_RESET: 1823 case UHF_PORT_TEST: 1824 case UHF_PORT_INDICATOR: 1825 /* nops */ 1826 break; 1827 case UHF_PORT_POWER: 1828 sc->sc_flags.port_powered = 1; 1829 break; 1830 default: 1831 err = USB_ERR_IOERROR; 1832 goto done; 1833 } 1834 goto tr_valid; 1835 1836tr_handle_get_port_status: 1837 1838 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1839 1840 if (index != 1) { 1841 goto tr_stalled; 1842 } 1843 if (sc->sc_flags.status_vbus) { 1844 avr32dci_clocks_on(sc); 1845 avr32dci_pull_up(sc); 1846 } else { 1847 avr32dci_pull_down(sc); 1848 avr32dci_clocks_off(sc); 1849 } 1850 1851 /* Select Device Side Mode */ 1852 1853 value = UPS_PORT_MODE_DEVICE; 1854 1855 /* Check for High Speed */ 1856 if (AVR32_READ_4(sc, AVR32_INTSTA) & AVR32_INT_SPEED) 1857 value |= UPS_HIGH_SPEED; 1858 1859 if (sc->sc_flags.port_powered) { 1860 value |= UPS_PORT_POWER; 1861 } 1862 if (sc->sc_flags.port_enabled) { 1863 value |= UPS_PORT_ENABLED; 1864 } 1865 if (sc->sc_flags.status_vbus && 1866 sc->sc_flags.status_bus_reset) { 1867 value |= UPS_CURRENT_CONNECT_STATUS; 1868 } 1869 if (sc->sc_flags.status_suspend) { 1870 value |= UPS_SUSPEND; 1871 } 1872 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1873 1874 value = 0; 1875 1876 if (sc->sc_flags.change_connect) { 1877 value |= UPS_C_CONNECT_STATUS; 1878 } 1879 if (sc->sc_flags.change_suspend) { 1880 value |= UPS_C_SUSPEND; 1881 } 1882 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1883 len = sizeof(sc->sc_hub_temp.ps); 1884 goto tr_valid; 1885 1886tr_handle_get_class_descriptor: 1887 if (value & 0xFF) { 1888 goto tr_stalled; 1889 } 1890 ptr = (const void *)&avr32dci_hubd; 1891 len = sizeof(avr32dci_hubd); 1892 goto tr_valid; 1893 1894tr_stalled: 1895 err = USB_ERR_STALLED; 1896tr_valid: 1897done: 1898 *plength = len; 1899 *pptr = ptr; 1900 return (err); 1901} 1902 1903static void 1904avr32dci_xfer_setup(struct usb_setup_params *parm) 1905{ 1906 const struct usb_hw_ep_profile *pf; 1907 struct avr32dci_softc *sc; 1908 struct usb_xfer *xfer; 1909 void *last_obj; 1910 uint32_t ntd; 1911 uint32_t n; 1912 uint8_t ep_no; 1913 1914 sc = AVR32_BUS2SC(parm->udev->bus); 1915 xfer = parm->curr_xfer; 1916 1917 /* 1918 * NOTE: This driver does not use any of the parameters that 1919 * are computed from the following values. Just set some 1920 * reasonable dummies: 1921 */ 1922 parm->hc_max_packet_size = 0x400; 1923 parm->hc_max_packet_count = 1; 1924 parm->hc_max_frame_size = 0x400; 1925 1926 usbd_transfer_setup_sub(parm); 1927 1928 /* 1929 * compute maximum number of TDs 1930 */ 1931 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 1932 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 1933 + 1 /* SYNC 2 */ ; 1934 } else { 1935 ntd = xfer->nframes + 1 /* SYNC */ ; 1936 } 1937 1938 /* 1939 * check if "usbd_transfer_setup_sub" set an error 1940 */ 1941 if (parm->err) 1942 return; 1943 1944 /* 1945 * allocate transfer descriptors 1946 */ 1947 last_obj = NULL; 1948 1949 /* 1950 * get profile stuff 1951 */ 1952 ep_no = xfer->endpointno & UE_ADDR; 1953 avr32dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 1954 1955 if (pf == NULL) { 1956 /* should not happen */ 1957 parm->err = USB_ERR_INVAL; 1958 return; 1959 } 1960 /* align data */ 1961 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 1962 1963 for (n = 0; n != ntd; n++) { 1964 struct avr32dci_td *td; 1965 1966 if (parm->buf) { 1967 uint32_t temp; 1968 1969 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 1970 1971 /* init TD */ 1972 td->max_packet_size = xfer->max_packet_size; 1973 td->ep_no = ep_no; 1974 temp = pf->max_in_frame_size | pf->max_out_frame_size; 1975 td->bank_shift = 0; 1976 while ((temp /= 2)) 1977 td->bank_shift++; 1978 if (pf->support_multi_buffer) { 1979 td->support_multi_buffer = 1; 1980 } 1981 td->obj_next = last_obj; 1982 1983 last_obj = td; 1984 } 1985 parm->size[0] += sizeof(*td); 1986 } 1987 1988 xfer->td_start[0] = last_obj; 1989} 1990 1991static void 1992avr32dci_xfer_unsetup(struct usb_xfer *xfer) 1993{ 1994 return; 1995} 1996 1997static void 1998avr32dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 1999 struct usb_endpoint *pipe) 2000{ 2001 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); 2002 2003 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2004 pipe, udev->address, 2005 edesc->bEndpointAddress, udev->flags.usb_mode, 2006 sc->sc_rt_addr, udev->device_index); 2007 2008 if (udev->device_index != sc->sc_rt_addr) { 2009 if ((udev->speed != USB_SPEED_FULL) && 2010 (udev->speed != USB_SPEED_HIGH)) { 2011 /* not supported */ 2012 return; 2013 } 2014 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2015 pipe->methods = &avr32dci_device_isoc_fs_methods; 2016 else 2017 pipe->methods = &avr32dci_device_non_isoc_methods; 2018 } 2019} 2020 2021static void 2022avr32dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2023{ 2024 struct avr32dci_softc *sc = AVR32_BUS2SC(bus); 2025 2026 switch (state) { 2027 case USB_HW_POWER_SUSPEND: 2028 avr32dci_suspend(sc); 2029 break; 2030 case USB_HW_POWER_SHUTDOWN: 2031 avr32dci_uninit(sc); 2032 break; 2033 case USB_HW_POWER_RESUME: 2034 avr32dci_resume(sc); 2035 break; 2036 default: 2037 break; 2038 } 2039} 2040 2041static const struct usb_bus_methods avr32dci_bus_methods = 2042{ 2043 .endpoint_init = &avr32dci_ep_init, 2044 .xfer_setup = &avr32dci_xfer_setup, 2045 .xfer_unsetup = &avr32dci_xfer_unsetup, 2046 .get_hw_ep_profile = &avr32dci_get_hw_ep_profile, 2047 .xfer_stall = &avr32dci_xfer_stall, 2048 .set_stall = &avr32dci_set_stall, 2049 .clear_stall = &avr32dci_clear_stall, 2050 .roothub_exec = &avr32dci_roothub_exec, 2051 .xfer_poll = &avr32dci_do_poll, 2052 .set_hw_power_sleep = &avr32dci_set_hw_power_sleep, 2053}; 2054