1/*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 37 * Manuals, sample driver and firmware source kits are available 38 * from http://www.alteon.com/support/openkits. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 50 * filtering and jumbo (9014 byte) frames. The hardware is largely 51 * controlled by firmware, which must be loaded into the NIC during 52 * initialization. 53 * 54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 55 * revision, which supports new features such as extended commands, 56 * extended jumbo receive ring descriptors and a mini receive ring. 57 * 58 * Alteon Networks is to be commended for releasing such a vast amount 59 * of development material for the Tigon NIC without requiring an NDA 60 * (although they really should have done it a long time ago). With 61 * any luck, the other vendors will finally wise up and follow Alteon's 62 * stellar example. 63 * 64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 65 * this driver by #including it as a C header file. This bloats the 66 * driver somewhat, but it's the easiest method considering that the 67 * driver code and firmware code need to be kept in sync. The source 68 * for the firmware is not provided with the FreeBSD distribution since 69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 70 * 71 * The following people deserve special thanks: 72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 73 * for testing 74 * - Raymond Lee of Netgear, for providing a pair of Netgear 75 * GA620 Tigon 2 boards for testing 76 * - Ulf Zimmermann, for bringing the GA260 to my attention and 77 * convincing me to write this driver. 78 * - Andrew Gallatin for providing FreeBSD/Alpha support. 79 */ 80 81#include <sys/cdefs.h> 82#include "opt_ti.h" 83 84#include <sys/param.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/kernel.h> 90#include <sys/module.h> 91#include <sys/socket.h> 92#include <sys/queue.h> 93#include <sys/conf.h> 94#include <sys/sf_buf.h> 95 96#include <net/if.h> 97#include <net/if_var.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102#include <net/if_types.h> 103#include <net/if_vlan_var.h> 104 105#include <net/bpf.h> 106 107#include <netinet/in_systm.h> 108#include <netinet/in.h> 109#include <netinet/ip.h> 110 111#include <machine/bus.h> 112#include <machine/resource.h> 113#include <sys/bus.h> 114#include <sys/rman.h> 115 116#ifdef TI_SF_BUF_JUMBO 117#include <vm/vm.h> 118#include <vm/vm_page.h> 119#endif 120 121#include <dev/pci/pcireg.h> 122#include <dev/pci/pcivar.h> 123 124#include <sys/tiio.h> 125#include <dev/ti/if_tireg.h> 126#include <dev/ti/ti_fw.h> 127#include <dev/ti/ti_fw2.h> 128 129#include <sys/sysctl.h> 130 131#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 132/* 133 * We can only turn on header splitting if we're using extended receive 134 * BDs. 135 */ 136#if defined(TI_JUMBO_HDRSPLIT) && !defined(TI_SF_BUF_JUMBO) 137#error "options TI_JUMBO_HDRSPLIT requires TI_SF_BUF_JUMBO" 138#endif /* TI_JUMBO_HDRSPLIT && !TI_SF_BUF_JUMBO */ 139 140typedef enum { 141 TI_SWAP_HTON, 142 TI_SWAP_NTOH 143} ti_swap_type; 144 145/* 146 * Various supported device vendors/types and their names. 147 */ 148 149static const struct ti_type ti_devs[] = { 150 { ALT_VENDORID, ALT_DEVICEID_ACENIC, 151 "Alteon AceNIC 1000baseSX Gigabit Ethernet" }, 152 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER, 153 "Alteon AceNIC 1000baseT Gigabit Ethernet" }, 154 { TC_VENDORID, TC_DEVICEID_3C985, 155 "3Com 3c985-SX Gigabit Ethernet" }, 156 { NG_VENDORID, NG_DEVICEID_GA620, 157 "Netgear GA620 1000baseSX Gigabit Ethernet" }, 158 { NG_VENDORID, NG_DEVICEID_GA620T, 159 "Netgear GA620 1000baseT Gigabit Ethernet" }, 160 { SGI_VENDORID, SGI_DEVICEID_TIGON, 161 "Silicon Graphics Gigabit Ethernet" }, 162 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX, 163 "Farallon PN9000SX Gigabit Ethernet" }, 164 { 0, 0, NULL } 165}; 166 167static d_open_t ti_open; 168static d_close_t ti_close; 169static d_ioctl_t ti_ioctl2; 170 171static struct cdevsw ti_cdevsw = { 172 .d_version = D_VERSION, 173 .d_flags = 0, 174 .d_open = ti_open, 175 .d_close = ti_close, 176 .d_ioctl = ti_ioctl2, 177 .d_name = "ti", 178}; 179 180static int ti_probe(device_t); 181static int ti_attach(device_t); 182static int ti_detach(device_t); 183static void ti_txeof(struct ti_softc *); 184static void ti_rxeof(struct ti_softc *); 185 186static int ti_encap(struct ti_softc *, struct mbuf **); 187 188static void ti_intr(void *); 189static void ti_start(if_t); 190static void ti_start_locked(if_t); 191static int ti_ioctl(if_t, u_long, caddr_t); 192static uint64_t ti_get_counter(if_t, ift_counter); 193static void ti_init(void *); 194static void ti_init_locked(void *); 195static void ti_init2(struct ti_softc *); 196static void ti_stop(struct ti_softc *); 197static void ti_watchdog(void *); 198static int ti_shutdown(device_t); 199static int ti_ifmedia_upd(if_t); 200static int ti_ifmedia_upd_locked(struct ti_softc *); 201static void ti_ifmedia_sts(if_t, struct ifmediareq *); 202 203static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 204static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 205static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 206 207static u_int ti_add_mcast(void *, struct sockaddr_dl *, u_int); 208static u_int ti_del_mcast(void *, struct sockaddr_dl *, u_int); 209static void ti_setmulti(struct ti_softc *); 210 211static void ti_mem_read(struct ti_softc *, uint32_t, uint32_t, void *); 212static void ti_mem_write(struct ti_softc *, uint32_t, uint32_t, void *); 213static void ti_mem_zero(struct ti_softc *, uint32_t, uint32_t); 214static int ti_copy_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t, int, 215 int); 216static int ti_copy_scratch(struct ti_softc *, uint32_t, uint32_t, caddr_t, 217 int, int, int); 218static int ti_bcopy_swap(const void *, void *, size_t, ti_swap_type); 219static void ti_loadfw(struct ti_softc *); 220static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 221static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 222static void ti_handle_events(struct ti_softc *); 223static void ti_dma_map_addr(void *, bus_dma_segment_t *, int, int); 224static int ti_dma_alloc(struct ti_softc *); 225static void ti_dma_free(struct ti_softc *); 226static int ti_dma_ring_alloc(struct ti_softc *, bus_size_t, bus_size_t, 227 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 228static void ti_dma_ring_free(struct ti_softc *, bus_dma_tag_t *, uint8_t **, 229 bus_dmamap_t, bus_addr_t *); 230static int ti_newbuf_std(struct ti_softc *, int); 231static int ti_newbuf_mini(struct ti_softc *, int); 232static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 233static int ti_init_rx_ring_std(struct ti_softc *); 234static void ti_free_rx_ring_std(struct ti_softc *); 235static int ti_init_rx_ring_jumbo(struct ti_softc *); 236static void ti_free_rx_ring_jumbo(struct ti_softc *); 237static int ti_init_rx_ring_mini(struct ti_softc *); 238static void ti_free_rx_ring_mini(struct ti_softc *); 239static void ti_free_tx_ring(struct ti_softc *); 240static int ti_init_tx_ring(struct ti_softc *); 241static void ti_discard_std(struct ti_softc *, int); 242#ifndef TI_SF_BUF_JUMBO 243static void ti_discard_jumbo(struct ti_softc *, int); 244#endif 245static void ti_discard_mini(struct ti_softc *, int); 246 247static int ti_64bitslot_war(struct ti_softc *); 248static int ti_chipinit(struct ti_softc *); 249static int ti_gibinit(struct ti_softc *); 250 251#ifdef TI_JUMBO_HDRSPLIT 252static __inline void ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, 253 int idx); 254#endif /* TI_JUMBO_HDRSPLIT */ 255 256static void ti_sysctl_node(struct ti_softc *); 257 258static device_method_t ti_methods[] = { 259 /* Device interface */ 260 DEVMETHOD(device_probe, ti_probe), 261 DEVMETHOD(device_attach, ti_attach), 262 DEVMETHOD(device_detach, ti_detach), 263 DEVMETHOD(device_shutdown, ti_shutdown), 264 { 0, 0 } 265}; 266 267static driver_t ti_driver = { 268 "ti", 269 ti_methods, 270 sizeof(struct ti_softc) 271}; 272 273DRIVER_MODULE(ti, pci, ti_driver, 0, 0); 274MODULE_DEPEND(ti, pci, 1, 1, 1); 275MODULE_DEPEND(ti, ether, 1, 1, 1); 276 277/* 278 * Send an instruction or address to the EEPROM, check for ACK. 279 */ 280static uint32_t 281ti_eeprom_putbyte(struct ti_softc *sc, int byte) 282{ 283 int i, ack = 0; 284 285 /* 286 * Make sure we're in TX mode. 287 */ 288 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 289 290 /* 291 * Feed in each bit and stobe the clock. 292 */ 293 for (i = 0x80; i; i >>= 1) { 294 if (byte & i) { 295 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 296 } else { 297 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 298 } 299 DELAY(1); 300 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 301 DELAY(1); 302 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 303 } 304 305 /* 306 * Turn off TX mode. 307 */ 308 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 309 310 /* 311 * Check for ack. 312 */ 313 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 314 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 315 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 316 317 return (ack); 318} 319 320/* 321 * Read a byte of data stored in the EEPROM at address 'addr.' 322 * We have to send two address bytes since the EEPROM can hold 323 * more than 256 bytes of data. 324 */ 325static uint8_t 326ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 327{ 328 int i; 329 uint8_t byte = 0; 330 331 EEPROM_START; 332 333 /* 334 * Send write control code to EEPROM. 335 */ 336 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 337 device_printf(sc->ti_dev, 338 "failed to send write command, status: %x\n", 339 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 340 return (1); 341 } 342 343 /* 344 * Send first byte of address of byte we want to read. 345 */ 346 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 347 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 348 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 349 return (1); 350 } 351 /* 352 * Send second byte address of byte we want to read. 353 */ 354 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 355 device_printf(sc->ti_dev, "failed to send address, status: %x\n", 356 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 357 return (1); 358 } 359 360 EEPROM_STOP; 361 EEPROM_START; 362 /* 363 * Send read control code to EEPROM. 364 */ 365 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 366 device_printf(sc->ti_dev, 367 "failed to send read command, status: %x\n", 368 CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 369 return (1); 370 } 371 372 /* 373 * Start reading bits from EEPROM. 374 */ 375 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 376 for (i = 0x80; i; i >>= 1) { 377 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 378 DELAY(1); 379 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 380 byte |= i; 381 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 382 DELAY(1); 383 } 384 385 EEPROM_STOP; 386 387 /* 388 * No ACK generated for read, so just return byte. 389 */ 390 391 *dest = byte; 392 393 return (0); 394} 395 396/* 397 * Read a sequence of bytes from the EEPROM. 398 */ 399static int 400ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt) 401{ 402 int err = 0, i; 403 uint8_t byte = 0; 404 405 for (i = 0; i < cnt; i++) { 406 err = ti_eeprom_getbyte(sc, off + i, &byte); 407 if (err) 408 break; 409 *(dest + i) = byte; 410 } 411 412 return (err ? 1 : 0); 413} 414 415/* 416 * NIC memory read function. 417 * Can be used to copy data from NIC local memory. 418 */ 419static void 420ti_mem_read(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 421{ 422 int segptr, segsize, cnt; 423 char *ptr; 424 425 segptr = addr; 426 cnt = len; 427 ptr = buf; 428 429 while (cnt) { 430 if (cnt < TI_WINLEN) 431 segsize = cnt; 432 else 433 segsize = TI_WINLEN - (segptr % TI_WINLEN); 434 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 435 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 436 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 437 segsize / 4); 438 ptr += segsize; 439 segptr += segsize; 440 cnt -= segsize; 441 } 442} 443 444/* 445 * NIC memory write function. 446 * Can be used to copy data into NIC local memory. 447 */ 448static void 449ti_mem_write(struct ti_softc *sc, uint32_t addr, uint32_t len, void *buf) 450{ 451 int segptr, segsize, cnt; 452 char *ptr; 453 454 segptr = addr; 455 cnt = len; 456 ptr = buf; 457 458 while (cnt) { 459 if (cnt < TI_WINLEN) 460 segsize = cnt; 461 else 462 segsize = TI_WINLEN - (segptr % TI_WINLEN); 463 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 464 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 465 TI_WINDOW + (segptr & (TI_WINLEN - 1)), (uint32_t *)ptr, 466 segsize / 4); 467 ptr += segsize; 468 segptr += segsize; 469 cnt -= segsize; 470 } 471} 472 473/* 474 * NIC memory read function. 475 * Can be used to clear a section of NIC local memory. 476 */ 477static void 478ti_mem_zero(struct ti_softc *sc, uint32_t addr, uint32_t len) 479{ 480 int segptr, segsize, cnt; 481 482 segptr = addr; 483 cnt = len; 484 485 while (cnt) { 486 if (cnt < TI_WINLEN) 487 segsize = cnt; 488 else 489 segsize = TI_WINLEN - (segptr % TI_WINLEN); 490 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 491 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 492 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, segsize / 4); 493 segptr += segsize; 494 cnt -= segsize; 495 } 496} 497 498static int 499ti_copy_mem(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 500 caddr_t buf, int useraddr, int readdata) 501{ 502 int segptr, segsize, cnt; 503 caddr_t ptr; 504 uint32_t origwin; 505 int error, resid, segresid; 506 int first_pass; 507 508 TI_LOCK_ASSERT(sc); 509 510 error = 0; 511 512 /* 513 * At the moment, we don't handle non-aligned cases, we just bail. 514 * If this proves to be a problem, it will be fixed. 515 */ 516 if (readdata == 0 && (tigon_addr & 0x3) != 0) { 517 device_printf(sc->ti_dev, "%s: tigon address %#x isn't " 518 "word-aligned\n", __func__, tigon_addr); 519 device_printf(sc->ti_dev, "%s: unaligned writes aren't " 520 "yet supported\n", __func__); 521 return (EINVAL); 522 } 523 524 segptr = tigon_addr & ~0x3; 525 segresid = tigon_addr - segptr; 526 527 /* 528 * This is the non-aligned amount left over that we'll need to 529 * copy. 530 */ 531 resid = len & 0x3; 532 533 /* Add in the left over amount at the front of the buffer */ 534 resid += segresid; 535 536 cnt = len & ~0x3; 537 /* 538 * If resid + segresid is >= 4, add multiples of 4 to the count and 539 * decrease the residual by that much. 540 */ 541 cnt += resid & ~0x3; 542 resid -= resid & ~0x3; 543 544 ptr = buf; 545 546 first_pass = 1; 547 548 /* 549 * Save the old window base value. 550 */ 551 origwin = CSR_READ_4(sc, TI_WINBASE); 552 553 while (cnt != 0 && error == 0) { 554 bus_size_t ti_offset; 555 556 if (cnt < TI_WINLEN) 557 segsize = cnt; 558 else 559 segsize = TI_WINLEN - (segptr % TI_WINLEN); 560 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 561 562 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN -1)); 563 564 if (readdata) { 565 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 566 ti_offset, (uint32_t *)sc->ti_membuf, segsize >> 2); 567 if (useraddr) { 568 /* 569 * Yeah, this is a little on the kludgy 570 * side, but at least this code is only 571 * used for debugging. 572 */ 573 ti_bcopy_swap(sc->ti_membuf, sc->ti_membuf2, 574 segsize, TI_SWAP_NTOH); 575 576 TI_UNLOCK(sc); 577 if (first_pass) { 578 error = copyout( 579 &sc->ti_membuf2[segresid], ptr, 580 segsize - segresid); 581 first_pass = 0; 582 } else 583 error = copyout(sc->ti_membuf2, ptr, 584 segsize); 585 TI_LOCK(sc); 586 } else { 587 if (first_pass) { 588 ti_bcopy_swap(sc->ti_membuf, 589 sc->ti_membuf2, segsize, 590 TI_SWAP_NTOH); 591 TI_UNLOCK(sc); 592 bcopy(&sc->ti_membuf2[segresid], ptr, 593 segsize - segresid); 594 TI_LOCK(sc); 595 first_pass = 0; 596 } else 597 ti_bcopy_swap(sc->ti_membuf, ptr, 598 segsize, TI_SWAP_NTOH); 599 } 600 601 } else { 602 if (useraddr) { 603 TI_UNLOCK(sc); 604 error = copyin(ptr, sc->ti_membuf2, segsize); 605 TI_LOCK(sc); 606 ti_bcopy_swap(sc->ti_membuf2, sc->ti_membuf, 607 segsize, TI_SWAP_HTON); 608 } else 609 ti_bcopy_swap(ptr, sc->ti_membuf, segsize, 610 TI_SWAP_HTON); 611 612 if (error == 0) { 613 bus_space_write_region_4(sc->ti_btag, 614 sc->ti_bhandle, ti_offset, 615 (uint32_t *)sc->ti_membuf, segsize >> 2); 616 } 617 } 618 segptr += segsize; 619 ptr += segsize; 620 cnt -= segsize; 621 } 622 623 /* 624 * Handle leftover, non-word-aligned bytes. 625 */ 626 if (resid != 0 && error == 0) { 627 uint32_t tmpval, tmpval2; 628 bus_size_t ti_offset; 629 630 /* 631 * Set the segment pointer. 632 */ 633 CSR_WRITE_4(sc, TI_WINBASE, rounddown2(segptr, TI_WINLEN)); 634 635 ti_offset = TI_WINDOW + (segptr & (TI_WINLEN - 1)); 636 637 /* 638 * First, grab whatever is in our source/destination. 639 * We'll obviously need this for reads, but also for 640 * writes, since we'll be doing read/modify/write. 641 */ 642 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 643 ti_offset, &tmpval, 1); 644 645 /* 646 * Next, translate this from little-endian to big-endian 647 * (at least on i386 boxes). 648 */ 649 tmpval2 = ntohl(tmpval); 650 651 if (readdata) { 652 /* 653 * If we're reading, just copy the leftover number 654 * of bytes from the host byte order buffer to 655 * the user's buffer. 656 */ 657 if (useraddr) { 658 TI_UNLOCK(sc); 659 error = copyout(&tmpval2, ptr, resid); 660 TI_LOCK(sc); 661 } else 662 bcopy(&tmpval2, ptr, resid); 663 } else { 664 /* 665 * If we're writing, first copy the bytes to be 666 * written into the network byte order buffer, 667 * leaving the rest of the buffer with whatever was 668 * originally in there. Then, swap the bytes 669 * around into host order and write them out. 670 * 671 * XXX KDM the read side of this has been verified 672 * to work, but the write side of it has not been 673 * verified. So user beware. 674 */ 675 if (useraddr) { 676 TI_UNLOCK(sc); 677 error = copyin(ptr, &tmpval2, resid); 678 TI_LOCK(sc); 679 } else 680 bcopy(ptr, &tmpval2, resid); 681 682 if (error == 0) { 683 tmpval = htonl(tmpval2); 684 bus_space_write_region_4(sc->ti_btag, 685 sc->ti_bhandle, ti_offset, &tmpval, 1); 686 } 687 } 688 } 689 690 CSR_WRITE_4(sc, TI_WINBASE, origwin); 691 692 return (error); 693} 694 695static int 696ti_copy_scratch(struct ti_softc *sc, uint32_t tigon_addr, uint32_t len, 697 caddr_t buf, int useraddr, int readdata, int cpu) 698{ 699 uint32_t segptr; 700 int cnt, error; 701 uint32_t tmpval, tmpval2; 702 caddr_t ptr; 703 704 TI_LOCK_ASSERT(sc); 705 706 /* 707 * At the moment, we don't handle non-aligned cases, we just bail. 708 * If this proves to be a problem, it will be fixed. 709 */ 710 if (tigon_addr & 0x3) { 711 device_printf(sc->ti_dev, "%s: tigon address %#x " 712 "isn't word-aligned\n", __func__, tigon_addr); 713 return (EINVAL); 714 } 715 716 if (len & 0x3) { 717 device_printf(sc->ti_dev, "%s: transfer length %d " 718 "isn't word-aligned\n", __func__, len); 719 return (EINVAL); 720 } 721 722 segptr = tigon_addr; 723 cnt = len; 724 ptr = buf; 725 726 while (cnt && error == 0) { 727 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_ADDR, cpu), segptr); 728 729 if (readdata) { 730 tmpval2 = CSR_READ_4(sc, CPU_REG(TI_SRAM_DATA, cpu)); 731 732 tmpval = ntohl(tmpval2); 733 734 /* 735 * Note: I've used this debugging interface 736 * extensively with Alteon's 12.3.15 firmware, 737 * compiled with GCC 2.7.2.1 and binutils 2.9.1. 738 * 739 * When you compile the firmware without 740 * optimization, which is necessary sometimes in 741 * order to properly step through it, you sometimes 742 * read out a bogus value of 0xc0017c instead of 743 * whatever was supposed to be in that scratchpad 744 * location. That value is on the stack somewhere, 745 * but I've never been able to figure out what was 746 * causing the problem. 747 * 748 * The address seems to pop up in random places, 749 * often not in the same place on two subsequent 750 * reads. 751 * 752 * In any case, the underlying data doesn't seem 753 * to be affected, just the value read out. 754 * 755 * KDM, 3/7/2000 756 */ 757 758 if (tmpval2 == 0xc0017c) 759 device_printf(sc->ti_dev, "found 0xc0017c at " 760 "%#x (tmpval2)\n", segptr); 761 762 if (tmpval == 0xc0017c) 763 device_printf(sc->ti_dev, "found 0xc0017c at " 764 "%#x (tmpval)\n", segptr); 765 766 if (useraddr) 767 error = copyout(&tmpval, ptr, 4); 768 else 769 bcopy(&tmpval, ptr, 4); 770 } else { 771 if (useraddr) 772 error = copyin(ptr, &tmpval2, 4); 773 else 774 bcopy(ptr, &tmpval2, 4); 775 776 if (error == 0) { 777 tmpval = htonl(tmpval2); 778 CSR_WRITE_4(sc, CPU_REG(TI_SRAM_DATA, cpu), 779 tmpval); 780 } 781 } 782 783 cnt -= 4; 784 segptr += 4; 785 ptr += 4; 786 } 787 788 return (error); 789} 790 791static int 792ti_bcopy_swap(const void *src, void *dst, size_t len, ti_swap_type swap_type) 793{ 794 const uint8_t *tmpsrc; 795 uint8_t *tmpdst; 796 size_t tmplen; 797 798 if (len & 0x3) { 799 printf("ti_bcopy_swap: length %zd isn't 32-bit aligned\n", len); 800 return (-1); 801 } 802 803 tmpsrc = src; 804 tmpdst = dst; 805 tmplen = len; 806 807 while (tmplen) { 808 if (swap_type == TI_SWAP_NTOH) 809 *(uint32_t *)tmpdst = ntohl(*(const uint32_t *)tmpsrc); 810 else 811 *(uint32_t *)tmpdst = htonl(*(const uint32_t *)tmpsrc); 812 tmpsrc += 4; 813 tmpdst += 4; 814 tmplen -= 4; 815 } 816 817 return (0); 818} 819 820/* 821 * Load firmware image into the NIC. Check that the firmware revision 822 * is acceptable and see if we want the firmware for the Tigon 1 or 823 * Tigon 2. 824 */ 825static void 826ti_loadfw(struct ti_softc *sc) 827{ 828 829 TI_LOCK_ASSERT(sc); 830 831 switch (sc->ti_hwrev) { 832 case TI_HWREV_TIGON: 833 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 834 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 835 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 836 device_printf(sc->ti_dev, "firmware revision mismatch; " 837 "want %d.%d.%d, got %d.%d.%d\n", 838 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 839 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 840 tigonFwReleaseMinor, tigonFwReleaseFix); 841 return; 842 } 843 ti_mem_write(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 844 ti_mem_write(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 845 ti_mem_write(sc, tigonFwRodataAddr, tigonFwRodataLen, 846 tigonFwRodata); 847 ti_mem_zero(sc, tigonFwBssAddr, tigonFwBssLen); 848 ti_mem_zero(sc, tigonFwSbssAddr, tigonFwSbssLen); 849 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 850 break; 851 case TI_HWREV_TIGON_II: 852 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 853 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 854 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 855 device_printf(sc->ti_dev, "firmware revision mismatch; " 856 "want %d.%d.%d, got %d.%d.%d\n", 857 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 858 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 859 tigon2FwReleaseMinor, tigon2FwReleaseFix); 860 return; 861 } 862 ti_mem_write(sc, tigon2FwTextAddr, tigon2FwTextLen, 863 tigon2FwText); 864 ti_mem_write(sc, tigon2FwDataAddr, tigon2FwDataLen, 865 tigon2FwData); 866 ti_mem_write(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 867 tigon2FwRodata); 868 ti_mem_zero(sc, tigon2FwBssAddr, tigon2FwBssLen); 869 ti_mem_zero(sc, tigon2FwSbssAddr, tigon2FwSbssLen); 870 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 871 break; 872 default: 873 device_printf(sc->ti_dev, 874 "can't load firmware: unknown hardware rev\n"); 875 break; 876 } 877} 878 879/* 880 * Send the NIC a command via the command ring. 881 */ 882static void 883ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 884{ 885 int index; 886 887 index = sc->ti_cmd_saved_prodidx; 888 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 889 TI_INC(index, TI_CMD_RING_CNT); 890 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 891 sc->ti_cmd_saved_prodidx = index; 892} 893 894/* 895 * Send the NIC an extended command. The 'len' parameter specifies the 896 * number of command slots to include after the initial command. 897 */ 898static void 899ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len) 900{ 901 int index; 902 int i; 903 904 index = sc->ti_cmd_saved_prodidx; 905 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 906 TI_INC(index, TI_CMD_RING_CNT); 907 for (i = 0; i < len; i++) { 908 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 909 *(uint32_t *)(&arg[i * 4])); 910 TI_INC(index, TI_CMD_RING_CNT); 911 } 912 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 913 sc->ti_cmd_saved_prodidx = index; 914} 915 916/* 917 * Handle events that have triggered interrupts. 918 */ 919static void 920ti_handle_events(struct ti_softc *sc) 921{ 922 struct ti_event_desc *e; 923 924 if (sc->ti_rdata.ti_event_ring == NULL) 925 return; 926 927 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 928 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_POSTREAD); 929 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 930 e = &sc->ti_rdata.ti_event_ring[sc->ti_ev_saved_considx]; 931 switch (TI_EVENT_EVENT(e)) { 932 case TI_EV_LINKSTAT_CHANGED: 933 sc->ti_linkstat = TI_EVENT_CODE(e); 934 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 935 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 936 if_setbaudrate(sc->ti_ifp, IF_Mbps(100)); 937 if (bootverbose) 938 device_printf(sc->ti_dev, 939 "10/100 link up\n"); 940 } else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 941 if_link_state_change(sc->ti_ifp, LINK_STATE_UP); 942 if_setbaudrate(sc->ti_ifp, IF_Gbps(1UL)); 943 if (bootverbose) 944 device_printf(sc->ti_dev, 945 "gigabit link up\n"); 946 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 947 if_link_state_change(sc->ti_ifp, 948 LINK_STATE_DOWN); 949 if_setbaudrate(sc->ti_ifp, 0); 950 if (bootverbose) 951 device_printf(sc->ti_dev, 952 "link down\n"); 953 } 954 break; 955 case TI_EV_ERROR: 956 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 957 device_printf(sc->ti_dev, "invalid command\n"); 958 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 959 device_printf(sc->ti_dev, "unknown command\n"); 960 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 961 device_printf(sc->ti_dev, "bad config data\n"); 962 break; 963 case TI_EV_FIRMWARE_UP: 964 ti_init2(sc); 965 break; 966 case TI_EV_STATS_UPDATED: 967 case TI_EV_RESET_JUMBO_RING: 968 case TI_EV_MCAST_UPDATED: 969 /* Who cares. */ 970 break; 971 default: 972 device_printf(sc->ti_dev, "unknown event: %d\n", 973 TI_EVENT_EVENT(e)); 974 break; 975 } 976 /* Advance the consumer index. */ 977 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 978 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 979 } 980 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 981 sc->ti_cdata.ti_event_ring_map, BUS_DMASYNC_PREREAD); 982} 983 984struct ti_dmamap_arg { 985 bus_addr_t ti_busaddr; 986}; 987 988static void 989ti_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 990{ 991 struct ti_dmamap_arg *ctx; 992 993 if (error) 994 return; 995 996 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 997 998 ctx = arg; 999 ctx->ti_busaddr = segs->ds_addr; 1000} 1001 1002static int 1003ti_dma_ring_alloc(struct ti_softc *sc, bus_size_t alignment, bus_size_t maxsize, 1004 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 1005 const char *msg) 1006{ 1007 struct ti_dmamap_arg ctx; 1008 int error; 1009 1010 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1011 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1012 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 1013 if (error != 0) { 1014 device_printf(sc->ti_dev, 1015 "could not create %s dma tag\n", msg); 1016 return (error); 1017 } 1018 /* Allocate DMA'able memory for ring. */ 1019 error = bus_dmamem_alloc(*tag, (void **)ring, 1020 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 1021 if (error != 0) { 1022 device_printf(sc->ti_dev, 1023 "could not allocate DMA'able memory for %s\n", msg); 1024 return (error); 1025 } 1026 /* Load the address of the ring. */ 1027 ctx.ti_busaddr = 0; 1028 error = bus_dmamap_load(*tag, *map, *ring, maxsize, ti_dma_map_addr, 1029 &ctx, BUS_DMA_NOWAIT); 1030 if (error != 0) { 1031 device_printf(sc->ti_dev, 1032 "could not load DMA'able memory for %s\n", msg); 1033 return (error); 1034 } 1035 *paddr = ctx.ti_busaddr; 1036 return (0); 1037} 1038 1039static void 1040ti_dma_ring_free(struct ti_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 1041 bus_dmamap_t map, bus_addr_t *paddr) 1042{ 1043 1044 if (*paddr != 0) { 1045 bus_dmamap_unload(*tag, map); 1046 *paddr = 0; 1047 } 1048 if (*ring != NULL) { 1049 bus_dmamem_free(*tag, *ring, map); 1050 *ring = NULL; 1051 } 1052 if (*tag) { 1053 bus_dma_tag_destroy(*tag); 1054 *tag = NULL; 1055 } 1056} 1057 1058static int 1059ti_dma_alloc(struct ti_softc *sc) 1060{ 1061 bus_addr_t lowaddr; 1062 int i, error; 1063 1064 lowaddr = BUS_SPACE_MAXADDR; 1065 if (sc->ti_dac == 0) 1066 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1067 1068 error = bus_dma_tag_create(bus_get_dma_tag(sc->ti_dev), 1, 0, lowaddr, 1069 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 1070 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 1071 &sc->ti_cdata.ti_parent_tag); 1072 if (error != 0) { 1073 device_printf(sc->ti_dev, 1074 "could not allocate parent dma tag\n"); 1075 return (ENOMEM); 1076 } 1077 1078 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_gib), 1079 &sc->ti_cdata.ti_gib_tag, (uint8_t **)&sc->ti_rdata.ti_info, 1080 &sc->ti_cdata.ti_gib_map, &sc->ti_rdata.ti_info_paddr, "GIB"); 1081 if (error) 1082 return (error); 1083 1084 /* Producer/consumer status */ 1085 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, sizeof(struct ti_status), 1086 &sc->ti_cdata.ti_status_tag, (uint8_t **)&sc->ti_rdata.ti_status, 1087 &sc->ti_cdata.ti_status_map, &sc->ti_rdata.ti_status_paddr, 1088 "event ring"); 1089 if (error) 1090 return (error); 1091 1092 /* Event ring */ 1093 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_EVENT_RING_SZ, 1094 &sc->ti_cdata.ti_event_ring_tag, 1095 (uint8_t **)&sc->ti_rdata.ti_event_ring, 1096 &sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr, 1097 "event ring"); 1098 if (error) 1099 return (error); 1100 1101 /* Command ring lives in shared memory so no need to create DMA area. */ 1102 1103 /* Standard RX ring */ 1104 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_STD_RX_RING_SZ, 1105 &sc->ti_cdata.ti_rx_std_ring_tag, 1106 (uint8_t **)&sc->ti_rdata.ti_rx_std_ring, 1107 &sc->ti_cdata.ti_rx_std_ring_map, 1108 &sc->ti_rdata.ti_rx_std_ring_paddr, "RX ring"); 1109 if (error) 1110 return (error); 1111 1112 /* Jumbo RX ring */ 1113 error = ti_dma_ring_alloc(sc, TI_JUMBO_RING_ALIGN, TI_JUMBO_RX_RING_SZ, 1114 &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1115 (uint8_t **)&sc->ti_rdata.ti_rx_jumbo_ring, 1116 &sc->ti_cdata.ti_rx_jumbo_ring_map, 1117 &sc->ti_rdata.ti_rx_jumbo_ring_paddr, "jumbo RX ring"); 1118 if (error) 1119 return (error); 1120 1121 /* RX return ring */ 1122 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_RX_RETURN_RING_SZ, 1123 &sc->ti_cdata.ti_rx_return_ring_tag, 1124 (uint8_t **)&sc->ti_rdata.ti_rx_return_ring, 1125 &sc->ti_cdata.ti_rx_return_ring_map, 1126 &sc->ti_rdata.ti_rx_return_ring_paddr, "RX return ring"); 1127 if (error) 1128 return (error); 1129 1130 /* Create DMA tag for standard RX mbufs. */ 1131 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1132 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 1133 MCLBYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_std_tag); 1134 if (error) { 1135 device_printf(sc->ti_dev, "could not allocate RX dma tag\n"); 1136 return (error); 1137 } 1138 1139 /* Create DMA tag for jumbo RX mbufs. */ 1140#ifdef TI_SF_BUF_JUMBO 1141 /* 1142 * The VM system will take care of providing aligned pages. Alignment 1143 * is set to 1 here so that busdma resources won't be wasted. 1144 */ 1145 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1146 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE * 4, 4, 1147 PAGE_SIZE, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1148#else 1149 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1150 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MJUM9BYTES, 1, 1151 MJUM9BYTES, 0, NULL, NULL, &sc->ti_cdata.ti_rx_jumbo_tag); 1152#endif 1153 if (error) { 1154 device_printf(sc->ti_dev, 1155 "could not allocate jumbo RX dma tag\n"); 1156 return (error); 1157 } 1158 1159 /* Create DMA tag for TX mbufs. */ 1160 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 1161 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1162 MCLBYTES * TI_MAXTXSEGS, TI_MAXTXSEGS, MCLBYTES, 0, NULL, NULL, 1163 &sc->ti_cdata.ti_tx_tag); 1164 if (error) { 1165 device_printf(sc->ti_dev, "could not allocate TX dma tag\n"); 1166 return (ENOMEM); 1167 } 1168 1169 /* Create DMA maps for RX buffers. */ 1170 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1171 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1172 &sc->ti_cdata.ti_rx_std_maps[i]); 1173 if (error) { 1174 device_printf(sc->ti_dev, 1175 "could not create DMA map for RX\n"); 1176 return (error); 1177 } 1178 } 1179 error = bus_dmamap_create(sc->ti_cdata.ti_rx_std_tag, 0, 1180 &sc->ti_cdata.ti_rx_std_sparemap); 1181 if (error) { 1182 device_printf(sc->ti_dev, 1183 "could not create spare DMA map for RX\n"); 1184 return (error); 1185 } 1186 1187 /* Create DMA maps for jumbo RX buffers. */ 1188 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1189 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1190 &sc->ti_cdata.ti_rx_jumbo_maps[i]); 1191 if (error) { 1192 device_printf(sc->ti_dev, 1193 "could not create DMA map for jumbo RX\n"); 1194 return (error); 1195 } 1196 } 1197 error = bus_dmamap_create(sc->ti_cdata.ti_rx_jumbo_tag, 0, 1198 &sc->ti_cdata.ti_rx_jumbo_sparemap); 1199 if (error) { 1200 device_printf(sc->ti_dev, 1201 "could not create spare DMA map for jumbo RX\n"); 1202 return (error); 1203 } 1204 1205 /* Create DMA maps for TX buffers. */ 1206 for (i = 0; i < TI_TX_RING_CNT; i++) { 1207 error = bus_dmamap_create(sc->ti_cdata.ti_tx_tag, 0, 1208 &sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1209 if (error) { 1210 device_printf(sc->ti_dev, 1211 "could not create DMA map for TX\n"); 1212 return (ENOMEM); 1213 } 1214 } 1215 1216 /* Mini ring and TX ring is not available on Tigon 1. */ 1217 if (sc->ti_hwrev == TI_HWREV_TIGON) 1218 return (0); 1219 1220 /* TX ring */ 1221 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_TX_RING_SZ, 1222 &sc->ti_cdata.ti_tx_ring_tag, (uint8_t **)&sc->ti_rdata.ti_tx_ring, 1223 &sc->ti_cdata.ti_tx_ring_map, &sc->ti_rdata.ti_tx_ring_paddr, 1224 "TX ring"); 1225 if (error) 1226 return (error); 1227 1228 /* Mini RX ring */ 1229 error = ti_dma_ring_alloc(sc, TI_RING_ALIGN, TI_MINI_RX_RING_SZ, 1230 &sc->ti_cdata.ti_rx_mini_ring_tag, 1231 (uint8_t **)&sc->ti_rdata.ti_rx_mini_ring, 1232 &sc->ti_cdata.ti_rx_mini_ring_map, 1233 &sc->ti_rdata.ti_rx_mini_ring_paddr, "mini RX ring"); 1234 if (error) 1235 return (error); 1236 1237 /* Create DMA tag for mini RX mbufs. */ 1238 error = bus_dma_tag_create(sc->ti_cdata.ti_parent_tag, 1, 0, 1239 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 1240 MHLEN, 0, NULL, NULL, &sc->ti_cdata.ti_rx_mini_tag); 1241 if (error) { 1242 device_printf(sc->ti_dev, 1243 "could not allocate mini RX dma tag\n"); 1244 return (error); 1245 } 1246 1247 /* Create DMA maps for mini RX buffers. */ 1248 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1249 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1250 &sc->ti_cdata.ti_rx_mini_maps[i]); 1251 if (error) { 1252 device_printf(sc->ti_dev, 1253 "could not create DMA map for mini RX\n"); 1254 return (error); 1255 } 1256 } 1257 error = bus_dmamap_create(sc->ti_cdata.ti_rx_mini_tag, 0, 1258 &sc->ti_cdata.ti_rx_mini_sparemap); 1259 if (error) { 1260 device_printf(sc->ti_dev, 1261 "could not create spare DMA map for mini RX\n"); 1262 return (error); 1263 } 1264 1265 return (0); 1266} 1267 1268static void 1269ti_dma_free(struct ti_softc *sc) 1270{ 1271 int i; 1272 1273 /* Destroy DMA maps for RX buffers. */ 1274 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1275 if (sc->ti_cdata.ti_rx_std_maps[i]) { 1276 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1277 sc->ti_cdata.ti_rx_std_maps[i]); 1278 sc->ti_cdata.ti_rx_std_maps[i] = NULL; 1279 } 1280 } 1281 if (sc->ti_cdata.ti_rx_std_sparemap) { 1282 bus_dmamap_destroy(sc->ti_cdata.ti_rx_std_tag, 1283 sc->ti_cdata.ti_rx_std_sparemap); 1284 sc->ti_cdata.ti_rx_std_sparemap = NULL; 1285 } 1286 if (sc->ti_cdata.ti_rx_std_tag) { 1287 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_std_tag); 1288 sc->ti_cdata.ti_rx_std_tag = NULL; 1289 } 1290 1291 /* Destroy DMA maps for jumbo RX buffers. */ 1292 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1293 if (sc->ti_cdata.ti_rx_jumbo_maps[i]) { 1294 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1295 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1296 sc->ti_cdata.ti_rx_jumbo_maps[i] = NULL; 1297 } 1298 } 1299 if (sc->ti_cdata.ti_rx_jumbo_sparemap) { 1300 bus_dmamap_destroy(sc->ti_cdata.ti_rx_jumbo_tag, 1301 sc->ti_cdata.ti_rx_jumbo_sparemap); 1302 sc->ti_cdata.ti_rx_jumbo_sparemap = NULL; 1303 } 1304 if (sc->ti_cdata.ti_rx_jumbo_tag) { 1305 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_jumbo_tag); 1306 sc->ti_cdata.ti_rx_jumbo_tag = NULL; 1307 } 1308 1309 /* Destroy DMA maps for mini RX buffers. */ 1310 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1311 if (sc->ti_cdata.ti_rx_mini_maps[i]) { 1312 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1313 sc->ti_cdata.ti_rx_mini_maps[i]); 1314 sc->ti_cdata.ti_rx_mini_maps[i] = NULL; 1315 } 1316 } 1317 if (sc->ti_cdata.ti_rx_mini_sparemap) { 1318 bus_dmamap_destroy(sc->ti_cdata.ti_rx_mini_tag, 1319 sc->ti_cdata.ti_rx_mini_sparemap); 1320 sc->ti_cdata.ti_rx_mini_sparemap = NULL; 1321 } 1322 if (sc->ti_cdata.ti_rx_mini_tag) { 1323 bus_dma_tag_destroy(sc->ti_cdata.ti_rx_mini_tag); 1324 sc->ti_cdata.ti_rx_mini_tag = NULL; 1325 } 1326 1327 /* Destroy DMA maps for TX buffers. */ 1328 for (i = 0; i < TI_TX_RING_CNT; i++) { 1329 if (sc->ti_cdata.ti_txdesc[i].tx_dmamap) { 1330 bus_dmamap_destroy(sc->ti_cdata.ti_tx_tag, 1331 sc->ti_cdata.ti_txdesc[i].tx_dmamap); 1332 sc->ti_cdata.ti_txdesc[i].tx_dmamap = NULL; 1333 } 1334 } 1335 if (sc->ti_cdata.ti_tx_tag) { 1336 bus_dma_tag_destroy(sc->ti_cdata.ti_tx_tag); 1337 sc->ti_cdata.ti_tx_tag = NULL; 1338 } 1339 1340 /* Destroy standard RX ring. */ 1341 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_std_ring_tag, 1342 (void *)&sc->ti_rdata.ti_rx_std_ring, 1343 sc->ti_cdata.ti_rx_std_ring_map, 1344 &sc->ti_rdata.ti_rx_std_ring_paddr); 1345 /* Destroy jumbo RX ring. */ 1346 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_jumbo_ring_tag, 1347 (void *)&sc->ti_rdata.ti_rx_jumbo_ring, 1348 sc->ti_cdata.ti_rx_jumbo_ring_map, 1349 &sc->ti_rdata.ti_rx_jumbo_ring_paddr); 1350 /* Destroy mini RX ring. */ 1351 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_mini_ring_tag, 1352 (void *)&sc->ti_rdata.ti_rx_mini_ring, 1353 sc->ti_cdata.ti_rx_mini_ring_map, 1354 &sc->ti_rdata.ti_rx_mini_ring_paddr); 1355 /* Destroy RX return ring. */ 1356 ti_dma_ring_free(sc, &sc->ti_cdata.ti_rx_return_ring_tag, 1357 (void *)&sc->ti_rdata.ti_rx_return_ring, 1358 sc->ti_cdata.ti_rx_return_ring_map, 1359 &sc->ti_rdata.ti_rx_return_ring_paddr); 1360 /* Destroy TX ring. */ 1361 ti_dma_ring_free(sc, &sc->ti_cdata.ti_tx_ring_tag, 1362 (void *)&sc->ti_rdata.ti_tx_ring, sc->ti_cdata.ti_tx_ring_map, 1363 &sc->ti_rdata.ti_tx_ring_paddr); 1364 /* Destroy status block. */ 1365 ti_dma_ring_free(sc, &sc->ti_cdata.ti_status_tag, 1366 (void *)&sc->ti_rdata.ti_status, sc->ti_cdata.ti_status_map, 1367 &sc->ti_rdata.ti_status_paddr); 1368 /* Destroy event ring. */ 1369 ti_dma_ring_free(sc, &sc->ti_cdata.ti_event_ring_tag, 1370 (void *)&sc->ti_rdata.ti_event_ring, 1371 sc->ti_cdata.ti_event_ring_map, &sc->ti_rdata.ti_event_ring_paddr); 1372 /* Destroy GIB */ 1373 ti_dma_ring_free(sc, &sc->ti_cdata.ti_gib_tag, 1374 (void *)&sc->ti_rdata.ti_info, sc->ti_cdata.ti_gib_map, 1375 &sc->ti_rdata.ti_info_paddr); 1376 1377 /* Destroy the parent tag. */ 1378 if (sc->ti_cdata.ti_parent_tag) { 1379 bus_dma_tag_destroy(sc->ti_cdata.ti_parent_tag); 1380 sc->ti_cdata.ti_parent_tag = NULL; 1381 } 1382} 1383 1384/* 1385 * Intialize a standard receive ring descriptor. 1386 */ 1387static int 1388ti_newbuf_std(struct ti_softc *sc, int i) 1389{ 1390 bus_dmamap_t map; 1391 bus_dma_segment_t segs[1]; 1392 struct mbuf *m; 1393 struct ti_rx_desc *r; 1394 int error, nsegs; 1395 1396 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1397 if (m == NULL) 1398 return (ENOBUFS); 1399 m->m_len = m->m_pkthdr.len = MCLBYTES; 1400 m_adj(m, ETHER_ALIGN); 1401 1402 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_std_tag, 1403 sc->ti_cdata.ti_rx_std_sparemap, m, segs, &nsegs, 0); 1404 if (error != 0) { 1405 m_freem(m); 1406 return (error); 1407 } 1408 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1409 1410 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1411 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1412 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_POSTREAD); 1413 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, 1414 sc->ti_cdata.ti_rx_std_maps[i]); 1415 } 1416 1417 map = sc->ti_cdata.ti_rx_std_maps[i]; 1418 sc->ti_cdata.ti_rx_std_maps[i] = sc->ti_cdata.ti_rx_std_sparemap; 1419 sc->ti_cdata.ti_rx_std_sparemap = map; 1420 sc->ti_cdata.ti_rx_std_chain[i] = m; 1421 1422 r = &sc->ti_rdata.ti_rx_std_ring[i]; 1423 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1424 r->ti_len = segs[0].ds_len; 1425 r->ti_type = TI_BDTYPE_RECV_BD; 1426 r->ti_flags = 0; 1427 r->ti_vlan_tag = 0; 1428 r->ti_tcp_udp_cksum = 0; 1429 if (if_getcapenable(sc->ti_ifp) & IFCAP_RXCSUM) 1430 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1431 r->ti_idx = i; 1432 1433 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, 1434 sc->ti_cdata.ti_rx_std_maps[i], BUS_DMASYNC_PREREAD); 1435 return (0); 1436} 1437 1438/* 1439 * Intialize a mini receive ring descriptor. This only applies to 1440 * the Tigon 2. 1441 */ 1442static int 1443ti_newbuf_mini(struct ti_softc *sc, int i) 1444{ 1445 bus_dmamap_t map; 1446 bus_dma_segment_t segs[1]; 1447 struct mbuf *m; 1448 struct ti_rx_desc *r; 1449 int error, nsegs; 1450 1451 MGETHDR(m, M_NOWAIT, MT_DATA); 1452 if (m == NULL) 1453 return (ENOBUFS); 1454 m->m_len = m->m_pkthdr.len = MHLEN; 1455 m_adj(m, ETHER_ALIGN); 1456 1457 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_mini_tag, 1458 sc->ti_cdata.ti_rx_mini_sparemap, m, segs, &nsegs, 0); 1459 if (error != 0) { 1460 m_freem(m); 1461 return (error); 1462 } 1463 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1464 1465 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1466 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1467 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_POSTREAD); 1468 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, 1469 sc->ti_cdata.ti_rx_mini_maps[i]); 1470 } 1471 1472 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1473 sc->ti_cdata.ti_rx_mini_maps[i] = sc->ti_cdata.ti_rx_mini_sparemap; 1474 sc->ti_cdata.ti_rx_mini_sparemap = map; 1475 sc->ti_cdata.ti_rx_mini_chain[i] = m; 1476 1477 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 1478 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1479 r->ti_len = segs[0].ds_len; 1480 r->ti_type = TI_BDTYPE_RECV_BD; 1481 r->ti_flags = TI_BDFLAG_MINI_RING; 1482 r->ti_vlan_tag = 0; 1483 r->ti_tcp_udp_cksum = 0; 1484 if (if_getcapenable(sc->ti_ifp) & IFCAP_RXCSUM) 1485 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1486 r->ti_idx = i; 1487 1488 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, 1489 sc->ti_cdata.ti_rx_mini_maps[i], BUS_DMASYNC_PREREAD); 1490 return (0); 1491} 1492 1493#ifndef TI_SF_BUF_JUMBO 1494 1495/* 1496 * Initialize a jumbo receive ring descriptor. This allocates 1497 * a jumbo buffer from the pool managed internally by the driver. 1498 */ 1499static int 1500ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *dummy) 1501{ 1502 bus_dmamap_t map; 1503 bus_dma_segment_t segs[1]; 1504 struct mbuf *m; 1505 struct ti_rx_desc *r; 1506 int error, nsegs; 1507 1508 (void)dummy; 1509 1510 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1511 if (m == NULL) 1512 return (ENOBUFS); 1513 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1514 m_adj(m, ETHER_ALIGN); 1515 1516 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, 1517 sc->ti_cdata.ti_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1518 if (error != 0) { 1519 m_freem(m); 1520 return (error); 1521 } 1522 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1523 1524 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1525 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1526 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_POSTREAD); 1527 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, 1528 sc->ti_cdata.ti_rx_jumbo_maps[i]); 1529 } 1530 1531 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1532 sc->ti_cdata.ti_rx_jumbo_maps[i] = sc->ti_cdata.ti_rx_jumbo_sparemap; 1533 sc->ti_cdata.ti_rx_jumbo_sparemap = map; 1534 sc->ti_cdata.ti_rx_jumbo_chain[i] = m; 1535 1536 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 1537 ti_hostaddr64(&r->ti_addr, segs[0].ds_addr); 1538 r->ti_len = segs[0].ds_len; 1539 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1540 r->ti_flags = TI_BDFLAG_JUMBO_RING; 1541 r->ti_vlan_tag = 0; 1542 r->ti_tcp_udp_cksum = 0; 1543 if (if_getcapenable(sc->ti_ifp) & IFCAP_RXCSUM) 1544 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 1545 r->ti_idx = i; 1546 1547 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, 1548 sc->ti_cdata.ti_rx_jumbo_maps[i], BUS_DMASYNC_PREREAD); 1549 return (0); 1550} 1551 1552#else 1553 1554#if (PAGE_SIZE == 4096) 1555#define NPAYLOAD 2 1556#else 1557#define NPAYLOAD 1 1558#endif 1559 1560#define TCP_HDR_LEN (52 + sizeof(struct ether_header)) 1561#define UDP_HDR_LEN (28 + sizeof(struct ether_header)) 1562#define NFS_HDR_LEN (UDP_HDR_LEN) 1563static int HDR_LEN = TCP_HDR_LEN; 1564 1565/* 1566 * Initialize a jumbo receive ring descriptor. This allocates 1567 * a jumbo buffer from the pool managed internally by the driver. 1568 */ 1569static int 1570ti_newbuf_jumbo(struct ti_softc *sc, int idx, struct mbuf *m_old) 1571{ 1572 bus_dmamap_t map; 1573 struct mbuf *cur, *m_new = NULL; 1574 struct mbuf *m[3] = {NULL, NULL, NULL}; 1575 struct ti_rx_desc_ext *r; 1576 vm_page_t frame; 1577 /* 1 extra buf to make nobufs easy*/ 1578 struct sf_buf *sf[3] = {NULL, NULL, NULL}; 1579 int i; 1580 bus_dma_segment_t segs[4]; 1581 int nsegs; 1582 1583 if (m_old != NULL) { 1584 m_new = m_old; 1585 cur = m_old->m_next; 1586 for (i = 0; i <= NPAYLOAD; i++){ 1587 m[i] = cur; 1588 cur = cur->m_next; 1589 } 1590 } else { 1591 /* Allocate the mbufs. */ 1592 MGETHDR(m_new, M_NOWAIT, MT_DATA); 1593 if (m_new == NULL) { 1594 device_printf(sc->ti_dev, "mbuf allocation failed " 1595 "-- packet dropped!\n"); 1596 goto nobufs; 1597 } 1598 MGET(m[NPAYLOAD], M_NOWAIT, MT_DATA); 1599 if (m[NPAYLOAD] == NULL) { 1600 device_printf(sc->ti_dev, "cluster mbuf allocation " 1601 "failed -- packet dropped!\n"); 1602 goto nobufs; 1603 } 1604 if (!(MCLGET(m[NPAYLOAD], M_NOWAIT))) { 1605 device_printf(sc->ti_dev, "mbuf allocation failed " 1606 "-- packet dropped!\n"); 1607 goto nobufs; 1608 } 1609 m[NPAYLOAD]->m_len = MCLBYTES; 1610 1611 for (i = 0; i < NPAYLOAD; i++){ 1612 MGET(m[i], M_NOWAIT, MT_DATA); 1613 if (m[i] == NULL) { 1614 device_printf(sc->ti_dev, "mbuf allocation " 1615 "failed -- packet dropped!\n"); 1616 goto nobufs; 1617 } 1618 frame = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT | 1619 VM_ALLOC_WIRED); 1620 if (frame == NULL) { 1621 device_printf(sc->ti_dev, "buffer allocation " 1622 "failed -- packet dropped!\n"); 1623 printf(" index %d page %d\n", idx, i); 1624 goto nobufs; 1625 } 1626 sf[i] = sf_buf_alloc(frame, SFB_NOWAIT); 1627 if (sf[i] == NULL) { 1628 vm_page_unwire_noq(frame); 1629 vm_page_free(frame); 1630 device_printf(sc->ti_dev, "buffer allocation " 1631 "failed -- packet dropped!\n"); 1632 printf(" index %d page %d\n", idx, i); 1633 goto nobufs; 1634 } 1635 } 1636 for (i = 0; i < NPAYLOAD; i++){ 1637 /* Attach the buffer to the mbuf. */ 1638 m[i]->m_data = (void *)sf_buf_kva(sf[i]); 1639 m[i]->m_len = PAGE_SIZE; 1640 MEXTADD(m[i], sf_buf_kva(sf[i]), PAGE_SIZE, 1641 sf_mext_free, (void*)sf_buf_kva(sf[i]), sf[i], 1642 0, EXT_DISPOSABLE); 1643 m[i]->m_next = m[i+1]; 1644 } 1645 /* link the buffers to the header */ 1646 m_new->m_next = m[0]; 1647 m_new->m_data += ETHER_ALIGN; 1648 if (sc->ti_hdrsplit) 1649 m_new->m_len = MHLEN - ETHER_ALIGN; 1650 else 1651 m_new->m_len = HDR_LEN; 1652 m_new->m_pkthdr.len = NPAYLOAD * PAGE_SIZE + m_new->m_len; 1653 } 1654 1655 /* Set up the descriptor. */ 1656 r = &sc->ti_rdata.ti_rx_jumbo_ring[idx]; 1657 sc->ti_cdata.ti_rx_jumbo_chain[idx] = m_new; 1658 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1659 if (bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_rx_jumbo_tag, map, m_new, 1660 segs, &nsegs, 0)) 1661 return (ENOBUFS); 1662 if ((nsegs < 1) || (nsegs > 4)) 1663 return (ENOBUFS); 1664 ti_hostaddr64(&r->ti_addr0, segs[0].ds_addr); 1665 r->ti_len0 = m_new->m_len; 1666 1667 ti_hostaddr64(&r->ti_addr1, segs[1].ds_addr); 1668 r->ti_len1 = PAGE_SIZE; 1669 1670 ti_hostaddr64(&r->ti_addr2, segs[2].ds_addr); 1671 r->ti_len2 = m[1]->m_ext.ext_size; /* could be PAGE_SIZE or MCLBYTES */ 1672 1673 if (PAGE_SIZE == 4096) { 1674 ti_hostaddr64(&r->ti_addr3, segs[3].ds_addr); 1675 r->ti_len3 = MCLBYTES; 1676 } else { 1677 r->ti_len3 = 0; 1678 } 1679 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 1680 1681 r->ti_flags = TI_BDFLAG_JUMBO_RING|TI_RCB_FLAG_USE_EXT_RX_BD; 1682 1683 if (if_getcapenable(sc->ti_ifp) & IFCAP_RXCSUM) 1684 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 1685 1686 r->ti_idx = idx; 1687 1688 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, BUS_DMASYNC_PREREAD); 1689 return (0); 1690 1691nobufs: 1692 1693 /* 1694 * Warning! : 1695 * This can only be called before the mbufs are strung together. 1696 * If the mbufs are strung together, m_freem() will free the chain, 1697 * so that the later mbufs will be freed multiple times. 1698 */ 1699 if (m_new) 1700 m_freem(m_new); 1701 1702 for (i = 0; i < 3; i++) { 1703 if (m[i]) 1704 m_freem(m[i]); 1705 if (sf[i]) 1706 sf_mext_free((void *)sf_buf_kva(sf[i]), sf[i]); 1707 } 1708 return (ENOBUFS); 1709} 1710#endif 1711 1712/* 1713 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1714 * that's 1MB or memory, which is a lot. For now, we fill only the first 1715 * 256 ring entries and hope that our CPU is fast enough to keep up with 1716 * the NIC. 1717 */ 1718static int 1719ti_init_rx_ring_std(struct ti_softc *sc) 1720{ 1721 int i; 1722 struct ti_cmd_desc cmd; 1723 1724 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1725 if (ti_newbuf_std(sc, i) != 0) 1726 return (ENOBUFS); 1727 } 1728 1729 sc->ti_std = TI_STD_RX_RING_CNT - 1; 1730 TI_UPDATE_STDPROD(sc, TI_STD_RX_RING_CNT - 1); 1731 1732 return (0); 1733} 1734 1735static void 1736ti_free_rx_ring_std(struct ti_softc *sc) 1737{ 1738 bus_dmamap_t map; 1739 int i; 1740 1741 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 1742 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 1743 map = sc->ti_cdata.ti_rx_std_maps[i]; 1744 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_tag, map, 1745 BUS_DMASYNC_POSTREAD); 1746 bus_dmamap_unload(sc->ti_cdata.ti_rx_std_tag, map); 1747 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 1748 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 1749 } 1750 } 1751 bzero(sc->ti_rdata.ti_rx_std_ring, TI_STD_RX_RING_SZ); 1752 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 1753 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1754} 1755 1756static int 1757ti_init_rx_ring_jumbo(struct ti_softc *sc) 1758{ 1759 struct ti_cmd_desc cmd; 1760 int i; 1761 1762 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1763 if (ti_newbuf_jumbo(sc, i, NULL) != 0) 1764 return (ENOBUFS); 1765 } 1766 1767 sc->ti_jumbo = TI_JUMBO_RX_RING_CNT - 1; 1768 TI_UPDATE_JUMBOPROD(sc, TI_JUMBO_RX_RING_CNT - 1); 1769 1770 return (0); 1771} 1772 1773static void 1774ti_free_rx_ring_jumbo(struct ti_softc *sc) 1775{ 1776 bus_dmamap_t map; 1777 int i; 1778 1779 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1780 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1781 map = sc->ti_cdata.ti_rx_jumbo_maps[i]; 1782 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 1783 BUS_DMASYNC_POSTREAD); 1784 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 1785 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1786 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1787 } 1788 } 1789 bzero(sc->ti_rdata.ti_rx_jumbo_ring, TI_JUMBO_RX_RING_SZ); 1790 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 1791 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1792} 1793 1794static int 1795ti_init_rx_ring_mini(struct ti_softc *sc) 1796{ 1797 int i; 1798 1799 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1800 if (ti_newbuf_mini(sc, i) != 0) 1801 return (ENOBUFS); 1802 } 1803 1804 sc->ti_mini = TI_MINI_RX_RING_CNT - 1; 1805 TI_UPDATE_MINIPROD(sc, TI_MINI_RX_RING_CNT - 1); 1806 1807 return (0); 1808} 1809 1810static void 1811ti_free_rx_ring_mini(struct ti_softc *sc) 1812{ 1813 bus_dmamap_t map; 1814 int i; 1815 1816 if (sc->ti_rdata.ti_rx_mini_ring == NULL) 1817 return; 1818 1819 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1820 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1821 map = sc->ti_cdata.ti_rx_mini_maps[i]; 1822 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_tag, map, 1823 BUS_DMASYNC_POSTREAD); 1824 bus_dmamap_unload(sc->ti_cdata.ti_rx_mini_tag, map); 1825 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1826 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1827 } 1828 } 1829 bzero(sc->ti_rdata.ti_rx_mini_ring, TI_MINI_RX_RING_SZ); 1830 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 1831 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 1832} 1833 1834static void 1835ti_free_tx_ring(struct ti_softc *sc) 1836{ 1837 struct ti_txdesc *txd; 1838 int i; 1839 1840 if (sc->ti_rdata.ti_tx_ring == NULL) 1841 return; 1842 1843 for (i = 0; i < TI_TX_RING_CNT; i++) { 1844 txd = &sc->ti_cdata.ti_txdesc[i]; 1845 if (txd->tx_m != NULL) { 1846 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 1847 BUS_DMASYNC_POSTWRITE); 1848 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, 1849 txd->tx_dmamap); 1850 m_freem(txd->tx_m); 1851 txd->tx_m = NULL; 1852 } 1853 } 1854 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 1855 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 1856 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 1857} 1858 1859static int 1860ti_init_tx_ring(struct ti_softc *sc) 1861{ 1862 struct ti_txdesc *txd; 1863 int i; 1864 1865 STAILQ_INIT(&sc->ti_cdata.ti_txfreeq); 1866 STAILQ_INIT(&sc->ti_cdata.ti_txbusyq); 1867 for (i = 0; i < TI_TX_RING_CNT; i++) { 1868 txd = &sc->ti_cdata.ti_txdesc[i]; 1869 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 1870 } 1871 sc->ti_txcnt = 0; 1872 sc->ti_tx_saved_considx = 0; 1873 sc->ti_tx_saved_prodidx = 0; 1874 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1875 return (0); 1876} 1877 1878/* 1879 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1880 * but we have to support the old way too so that Tigon 1 cards will 1881 * work. 1882 */ 1883static u_int 1884ti_add_mcast(void *arg, struct sockaddr_dl *sdl, u_int count) 1885{ 1886 struct ti_softc *sc = arg; 1887 struct ti_cmd_desc cmd; 1888 uint16_t *m; 1889 uint32_t ext[2] = {0, 0}; 1890 1891 m = (uint16_t *)LLADDR(sdl); 1892 1893 switch (sc->ti_hwrev) { 1894 case TI_HWREV_TIGON: 1895 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1896 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1897 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1898 break; 1899 case TI_HWREV_TIGON_II: 1900 ext[0] = htons(m[0]); 1901 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1902 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1903 break; 1904 default: 1905 device_printf(sc->ti_dev, "unknown hwrev\n"); 1906 return (0); 1907 } 1908 return (1); 1909} 1910 1911static u_int 1912ti_del_mcast(void *arg, struct sockaddr_dl *sdl, u_int count) 1913{ 1914 struct ti_softc *sc = arg; 1915 struct ti_cmd_desc cmd; 1916 uint16_t *m; 1917 uint32_t ext[2] = {0, 0}; 1918 1919 m = (uint16_t *)LLADDR(sdl); 1920 1921 switch (sc->ti_hwrev) { 1922 case TI_HWREV_TIGON: 1923 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1924 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1925 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1926 break; 1927 case TI_HWREV_TIGON_II: 1928 ext[0] = htons(m[0]); 1929 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1930 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1931 break; 1932 default: 1933 device_printf(sc->ti_dev, "unknown hwrev\n"); 1934 return (0); 1935 } 1936 1937 return (1); 1938} 1939 1940/* 1941 * Configure the Tigon's multicast address filter. 1942 * 1943 * The actual multicast table management is a bit of a pain, thanks to 1944 * slight brain damage on the part of both Alteon and us. With our 1945 * multicast code, we are only alerted when the multicast address table 1946 * changes and at that point we only have the current list of addresses: 1947 * we only know the current state, not the previous state, so we don't 1948 * actually know what addresses were removed or added. The firmware has 1949 * state, but we can't get our grubby mits on it, and there is no 'delete 1950 * all multicast addresses' command. Hence, we have to maintain our own 1951 * state so we know what addresses have been programmed into the NIC at 1952 * any given time. 1953 */ 1954static void 1955ti_setmulti(struct ti_softc *sc) 1956{ 1957 if_t ifp; 1958 struct ti_cmd_desc cmd; 1959 uint32_t intrs; 1960 1961 TI_LOCK_ASSERT(sc); 1962 1963 ifp = sc->ti_ifp; 1964 1965 if (if_getflags(ifp) & IFF_ALLMULTI) { 1966 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1967 return; 1968 } else { 1969 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1970 } 1971 1972 /* Disable interrupts. */ 1973 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1974 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1975 1976 /* First, zot all the existing filters. */ 1977 if_foreach_llmaddr(ifp, ti_del_mcast, sc); 1978 1979 /* Now program new ones. */ 1980 if_foreach_llmaddr(ifp, ti_add_mcast, sc); 1981 1982 /* Re-enable interrupts. */ 1983 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1984} 1985 1986/* 1987 * Check to see if the BIOS has configured us for a 64 bit slot when 1988 * we aren't actually in one. If we detect this condition, we can work 1989 * around it on the Tigon 2 by setting a bit in the PCI state register, 1990 * but for the Tigon 1 we must give up and abort the interface attach. 1991 */ 1992static int 1993ti_64bitslot_war(struct ti_softc *sc) 1994{ 1995 1996 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1997 CSR_WRITE_4(sc, 0x600, 0); 1998 CSR_WRITE_4(sc, 0x604, 0); 1999 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 2000 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 2001 if (sc->ti_hwrev == TI_HWREV_TIGON) 2002 return (EINVAL); 2003 else { 2004 TI_SETBIT(sc, TI_PCI_STATE, 2005 TI_PCISTATE_32BIT_BUS); 2006 return (0); 2007 } 2008 } 2009 } 2010 2011 return (0); 2012} 2013 2014/* 2015 * Do endian, PCI and DMA initialization. Also check the on-board ROM 2016 * self-test results. 2017 */ 2018static int 2019ti_chipinit(struct ti_softc *sc) 2020{ 2021 uint32_t cacheline; 2022 uint32_t pci_writemax = 0; 2023 uint32_t hdrsplit; 2024 2025 /* Initialize link to down state. */ 2026 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 2027 2028 /* Set endianness before we access any non-PCI registers. */ 2029#if 0 && BYTE_ORDER == BIG_ENDIAN 2030 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2031 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 2032#else 2033 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 2034 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 2035#endif 2036 2037 /* Check the ROM failed bit to see if self-tests passed. */ 2038 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 2039 device_printf(sc->ti_dev, "board self-diagnostics failed!\n"); 2040 return (ENODEV); 2041 } 2042 2043 /* Halt the CPU. */ 2044 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 2045 2046 /* Figure out the hardware revision. */ 2047 switch (CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 2048 case TI_REV_TIGON_I: 2049 sc->ti_hwrev = TI_HWREV_TIGON; 2050 break; 2051 case TI_REV_TIGON_II: 2052 sc->ti_hwrev = TI_HWREV_TIGON_II; 2053 break; 2054 default: 2055 device_printf(sc->ti_dev, "unsupported chip revision\n"); 2056 return (ENODEV); 2057 } 2058 2059 /* Do special setup for Tigon 2. */ 2060 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2061 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 2062 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K); 2063 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 2064 } 2065 2066 /* 2067 * We don't have firmware source for the Tigon 1, so Tigon 1 boards 2068 * can't do header splitting. 2069 */ 2070#ifdef TI_JUMBO_HDRSPLIT 2071 if (sc->ti_hwrev != TI_HWREV_TIGON) 2072 sc->ti_hdrsplit = 1; 2073 else 2074 device_printf(sc->ti_dev, 2075 "can't do header splitting on a Tigon I board\n"); 2076#endif /* TI_JUMBO_HDRSPLIT */ 2077 2078 /* Set up the PCI state register. */ 2079 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 2080 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 2081 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 2082 } 2083 2084 /* Clear the read/write max DMA parameters. */ 2085 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 2086 TI_PCISTATE_READ_MAXDMA)); 2087 2088 /* Get cache line size. */ 2089 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; 2090 2091 /* 2092 * If the system has set enabled the PCI memory write 2093 * and invalidate command in the command register, set 2094 * the write max parameter accordingly. This is necessary 2095 * to use MWI with the Tigon 2. 2096 */ 2097 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) { 2098 switch (cacheline) { 2099 case 1: 2100 case 4: 2101 case 8: 2102 case 16: 2103 case 32: 2104 case 64: 2105 break; 2106 default: 2107 /* Disable PCI memory write and invalidate. */ 2108 if (bootverbose) 2109 device_printf(sc->ti_dev, "cache line size %d" 2110 " not supported; disabling PCI MWI\n", 2111 cacheline); 2112 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc, 2113 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN); 2114 break; 2115 } 2116 } 2117 2118 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 2119 2120 /* This sets the min dma param all the way up (0xff). */ 2121 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 2122 2123 if (sc->ti_hdrsplit) 2124 hdrsplit = TI_OPMODE_JUMBO_HDRSPLIT; 2125 else 2126 hdrsplit = 0; 2127 2128 /* Configure DMA variables. */ 2129#if BYTE_ORDER == BIG_ENDIAN 2130 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 2131 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 2132 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 2133 TI_OPMODE_DONT_FRAG_JUMBO | hdrsplit); 2134#else /* BYTE_ORDER */ 2135 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 2136 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 2137 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB | hdrsplit); 2138#endif /* BYTE_ORDER */ 2139 2140 /* 2141 * Only allow 1 DMA channel to be active at a time. 2142 * I don't think this is a good idea, but without it 2143 * the firmware racks up lots of nicDmaReadRingFull 2144 * errors. This is not compatible with hardware checksums. 2145 */ 2146 if ((if_getcapenable(sc->ti_ifp) & (IFCAP_TXCSUM | IFCAP_RXCSUM)) == 0) 2147 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 2148 2149 /* Recommended settings from Tigon manual. */ 2150 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 2151 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 2152 2153 if (ti_64bitslot_war(sc)) { 2154 device_printf(sc->ti_dev, "bios thinks we're in a 64 bit slot, " 2155 "but we aren't"); 2156 return (EINVAL); 2157 } 2158 2159 return (0); 2160} 2161 2162/* 2163 * Initialize the general information block and firmware, and 2164 * start the CPU(s) running. 2165 */ 2166static int 2167ti_gibinit(struct ti_softc *sc) 2168{ 2169 if_t ifp; 2170 struct ti_rcb *rcb; 2171 int i; 2172 2173 TI_LOCK_ASSERT(sc); 2174 2175 ifp = sc->ti_ifp; 2176 2177 /* Disable interrupts for now. */ 2178 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2179 2180 /* Tell the chip where to find the general information block. */ 2181 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 2182 (uint64_t)sc->ti_rdata.ti_info_paddr >> 32); 2183 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, 2184 sc->ti_rdata.ti_info_paddr & 0xFFFFFFFF); 2185 2186 /* Load the firmware into SRAM. */ 2187 ti_loadfw(sc); 2188 2189 /* Set up the contents of the general info and ring control blocks. */ 2190 2191 /* Set up the event ring and producer pointer. */ 2192 bzero(sc->ti_rdata.ti_event_ring, TI_EVENT_RING_SZ); 2193 rcb = &sc->ti_rdata.ti_info->ti_ev_rcb; 2194 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_event_ring_paddr); 2195 rcb->ti_flags = 0; 2196 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_ev_prodidx_ptr, 2197 sc->ti_rdata.ti_status_paddr + 2198 offsetof(struct ti_status, ti_ev_prodidx_r)); 2199 sc->ti_ev_prodidx.ti_idx = 0; 2200 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 2201 sc->ti_ev_saved_considx = 0; 2202 2203 /* Set up the command ring and producer mailbox. */ 2204 rcb = &sc->ti_rdata.ti_info->ti_cmd_rcb; 2205 ti_hostaddr64(&rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING)); 2206 rcb->ti_flags = 0; 2207 rcb->ti_max_len = 0; 2208 for (i = 0; i < TI_CMD_RING_CNT; i++) { 2209 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 2210 } 2211 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 2212 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 2213 sc->ti_cmd_saved_prodidx = 0; 2214 2215 /* 2216 * Assign the address of the stats refresh buffer. 2217 * We re-use the current stats buffer for this to 2218 * conserve memory. 2219 */ 2220 bzero(&sc->ti_rdata.ti_info->ti_stats, sizeof(struct ti_stats)); 2221 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_refresh_stats_ptr, 2222 sc->ti_rdata.ti_info_paddr + offsetof(struct ti_gib, ti_stats)); 2223 2224 /* Set up the standard receive ring. */ 2225 rcb = &sc->ti_rdata.ti_info->ti_std_rx_rcb; 2226 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_std_ring_paddr); 2227 rcb->ti_max_len = TI_FRAMELEN; 2228 rcb->ti_flags = 0; 2229 if (if_getcapenable(ifp) & IFCAP_RXCSUM) 2230 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2231 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2232 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 2233 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2234 2235 /* Set up the jumbo receive ring. */ 2236 rcb = &sc->ti_rdata.ti_info->ti_jumbo_rx_rcb; 2237 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_jumbo_ring_paddr); 2238 2239#ifndef TI_SF_BUF_JUMBO 2240 rcb->ti_max_len = MJUM9BYTES - ETHER_ALIGN; 2241 rcb->ti_flags = 0; 2242#else 2243 rcb->ti_max_len = PAGE_SIZE; 2244 rcb->ti_flags = TI_RCB_FLAG_USE_EXT_RX_BD; 2245#endif 2246 if (if_getcapenable(ifp) & IFCAP_RXCSUM) 2247 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2248 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2249 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 2250 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2251 2252 /* 2253 * Set up the mini ring. Only activated on the 2254 * Tigon 2 but the slot in the config block is 2255 * still there on the Tigon 1. 2256 */ 2257 rcb = &sc->ti_rdata.ti_info->ti_mini_rx_rcb; 2258 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_mini_ring_paddr); 2259 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 2260 if (sc->ti_hwrev == TI_HWREV_TIGON) 2261 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 2262 else 2263 rcb->ti_flags = 0; 2264 if (if_getcapenable(ifp) & IFCAP_RXCSUM) 2265 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2266 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2267 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 2268 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2269 2270 /* 2271 * Set up the receive return ring. 2272 */ 2273 rcb = &sc->ti_rdata.ti_info->ti_return_rcb; 2274 ti_hostaddr64(&rcb->ti_hostaddr, sc->ti_rdata.ti_rx_return_ring_paddr); 2275 rcb->ti_flags = 0; 2276 rcb->ti_max_len = TI_RETURN_RING_CNT; 2277 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_return_prodidx_ptr, 2278 sc->ti_rdata.ti_status_paddr + 2279 offsetof(struct ti_status, ti_return_prodidx_r)); 2280 2281 /* 2282 * Set up the tx ring. Note: for the Tigon 2, we have the option 2283 * of putting the transmit ring in the host's address space and 2284 * letting the chip DMA it instead of leaving the ring in the NIC's 2285 * memory and accessing it through the shared memory region. We 2286 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 2287 * so we have to revert to the shared memory scheme if we detect 2288 * a Tigon 1 chip. 2289 */ 2290 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 2291 if (sc->ti_rdata.ti_tx_ring != NULL) 2292 bzero(sc->ti_rdata.ti_tx_ring, TI_TX_RING_SZ); 2293 rcb = &sc->ti_rdata.ti_info->ti_tx_rcb; 2294 if (sc->ti_hwrev == TI_HWREV_TIGON) 2295 rcb->ti_flags = 0; 2296 else 2297 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 2298 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 2299 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 2300 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2301 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 2302 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM; 2303 rcb->ti_max_len = TI_TX_RING_CNT; 2304 if (sc->ti_hwrev == TI_HWREV_TIGON) 2305 ti_hostaddr64(&rcb->ti_hostaddr, TI_TX_RING_BASE); 2306 else 2307 ti_hostaddr64(&rcb->ti_hostaddr, 2308 sc->ti_rdata.ti_tx_ring_paddr); 2309 ti_hostaddr64(&sc->ti_rdata.ti_info->ti_tx_considx_ptr, 2310 sc->ti_rdata.ti_status_paddr + 2311 offsetof(struct ti_status, ti_tx_considx_r)); 2312 2313 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, sc->ti_cdata.ti_gib_map, 2314 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2315 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, sc->ti_cdata.ti_status_map, 2316 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2317 bus_dmamap_sync(sc->ti_cdata.ti_event_ring_tag, 2318 sc->ti_cdata.ti_event_ring_map, 2319 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2320 if (sc->ti_rdata.ti_tx_ring != NULL) 2321 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2322 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 2323 2324 /* Set up tunables */ 2325#if 0 2326 if (if_getmtu(ifp) > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2327 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 2328 (sc->ti_rx_coal_ticks / 10)); 2329 else 2330#endif 2331 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 2332 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 2333 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 2334 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 2335 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 2336 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 2337 2338 /* Turn interrupts on. */ 2339 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 2340 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2341 2342 /* Start CPU. */ 2343 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 2344 2345 return (0); 2346} 2347 2348/* 2349 * Probe for a Tigon chip. Check the PCI vendor and device IDs 2350 * against our list and return its name if we find a match. 2351 */ 2352static int 2353ti_probe(device_t dev) 2354{ 2355 const struct ti_type *t; 2356 2357 t = ti_devs; 2358 2359 while (t->ti_name != NULL) { 2360 if ((pci_get_vendor(dev) == t->ti_vid) && 2361 (pci_get_device(dev) == t->ti_did)) { 2362 device_set_desc(dev, t->ti_name); 2363 return (BUS_PROBE_DEFAULT); 2364 } 2365 t++; 2366 } 2367 2368 return (ENXIO); 2369} 2370 2371static int 2372ti_attach(device_t dev) 2373{ 2374 if_t ifp; 2375 struct ti_softc *sc; 2376 int error = 0, rid; 2377 u_char eaddr[6]; 2378 2379 sc = device_get_softc(dev); 2380 sc->ti_dev = dev; 2381 2382 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2383 MTX_DEF); 2384 callout_init_mtx(&sc->ti_watchdog, &sc->ti_mtx, 0); 2385 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 2386 ifp = sc->ti_ifp = if_alloc(IFT_ETHER); 2387 if (ifp == NULL) { 2388 device_printf(dev, "can not if_alloc()\n"); 2389 error = ENOSPC; 2390 goto fail; 2391 } 2392 if_sethwassist(ifp, TI_CSUM_FEATURES); 2393 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_RXCSUM); 2394 if_setcapenable(ifp, if_getcapabilities(sc->ti_ifp)); 2395 2396 /* 2397 * Map control/status registers. 2398 */ 2399 pci_enable_busmaster(dev); 2400 2401 rid = PCIR_BAR(0); 2402 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2403 RF_ACTIVE); 2404 2405 if (sc->ti_res == NULL) { 2406 device_printf(dev, "couldn't map memory\n"); 2407 error = ENXIO; 2408 goto fail; 2409 } 2410 2411 sc->ti_btag = rman_get_bustag(sc->ti_res); 2412 sc->ti_bhandle = rman_get_bushandle(sc->ti_res); 2413 2414 /* Allocate interrupt */ 2415 rid = 0; 2416 2417 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2418 RF_SHAREABLE | RF_ACTIVE); 2419 2420 if (sc->ti_irq == NULL) { 2421 device_printf(dev, "couldn't map interrupt\n"); 2422 error = ENXIO; 2423 goto fail; 2424 } 2425 2426 if (ti_chipinit(sc)) { 2427 device_printf(dev, "chip initialization failed\n"); 2428 error = ENXIO; 2429 goto fail; 2430 } 2431 2432 /* Zero out the NIC's on-board SRAM. */ 2433 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 2434 2435 /* Init again -- zeroing memory may have clobbered some registers. */ 2436 if (ti_chipinit(sc)) { 2437 device_printf(dev, "chip initialization failed\n"); 2438 error = ENXIO; 2439 goto fail; 2440 } 2441 2442 /* 2443 * Get station address from the EEPROM. Note: the manual states 2444 * that the MAC address is at offset 0x8c, however the data is 2445 * stored as two longwords (since that's how it's loaded into 2446 * the NIC). This means the MAC address is actually preceded 2447 * by two zero bytes. We need to skip over those. 2448 */ 2449 if (ti_read_eeprom(sc, eaddr, TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2450 device_printf(dev, "failed to read station address\n"); 2451 error = ENXIO; 2452 goto fail; 2453 } 2454 2455 /* Allocate working area for memory dump. */ 2456 sc->ti_membuf = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, M_NOWAIT); 2457 sc->ti_membuf2 = malloc(sizeof(uint8_t) * TI_WINLEN, M_DEVBUF, 2458 M_NOWAIT); 2459 if (sc->ti_membuf == NULL || sc->ti_membuf2 == NULL) { 2460 device_printf(dev, "cannot allocate memory buffer\n"); 2461 error = ENOMEM; 2462 goto fail; 2463 } 2464 if ((error = ti_dma_alloc(sc)) != 0) 2465 goto fail; 2466 2467 /* 2468 * We really need a better way to tell a 1000baseTX card 2469 * from a 1000baseSX one, since in theory there could be 2470 * OEMed 1000baseTX cards from lame vendors who aren't 2471 * clever enough to change the PCI ID. For the moment 2472 * though, the AceNIC is the only copper card available. 2473 */ 2474 if (pci_get_vendor(dev) == ALT_VENDORID && 2475 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER) 2476 sc->ti_copper = 1; 2477 /* Ok, it's not the only copper card available. */ 2478 if (pci_get_vendor(dev) == NG_VENDORID && 2479 pci_get_device(dev) == NG_DEVICEID_GA620T) 2480 sc->ti_copper = 1; 2481 2482 /* Set default tunable values. */ 2483 ti_sysctl_node(sc); 2484 2485 /* Set up ifnet structure */ 2486 if_setsoftc(ifp, sc); 2487 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2488 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 2489 if_setioctlfn(ifp, ti_ioctl); 2490 if_setstartfn(ifp, ti_start); 2491 if_setinitfn(ifp, ti_init); 2492 if_setgetcounterfn(ifp, ti_get_counter); 2493 if_setbaudrate(ifp, IF_Gbps(1UL)); 2494 if_setsendqlen(ifp, TI_TX_RING_CNT - 1); 2495 if_setsendqready(ifp); 2496 2497 /* Set up ifmedia support. */ 2498 if (sc->ti_copper) { 2499 /* 2500 * Copper cards allow manual 10/100 mode selection, 2501 * but not manual 1000baseTX mode selection. Why? 2502 * Because currently there's no way to specify the 2503 * master/slave setting through the firmware interface, 2504 * so Alteon decided to just bag it and handle it 2505 * via autonegotiation. 2506 */ 2507 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 2508 ifmedia_add(&sc->ifmedia, 2509 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 2510 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 2511 ifmedia_add(&sc->ifmedia, 2512 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 2513 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 2514 ifmedia_add(&sc->ifmedia, 2515 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 2516 } else { 2517 /* Fiber cards don't support 10/100 modes. */ 2518 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2519 ifmedia_add(&sc->ifmedia, 2520 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2521 } 2522 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2523 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 2524 2525 /* 2526 * We're assuming here that card initialization is a sequential 2527 * thing. If it isn't, multiple cards probing at the same time 2528 * could stomp on the list of softcs here. 2529 */ 2530 2531 /* Register the device */ 2532 sc->dev = make_dev(&ti_cdevsw, device_get_unit(dev), UID_ROOT, 2533 GID_OPERATOR, 0600, "ti%d", device_get_unit(dev)); 2534 sc->dev->si_drv1 = sc; 2535 2536 /* 2537 * Call MI attach routine. 2538 */ 2539 ether_ifattach(ifp, eaddr); 2540 2541 /* VLAN capability setup. */ 2542 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM | 2543 IFCAP_VLAN_HWTAGGING, 0); 2544 if_setcapenable(ifp, if_getcapabilities(ifp)); 2545 /* Tell the upper layer we support VLAN over-sized frames. */ 2546 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2547 2548 /* Driver supports link state tracking. */ 2549 if_setcapabilitiesbit(ifp, IFCAP_LINKSTATE, 0); 2550 if_setcapenablebit(ifp, IFCAP_LINKSTATE, 0); 2551 2552 /* Hook interrupt last to avoid having to lock softc */ 2553 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET|INTR_MPSAFE, 2554 NULL, ti_intr, sc, &sc->ti_intrhand); 2555 2556 if (error) { 2557 device_printf(dev, "couldn't set up irq\n"); 2558 goto fail; 2559 } 2560 2561fail: 2562 if (error) 2563 ti_detach(dev); 2564 2565 return (error); 2566} 2567 2568/* 2569 * Shutdown hardware and free up resources. This can be called any 2570 * time after the mutex has been initialized. It is called in both 2571 * the error case in attach and the normal detach case so it needs 2572 * to be careful about only freeing resources that have actually been 2573 * allocated. 2574 */ 2575static int 2576ti_detach(device_t dev) 2577{ 2578 struct ti_softc *sc; 2579 if_t ifp; 2580 2581 sc = device_get_softc(dev); 2582 if (sc->dev) 2583 destroy_dev(sc->dev); 2584 KASSERT(mtx_initialized(&sc->ti_mtx), ("ti mutex not initialized")); 2585 ifp = sc->ti_ifp; 2586 if (device_is_attached(dev)) { 2587 ether_ifdetach(ifp); 2588 TI_LOCK(sc); 2589 ti_stop(sc); 2590 TI_UNLOCK(sc); 2591 } 2592 2593 /* These should only be active if attach succeeded */ 2594 callout_drain(&sc->ti_watchdog); 2595 bus_generic_detach(dev); 2596 ti_dma_free(sc); 2597 ifmedia_removeall(&sc->ifmedia); 2598 2599 if (sc->ti_intrhand) 2600 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand); 2601 if (sc->ti_irq) 2602 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq); 2603 if (sc->ti_res) { 2604 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 2605 sc->ti_res); 2606 } 2607 if (ifp) 2608 if_free(ifp); 2609 if (sc->ti_membuf) 2610 free(sc->ti_membuf, M_DEVBUF); 2611 if (sc->ti_membuf2) 2612 free(sc->ti_membuf2, M_DEVBUF); 2613 2614 mtx_destroy(&sc->ti_mtx); 2615 2616 return (0); 2617} 2618 2619#ifdef TI_JUMBO_HDRSPLIT 2620/* 2621 * If hdr_len is 0, that means that header splitting wasn't done on 2622 * this packet for some reason. The two most likely reasons are that 2623 * the protocol isn't a supported protocol for splitting, or this 2624 * packet had a fragment offset that wasn't 0. 2625 * 2626 * The header length, if it is non-zero, will always be the length of 2627 * the headers on the packet, but that length could be longer than the 2628 * first mbuf. So we take the minimum of the two as the actual 2629 * length. 2630 */ 2631static __inline void 2632ti_hdr_split(struct mbuf *top, int hdr_len, int pkt_len, int idx) 2633{ 2634 int i = 0; 2635 int lengths[4] = {0, 0, 0, 0}; 2636 struct mbuf *m, *mp; 2637 2638 if (hdr_len != 0) 2639 top->m_len = min(hdr_len, top->m_len); 2640 pkt_len -= top->m_len; 2641 lengths[i++] = top->m_len; 2642 2643 mp = top; 2644 for (m = top->m_next; m && pkt_len; m = m->m_next) { 2645 m->m_len = m->m_ext.ext_size = min(m->m_len, pkt_len); 2646 pkt_len -= m->m_len; 2647 lengths[i++] = m->m_len; 2648 mp = m; 2649 } 2650 2651#if 0 2652 if (hdr_len != 0) 2653 printf("got split packet: "); 2654 else 2655 printf("got non-split packet: "); 2656 2657 printf("%d,%d,%d,%d = %d\n", lengths[0], 2658 lengths[1], lengths[2], lengths[3], 2659 lengths[0] + lengths[1] + lengths[2] + 2660 lengths[3]); 2661#endif 2662 2663 if (pkt_len) 2664 panic("header splitting didn't"); 2665 2666 if (m) { 2667 m_freem(m); 2668 mp->m_next = NULL; 2669 } 2670 if (mp->m_next != NULL) 2671 panic("ti_hdr_split: last mbuf in chain should be null"); 2672} 2673#endif /* TI_JUMBO_HDRSPLIT */ 2674 2675static void 2676ti_discard_std(struct ti_softc *sc, int i) 2677{ 2678 2679 struct ti_rx_desc *r; 2680 2681 r = &sc->ti_rdata.ti_rx_std_ring[i]; 2682 r->ti_len = MCLBYTES - ETHER_ALIGN; 2683 r->ti_type = TI_BDTYPE_RECV_BD; 2684 r->ti_flags = 0; 2685 r->ti_vlan_tag = 0; 2686 r->ti_tcp_udp_cksum = 0; 2687 if (if_getcapenable(sc->ti_ifp) & IFCAP_RXCSUM) 2688 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2689 r->ti_idx = i; 2690} 2691 2692static void 2693ti_discard_mini(struct ti_softc *sc, int i) 2694{ 2695 2696 struct ti_rx_desc *r; 2697 2698 r = &sc->ti_rdata.ti_rx_mini_ring[i]; 2699 r->ti_len = MHLEN - ETHER_ALIGN; 2700 r->ti_type = TI_BDTYPE_RECV_BD; 2701 r->ti_flags = TI_BDFLAG_MINI_RING; 2702 r->ti_vlan_tag = 0; 2703 r->ti_tcp_udp_cksum = 0; 2704 if (if_getcapenable(sc->ti_ifp) & IFCAP_RXCSUM) 2705 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2706 r->ti_idx = i; 2707} 2708 2709#ifndef TI_SF_BUF_JUMBO 2710static void 2711ti_discard_jumbo(struct ti_softc *sc, int i) 2712{ 2713 2714 struct ti_rx_desc *r; 2715 2716 r = &sc->ti_rdata.ti_rx_jumbo_ring[i]; 2717 r->ti_len = MJUM9BYTES - ETHER_ALIGN; 2718 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 2719 r->ti_flags = TI_BDFLAG_JUMBO_RING; 2720 r->ti_vlan_tag = 0; 2721 r->ti_tcp_udp_cksum = 0; 2722 if (if_getcapenable(sc->ti_ifp) & IFCAP_RXCSUM) 2723 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM; 2724 r->ti_idx = i; 2725} 2726#endif 2727 2728/* 2729 * Frame reception handling. This is called if there's a frame 2730 * on the receive return list. 2731 * 2732 * Note: we have to be able to handle three possibilities here: 2733 * 1) the frame is from the mini receive ring (can only happen) 2734 * on Tigon 2 boards) 2735 * 2) the frame is from the jumbo receive ring 2736 * 3) the frame is from the standard receive ring 2737 */ 2738 2739static void 2740ti_rxeof(struct ti_softc *sc) 2741{ 2742 if_t ifp; 2743#ifdef TI_SF_BUF_JUMBO 2744 bus_dmamap_t map; 2745#endif 2746 struct ti_cmd_desc cmd; 2747 int jumbocnt, minicnt, stdcnt, ti_len; 2748 2749 TI_LOCK_ASSERT(sc); 2750 2751 ifp = sc->ti_ifp; 2752 2753 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2754 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 2755 if (if_getmtu(ifp) > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) 2756 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2757 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 2758 if (sc->ti_rdata.ti_rx_mini_ring != NULL) 2759 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2760 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_POSTWRITE); 2761 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2762 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 2763 2764 jumbocnt = minicnt = stdcnt = 0; 2765 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 2766 struct ti_rx_desc *cur_rx; 2767 uint32_t rxidx; 2768 struct mbuf *m = NULL; 2769 uint16_t vlan_tag = 0; 2770 int have_tag = 0; 2771 2772 cur_rx = 2773 &sc->ti_rdata.ti_rx_return_ring[sc->ti_rx_saved_considx]; 2774 rxidx = cur_rx->ti_idx; 2775 ti_len = cur_rx->ti_len; 2776 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 2777 2778 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2779 have_tag = 1; 2780 vlan_tag = cur_rx->ti_vlan_tag; 2781 } 2782 2783 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 2784 jumbocnt++; 2785 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 2786 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 2787#ifndef TI_SF_BUF_JUMBO 2788 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2789 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2790 ti_discard_jumbo(sc, rxidx); 2791 continue; 2792 } 2793 if (ti_newbuf_jumbo(sc, rxidx, NULL) != 0) { 2794 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2795 ti_discard_jumbo(sc, rxidx); 2796 continue; 2797 } 2798 m->m_len = ti_len; 2799#else /* !TI_SF_BUF_JUMBO */ 2800 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 2801 map = sc->ti_cdata.ti_rx_jumbo_maps[rxidx]; 2802 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_tag, map, 2803 BUS_DMASYNC_POSTREAD); 2804 bus_dmamap_unload(sc->ti_cdata.ti_rx_jumbo_tag, map); 2805 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2806 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2807 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2808 continue; 2809 } 2810 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) { 2811 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2812 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 2813 continue; 2814 } 2815#ifdef TI_JUMBO_HDRSPLIT 2816 if (sc->ti_hdrsplit) 2817 ti_hdr_split(m, TI_HOSTADDR(cur_rx->ti_addr), 2818 ti_len, rxidx); 2819 else 2820#endif /* TI_JUMBO_HDRSPLIT */ 2821 m_adj(m, ti_len - m->m_pkthdr.len); 2822#endif /* TI_SF_BUF_JUMBO */ 2823 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 2824 minicnt++; 2825 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 2826 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 2827 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2828 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2829 ti_discard_mini(sc, rxidx); 2830 continue; 2831 } 2832 if (ti_newbuf_mini(sc, rxidx) != 0) { 2833 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2834 ti_discard_mini(sc, rxidx); 2835 continue; 2836 } 2837 m->m_len = ti_len; 2838 } else { 2839 stdcnt++; 2840 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2841 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2842 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2843 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2844 ti_discard_std(sc, rxidx); 2845 continue; 2846 } 2847 if (ti_newbuf_std(sc, rxidx) != 0) { 2848 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2849 ti_discard_std(sc, rxidx); 2850 continue; 2851 } 2852 m->m_len = ti_len; 2853 } 2854 2855 m->m_pkthdr.len = ti_len; 2856 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2857 m->m_pkthdr.rcvif = ifp; 2858 2859 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 2860 if (cur_rx->ti_flags & TI_BDFLAG_IP_CKSUM) { 2861 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2862 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0) 2863 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2864 } 2865 if (cur_rx->ti_flags & TI_BDFLAG_TCP_UDP_CKSUM) { 2866 m->m_pkthdr.csum_data = 2867 cur_rx->ti_tcp_udp_cksum; 2868 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2869 } 2870 } 2871 2872 /* 2873 * If we received a packet with a vlan tag, 2874 * tag it before passing the packet upward. 2875 */ 2876 if (have_tag) { 2877 m->m_pkthdr.ether_vtag = vlan_tag; 2878 m->m_flags |= M_VLANTAG; 2879 } 2880 TI_UNLOCK(sc); 2881 if_input(ifp, m); 2882 TI_LOCK(sc); 2883 } 2884 2885 bus_dmamap_sync(sc->ti_cdata.ti_rx_return_ring_tag, 2886 sc->ti_cdata.ti_rx_return_ring_map, BUS_DMASYNC_PREREAD); 2887 /* Only necessary on the Tigon 1. */ 2888 if (sc->ti_hwrev == TI_HWREV_TIGON) 2889 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2890 sc->ti_rx_saved_considx); 2891 2892 if (stdcnt > 0) { 2893 bus_dmamap_sync(sc->ti_cdata.ti_rx_std_ring_tag, 2894 sc->ti_cdata.ti_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 2895 TI_UPDATE_STDPROD(sc, sc->ti_std); 2896 } 2897 if (minicnt > 0) { 2898 bus_dmamap_sync(sc->ti_cdata.ti_rx_mini_ring_tag, 2899 sc->ti_cdata.ti_rx_mini_ring_map, BUS_DMASYNC_PREWRITE); 2900 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2901 } 2902 if (jumbocnt > 0) { 2903 bus_dmamap_sync(sc->ti_cdata.ti_rx_jumbo_ring_tag, 2904 sc->ti_cdata.ti_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 2905 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2906 } 2907} 2908 2909static void 2910ti_txeof(struct ti_softc *sc) 2911{ 2912 struct ti_txdesc *txd; 2913 struct ti_tx_desc txdesc; 2914 struct ti_tx_desc *cur_tx = NULL; 2915 if_t ifp; 2916 int idx; 2917 2918 ifp = sc->ti_ifp; 2919 2920 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2921 if (txd == NULL) 2922 return; 2923 2924 if (sc->ti_rdata.ti_tx_ring != NULL) 2925 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 2926 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2927 /* 2928 * Go through our tx ring and free mbufs for those 2929 * frames that have been sent. 2930 */ 2931 for (idx = sc->ti_tx_saved_considx; idx != sc->ti_tx_considx.ti_idx; 2932 TI_INC(idx, TI_TX_RING_CNT)) { 2933 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2934 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc), 2935 sizeof(txdesc), &txdesc); 2936 cur_tx = &txdesc; 2937 } else 2938 cur_tx = &sc->ti_rdata.ti_tx_ring[idx]; 2939 sc->ti_txcnt--; 2940 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2941 if ((cur_tx->ti_flags & TI_BDFLAG_END) == 0) 2942 continue; 2943 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 2944 BUS_DMASYNC_POSTWRITE); 2945 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 2946 2947 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2948 m_freem(txd->tx_m); 2949 txd->tx_m = NULL; 2950 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txbusyq, tx_q); 2951 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txfreeq, txd, tx_q); 2952 txd = STAILQ_FIRST(&sc->ti_cdata.ti_txbusyq); 2953 } 2954 sc->ti_tx_saved_considx = idx; 2955 if (sc->ti_txcnt == 0) 2956 sc->ti_timer = 0; 2957} 2958 2959static void 2960ti_intr(void *xsc) 2961{ 2962 struct ti_softc *sc; 2963 if_t ifp; 2964 2965 sc = xsc; 2966 TI_LOCK(sc); 2967 ifp = sc->ti_ifp; 2968 2969 /* Make sure this is really our interrupt. */ 2970 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) { 2971 TI_UNLOCK(sc); 2972 return; 2973 } 2974 2975 /* Ack interrupt and stop others from occurring. */ 2976 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2977 2978 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2979 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 2980 sc->ti_cdata.ti_status_map, BUS_DMASYNC_POSTREAD); 2981 /* Check RX return ring producer/consumer */ 2982 ti_rxeof(sc); 2983 2984 /* Check TX ring producer/consumer */ 2985 ti_txeof(sc); 2986 bus_dmamap_sync(sc->ti_cdata.ti_status_tag, 2987 sc->ti_cdata.ti_status_map, BUS_DMASYNC_PREREAD); 2988 } 2989 2990 ti_handle_events(sc); 2991 2992 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 2993 /* Re-enable interrupts. */ 2994 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2995 if (!if_sendq_empty(ifp)) 2996 ti_start_locked(ifp); 2997 } 2998 2999 TI_UNLOCK(sc); 3000} 3001 3002static uint64_t 3003ti_get_counter(if_t ifp, ift_counter cnt) 3004{ 3005 3006 switch (cnt) { 3007 case IFCOUNTER_COLLISIONS: 3008 { 3009 struct ti_softc *sc; 3010 struct ti_stats *s; 3011 uint64_t rv; 3012 3013 sc = if_getsoftc(ifp); 3014 s = &sc->ti_rdata.ti_info->ti_stats; 3015 3016 TI_LOCK(sc); 3017 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3018 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD); 3019 rv = s->dot3StatsSingleCollisionFrames + 3020 s->dot3StatsMultipleCollisionFrames + 3021 s->dot3StatsExcessiveCollisions + 3022 s->dot3StatsLateCollisions; 3023 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3024 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_PREREAD); 3025 TI_UNLOCK(sc); 3026 return (rv); 3027 } 3028 default: 3029 return (if_get_counter_default(ifp, cnt)); 3030 } 3031} 3032 3033/* 3034 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3035 * pointers to descriptors. 3036 */ 3037static int 3038ti_encap(struct ti_softc *sc, struct mbuf **m_head) 3039{ 3040 struct ti_txdesc *txd; 3041 struct ti_tx_desc *f; 3042 struct ti_tx_desc txdesc; 3043 struct mbuf *m; 3044 bus_dma_segment_t txsegs[TI_MAXTXSEGS]; 3045 uint16_t csum_flags; 3046 int error, frag, i, nseg; 3047 3048 if ((txd = STAILQ_FIRST(&sc->ti_cdata.ti_txfreeq)) == NULL) 3049 return (ENOBUFS); 3050 3051 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3052 *m_head, txsegs, &nseg, 0); 3053 if (error == EFBIG) { 3054 m = m_defrag(*m_head, M_NOWAIT); 3055 if (m == NULL) { 3056 m_freem(*m_head); 3057 *m_head = NULL; 3058 return (ENOMEM); 3059 } 3060 *m_head = m; 3061 error = bus_dmamap_load_mbuf_sg(sc->ti_cdata.ti_tx_tag, 3062 txd->tx_dmamap, *m_head, txsegs, &nseg, 0); 3063 if (error) { 3064 m_freem(*m_head); 3065 *m_head = NULL; 3066 return (error); 3067 } 3068 } else if (error != 0) 3069 return (error); 3070 if (nseg == 0) { 3071 m_freem(*m_head); 3072 *m_head = NULL; 3073 return (EIO); 3074 } 3075 3076 if (sc->ti_txcnt + nseg >= TI_TX_RING_CNT) { 3077 bus_dmamap_unload(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap); 3078 return (ENOBUFS); 3079 } 3080 bus_dmamap_sync(sc->ti_cdata.ti_tx_tag, txd->tx_dmamap, 3081 BUS_DMASYNC_PREWRITE); 3082 3083 m = *m_head; 3084 csum_flags = 0; 3085 if (m->m_pkthdr.csum_flags & CSUM_IP) 3086 csum_flags |= TI_BDFLAG_IP_CKSUM; 3087 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3088 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 3089 3090 frag = sc->ti_tx_saved_prodidx; 3091 for (i = 0; i < nseg; i++) { 3092 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3093 bzero(&txdesc, sizeof(txdesc)); 3094 f = &txdesc; 3095 } else 3096 f = &sc->ti_rdata.ti_tx_ring[frag]; 3097 ti_hostaddr64(&f->ti_addr, txsegs[i].ds_addr); 3098 f->ti_len = txsegs[i].ds_len; 3099 f->ti_flags = csum_flags; 3100 if (m->m_flags & M_VLANTAG) { 3101 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 3102 f->ti_vlan_tag = m->m_pkthdr.ether_vtag; 3103 } else { 3104 f->ti_vlan_tag = 0; 3105 } 3106 3107 if (sc->ti_hwrev == TI_HWREV_TIGON) 3108 ti_mem_write(sc, TI_TX_RING_BASE + frag * 3109 sizeof(txdesc), sizeof(txdesc), &txdesc); 3110 TI_INC(frag, TI_TX_RING_CNT); 3111 } 3112 3113 sc->ti_tx_saved_prodidx = frag; 3114 /* set TI_BDFLAG_END on the last descriptor */ 3115 frag = (frag + TI_TX_RING_CNT - 1) % TI_TX_RING_CNT; 3116 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3117 txdesc.ti_flags |= TI_BDFLAG_END; 3118 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc), 3119 sizeof(txdesc), &txdesc); 3120 } else 3121 sc->ti_rdata.ti_tx_ring[frag].ti_flags |= TI_BDFLAG_END; 3122 3123 STAILQ_REMOVE_HEAD(&sc->ti_cdata.ti_txfreeq, tx_q); 3124 STAILQ_INSERT_TAIL(&sc->ti_cdata.ti_txbusyq, txd, tx_q); 3125 txd->tx_m = m; 3126 sc->ti_txcnt += nseg; 3127 3128 return (0); 3129} 3130 3131static void 3132ti_start(if_t ifp) 3133{ 3134 struct ti_softc *sc; 3135 3136 sc = if_getsoftc(ifp); 3137 TI_LOCK(sc); 3138 ti_start_locked(ifp); 3139 TI_UNLOCK(sc); 3140} 3141 3142/* 3143 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3144 * to the mbuf data regions directly in the transmit descriptors. 3145 */ 3146static void 3147ti_start_locked(if_t ifp) 3148{ 3149 struct ti_softc *sc; 3150 struct mbuf *m_head = NULL; 3151 int enq = 0; 3152 3153 sc = if_getsoftc(ifp); 3154 3155 for (; !if_sendq_empty(ifp) && 3156 sc->ti_txcnt < (TI_TX_RING_CNT - 16);) { 3157 m_head = if_dequeue(ifp); 3158 if (m_head == NULL) 3159 break; 3160 3161 /* 3162 * Pack the data into the transmit ring. If we 3163 * don't have room, set the OACTIVE flag and wait 3164 * for the NIC to drain the ring. 3165 */ 3166 if (ti_encap(sc, &m_head)) { 3167 if (m_head == NULL) 3168 break; 3169 if_sendq_prepend(ifp, m_head); 3170 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 3171 break; 3172 } 3173 3174 enq++; 3175 /* 3176 * If there's a BPF listener, bounce a copy of this frame 3177 * to him. 3178 */ 3179 ETHER_BPF_MTAP(ifp, m_head); 3180 } 3181 3182 if (enq > 0) { 3183 if (sc->ti_rdata.ti_tx_ring != NULL) 3184 bus_dmamap_sync(sc->ti_cdata.ti_tx_ring_tag, 3185 sc->ti_cdata.ti_tx_ring_map, BUS_DMASYNC_PREWRITE); 3186 /* Transmit */ 3187 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, sc->ti_tx_saved_prodidx); 3188 3189 /* 3190 * Set a timeout in case the chip goes out to lunch. 3191 */ 3192 sc->ti_timer = 5; 3193 } 3194} 3195 3196static void 3197ti_init(void *xsc) 3198{ 3199 struct ti_softc *sc; 3200 3201 sc = xsc; 3202 TI_LOCK(sc); 3203 ti_init_locked(sc); 3204 TI_UNLOCK(sc); 3205} 3206 3207static void 3208ti_init_locked(void *xsc) 3209{ 3210 struct ti_softc *sc = xsc; 3211 3212 if (if_getdrvflags(sc->ti_ifp) & IFF_DRV_RUNNING) 3213 return; 3214 3215 /* Cancel pending I/O and flush buffers. */ 3216 ti_stop(sc); 3217 3218 /* Init the gen info block, ring control blocks and firmware. */ 3219 if (ti_gibinit(sc)) { 3220 device_printf(sc->ti_dev, "initialization failure\n"); 3221 return; 3222 } 3223} 3224 3225static void ti_init2(struct ti_softc *sc) 3226{ 3227 struct ti_cmd_desc cmd; 3228 if_t ifp; 3229 uint8_t *ea; 3230 struct ifmedia *ifm; 3231 int tmp; 3232 3233 TI_LOCK_ASSERT(sc); 3234 3235 ifp = sc->ti_ifp; 3236 3237 /* Specify MTU and interface index. */ 3238 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_get_unit(sc->ti_dev)); 3239 CSR_WRITE_4(sc, TI_GCR_IFMTU, if_getmtu(ifp) + 3240 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3241 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 3242 3243 /* Load our MAC address. */ 3244 ea = if_getlladdr(sc->ti_ifp); 3245 CSR_WRITE_4(sc, TI_GCR_PAR0, (ea[0] << 8) | ea[1]); 3246 CSR_WRITE_4(sc, TI_GCR_PAR1, 3247 (ea[2] << 24) | (ea[3] << 16) | (ea[4] << 8) | ea[5]); 3248 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 3249 3250 /* Enable or disable promiscuous mode as needed. */ 3251 if (if_getflags(ifp) & IFF_PROMISC) { 3252 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 3253 } else { 3254 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 3255 } 3256 3257 /* Program multicast filter. */ 3258 ti_setmulti(sc); 3259 3260 /* 3261 * If this is a Tigon 1, we should tell the 3262 * firmware to use software packet filtering. 3263 */ 3264 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3265 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 3266 } 3267 3268 /* Init RX ring. */ 3269 if (ti_init_rx_ring_std(sc) != 0) { 3270 /* XXX */ 3271 device_printf(sc->ti_dev, "no memory for std Rx buffers.\n"); 3272 return; 3273 } 3274 3275 /* Init jumbo RX ring. */ 3276 if (if_getmtu(ifp) > ETHERMTU + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) { 3277 if (ti_init_rx_ring_jumbo(sc) != 0) { 3278 /* XXX */ 3279 device_printf(sc->ti_dev, 3280 "no memory for jumbo Rx buffers.\n"); 3281 return; 3282 } 3283 } 3284 3285 /* 3286 * If this is a Tigon 2, we can also configure the 3287 * mini ring. 3288 */ 3289 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 3290 if (ti_init_rx_ring_mini(sc) != 0) { 3291 /* XXX */ 3292 device_printf(sc->ti_dev, 3293 "no memory for mini Rx buffers.\n"); 3294 return; 3295 } 3296 } 3297 3298 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 3299 sc->ti_rx_saved_considx = 0; 3300 3301 /* Init TX ring. */ 3302 ti_init_tx_ring(sc); 3303 3304 /* Tell firmware we're alive. */ 3305 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 3306 3307 /* Enable host interrupts. */ 3308 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 3309 3310 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 3311 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3312 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3313 3314 /* 3315 * Make sure to set media properly. We have to do this 3316 * here since we have to issue commands in order to set 3317 * the link negotiation and we can't issue commands until 3318 * the firmware is running. 3319 */ 3320 ifm = &sc->ifmedia; 3321 tmp = ifm->ifm_media; 3322 ifm->ifm_media = ifm->ifm_cur->ifm_media; 3323 ti_ifmedia_upd_locked(sc); 3324 ifm->ifm_media = tmp; 3325} 3326 3327/* 3328 * Set media options. 3329 */ 3330static int 3331ti_ifmedia_upd(if_t ifp) 3332{ 3333 struct ti_softc *sc; 3334 int error; 3335 3336 sc = if_getsoftc(ifp); 3337 TI_LOCK(sc); 3338 error = ti_ifmedia_upd_locked(sc); 3339 TI_UNLOCK(sc); 3340 3341 return (error); 3342} 3343 3344static int 3345ti_ifmedia_upd_locked(struct ti_softc *sc) 3346{ 3347 struct ifmedia *ifm; 3348 struct ti_cmd_desc cmd; 3349 uint32_t flowctl; 3350 3351 ifm = &sc->ifmedia; 3352 3353 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3354 return (EINVAL); 3355 3356 flowctl = 0; 3357 3358 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3359 case IFM_AUTO: 3360 /* 3361 * Transmit flow control doesn't work on the Tigon 1. 3362 */ 3363 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3364 3365 /* 3366 * Transmit flow control can also cause problems on the 3367 * Tigon 2, apparently with both the copper and fiber 3368 * boards. The symptom is that the interface will just 3369 * hang. This was reproduced with Alteon 180 switches. 3370 */ 3371#if 0 3372 if (sc->ti_hwrev != TI_HWREV_TIGON) 3373 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3374#endif 3375 3376 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3377 TI_GLNK_FULL_DUPLEX| flowctl | 3378 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 3379 3380 flowctl = TI_LNK_RX_FLOWCTL_Y; 3381#if 0 3382 if (sc->ti_hwrev != TI_HWREV_TIGON) 3383 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3384#endif 3385 3386 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 3387 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| flowctl | 3388 TI_LNK_AUTONEGENB|TI_LNK_ENB); 3389 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3390 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 3391 break; 3392 case IFM_1000_SX: 3393 case IFM_1000_T: 3394 flowctl = TI_GLNK_RX_FLOWCTL_Y; 3395#if 0 3396 if (sc->ti_hwrev != TI_HWREV_TIGON) 3397 flowctl |= TI_GLNK_TX_FLOWCTL_Y; 3398#endif 3399 3400 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 3401 flowctl |TI_GLNK_ENB); 3402 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 3403 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3404 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX); 3405 } 3406 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3407 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 3408 break; 3409 case IFM_100_FX: 3410 case IFM_10_FL: 3411 case IFM_100_TX: 3412 case IFM_10_T: 3413 flowctl = TI_LNK_RX_FLOWCTL_Y; 3414#if 0 3415 if (sc->ti_hwrev != TI_HWREV_TIGON) 3416 flowctl |= TI_LNK_TX_FLOWCTL_Y; 3417#endif 3418 3419 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 3420 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF|flowctl); 3421 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 3422 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 3423 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 3424 } else { 3425 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 3426 } 3427 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3428 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 3429 } else { 3430 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 3431 } 3432 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 3433 TI_CMD_CODE_NEGOTIATE_10_100, 0); 3434 break; 3435 } 3436 3437 return (0); 3438} 3439 3440/* 3441 * Report current media status. 3442 */ 3443static void 3444ti_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 3445{ 3446 struct ti_softc *sc; 3447 uint32_t media = 0; 3448 3449 sc = if_getsoftc(ifp); 3450 3451 TI_LOCK(sc); 3452 3453 ifmr->ifm_status = IFM_AVALID; 3454 ifmr->ifm_active = IFM_ETHER; 3455 3456 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) { 3457 TI_UNLOCK(sc); 3458 return; 3459 } 3460 3461 ifmr->ifm_status |= IFM_ACTIVE; 3462 3463 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 3464 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 3465 if (sc->ti_copper) 3466 ifmr->ifm_active |= IFM_1000_T; 3467 else 3468 ifmr->ifm_active |= IFM_1000_SX; 3469 if (media & TI_GLNK_FULL_DUPLEX) 3470 ifmr->ifm_active |= IFM_FDX; 3471 else 3472 ifmr->ifm_active |= IFM_HDX; 3473 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 3474 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 3475 if (sc->ti_copper) { 3476 if (media & TI_LNK_100MB) 3477 ifmr->ifm_active |= IFM_100_TX; 3478 if (media & TI_LNK_10MB) 3479 ifmr->ifm_active |= IFM_10_T; 3480 } else { 3481 if (media & TI_LNK_100MB) 3482 ifmr->ifm_active |= IFM_100_FX; 3483 if (media & TI_LNK_10MB) 3484 ifmr->ifm_active |= IFM_10_FL; 3485 } 3486 if (media & TI_LNK_FULL_DUPLEX) 3487 ifmr->ifm_active |= IFM_FDX; 3488 if (media & TI_LNK_HALF_DUPLEX) 3489 ifmr->ifm_active |= IFM_HDX; 3490 } 3491 TI_UNLOCK(sc); 3492} 3493 3494static int 3495ti_ioctl(if_t ifp, u_long command, caddr_t data) 3496{ 3497 struct ti_softc *sc = if_getsoftc(ifp); 3498 struct ifreq *ifr = (struct ifreq *) data; 3499 struct ti_cmd_desc cmd; 3500 int mask, error = 0; 3501 3502 switch (command) { 3503 case SIOCSIFMTU: 3504 TI_LOCK(sc); 3505 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > TI_JUMBO_MTU) 3506 error = EINVAL; 3507 else { 3508 if_setmtu(ifp, ifr->ifr_mtu); 3509 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3510 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3511 ti_init_locked(sc); 3512 } 3513 } 3514 TI_UNLOCK(sc); 3515 break; 3516 case SIOCSIFFLAGS: 3517 TI_LOCK(sc); 3518 if (if_getflags(ifp) & IFF_UP) { 3519 /* 3520 * If only the state of the PROMISC flag changed, 3521 * then just use the 'set promisc mode' command 3522 * instead of reinitializing the entire NIC. Doing 3523 * a full re-init means reloading the firmware and 3524 * waiting for it to start up, which may take a 3525 * second or two. 3526 */ 3527 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 3528 if_getflags(ifp) & IFF_PROMISC && 3529 !(sc->ti_if_flags & IFF_PROMISC)) { 3530 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3531 TI_CMD_CODE_PROMISC_ENB, 0); 3532 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 3533 !(if_getflags(ifp) & IFF_PROMISC) && 3534 sc->ti_if_flags & IFF_PROMISC) { 3535 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 3536 TI_CMD_CODE_PROMISC_DIS, 0); 3537 } else 3538 ti_init_locked(sc); 3539 } else { 3540 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3541 ti_stop(sc); 3542 } 3543 } 3544 sc->ti_if_flags = if_getflags(ifp); 3545 TI_UNLOCK(sc); 3546 break; 3547 case SIOCADDMULTI: 3548 case SIOCDELMULTI: 3549 TI_LOCK(sc); 3550 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 3551 ti_setmulti(sc); 3552 TI_UNLOCK(sc); 3553 break; 3554 case SIOCSIFMEDIA: 3555 case SIOCGIFMEDIA: 3556 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 3557 break; 3558 case SIOCSIFCAP: 3559 TI_LOCK(sc); 3560 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3561 if ((mask & IFCAP_TXCSUM) != 0 && 3562 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 3563 if_togglecapenable(ifp, IFCAP_TXCSUM); 3564 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 3565 if_sethwassistbits(ifp, TI_CSUM_FEATURES, 0); 3566 else 3567 if_sethwassistbits(ifp, 0, TI_CSUM_FEATURES); 3568 } 3569 if ((mask & IFCAP_RXCSUM) != 0 && 3570 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 3571 if_togglecapenable(ifp, IFCAP_RXCSUM); 3572 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3573 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3574 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3575 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3576 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 3577 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 3578 if ((mask & (IFCAP_TXCSUM | IFCAP_RXCSUM | 3579 IFCAP_VLAN_HWTAGGING)) != 0) { 3580 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3581 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3582 ti_init_locked(sc); 3583 } 3584 } 3585 TI_UNLOCK(sc); 3586 VLAN_CAPABILITIES(ifp); 3587 break; 3588 default: 3589 error = ether_ioctl(ifp, command, data); 3590 break; 3591 } 3592 3593 return (error); 3594} 3595 3596static int 3597ti_open(struct cdev *dev, int flags, int fmt, struct thread *td) 3598{ 3599 struct ti_softc *sc; 3600 3601 sc = dev->si_drv1; 3602 if (sc == NULL) 3603 return (ENODEV); 3604 3605 TI_LOCK(sc); 3606 sc->ti_flags |= TI_FLAG_DEBUGING; 3607 TI_UNLOCK(sc); 3608 3609 return (0); 3610} 3611 3612static int 3613ti_close(struct cdev *dev, int flag, int fmt, struct thread *td) 3614{ 3615 struct ti_softc *sc; 3616 3617 sc = dev->si_drv1; 3618 if (sc == NULL) 3619 return (ENODEV); 3620 3621 TI_LOCK(sc); 3622 sc->ti_flags &= ~TI_FLAG_DEBUGING; 3623 TI_UNLOCK(sc); 3624 3625 return (0); 3626} 3627 3628/* 3629 * This ioctl routine goes along with the Tigon character device. 3630 */ 3631static int 3632ti_ioctl2(struct cdev *dev, u_long cmd, caddr_t addr, int flag, 3633 struct thread *td) 3634{ 3635 struct ti_softc *sc; 3636 int error; 3637 3638 sc = dev->si_drv1; 3639 if (sc == NULL) 3640 return (ENODEV); 3641 3642 error = 0; 3643 3644 switch (cmd) { 3645 case TIIOCGETSTATS: 3646 { 3647 struct ti_stats *outstats; 3648 3649 outstats = (struct ti_stats *)addr; 3650 3651 TI_LOCK(sc); 3652 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3653 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_POSTREAD); 3654 bcopy(&sc->ti_rdata.ti_info->ti_stats, outstats, 3655 sizeof(struct ti_stats)); 3656 bus_dmamap_sync(sc->ti_cdata.ti_gib_tag, 3657 sc->ti_cdata.ti_gib_map, BUS_DMASYNC_PREREAD); 3658 TI_UNLOCK(sc); 3659 break; 3660 } 3661 case TIIOCGETPARAMS: 3662 { 3663 struct ti_params *params; 3664 3665 params = (struct ti_params *)addr; 3666 3667 TI_LOCK(sc); 3668 params->ti_stat_ticks = sc->ti_stat_ticks; 3669 params->ti_rx_coal_ticks = sc->ti_rx_coal_ticks; 3670 params->ti_tx_coal_ticks = sc->ti_tx_coal_ticks; 3671 params->ti_rx_max_coal_bds = sc->ti_rx_max_coal_bds; 3672 params->ti_tx_max_coal_bds = sc->ti_tx_max_coal_bds; 3673 params->ti_tx_buf_ratio = sc->ti_tx_buf_ratio; 3674 params->param_mask = TI_PARAM_ALL; 3675 TI_UNLOCK(sc); 3676 break; 3677 } 3678 case TIIOCSETPARAMS: 3679 { 3680 struct ti_params *params; 3681 3682 params = (struct ti_params *)addr; 3683 3684 TI_LOCK(sc); 3685 if (params->param_mask & TI_PARAM_STAT_TICKS) { 3686 sc->ti_stat_ticks = params->ti_stat_ticks; 3687 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 3688 } 3689 3690 if (params->param_mask & TI_PARAM_RX_COAL_TICKS) { 3691 sc->ti_rx_coal_ticks = params->ti_rx_coal_ticks; 3692 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 3693 sc->ti_rx_coal_ticks); 3694 } 3695 3696 if (params->param_mask & TI_PARAM_TX_COAL_TICKS) { 3697 sc->ti_tx_coal_ticks = params->ti_tx_coal_ticks; 3698 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, 3699 sc->ti_tx_coal_ticks); 3700 } 3701 3702 if (params->param_mask & TI_PARAM_RX_COAL_BDS) { 3703 sc->ti_rx_max_coal_bds = params->ti_rx_max_coal_bds; 3704 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, 3705 sc->ti_rx_max_coal_bds); 3706 } 3707 3708 if (params->param_mask & TI_PARAM_TX_COAL_BDS) { 3709 sc->ti_tx_max_coal_bds = params->ti_tx_max_coal_bds; 3710 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, 3711 sc->ti_tx_max_coal_bds); 3712 } 3713 3714 if (params->param_mask & TI_PARAM_TX_BUF_RATIO) { 3715 sc->ti_tx_buf_ratio = params->ti_tx_buf_ratio; 3716 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, 3717 sc->ti_tx_buf_ratio); 3718 } 3719 TI_UNLOCK(sc); 3720 break; 3721 } 3722 case TIIOCSETTRACE: { 3723 ti_trace_type trace_type; 3724 3725 trace_type = *(ti_trace_type *)addr; 3726 3727 /* 3728 * Set tracing to whatever the user asked for. Setting 3729 * this register to 0 should have the effect of disabling 3730 * tracing. 3731 */ 3732 TI_LOCK(sc); 3733 CSR_WRITE_4(sc, TI_GCR_NIC_TRACING, trace_type); 3734 TI_UNLOCK(sc); 3735 break; 3736 } 3737 case TIIOCGETTRACE: { 3738 struct ti_trace_buf *trace_buf; 3739 uint32_t trace_start, cur_trace_ptr, trace_len; 3740 3741 trace_buf = (struct ti_trace_buf *)addr; 3742 3743 TI_LOCK(sc); 3744 trace_start = CSR_READ_4(sc, TI_GCR_NICTRACE_START); 3745 cur_trace_ptr = CSR_READ_4(sc, TI_GCR_NICTRACE_PTR); 3746 trace_len = CSR_READ_4(sc, TI_GCR_NICTRACE_LEN); 3747#if 0 3748 if_printf(sc->ti_ifp, "trace_start = %#x, cur_trace_ptr = %#x, " 3749 "trace_len = %d\n", trace_start, 3750 cur_trace_ptr, trace_len); 3751 if_printf(sc->ti_ifp, "trace_buf->buf_len = %d\n", 3752 trace_buf->buf_len); 3753#endif 3754 error = ti_copy_mem(sc, trace_start, min(trace_len, 3755 trace_buf->buf_len), (caddr_t)trace_buf->buf, 1, 1); 3756 if (error == 0) { 3757 trace_buf->fill_len = min(trace_len, 3758 trace_buf->buf_len); 3759 if (cur_trace_ptr < trace_start) 3760 trace_buf->cur_trace_ptr = 3761 trace_start - cur_trace_ptr; 3762 else 3763 trace_buf->cur_trace_ptr = 3764 cur_trace_ptr - trace_start; 3765 } else 3766 trace_buf->fill_len = 0; 3767 TI_UNLOCK(sc); 3768 break; 3769 } 3770 3771 /* 3772 * For debugging, five ioctls are needed: 3773 * ALT_ATTACH 3774 * ALT_READ_TG_REG 3775 * ALT_WRITE_TG_REG 3776 * ALT_READ_TG_MEM 3777 * ALT_WRITE_TG_MEM 3778 */ 3779 case ALT_ATTACH: 3780 /* 3781 * From what I can tell, Alteon's Solaris Tigon driver 3782 * only has one character device, so you have to attach 3783 * to the Tigon board you're interested in. This seems 3784 * like a not-so-good way to do things, since unless you 3785 * subsequently specify the unit number of the device 3786 * you're interested in every ioctl, you'll only be 3787 * able to debug one board at a time. 3788 */ 3789 break; 3790 case ALT_READ_TG_MEM: 3791 case ALT_WRITE_TG_MEM: 3792 { 3793 struct tg_mem *mem_param; 3794 uint32_t sram_end, scratch_end; 3795 3796 mem_param = (struct tg_mem *)addr; 3797 3798 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3799 sram_end = TI_END_SRAM_I; 3800 scratch_end = TI_END_SCRATCH_I; 3801 } else { 3802 sram_end = TI_END_SRAM_II; 3803 scratch_end = TI_END_SCRATCH_II; 3804 } 3805 3806 /* 3807 * For now, we'll only handle accessing regular SRAM, 3808 * nothing else. 3809 */ 3810 TI_LOCK(sc); 3811 if (mem_param->tgAddr >= TI_BEG_SRAM && 3812 mem_param->tgAddr + mem_param->len <= sram_end) { 3813 /* 3814 * In this instance, we always copy to/from user 3815 * space, so the user space argument is set to 1. 3816 */ 3817 error = ti_copy_mem(sc, mem_param->tgAddr, 3818 mem_param->len, mem_param->userAddr, 1, 3819 cmd == ALT_READ_TG_MEM ? 1 : 0); 3820 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH && 3821 mem_param->tgAddr <= scratch_end) { 3822 error = ti_copy_scratch(sc, mem_param->tgAddr, 3823 mem_param->len, mem_param->userAddr, 1, 3824 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_A); 3825 } else if (mem_param->tgAddr >= TI_BEG_SCRATCH_B_DEBUG && 3826 mem_param->tgAddr <= TI_BEG_SCRATCH_B_DEBUG) { 3827 if (sc->ti_hwrev == TI_HWREV_TIGON) { 3828 if_printf(sc->ti_ifp, 3829 "invalid memory range for Tigon I\n"); 3830 error = EINVAL; 3831 break; 3832 } 3833 error = ti_copy_scratch(sc, mem_param->tgAddr - 3834 TI_SCRATCH_DEBUG_OFF, mem_param->len, 3835 mem_param->userAddr, 1, 3836 cmd == ALT_READ_TG_MEM ? 1 : 0, TI_PROCESSOR_B); 3837 } else { 3838 if_printf(sc->ti_ifp, "memory address %#x len %d is " 3839 "out of supported range\n", 3840 mem_param->tgAddr, mem_param->len); 3841 error = EINVAL; 3842 } 3843 TI_UNLOCK(sc); 3844 break; 3845 } 3846 case ALT_READ_TG_REG: 3847 case ALT_WRITE_TG_REG: 3848 { 3849 struct tg_reg *regs; 3850 uint32_t tmpval; 3851 3852 regs = (struct tg_reg *)addr; 3853 3854 /* 3855 * Make sure the address in question isn't out of range. 3856 */ 3857 if (regs->addr > TI_REG_MAX) { 3858 error = EINVAL; 3859 break; 3860 } 3861 TI_LOCK(sc); 3862 if (cmd == ALT_READ_TG_REG) { 3863 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle, 3864 regs->addr, &tmpval, 1); 3865 regs->data = ntohl(tmpval); 3866#if 0 3867 if ((regs->addr == TI_CPU_STATE) 3868 || (regs->addr == TI_CPU_CTL_B)) { 3869 if_printf(sc->ti_ifp, "register %#x = %#x\n", 3870 regs->addr, tmpval); 3871 } 3872#endif 3873 } else { 3874 tmpval = htonl(regs->data); 3875 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 3876 regs->addr, &tmpval, 1); 3877 } 3878 TI_UNLOCK(sc); 3879 break; 3880 } 3881 default: 3882 error = ENOTTY; 3883 break; 3884 } 3885 return (error); 3886} 3887 3888static void 3889ti_watchdog(void *arg) 3890{ 3891 struct ti_softc *sc; 3892 if_t ifp; 3893 3894 sc = arg; 3895 TI_LOCK_ASSERT(sc); 3896 callout_reset(&sc->ti_watchdog, hz, ti_watchdog, sc); 3897 if (sc->ti_timer == 0 || --sc->ti_timer > 0) 3898 return; 3899 3900 /* 3901 * When we're debugging, the chip is often stopped for long periods 3902 * of time, and that would normally cause the watchdog timer to fire. 3903 * Since that impedes debugging, we don't want to do that. 3904 */ 3905 if (sc->ti_flags & TI_FLAG_DEBUGING) 3906 return; 3907 3908 ifp = sc->ti_ifp; 3909 if_printf(ifp, "watchdog timeout -- resetting\n"); 3910 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3911 ti_init_locked(sc); 3912 3913 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3914} 3915 3916/* 3917 * Stop the adapter and free any mbufs allocated to the 3918 * RX and TX lists. 3919 */ 3920static void 3921ti_stop(struct ti_softc *sc) 3922{ 3923 if_t ifp; 3924 struct ti_cmd_desc cmd; 3925 3926 TI_LOCK_ASSERT(sc); 3927 3928 ifp = sc->ti_ifp; 3929 3930 /* Disable host interrupts. */ 3931 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 3932 /* 3933 * Tell firmware we're shutting down. 3934 */ 3935 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 3936 3937 /* Halt and reinitialize. */ 3938 if (ti_chipinit(sc) == 0) { 3939 ti_mem_zero(sc, 0x2000, 0x100000 - 0x2000); 3940 /* XXX ignore init errors. */ 3941 ti_chipinit(sc); 3942 } 3943 3944 /* Free the RX lists. */ 3945 ti_free_rx_ring_std(sc); 3946 3947 /* Free jumbo RX list. */ 3948 ti_free_rx_ring_jumbo(sc); 3949 3950 /* Free mini RX list. */ 3951 ti_free_rx_ring_mini(sc); 3952 3953 /* Free TX buffers. */ 3954 ti_free_tx_ring(sc); 3955 3956 sc->ti_ev_prodidx.ti_idx = 0; 3957 sc->ti_return_prodidx.ti_idx = 0; 3958 sc->ti_tx_considx.ti_idx = 0; 3959 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 3960 3961 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 3962 callout_stop(&sc->ti_watchdog); 3963} 3964 3965/* 3966 * Stop all chip I/O so that the kernel's probe routines don't 3967 * get confused by errant DMAs when rebooting. 3968 */ 3969static int 3970ti_shutdown(device_t dev) 3971{ 3972 struct ti_softc *sc; 3973 3974 sc = device_get_softc(dev); 3975 TI_LOCK(sc); 3976 ti_chipinit(sc); 3977 TI_UNLOCK(sc); 3978 3979 return (0); 3980} 3981 3982static void 3983ti_sysctl_node(struct ti_softc *sc) 3984{ 3985 struct sysctl_ctx_list *ctx; 3986 struct sysctl_oid_list *child; 3987 char tname[32]; 3988 3989 ctx = device_get_sysctl_ctx(sc->ti_dev); 3990 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ti_dev)); 3991 3992 /* Use DAC */ 3993 sc->ti_dac = 1; 3994 snprintf(tname, sizeof(tname), "dev.ti.%d.dac", 3995 device_get_unit(sc->ti_dev)); 3996 TUNABLE_INT_FETCH(tname, &sc->ti_dac); 3997 3998 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_coal_ticks", CTLFLAG_RW, 3999 &sc->ti_rx_coal_ticks, 0, "Receive coalcesced ticks"); 4000 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_max_coal_bds", CTLFLAG_RW, 4001 &sc->ti_rx_max_coal_bds, 0, "Receive max coalcesced BDs"); 4002 4003 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_coal_ticks", CTLFLAG_RW, 4004 &sc->ti_tx_coal_ticks, 0, "Send coalcesced ticks"); 4005 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_max_coal_bds", CTLFLAG_RW, 4006 &sc->ti_tx_max_coal_bds, 0, "Send max coalcesced BDs"); 4007 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_buf_ratio", CTLFLAG_RW, 4008 &sc->ti_tx_buf_ratio, 0, 4009 "Ratio of NIC memory devoted to TX buffer"); 4010 4011 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stat_ticks", CTLFLAG_RW, 4012 &sc->ti_stat_ticks, 0, 4013 "Number of clock ticks for statistics update interval"); 4014 4015 /* Pull in device tunables. */ 4016 sc->ti_rx_coal_ticks = 170; 4017 resource_int_value(device_get_name(sc->ti_dev), 4018 device_get_unit(sc->ti_dev), "rx_coal_ticks", 4019 &sc->ti_rx_coal_ticks); 4020 sc->ti_rx_max_coal_bds = 64; 4021 resource_int_value(device_get_name(sc->ti_dev), 4022 device_get_unit(sc->ti_dev), "rx_max_coal_bds", 4023 &sc->ti_rx_max_coal_bds); 4024 4025 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 4026 resource_int_value(device_get_name(sc->ti_dev), 4027 device_get_unit(sc->ti_dev), "tx_coal_ticks", 4028 &sc->ti_tx_coal_ticks); 4029 sc->ti_tx_max_coal_bds = 32; 4030 resource_int_value(device_get_name(sc->ti_dev), 4031 device_get_unit(sc->ti_dev), "tx_max_coal_bds", 4032 &sc->ti_tx_max_coal_bds); 4033 sc->ti_tx_buf_ratio = 21; 4034 resource_int_value(device_get_name(sc->ti_dev), 4035 device_get_unit(sc->ti_dev), "tx_buf_ratio", 4036 &sc->ti_tx_buf_ratio); 4037 4038 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 4039 resource_int_value(device_get_name(sc->ti_dev), 4040 device_get_unit(sc->ti_dev), "stat_ticks", 4041 &sc->ti_stat_ticks); 4042} 4043