1/*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * Register definitions for the SiS 900 and SiS 7016 chipsets. The 37 * 7016 is actually an older chip and some of its registers differ 38 * from the 900, however the core operational registers are the same: 39 * the differences lie in the OnNow/Wake on LAN stuff which we don't 40 * use anyway. The 7016 needs an external MII compliant PHY while the 41 * SiS 900 has one built in. All registers are 32-bits wide. 42 */ 43 44/* Registers common to SiS 900 and SiS 7016 */ 45#define SIS_CSR 0x00 46#define SIS_CFG 0x04 47#define SIS_EECTL 0x08 48#define SIS_PCICTL 0x0C 49#define SIS_ISR 0x10 50#define SIS_IMR 0x14 51#define SIS_IER 0x18 52#define SIS_PHYCTL 0x1C 53#define SIS_TX_LISTPTR 0x20 54#define SIS_TX_CFG 0x24 55#define SIS_RX_LISTPTR 0x30 56#define SIS_RX_CFG 0x34 57#define SIS_FLOWCTL 0x38 58#define SIS_RXFILT_CTL 0x48 59#define SIS_RXFILT_DATA 0x4C 60#define SIS_PWRMAN_CTL 0xB0 61#define SIS_PWERMAN_WKUP_EVENT 0xB4 62#define SIS_WKUP_FRAME_CRC 0xBC 63#define SIS_WKUP_FRAME_MASK0 0xC0 64#define SIS_WKUP_FRAME_MASKXX 0xEC 65 66/* SiS 7016 specific registers */ 67#define SIS_SILICON_REV 0x5C 68#define SIS_MIB_CTL0 0x60 69#define SIS_MIB_CTL1 0x64 70#define SIS_MIB_CTL2 0x68 71#define SIS_MIB_CTL3 0x6C 72#define SIS_MIB 0x80 73#define SIS_LINKSTS 0xA0 74#define SIS_TIMEUNIT 0xA4 75#define SIS_GPIO 0xB8 76 77/* NS DP83815/6 registers */ 78#define NS_IHR 0x1C 79#define NS_CLKRUN 0x3C 80#define NS_WCSR 0x40 81#define NS_SRR 0x58 82#define NS_BMCR 0x80 83#define NS_BMSR 0x84 84#define NS_PHYIDR1 0x88 85#define NS_PHYIDR2 0x8C 86#define NS_ANAR 0x90 87#define NS_ANLPAR 0x94 88#define NS_ANER 0x98 89#define NS_ANNPTR 0x9C 90 91#define NS_PHY_CR 0xE4 92#define NS_PHY_10BTSCR 0xE8 93#define NS_PHY_PAGE 0xCC 94#define NS_PHY_EXTCFG 0xF0 95#define NS_PHY_DSPCFG 0xF4 96#define NS_PHY_SDCFG 0xF8 97#define NS_PHY_TDATA 0xFC 98 99#define NS_CLKRUN_PMESTS 0x00008000 100#define NS_CLKRUN_PMEENB 0x00000100 101#define NS_CLNRUN_CLKRUN_ENB 0x00000001 102 103#define NS_WCSR_WAKE_PHYINTR 0x00000001 104#define NS_WCSR_WAKE_UCAST 0x00000002 105#define NS_WCSR_WAKE_MCAST 0x00000004 106#define NS_WCSR_WAKE_BCAST 0x00000008 107#define NS_WCSR_WAKE_ARP 0x00000010 108#define NS_WCSR_WAKE_PATTERN0 0x00000020 109#define NS_WCSR_WAKE_PATTERN1 0x00000040 110#define NS_WCSR_WAKE_PATTERN2 0x00000080 111#define NS_WCSR_WAKE_PATTERN3 0x00000100 112#define NS_WCSR_WAKE_MAGIC 0x00000200 113#define NS_WCSR_WAKE_MAGIC_SEC 0x00000400 114#define NS_WCSR_DET_MAGIC_SECH 0x00100000 115#define NS_WCSR_DET_PHYINTR 0x00400000 116#define NS_WCSR_DET_UCAST 0x00800000 117#define NS_WCSR_DET_MCAST 0x01000000 118#define NS_WCSR_DET_BCAST 0x02000000 119#define NS_WCSR_DET_ARP 0x04000000 120#define NS_WCSR_DET_PATTERN0 0x08000000 121#define NS_WCSR_DET_PATTERN1 0x10000000 122#define NS_WCSR_DET_PATTERN2 0x20000000 123#define NS_WCSR_DET_PATTERN3 0x40000000 124#define NS_WCSR_DET_MAGIC 0x80000000 125 126/* NS silicon revisions */ 127#define NS_SRR_15C 0x302 128#define NS_SRR_15D 0x403 129#define NS_SRR_16A 0x505 130 131#define SIS_CSR_TX_ENABLE 0x00000001 132#define SIS_CSR_TX_DISABLE 0x00000002 133#define SIS_CSR_RX_ENABLE 0x00000004 134#define SIS_CSR_RX_DISABLE 0x00000008 135#define SIS_CSR_TX_RESET 0x00000010 136#define SIS_CSR_RX_RESET 0x00000020 137#define SIS_CSR_SOFTINTR 0x00000080 138#define SIS_CSR_RESET 0x00000100 139#define SIS_CSR_ACCESS_MODE 0x00000200 140#define SIS_CSR_RELOAD 0x00000400 141 142#define SIS_CFG_BIGENDIAN 0x00000001 143#define SIS_CFG_PERR_DETECT 0x00000008 144#define SIS_CFG_DEFER_DISABLE 0x00000010 145#define SIS_CFG_OUTOFWIN_TIMER 0x00000020 146#define SIS_CFG_SINGLE_BACKOFF 0x00000040 147#define SIS_CFG_PCIREQ_ALG 0x00000080 148#define SIS_CFG_FAIR_BACKOFF 0x00000200 /* 635 & 900B Specific */ 149#define SIS_CFG_RND_CNT 0x00000400 /* 635 & 900B Specific */ 150#define SIS_CFG_EDB_MASTER_EN 0x00002000 151 152#define SIS_EECTL_DIN 0x00000001 153#define SIS_EECTL_DOUT 0x00000002 154#define SIS_EECTL_CLK 0x00000004 155#define SIS_EECTL_CSEL 0x00000008 156 157#define SIS_MII_CLK 0x00000040 158#define SIS_MII_DIR 0x00000020 159#define SIS_MII_DATA 0x00000010 160 161#define SIS_EECMD_WRITE 0x140 162#define SIS_EECMD_READ 0x180 163#define SIS_EECMD_ERASE 0x1c0 164 165/* 166 * EEPROM Commands for SiS96x 167 * chipsets. 168 */ 169#define SIS_EECMD_REQ 0x00000400 170#define SIS_EECMD_DONE 0x00000200 171#define SIS_EECMD_GNT 0x00000100 172 173#define SIS_EE_NODEADDR 0x8 174#define NS_EE_NODEADDR 0x6 175 176#define SIS_PCICTL_SRAMADDR 0x0000001F 177#define SIS_PCICTL_RAMTSTENB 0x00000020 178#define SIS_PCICTL_TXTSTENB 0x00000040 179#define SIS_PCICTL_RXTSTENB 0x00000080 180#define SIS_PCICTL_BMTSTENB 0x00000200 181#define SIS_PCICTL_RAMADDR 0x001F0000 182#define SIS_PCICTL_ROMTIME 0x0F000000 183#define SIS_PCICTL_DISCTEST 0x40000000 184 185#define SIS_ISR_RX_OK 0x00000001 186#define SIS_ISR_RX_DESC_OK 0x00000002 187#define SIS_ISR_RX_ERR 0x00000004 188#define SIS_ISR_RX_EARLY 0x00000008 189#define SIS_ISR_RX_IDLE 0x00000010 190#define SIS_ISR_RX_OFLOW 0x00000020 191#define SIS_ISR_TX_OK 0x00000040 192#define SIS_ISR_TX_DESC_OK 0x00000080 193#define SIS_ISR_TX_ERR 0x00000100 194#define SIS_ISR_TX_IDLE 0x00000200 195#define SIS_ISR_TX_UFLOW 0x00000400 196#define SIS_ISR_SOFTINTR 0x00000800 197#define SIS_ISR_HIBITS 0x00008000 198#define SIS_ISR_RX_FIFO_OFLOW 0x00010000 199#define SIS_ISR_TGT_ABRT 0x00100000 200#define SIS_ISR_BM_ABRT 0x00200000 201#define SIS_ISR_SYSERR 0x00400000 202#define SIS_ISR_PARITY_ERR 0x00800000 203#define SIS_ISR_RX_RESET_DONE 0x01000000 204#define SIS_ISR_TX_RESET_DONE 0x02000000 205#define SIS_ISR_TX_PAUSE_START 0x04000000 206#define SIS_ISR_TX_PAUSE_DONE 0x08000000 207#define SIS_ISR_WAKE_EVENT 0x10000000 208 209#define SIS_IMR_RX_OK 0x00000001 210#define SIS_IMR_RX_DESC_OK 0x00000002 211#define SIS_IMR_RX_ERR 0x00000004 212#define SIS_IMR_RX_EARLY 0x00000008 213#define SIS_IMR_RX_IDLE 0x00000010 214#define SIS_IMR_RX_OFLOW 0x00000020 215#define SIS_IMR_TX_OK 0x00000040 216#define SIS_IMR_TX_DESC_OK 0x00000080 217#define SIS_IMR_TX_ERR 0x00000100 218#define SIS_IMR_TX_IDLE 0x00000200 219#define SIS_IMR_TX_UFLOW 0x00000400 220#define SIS_IMR_SOFTINTR 0x00000800 221#define SIS_IMR_HIBITS 0x00008000 222#define SIS_IMR_RX_FIFO_OFLOW 0x00010000 223#define SIS_IMR_TGT_ABRT 0x00100000 224#define SIS_IMR_BM_ABRT 0x00200000 225#define SIS_IMR_SYSERR 0x00400000 226#define SIS_IMR_PARITY_ERR 0x00800000 227#define SIS_IMR_RX_RESET_DONE 0x01000000 228#define SIS_IMR_TX_RESET_DONE 0x02000000 229#define SIS_IMR_TX_PAUSE_START 0x04000000 230#define SIS_IMR_TX_PAUSE_DONE 0x08000000 231#define SIS_IMR_WAKE_EVENT 0x10000000 232 233#define SIS_INTRS \ 234 (SIS_IMR_RX_OFLOW|SIS_IMR_TX_UFLOW|SIS_IMR_TX_OK|\ 235 SIS_IMR_TX_IDLE|SIS_IMR_RX_OK|SIS_IMR_RX_ERR|\ 236 SIS_IMR_RX_IDLE|\ 237 SIS_IMR_SYSERR) 238 239#define SIS_IER_INTRENB 0x00000001 240 241#define SIS_PHYCTL_ACCESS 0x00000010 242#define SIS_PHYCTL_OP 0x00000020 243#define SIS_PHYCTL_REGADDR 0x000007C0 244#define SIS_PHYCTL_PHYADDR 0x0000F800 245#define SIS_PHYCTL_PHYDATA 0xFFFF0000 246 247#define SIS_PHYOP_READ 0x00000020 248#define SIS_PHYOP_WRITE 0x00000000 249 250#define SIS_TXCFG_DRAIN_THRESH 0x0000003F /* 32-byte units */ 251#define SIS_TXCFG_FILL_THRESH 0x00003F00 /* 32-byte units */ 252#define SIS_TXCFG_DMABURST 0x00700000 253#define SIS_TXCFG_AUTOPAD 0x10000000 254#define SIS_TXCFG_LOOPBK 0x20000000 255#define SIS_TXCFG_IGN_HBEAT 0x40000000 256#define SIS_TXCFG_IGN_CARR 0x80000000 257 258#define SIS_TXCFG_DRAIN(x) (((x) >> 5) & SIS_TXCFG_DRAIN_THRESH) 259#define SIS_TXCFG_FILL(x) ((((x) >> 5) << 8) & SIS_TXCFG_FILL_THRESH) 260 261#define SIS_TXDMA_512BYTES 0x00000000 262#define SIS_TXDMA_4BYTES 0x00100000 263#define SIS_TXDMA_8BYTES 0x00200000 264#define SIS_TXDMA_16BYTES 0x00300000 265#define SIS_TXDMA_32BYTES 0x00400000 266#define SIS_TXDMA_64BYTES 0x00500000 267#define SIS_TXDMA_128BYTES 0x00600000 268#define SIS_TXDMA_256BYTES 0x00700000 269 270#define SIS_TXCFG_100 \ 271 (SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\ 272 SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536)) 273 274#define SIS_TXCFG_10 \ 275 (SIS_TXDMA_32BYTES|SIS_TXCFG_AUTOPAD|\ 276 SIS_TXCFG_FILL(64)|SIS_TXCFG_DRAIN(1536)) 277 278#define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */ 279#define SIS_TXCFG_MPII03D 0x00040000 /* "Must be 1" */ 280#define SIS_RXCFG_DMABURST 0x00700000 281#define SIS_RXCFG_RX_JABBER 0x08000000 282#define SIS_RXCFG_RX_TXPKTS 0x10000000 283#define SIS_RXCFG_RX_RUNTS 0x40000000 284#define SIS_RXCFG_RX_GIANTS 0x80000000 285 286#define SIS_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & SIS_RXCFG_DRAIN_THRESH) 287 288#define SIS_RXDMA_512BYTES 0x00000000 289#define SIS_RXDMA_4BYTES 0x00100000 290#define SIS_RXDMA_8BYTES 0x00200000 291#define SIS_RXDMA_16BYTES 0x00300000 292#define SIS_RXDMA_32BYTES 0x00400000 293#define SIS_RXDMA_64BYTES 0x00500000 294#define SIS_RXDMA_128BYTES 0x00600000 295#define SIS_RXDMA_256BYTES 0x00700000 296 297#define SIS_RXCFG256 \ 298 (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_256BYTES) 299#define SIS_RXCFG64 \ 300 (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_64BYTES) 301 302#define SIS_RXFILTCTL_ADDR 0x000F0000 303#define NS_RXFILTCTL_MCHASH 0x00200000 304#define NS_RXFILTCTL_ARP 0x00400000 305#define NS_RXFILTCTL_PERFECT 0x08000000 306#define SIS_RXFILTCTL_ALLPHYS 0x10000000 307#define SIS_RXFILTCTL_ALLMULTI 0x20000000 308#define SIS_RXFILTCTL_BROAD 0x40000000 309#define SIS_RXFILTCTL_ENABLE 0x80000000 310 311#define SIS_FILTADDR_PAR0 0x00000000 312#define SIS_FILTADDR_PAR1 0x00010000 313#define SIS_FILTADDR_PAR2 0x00020000 314#define SIS_FILTADDR_MAR0 0x00040000 315#define SIS_FILTADDR_MAR1 0x00050000 316#define SIS_FILTADDR_MAR2 0x00060000 317#define SIS_FILTADDR_MAR3 0x00070000 318#define SIS_FILTADDR_MAR4 0x00080000 319#define SIS_FILTADDR_MAR5 0x00090000 320#define SIS_FILTADDR_MAR6 0x000A0000 321#define SIS_FILTADDR_MAR7 0x000B0000 322 323#define NS_FILTADDR_PAR0 0x00000000 324#define NS_FILTADDR_PAR1 0x00000002 325#define NS_FILTADDR_PAR2 0x00000004 326 327#define NS_FILTADDR_FMEM_LO 0x00000200 328#define NS_FILTADDR_FMEM_HI 0x000003FE 329 330#define SIS_PWRMAN_WOL_LINK_OFF 0x00000001 331#define SIS_PWRMAN_WOL_LINK_ON 0x00000002 332#define SIS_PWRMAN_WOL_MAGIC 0x00000400 333 334/* 335 * TX/RX DMA descriptor structures. 336 */ 337struct sis_desc { 338 /* SiS hardware descriptor section */ 339 uint32_t sis_next; 340 volatile uint32_t sis_cmdsts; 341 volatile uint32_t sis_ptr; 342}; 343 344#define SIS_CMDSTS_BUFLEN 0x00000FFF 345#define SIS_CMDSTS_PKT_OK 0x08000000 346#define SIS_CMDSTS_CRC 0x10000000 347#define SIS_CMDSTS_INTR 0x20000000 348#define SIS_CMDSTS_MORE 0x40000000 349#define SIS_CMDSTS_OWN 0x80000000 350 351#define SIS_RXSTAT_COLL 0x00010000 352#define SIS_RXSTAT_LOOPBK 0x00020000 353#define SIS_RXSTAT_ALIGNERR 0x00040000 354#define SIS_RXSTAT_CRCERR 0x00080000 355#define SIS_RXSTAT_SYMBOLERR 0x00100000 356#define SIS_RXSTAT_RUNT 0x00200000 357#define SIS_RXSTAT_GIANT 0x00400000 358#define SIS_RXSTAT_DSTCLASS 0x01800000 359#define SIS_RXSTAT_OVERRUN 0x02000000 360#define SIS_RXSTAT_RX_ABORT 0x04000000 361 362#define SIS_RXSTAT_ERROR(x) \ 363 ((x) & (SIS_RXSTAT_RX_ABORT | SIS_RXSTAT_OVERRUN | \ 364 SIS_RXSTAT_GIANT | SIS_RXSTAT_SYMBOLERR | SIS_RXSTAT_RUNT | \ 365 SIS_RXSTAT_CRCERR | SIS_RXSTAT_ALIGNERR)) 366 367#define SIS_DSTCLASS_REJECT 0x00000000 368#define SIS_DSTCLASS_UNICAST 0x00800000 369#define SIS_DSTCLASS_MULTICAST 0x01000000 370#define SIS_DSTCLASS_BROADCAST 0x02000000 371 372#define SIS_TXSTAT_COLLCNT 0x000F0000 373#define SIS_TXSTAT_EXCESSCOLLS 0x00100000 374#define SIS_TXSTAT_OUTOFWINCOLL 0x00200000 375#define SIS_TXSTAT_EXCESS_DEFER 0x00400000 376#define SIS_TXSTAT_DEFERED 0x00800000 377#define SIS_TXSTAT_CARR_LOST 0x01000000 378#define SIS_TXSTAT_UNDERRUN 0x02000000 379#define SIS_TXSTAT_TX_ABORT 0x04000000 380 381#define SIS_DESC_ALIGN 16 382#define SIS_RX_BUF_ALIGN 4 383#define SIS_MAXTXSEGS 16 384#define SIS_RX_LIST_CNT 64 385#define SIS_TX_LIST_CNT 128 386 387#define SIS_RX_LIST_SZ SIS_RX_LIST_CNT * sizeof(struct sis_desc) 388#define SIS_TX_LIST_SZ SIS_TX_LIST_CNT * sizeof(struct sis_desc) 389 390#define SIS_ADDR_LO(x) ((uint64_t) (x) & 0xffffffff) 391#define SIS_ADDR_HI(x) ((uint64_t) (x) >> 32) 392 393#define SIS_RX_RING_ADDR(sc, i) \ 394 ((sc)->sis_rx_paddr + sizeof(struct sis_desc) * (i)) 395#define SIS_TX_RING_ADDR(sc, i) \ 396 ((sc)->sis_tx_paddr + sizeof(struct sis_desc) * (i)) 397 398#define SIS_INC(x, y) (x) = (x + 1) % (y) 399 400/* 401 * SiS PCI vendor ID. 402 */ 403#define SIS_VENDORID 0x1039 404 405/* 406 * SiS PCI device IDs 407 */ 408#define SIS_DEVICEID_900 0x0900 409#define SIS_DEVICEID_7016 0x7016 410 411/* 412 * SiS 900 PCI revision codes. 413 */ 414#define SIS_REV_900B 0x0003 415#define SIS_REV_630A 0x0080 416#define SIS_REV_630E 0x0081 417#define SIS_REV_630S 0x0082 418#define SIS_REV_630EA1 0x0083 419#define SIS_REV_630ET 0x0084 420#define SIS_REV_635 0x0090 421#define SIS_REV_96x 0x0091 422 423/* 424 * NatSemi vendor ID 425 */ 426#define NS_VENDORID 0x100B 427 428/* 429 * DP83815 device ID 430 */ 431#define NS_DEVICEID_DP83815 0x0020 432 433struct sis_type { 434 uint16_t sis_vid; 435 uint16_t sis_did; 436 const char *sis_name; 437}; 438 439#define SIS_TYPE_900 1 440#define SIS_TYPE_7016 2 441#define SIS_TYPE_83815 3 442 443struct sis_txdesc { 444 struct mbuf *tx_m; 445 bus_dmamap_t tx_dmamap; 446}; 447 448struct sis_rxdesc { 449 struct mbuf *rx_m; 450 bus_dmamap_t rx_dmamap; 451 struct sis_desc *rx_desc; 452}; 453 454struct sis_softc { 455 if_t sis_ifp; /* interface info */ 456 struct resource *sis_res[2]; 457 void *sis_intrhand; 458 device_t sis_dev; 459 device_t sis_miibus; 460 uint8_t sis_type; 461 uint8_t sis_rev; 462 uint32_t sis_flags; 463#define SIS_FLAG_MANUAL_PAD 0x0800 464#define SIS_FLAG_LINK 0x8000 465 int sis_manual_pad; 466 uint32_t sis_srr; 467 struct sis_desc *sis_rx_list; 468 struct sis_desc *sis_tx_list; 469 bus_dma_tag_t sis_rx_list_tag; 470 bus_dmamap_t sis_rx_list_map; 471 bus_dma_tag_t sis_tx_list_tag; 472 bus_dmamap_t sis_tx_list_map; 473 bus_dma_tag_t sis_parent_tag; 474 bus_dma_tag_t sis_rx_tag; 475 bus_dmamap_t sis_rx_sparemap; 476 bus_dma_tag_t sis_tx_tag; 477 struct sis_rxdesc sis_rxdesc[SIS_RX_LIST_CNT]; 478 struct sis_txdesc sis_txdesc[SIS_TX_LIST_CNT]; 479 int sis_tx_prod; 480 int sis_tx_cons; 481 int sis_tx_cnt; 482 int sis_rx_cons; 483 bus_addr_t sis_rx_paddr; 484 bus_addr_t sis_tx_paddr; 485 struct callout sis_stat_ch; 486 int sis_watchdog_timer; 487 int sis_if_flags; 488#ifdef DEVICE_POLLING 489 int rxcycles; 490#endif 491 struct mtx sis_mtx; 492}; 493 494#define SIS_TIMEOUT 1000 495#define ETHER_ALIGN 2 496#define SIS_RXLEN 1536 497#define SIS_MIN_FRAMELEN 60 498 499/* 500 * PCI low memory base and low I/O base register, and 501 * other PCI registers. 502 */ 503 504#define SIS_PCI_VENDOR_ID 0x00 505#define SIS_PCI_DEVICE_ID 0x02 506#define SIS_PCI_COMMAND 0x04 507#define SIS_PCI_STATUS 0x06 508#define SIS_PCI_REVID 0x08 509#define SIS_PCI_CLASSCODE 0x09 510#define SIS_PCI_CACHELEN 0x0C 511#define SIS_PCI_LATENCY_TIMER 0x0D 512#define SIS_PCI_HEADER_TYPE 0x0E 513#define SIS_PCI_LOIO 0x10 514#define SIS_PCI_LOMEM 0x14 515#define SIS_PCI_BIOSROM 0x30 516#define SIS_PCI_INTLINE 0x3C 517#define SIS_PCI_INTPIN 0x3D 518#define SIS_PCI_MINGNT 0x3E 519#define SIS_PCI_MINLAT 0x0F 520#define SIS_PCI_RESETOPT 0x48 521#define SIS_PCI_EEPROM_DATA 0x4C 522 523/* power management registers */ 524#define SIS_PCI_CAPID 0x50 /* 8 bits */ 525#define SIS_PCI_NEXTPTR 0x51 /* 8 bits */ 526#define SIS_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 527#define SIS_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 528 529#define SIS_PSTATE_MASK 0x0003 530#define SIS_PSTATE_D0 0x0000 531#define SIS_PSTATE_D1 0x0001 532#define SIS_PSTATE_D2 0x0002 533#define SIS_PSTATE_D3 0x0003 534#define SIS_PME_EN 0x0010 535#define SIS_PME_STATUS 0x8000 536