1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 */ 32 33#ifndef _SYS_SIENA_FLASH_H 34#define _SYS_SIENA_FLASH_H 35 36#pragma pack(1) 37 38/* Fixed locations near the start of flash (which may be in the internal PHY 39 * firmware header) point to the boot header. 40 * 41 * - parsed by MC boot ROM and firmware 42 * - reserved (but not parsed) by PHY firmware 43 * - opaque to driver 44 */ 45 46#define SIENA_MC_BOOT_PHY_FW_HDR_LEN (0x20) 47 48#define SIENA_MC_BOOT_PTR_LOCATION (0x18) /* First thing we try to boot */ 49#define SIENA_MC_BOOT_ALT_PTR_LOCATION (0x1c) /* Alternative if that fails */ 50 51#define SIENA_MC_BOOT_HDR_LEN (0x200) 52 53#define SIENA_MC_BOOT_MAGIC (0x51E4A001) 54#define SIENA_MC_BOOT_VERSION (1) 55 56/*Structures supporting an arbitrary number of binary blobs in the flash image 57 intended to house code and tables for the satellite cpus*/ 58/*thanks to random.org for:*/ 59#define BLOBS_HEADER_MAGIC (0xBDA3BBD4) 60#define BLOB_HEADER_MAGIC (0xA1478A91) 61 62typedef struct blobs_hdr_s { /* GENERATED BY scripts/genfwdef */ 63 efx_dword_t magic; 64 efx_dword_t no_of_blobs; 65} blobs_hdr_t; 66 67typedef struct blob_hdr_s { /* GENERATED BY scripts/genfwdef */ 68 efx_dword_t magic; 69 efx_dword_t cpu_type; 70 efx_dword_t build_variant; 71 efx_dword_t offset; 72 efx_dword_t length; 73 efx_dword_t checksum; 74} blob_hdr_t; 75 76#define BLOB_CPU_TYPE_TXDI_TEXT (0) 77#define BLOB_CPU_TYPE_RXDI_TEXT (1) 78#define BLOB_CPU_TYPE_TXDP_TEXT (2) 79#define BLOB_CPU_TYPE_RXDP_TEXT (3) 80#define BLOB_CPU_TYPE_RXHRSL_HR_LUT (4) 81#define BLOB_CPU_TYPE_RXHRSL_HR_LUT_CFG (5) 82#define BLOB_CPU_TYPE_TXHRSL_HR_LUT (6) 83#define BLOB_CPU_TYPE_TXHRSL_HR_LUT_CFG (7) 84#define BLOB_CPU_TYPE_RXHRSL_HR_PGM (8) 85#define BLOB_CPU_TYPE_RXHRSL_SL_PGM (9) 86#define BLOB_CPU_TYPE_TXHRSL_HR_PGM (10) 87#define BLOB_CPU_TYPE_TXHRSL_SL_PGM (11) 88#define BLOB_CPU_TYPE_RXDI_VTBL0 (12) 89#define BLOB_CPU_TYPE_TXDI_VTBL0 (13) 90#define BLOB_CPU_TYPE_RXDI_VTBL1 (14) 91#define BLOB_CPU_TYPE_TXDI_VTBL1 (15) 92#define BLOB_CPU_TYPE_DUMPSPEC (32) 93#define BLOB_CPU_TYPE_MC_XIP (33) 94 95#define BLOB_CPU_TYPE_INVALID (31) 96 97/* 98 * The upper four bits of the CPU type field specify the compression 99 * algorithm used for this blob. 100 */ 101#define BLOB_COMPRESSION_MASK (0xf0000000) 102#define BLOB_CPU_TYPE_MASK (0x0fffffff) 103 104#define BLOB_COMPRESSION_NONE (0x00000000) /* Stored as is */ 105#define BLOB_COMPRESSION_LZ (0x10000000) /* see lib/lzdecoder.c */ 106 107typedef struct siena_mc_boot_hdr_s { /* GENERATED BY scripts/genfwdef */ 108 efx_dword_t magic; /* = SIENA_MC_BOOT_MAGIC */ 109 efx_word_t hdr_version; /* this structure definition is version 1 */ 110 efx_byte_t board_type; 111 efx_byte_t firmware_version_a; 112 efx_byte_t firmware_version_b; 113 efx_byte_t firmware_version_c; 114 efx_word_t checksum; /* of whole header area + firmware image */ 115 efx_word_t firmware_version_d; 116 efx_byte_t mcfw_subtype; 117 efx_byte_t generation; /* MC (Medford and later): MC partition generation when */ 118 /* written to NVRAM. */ 119 /* MUM & SUC images: subtype. */ 120 /* (Otherwise set to 0) */ 121 efx_dword_t firmware_text_offset; /* offset to firmware .text */ 122 efx_dword_t firmware_text_size; /* length of firmware .text, in bytes */ 123 efx_dword_t firmware_data_offset; /* offset to firmware .data */ 124 efx_dword_t firmware_data_size; /* length of firmware .data, in bytes */ 125 efx_byte_t spi_rate; /* SPI rate for reading image, 0 is BootROM default */ 126 efx_byte_t spi_phase_adj; /* SPI SDO/SCL phase adjustment, 0 is default (no adj) */ 127 efx_word_t xpm_sector; /* XPM (MEDFORD and later): The sector that contains */ 128 /* the key, or 0xffff if unsigned. (Otherwise set to 0) */ 129 efx_byte_t mumfw_subtype; /* MUM & SUC images: subtype. (Otherwise set to 0) */ 130 efx_byte_t reserved_b[3]; /* (set to 0) */ 131 efx_dword_t security_level; /* This number increases every time a serious security flaw */ 132 /* is fixed. A secure NIC may not downgrade to any image */ 133 /* with a lower security level than the current image. */ 134 /* Note: The number in this header should only be used for */ 135 /* determining the level of new images, not to determine */ 136 /* the level of the current image as this header is not */ 137 /* protected by a CMAC. */ 138 efx_dword_t reserved_c[5]; /* (set to 0) */ 139} siena_mc_boot_hdr_t; 140 141#define SIENA_MC_BOOT_HDR_PADDING \ 142 (SIENA_MC_BOOT_HDR_LEN - sizeof(siena_mc_boot_hdr_t)) 143 144#define SIENA_MC_STATIC_CONFIG_MAGIC (0xBDCF5555) 145#define SIENA_MC_STATIC_CONFIG_VERSION (0) 146 147typedef struct siena_mc_static_config_hdr_s { /* GENERATED BY scripts/genfwdef */ 148 efx_dword_t magic; /* = SIENA_MC_STATIC_CONFIG_MAGIC */ 149 efx_word_t length; /* of header area (i.e. not including VPD) */ 150 efx_byte_t version; 151 efx_byte_t csum; /* over header area (i.e. not including VPD) */ 152 efx_dword_t static_vpd_offset; 153 efx_dword_t static_vpd_length; 154 efx_dword_t capabilities; 155 efx_byte_t mac_addr_base[6]; 156 efx_byte_t green_mode_cal; /* Green mode calibration result */ 157 efx_byte_t green_mode_valid; /* Whether cal holds a valid value */ 158 efx_word_t mac_addr_count; 159 efx_word_t mac_addr_stride; 160 efx_word_t calibrated_vref; /* Vref as measured during production */ 161 efx_word_t adc_vref; /* Vref as read by ADC */ 162 efx_dword_t reserved2[1]; /* (write as zero) */ 163 efx_dword_t num_dbi_items; 164 struct { 165 efx_word_t addr; 166 efx_word_t byte_enables; 167 efx_dword_t value; 168 } dbi[]; 169} siena_mc_static_config_hdr_t; 170 171#define SIENA_MC_DYNAMIC_CONFIG_MAGIC (0xBDCFDDDD) 172#define SIENA_MC_DYNAMIC_CONFIG_VERSION (0) 173 174typedef struct siena_mc_fw_version_s { /* GENERATED BY scripts/genfwdef */ 175 efx_dword_t fw_subtype; 176 efx_word_t version_w; 177 efx_word_t version_x; 178 efx_word_t version_y; 179 efx_word_t version_z; 180} siena_mc_fw_version_t; 181 182typedef struct siena_mc_dynamic_config_hdr_s { /* GENERATED BY scripts/genfwdef */ 183 efx_dword_t magic; /* = SIENA_MC_DYNAMIC_CONFIG_MAGIC */ 184 efx_word_t length; /* of header area (i.e. not including VPD) */ 185 efx_byte_t version; 186 efx_byte_t csum; /* over header area (i.e. not including VPD) */ 187 efx_dword_t dynamic_vpd_offset; 188 efx_dword_t dynamic_vpd_length; 189 efx_dword_t num_fw_version_items; 190 siena_mc_fw_version_t fw_version[]; 191} siena_mc_dynamic_config_hdr_t; 192 193#define SIENA_MC_EXPROM_SINGLE_MAGIC (0xAA55) /* little-endian uint16_t */ 194 195#define SIENA_MC_EXPROM_COMBO_MAGIC (0xB0070102) /* little-endian uint32_t */ 196#define SIENA_MC_EXPROM_COMBO_V2_MAGIC (0xB0070103) /* little-endian uint32_t */ 197 198typedef struct siena_mc_combo_rom_hdr_s { /* GENERATED BY scripts/genfwdef */ 199 efx_dword_t magic; /* = SIENA_MC_EXPROM_COMBO_MAGIC or SIENA_MC_EXPROM_COMBO_V2_MAGIC */ 200 union { 201 struct { 202 efx_dword_t len1; /* length of first image */ 203 efx_dword_t len2; /* length of second image */ 204 efx_dword_t off1; /* offset of first byte to edit to combine images */ 205 efx_dword_t off2; /* offset of second byte to edit to combine images */ 206 efx_word_t infoblk0_off;/* infoblk offset */ 207 efx_word_t infoblk1_off;/* infoblk offset */ 208 efx_byte_t infoblk_len;/* length of space reserved for one infoblk structure */ 209 efx_byte_t reserved[7];/* (set to 0) */ 210 } v1; 211 struct { 212 efx_dword_t len1; /* length of first image */ 213 efx_dword_t len2; /* length of second image */ 214 efx_dword_t off1; /* offset of first byte to edit to combine images */ 215 efx_dword_t off2; /* offset of second byte to edit to combine images */ 216 efx_word_t infoblk_off;/* infoblk start offset */ 217 efx_word_t infoblk_count;/* infoblk count */ 218 efx_byte_t infoblk_len;/* length of space reserved for one infoblk structure */ 219 efx_byte_t reserved[7];/* (set to 0) */ 220 } v2; 221 } data; 222} siena_mc_combo_rom_hdr_t; 223 224#pragma pack() 225 226#endif /* _SYS_SIENA_FLASH_H */ 227