1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 */ 32 33#ifndef _SYS_EFX_REGS_H 34#define _SYS_EFX_REGS_H 35 36#ifdef __cplusplus 37extern "C" { 38#endif 39 40/************************************************************************** 41 * 42 * Falcon/Siena registers and descriptors 43 * 44 ************************************************************************** 45 */ 46 47/* 48 * FR_AB_EE_VPD_CFG0_REG_SF(128bit): 49 * SPI/VPD configuration register 0 50 */ 51#define FR_AB_EE_VPD_CFG0_REG_SF_OFST 0x00000300 52/* falcona0,falconb0=eeprom_flash */ 53/* 54 * FR_AB_EE_VPD_CFG0_REG(128bit): 55 * SPI/VPD configuration register 0 56 */ 57#define FR_AB_EE_VPD_CFG0_REG_OFST 0x00000140 58/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 59 60#define FRF_AB_EE_SF_FASTRD_EN_LBN 127 61#define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1 62#define FRF_AB_EE_SF_CLOCK_DIV_LBN 120 63#define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7 64#define FRF_AB_EE_VPD_WIP_POLL_LBN 119 65#define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1 66#define FRF_AB_EE_EE_CLOCK_DIV_LBN 112 67#define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7 68#define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96 69#define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16 70#define FRF_AB_EE_VPDW_LENGTH_LBN 80 71#define FRF_AB_EE_VPDW_LENGTH_WIDTH 15 72#define FRF_AB_EE_VPDW_BASE_LBN 64 73#define FRF_AB_EE_VPDW_BASE_WIDTH 15 74#define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56 75#define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8 76#define FRF_AB_EE_VPD_BASE_LBN 32 77#define FRF_AB_EE_VPD_BASE_WIDTH 24 78#define FRF_AB_EE_VPD_LENGTH_LBN 16 79#define FRF_AB_EE_VPD_LENGTH_WIDTH 15 80#define FRF_AB_EE_VPD_AD_SIZE_LBN 8 81#define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5 82#define FRF_AB_EE_VPD_ACCESS_ON_LBN 5 83#define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1 84#define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4 85#define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1 86#define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2 87#define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1 88#define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1 89#define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1 90#define FRF_AB_EE_VPD_EN_LBN 0 91#define FRF_AB_EE_VPD_EN_WIDTH 1 92 93/* 94 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit): 95 * PCIE SerDes control register 0 to 3 96 */ 97#define FR_AB_PCIE_SD_CTL0123_REG_SF_OFST 0x00000320 98/* falcona0,falconb0=eeprom_flash */ 99/* 100 * FR_AB_PCIE_SD_CTL0123_REG(128bit): 101 * PCIE SerDes control register 0 to 3 102 */ 103#define FR_AB_PCIE_SD_CTL0123_REG_OFST 0x00000320 104/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 105 106#define FRF_AB_PCIE_TESTSIG_H_LBN 96 107#define FRF_AB_PCIE_TESTSIG_H_WIDTH 19 108#define FRF_AB_PCIE_TESTSIG_L_LBN 64 109#define FRF_AB_PCIE_TESTSIG_L_WIDTH 19 110#define FRF_AB_PCIE_OFFSET_LBN 56 111#define FRF_AB_PCIE_OFFSET_WIDTH 8 112#define FRF_AB_PCIE_OFFSETEN_H_LBN 55 113#define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1 114#define FRF_AB_PCIE_OFFSETEN_L_LBN 54 115#define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1 116#define FRF_AB_PCIE_HIVMODE_H_LBN 53 117#define FRF_AB_PCIE_HIVMODE_H_WIDTH 1 118#define FRF_AB_PCIE_HIVMODE_L_LBN 52 119#define FRF_AB_PCIE_HIVMODE_L_WIDTH 1 120#define FRF_AB_PCIE_PARRESET_H_LBN 51 121#define FRF_AB_PCIE_PARRESET_H_WIDTH 1 122#define FRF_AB_PCIE_PARRESET_L_LBN 50 123#define FRF_AB_PCIE_PARRESET_L_WIDTH 1 124#define FRF_AB_PCIE_LPBKWDRV_H_LBN 49 125#define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1 126#define FRF_AB_PCIE_LPBKWDRV_L_LBN 48 127#define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1 128#define FRF_AB_PCIE_LPBK_LBN 40 129#define FRF_AB_PCIE_LPBK_WIDTH 8 130#define FRF_AB_PCIE_PARLPBK_LBN 32 131#define FRF_AB_PCIE_PARLPBK_WIDTH 8 132#define FRF_AB_PCIE_RXTERMADJ_H_LBN 30 133#define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2 134#define FRF_AB_PCIE_RXTERMADJ_L_LBN 28 135#define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2 136#define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3 137#define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2 138#define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1 139#define FFE_AB_PCIE_RXTERMADJ_NOMNL 0 140#define FRF_AB_PCIE_TXTERMADJ_H_LBN 26 141#define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2 142#define FRF_AB_PCIE_TXTERMADJ_L_LBN 24 143#define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2 144#define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3 145#define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2 146#define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1 147#define FFE_AB_PCIE_TXTERMADJ_NOMNL 0 148#define FRF_AB_PCIE_RXEQCTL_H_LBN 18 149#define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2 150#define FRF_AB_PCIE_RXEQCTL_L_LBN 16 151#define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2 152#define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3 153#define FFE_AB_PCIE_RXEQCTL_OFF 2 154#define FFE_AB_PCIE_RXEQCTL_MIN 1 155#define FFE_AB_PCIE_RXEQCTL_MAX 0 156#define FRF_AB_PCIE_HIDRV_LBN 8 157#define FRF_AB_PCIE_HIDRV_WIDTH 8 158#define FRF_AB_PCIE_LODRV_LBN 0 159#define FRF_AB_PCIE_LODRV_WIDTH 8 160 161/* 162 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit): 163 * PCIE SerDes control register 4 and 5 164 */ 165#define FR_AB_PCIE_SD_CTL45_REG_SF_OFST 0x00000330 166/* falcona0,falconb0=eeprom_flash */ 167/* 168 * FR_AB_PCIE_SD_CTL45_REG(128bit): 169 * PCIE SerDes control register 4 and 5 170 */ 171#define FR_AB_PCIE_SD_CTL45_REG_OFST 0x00000330 172/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 173 174#define FRF_AB_PCIE_DTX7_LBN 60 175#define FRF_AB_PCIE_DTX7_WIDTH 4 176#define FRF_AB_PCIE_DTX6_LBN 56 177#define FRF_AB_PCIE_DTX6_WIDTH 4 178#define FRF_AB_PCIE_DTX5_LBN 52 179#define FRF_AB_PCIE_DTX5_WIDTH 4 180#define FRF_AB_PCIE_DTX4_LBN 48 181#define FRF_AB_PCIE_DTX4_WIDTH 4 182#define FRF_AB_PCIE_DTX3_LBN 44 183#define FRF_AB_PCIE_DTX3_WIDTH 4 184#define FRF_AB_PCIE_DTX2_LBN 40 185#define FRF_AB_PCIE_DTX2_WIDTH 4 186#define FRF_AB_PCIE_DTX1_LBN 36 187#define FRF_AB_PCIE_DTX1_WIDTH 4 188#define FRF_AB_PCIE_DTX0_LBN 32 189#define FRF_AB_PCIE_DTX0_WIDTH 4 190#define FRF_AB_PCIE_DEQ7_LBN 28 191#define FRF_AB_PCIE_DEQ7_WIDTH 4 192#define FRF_AB_PCIE_DEQ6_LBN 24 193#define FRF_AB_PCIE_DEQ6_WIDTH 4 194#define FRF_AB_PCIE_DEQ5_LBN 20 195#define FRF_AB_PCIE_DEQ5_WIDTH 4 196#define FRF_AB_PCIE_DEQ4_LBN 16 197#define FRF_AB_PCIE_DEQ4_WIDTH 4 198#define FRF_AB_PCIE_DEQ3_LBN 12 199#define FRF_AB_PCIE_DEQ3_WIDTH 4 200#define FRF_AB_PCIE_DEQ2_LBN 8 201#define FRF_AB_PCIE_DEQ2_WIDTH 4 202#define FRF_AB_PCIE_DEQ1_LBN 4 203#define FRF_AB_PCIE_DEQ1_WIDTH 4 204#define FRF_AB_PCIE_DEQ0_LBN 0 205#define FRF_AB_PCIE_DEQ0_WIDTH 4 206 207/* 208 * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit): 209 * PCIE PCS control and status register 210 */ 211#define FR_AB_PCIE_PCS_CTL_STAT_REG_SF_OFST 0x00000340 212/* falcona0,falconb0=eeprom_flash */ 213/* 214 * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit): 215 * PCIE PCS control and status register 216 */ 217#define FR_AB_PCIE_PCS_CTL_STAT_REG_OFST 0x00000340 218/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 219 220#define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52 221#define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4 222#define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48 223#define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4 224#define FRF_AB_PCIE_PRBSERR_LBN 40 225#define FRF_AB_PCIE_PRBSERR_WIDTH 8 226#define FRF_AB_PCIE_PRBSERRH0_LBN 32 227#define FRF_AB_PCIE_PRBSERRH0_WIDTH 8 228#define FRF_AB_PCIE_FASTINIT_H_LBN 15 229#define FRF_AB_PCIE_FASTINIT_H_WIDTH 1 230#define FRF_AB_PCIE_FASTINIT_L_LBN 14 231#define FRF_AB_PCIE_FASTINIT_L_WIDTH 1 232#define FRF_AB_PCIE_CTCDISABLE_H_LBN 13 233#define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1 234#define FRF_AB_PCIE_CTCDISABLE_L_LBN 12 235#define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1 236#define FRF_AB_PCIE_PRBSSYNC_H_LBN 11 237#define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1 238#define FRF_AB_PCIE_PRBSSYNC_L_LBN 10 239#define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1 240#define FRF_AB_PCIE_PRBSERRACK_H_LBN 9 241#define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1 242#define FRF_AB_PCIE_PRBSERRACK_L_LBN 8 243#define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1 244#define FRF_AB_PCIE_PRBSSEL_LBN 0 245#define FRF_AB_PCIE_PRBSSEL_WIDTH 8 246 247/* 248 * FR_AB_HW_INIT_REG_SF(128bit): 249 * Hardware initialization register 250 */ 251#define FR_AB_HW_INIT_REG_SF_OFST 0x00000350 252/* falcona0,falconb0=eeprom_flash */ 253/* 254 * FR_AZ_HW_INIT_REG(128bit): 255 * Hardware initialization register 256 */ 257#define FR_AZ_HW_INIT_REG_OFST 0x000000c0 258/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 259 260#define FRF_BB_BDMRD_CPLF_FULL_LBN 124 261#define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1 262#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121 263#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3 264#define FRF_CZ_TX_MRG_TAGS_LBN 120 265#define FRF_CZ_TX_MRG_TAGS_WIDTH 1 266#define FRF_AZ_TRGT_MASK_ALL_LBN 100 267#define FRF_AZ_TRGT_MASK_ALL_WIDTH 1 268#define FRF_AZ_DOORBELL_DROP_LBN 92 269#define FRF_AZ_DOORBELL_DROP_WIDTH 8 270#define FRF_AB_TX_RREQ_MASK_EN_LBN 76 271#define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1 272#define FRF_AB_PE_EIDLE_DIS_LBN 75 273#define FRF_AB_PE_EIDLE_DIS_WIDTH 1 274#define FRF_AZ_FC_BLOCKING_EN_LBN 45 275#define FRF_AZ_FC_BLOCKING_EN_WIDTH 1 276#define FRF_AZ_B2B_REQ_EN_LBN 44 277#define FRF_AZ_B2B_REQ_EN_WIDTH 1 278#define FRF_AZ_POST_WR_MASK_LBN 40 279#define FRF_AZ_POST_WR_MASK_WIDTH 4 280#define FRF_AZ_TLP_TC_LBN 34 281#define FRF_AZ_TLP_TC_WIDTH 3 282#define FRF_AZ_TLP_ATTR_LBN 32 283#define FRF_AZ_TLP_ATTR_WIDTH 2 284#define FRF_AB_INTB_VEC_LBN 24 285#define FRF_AB_INTB_VEC_WIDTH 5 286#define FRF_AB_INTA_VEC_LBN 16 287#define FRF_AB_INTA_VEC_WIDTH 5 288#define FRF_AZ_WD_TIMER_LBN 8 289#define FRF_AZ_WD_TIMER_WIDTH 8 290#define FRF_AZ_US_DISABLE_LBN 5 291#define FRF_AZ_US_DISABLE_WIDTH 1 292#define FRF_AZ_TLP_EP_LBN 4 293#define FRF_AZ_TLP_EP_WIDTH 1 294#define FRF_AZ_ATTR_SEL_LBN 3 295#define FRF_AZ_ATTR_SEL_WIDTH 1 296#define FRF_AZ_TD_SEL_LBN 1 297#define FRF_AZ_TD_SEL_WIDTH 1 298#define FRF_AZ_TLP_TD_LBN 0 299#define FRF_AZ_TLP_TD_WIDTH 1 300 301/* 302 * FR_AB_NIC_STAT_REG_SF(128bit): 303 * NIC status register 304 */ 305#define FR_AB_NIC_STAT_REG_SF_OFST 0x00000360 306/* falcona0,falconb0=eeprom_flash */ 307/* 308 * FR_AB_NIC_STAT_REG(128bit): 309 * NIC status register 310 */ 311#define FR_AB_NIC_STAT_REG_OFST 0x00000200 312/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 313 314#define FRF_BB_AER_DIS_LBN 34 315#define FRF_BB_AER_DIS_WIDTH 1 316#define FRF_BB_EE_STRAP_EN_LBN 31 317#define FRF_BB_EE_STRAP_EN_WIDTH 1 318#define FRF_BB_EE_STRAP_LBN 24 319#define FRF_BB_EE_STRAP_WIDTH 4 320#define FRF_BB_REVISION_ID_LBN 17 321#define FRF_BB_REVISION_ID_WIDTH 7 322#define FRF_AB_ONCHIP_SRAM_LBN 16 323#define FRF_AB_ONCHIP_SRAM_WIDTH 1 324#define FRF_AB_SF_PRST_LBN 9 325#define FRF_AB_SF_PRST_WIDTH 1 326#define FRF_AB_EE_PRST_LBN 8 327#define FRF_AB_EE_PRST_WIDTH 1 328#define FRF_AB_ATE_MODE_LBN 3 329#define FRF_AB_ATE_MODE_WIDTH 1 330#define FRF_AB_STRAP_PINS_LBN 0 331#define FRF_AB_STRAP_PINS_WIDTH 3 332 333/* 334 * FR_AB_GLB_CTL_REG_SF(128bit): 335 * Global control register 336 */ 337#define FR_AB_GLB_CTL_REG_SF_OFST 0x00000370 338/* falcona0,falconb0=eeprom_flash */ 339/* 340 * FR_AB_GLB_CTL_REG(128bit): 341 * Global control register 342 */ 343#define FR_AB_GLB_CTL_REG_OFST 0x00000220 344/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 345 346#define FRF_AB_EXT_PHY_RST_CTL_LBN 63 347#define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1 348#define FRF_AB_XAUI_SD_RST_CTL_LBN 62 349#define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1 350#define FRF_AB_PCIE_SD_RST_CTL_LBN 61 351#define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1 352#define FRF_AA_PCIX_RST_CTL_LBN 60 353#define FRF_AA_PCIX_RST_CTL_WIDTH 1 354#define FRF_BB_BIU_RST_CTL_LBN 60 355#define FRF_BB_BIU_RST_CTL_WIDTH 1 356#define FRF_AB_PCIE_STKY_RST_CTL_LBN 59 357#define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1 358#define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58 359#define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1 360#define FRF_AB_PCIE_CORE_RST_CTL_LBN 57 361#define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1 362#define FRF_AB_XGRX_RST_CTL_LBN 56 363#define FRF_AB_XGRX_RST_CTL_WIDTH 1 364#define FRF_AB_XGTX_RST_CTL_LBN 55 365#define FRF_AB_XGTX_RST_CTL_WIDTH 1 366#define FRF_AB_EM_RST_CTL_LBN 54 367#define FRF_AB_EM_RST_CTL_WIDTH 1 368#define FRF_AB_EV_RST_CTL_LBN 53 369#define FRF_AB_EV_RST_CTL_WIDTH 1 370#define FRF_AB_SR_RST_CTL_LBN 52 371#define FRF_AB_SR_RST_CTL_WIDTH 1 372#define FRF_AB_RX_RST_CTL_LBN 51 373#define FRF_AB_RX_RST_CTL_WIDTH 1 374#define FRF_AB_TX_RST_CTL_LBN 50 375#define FRF_AB_TX_RST_CTL_WIDTH 1 376#define FRF_AB_EE_RST_CTL_LBN 49 377#define FRF_AB_EE_RST_CTL_WIDTH 1 378#define FRF_AB_CS_RST_CTL_LBN 48 379#define FRF_AB_CS_RST_CTL_WIDTH 1 380#define FRF_AB_HOT_RST_CTL_LBN 40 381#define FRF_AB_HOT_RST_CTL_WIDTH 2 382#define FRF_AB_RST_EXT_PHY_LBN 31 383#define FRF_AB_RST_EXT_PHY_WIDTH 1 384#define FRF_AB_RST_XAUI_SD_LBN 30 385#define FRF_AB_RST_XAUI_SD_WIDTH 1 386#define FRF_AB_RST_PCIE_SD_LBN 29 387#define FRF_AB_RST_PCIE_SD_WIDTH 1 388#define FRF_AA_RST_PCIX_LBN 28 389#define FRF_AA_RST_PCIX_WIDTH 1 390#define FRF_BB_RST_BIU_LBN 28 391#define FRF_BB_RST_BIU_WIDTH 1 392#define FRF_AB_RST_PCIE_STKY_LBN 27 393#define FRF_AB_RST_PCIE_STKY_WIDTH 1 394#define FRF_AB_RST_PCIE_NSTKY_LBN 26 395#define FRF_AB_RST_PCIE_NSTKY_WIDTH 1 396#define FRF_AB_RST_PCIE_CORE_LBN 25 397#define FRF_AB_RST_PCIE_CORE_WIDTH 1 398#define FRF_AB_RST_XGRX_LBN 24 399#define FRF_AB_RST_XGRX_WIDTH 1 400#define FRF_AB_RST_XGTX_LBN 23 401#define FRF_AB_RST_XGTX_WIDTH 1 402#define FRF_AB_RST_EM_LBN 22 403#define FRF_AB_RST_EM_WIDTH 1 404#define FRF_AB_RST_EV_LBN 21 405#define FRF_AB_RST_EV_WIDTH 1 406#define FRF_AB_RST_SR_LBN 20 407#define FRF_AB_RST_SR_WIDTH 1 408#define FRF_AB_RST_RX_LBN 19 409#define FRF_AB_RST_RX_WIDTH 1 410#define FRF_AB_RST_TX_LBN 18 411#define FRF_AB_RST_TX_WIDTH 1 412#define FRF_AB_RST_SF_LBN 17 413#define FRF_AB_RST_SF_WIDTH 1 414#define FRF_AB_RST_CS_LBN 16 415#define FRF_AB_RST_CS_WIDTH 1 416#define FRF_AB_INT_RST_DUR_LBN 4 417#define FRF_AB_INT_RST_DUR_WIDTH 3 418#define FRF_AB_EXT_PHY_RST_DUR_LBN 1 419#define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3 420#define FFE_AB_EXT_PHY_RST_DUR_10240US 7 421#define FFE_AB_EXT_PHY_RST_DUR_5120US 6 422#define FFE_AB_EXT_PHY_RST_DUR_2560US 5 423#define FFE_AB_EXT_PHY_RST_DUR_1280US 4 424#define FFE_AB_EXT_PHY_RST_DUR_640US 3 425#define FFE_AB_EXT_PHY_RST_DUR_320US 2 426#define FFE_AB_EXT_PHY_RST_DUR_160US 1 427#define FFE_AB_EXT_PHY_RST_DUR_80US 0 428#define FRF_AB_SWRST_LBN 0 429#define FRF_AB_SWRST_WIDTH 1 430 431/* 432 * FR_AZ_IOM_IND_ADR_REG(32bit): 433 * IO-mapped indirect access address register 434 */ 435#define FR_AZ_IOM_IND_ADR_REG_OFST 0x00000000 436/* falcona0,falconb0,sienaa0=net_func_bar0 */ 437 438#define FRF_AZ_IOM_AUTO_ADR_INC_EN_LBN 24 439#define FRF_AZ_IOM_AUTO_ADR_INC_EN_WIDTH 1 440#define FRF_AZ_IOM_IND_ADR_LBN 0 441#define FRF_AZ_IOM_IND_ADR_WIDTH 24 442 443/* 444 * FR_AZ_IOM_IND_DAT_REG(32bit): 445 * IO-mapped indirect access data register 446 */ 447#define FR_AZ_IOM_IND_DAT_REG_OFST 0x00000004 448/* falcona0,falconb0,sienaa0=net_func_bar0 */ 449 450#define FRF_AZ_IOM_IND_DAT_LBN 0 451#define FRF_AZ_IOM_IND_DAT_WIDTH 32 452 453/* 454 * FR_AZ_ADR_REGION_REG(128bit): 455 * Address region register 456 */ 457#define FR_AZ_ADR_REGION_REG_OFST 0x00000000 458/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 459 460#define FRF_AZ_ADR_REGION3_LBN 96 461#define FRF_AZ_ADR_REGION3_WIDTH 18 462#define FRF_AZ_ADR_REGION2_LBN 64 463#define FRF_AZ_ADR_REGION2_WIDTH 18 464#define FRF_AZ_ADR_REGION1_LBN 32 465#define FRF_AZ_ADR_REGION1_WIDTH 18 466#define FRF_AZ_ADR_REGION0_LBN 0 467#define FRF_AZ_ADR_REGION0_WIDTH 18 468 469/* 470 * FR_AZ_INT_EN_REG_KER(128bit): 471 * Kernel driver Interrupt enable register 472 */ 473#define FR_AZ_INT_EN_REG_KER_OFST 0x00000010 474/* falcona0,falconb0,sienaa0=net_func_bar2 */ 475 476#define FRF_AZ_KER_INT_LEVE_SEL_LBN 8 477#define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6 478#define FRF_AZ_KER_INT_CHAR_LBN 4 479#define FRF_AZ_KER_INT_CHAR_WIDTH 1 480#define FRF_AZ_KER_INT_KER_LBN 3 481#define FRF_AZ_KER_INT_KER_WIDTH 1 482#define FRF_AZ_DRV_INT_EN_KER_LBN 0 483#define FRF_AZ_DRV_INT_EN_KER_WIDTH 1 484 485/* 486 * FR_AZ_INT_EN_REG_CHAR(128bit): 487 * Char Driver interrupt enable register 488 */ 489#define FR_AZ_INT_EN_REG_CHAR_OFST 0x00000020 490/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 491 492#define FRF_AZ_CHAR_INT_LEVE_SEL_LBN 8 493#define FRF_AZ_CHAR_INT_LEVE_SEL_WIDTH 6 494#define FRF_AZ_CHAR_INT_CHAR_LBN 4 495#define FRF_AZ_CHAR_INT_CHAR_WIDTH 1 496#define FRF_AZ_CHAR_INT_KER_LBN 3 497#define FRF_AZ_CHAR_INT_KER_WIDTH 1 498#define FRF_AZ_DRV_INT_EN_CHAR_LBN 0 499#define FRF_AZ_DRV_INT_EN_CHAR_WIDTH 1 500 501/* 502 * FR_AZ_INT_ADR_REG_KER(128bit): 503 * Interrupt host address for Kernel driver 504 */ 505#define FR_AZ_INT_ADR_REG_KER_OFST 0x00000030 506/* falcona0,falconb0,sienaa0=net_func_bar2 */ 507 508#define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64 509#define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1 510#define FRF_AZ_INT_ADR_KER_LBN 0 511#define FRF_AZ_INT_ADR_KER_WIDTH 64 512#define FRF_AZ_INT_ADR_KER_DW0_LBN 0 513#define FRF_AZ_INT_ADR_KER_DW0_WIDTH 32 514#define FRF_AZ_INT_ADR_KER_DW1_LBN 32 515#define FRF_AZ_INT_ADR_KER_DW1_WIDTH 32 516 517/* 518 * FR_AZ_INT_ADR_REG_CHAR(128bit): 519 * Interrupt host address for Char driver 520 */ 521#define FR_AZ_INT_ADR_REG_CHAR_OFST 0x00000040 522/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 523 524#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_LBN 64 525#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1 526#define FRF_AZ_INT_ADR_CHAR_LBN 0 527#define FRF_AZ_INT_ADR_CHAR_WIDTH 64 528#define FRF_AZ_INT_ADR_CHAR_DW0_LBN 0 529#define FRF_AZ_INT_ADR_CHAR_DW0_WIDTH 32 530#define FRF_AZ_INT_ADR_CHAR_DW1_LBN 32 531#define FRF_AZ_INT_ADR_CHAR_DW1_WIDTH 32 532 533/* 534 * FR_AA_INT_ACK_KER(32bit): 535 * Kernel interrupt acknowledge register 536 */ 537#define FR_AA_INT_ACK_KER_OFST 0x00000050 538/* falcona0=net_func_bar2 */ 539 540#define FRF_AA_INT_ACK_KER_FIELD_LBN 0 541#define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32 542 543/* 544 * FR_BZ_INT_ISR0_REG(128bit): 545 * Function 0 Interrupt Acknowlege Status register 546 */ 547#define FR_BZ_INT_ISR0_REG_OFST 0x00000090 548/* falconb0,sienaa0=net_func_bar2 */ 549 550#define FRF_BZ_INT_ISR_REG_LBN 0 551#define FRF_BZ_INT_ISR_REG_WIDTH 64 552#define FRF_BZ_INT_ISR_REG_DW0_LBN 0 553#define FRF_BZ_INT_ISR_REG_DW0_WIDTH 32 554#define FRF_BZ_INT_ISR_REG_DW1_LBN 32 555#define FRF_BZ_INT_ISR_REG_DW1_WIDTH 32 556 557/* 558 * FR_AB_EE_SPI_HCMD_REG(128bit): 559 * SPI host command register 560 */ 561#define FR_AB_EE_SPI_HCMD_REG_OFST 0x00000100 562/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 563 564#define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31 565#define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1 566#define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28 567#define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1 568#define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24 569#define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1 570#define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16 571#define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5 572#define FRF_AB_EE_SPI_HCMD_READ_LBN 15 573#define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1 574#define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12 575#define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2 576#define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8 577#define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2 578#define FRF_AB_EE_SPI_HCMD_ENC_LBN 0 579#define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8 580 581/* 582 * FR_CZ_USR_EV_CFG(32bit): 583 * User Level Event Configuration register 584 */ 585#define FR_CZ_USR_EV_CFG_OFST 0x00000100 586/* sienaa0=net_func_bar2 */ 587 588#define FRF_CZ_USREV_DIS_LBN 16 589#define FRF_CZ_USREV_DIS_WIDTH 1 590#define FRF_CZ_DFLT_EVQ_LBN 0 591#define FRF_CZ_DFLT_EVQ_WIDTH 10 592 593/* 594 * FR_AB_EE_SPI_HADR_REG(128bit): 595 * SPI host address register 596 */ 597#define FR_AB_EE_SPI_HADR_REG_OFST 0x00000110 598/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 599 600#define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24 601#define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8 602#define FRF_AB_EE_SPI_HADR_ADR_LBN 0 603#define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24 604 605/* 606 * FR_AB_EE_SPI_HDATA_REG(128bit): 607 * SPI host data register 608 */ 609#define FR_AB_EE_SPI_HDATA_REG_OFST 0x00000120 610/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 611 612#define FRF_AB_EE_SPI_HDATA3_LBN 96 613#define FRF_AB_EE_SPI_HDATA3_WIDTH 32 614#define FRF_AB_EE_SPI_HDATA2_LBN 64 615#define FRF_AB_EE_SPI_HDATA2_WIDTH 32 616#define FRF_AB_EE_SPI_HDATA1_LBN 32 617#define FRF_AB_EE_SPI_HDATA1_WIDTH 32 618#define FRF_AB_EE_SPI_HDATA0_LBN 0 619#define FRF_AB_EE_SPI_HDATA0_WIDTH 32 620 621/* 622 * FR_AB_EE_BASE_PAGE_REG(128bit): 623 * Expansion ROM base mirror register 624 */ 625#define FR_AB_EE_BASE_PAGE_REG_OFST 0x00000130 626/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 627 628#define FRF_AB_EE_EXPROM_MASK_LBN 16 629#define FRF_AB_EE_EXPROM_MASK_WIDTH 13 630#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0 631#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13 632 633/* 634 * FR_AB_EE_VPD_SW_CNTL_REG(128bit): 635 * VPD access SW control register 636 */ 637#define FR_AB_EE_VPD_SW_CNTL_REG_OFST 0x00000150 638/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 639 640#define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31 641#define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1 642#define FRF_AB_EE_VPD_CYC_WRITE_LBN 28 643#define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1 644#define FRF_AB_EE_VPD_CYC_ADR_LBN 0 645#define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15 646 647/* 648 * FR_AB_EE_VPD_SW_DATA_REG(128bit): 649 * VPD access SW data register 650 */ 651#define FR_AB_EE_VPD_SW_DATA_REG_OFST 0x00000160 652/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 653 654#define FRF_AB_EE_VPD_CYC_DAT_LBN 0 655#define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32 656 657/* 658 * FR_BB_PCIE_CORE_INDIRECT_REG(64bit): 659 * Indirect Access to PCIE Core registers 660 */ 661#define FR_BB_PCIE_CORE_INDIRECT_REG_OFST 0x000001f0 662/* falconb0=net_func_bar2 */ 663 664#define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32 665#define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32 666#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15 667#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1 668#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0 669#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12 670 671/* 672 * FR_AB_GPIO_CTL_REG(128bit): 673 * GPIO control register 674 */ 675#define FR_AB_GPIO_CTL_REG_OFST 0x00000210 676/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 677 678#define FRF_AB_GPIO15_OEN_LBN 63 679#define FRF_AB_GPIO15_OEN_WIDTH 1 680#define FRF_AB_GPIO14_OEN_LBN 62 681#define FRF_AB_GPIO14_OEN_WIDTH 1 682#define FRF_AB_GPIO13_OEN_LBN 61 683#define FRF_AB_GPIO13_OEN_WIDTH 1 684#define FRF_AB_GPIO12_OEN_LBN 60 685#define FRF_AB_GPIO12_OEN_WIDTH 1 686#define FRF_AB_GPIO11_OEN_LBN 59 687#define FRF_AB_GPIO11_OEN_WIDTH 1 688#define FRF_AB_GPIO10_OEN_LBN 58 689#define FRF_AB_GPIO10_OEN_WIDTH 1 690#define FRF_AB_GPIO9_OEN_LBN 57 691#define FRF_AB_GPIO9_OEN_WIDTH 1 692#define FRF_AB_GPIO8_OEN_LBN 56 693#define FRF_AB_GPIO8_OEN_WIDTH 1 694#define FRF_AB_GPIO15_OUT_LBN 55 695#define FRF_AB_GPIO15_OUT_WIDTH 1 696#define FRF_AB_GPIO14_OUT_LBN 54 697#define FRF_AB_GPIO14_OUT_WIDTH 1 698#define FRF_AB_GPIO13_OUT_LBN 53 699#define FRF_AB_GPIO13_OUT_WIDTH 1 700#define FRF_AB_GPIO12_OUT_LBN 52 701#define FRF_AB_GPIO12_OUT_WIDTH 1 702#define FRF_AB_GPIO11_OUT_LBN 51 703#define FRF_AB_GPIO11_OUT_WIDTH 1 704#define FRF_AB_GPIO10_OUT_LBN 50 705#define FRF_AB_GPIO10_OUT_WIDTH 1 706#define FRF_AB_GPIO9_OUT_LBN 49 707#define FRF_AB_GPIO9_OUT_WIDTH 1 708#define FRF_AB_GPIO8_OUT_LBN 48 709#define FRF_AB_GPIO8_OUT_WIDTH 1 710#define FRF_AB_GPIO15_IN_LBN 47 711#define FRF_AB_GPIO15_IN_WIDTH 1 712#define FRF_AB_GPIO14_IN_LBN 46 713#define FRF_AB_GPIO14_IN_WIDTH 1 714#define FRF_AB_GPIO13_IN_LBN 45 715#define FRF_AB_GPIO13_IN_WIDTH 1 716#define FRF_AB_GPIO12_IN_LBN 44 717#define FRF_AB_GPIO12_IN_WIDTH 1 718#define FRF_AB_GPIO11_IN_LBN 43 719#define FRF_AB_GPIO11_IN_WIDTH 1 720#define FRF_AB_GPIO10_IN_LBN 42 721#define FRF_AB_GPIO10_IN_WIDTH 1 722#define FRF_AB_GPIO9_IN_LBN 41 723#define FRF_AB_GPIO9_IN_WIDTH 1 724#define FRF_AB_GPIO8_IN_LBN 40 725#define FRF_AB_GPIO8_IN_WIDTH 1 726#define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39 727#define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1 728#define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38 729#define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1 730#define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37 731#define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1 732#define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36 733#define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1 734#define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35 735#define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1 736#define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34 737#define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1 738#define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33 739#define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1 740#define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32 741#define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1 742#define FRF_BB_CLK156_OUT_EN_LBN 31 743#define FRF_BB_CLK156_OUT_EN_WIDTH 1 744#define FRF_BB_USE_NIC_CLK_LBN 30 745#define FRF_BB_USE_NIC_CLK_WIDTH 1 746#define FRF_AB_GPIO5_OEN_LBN 29 747#define FRF_AB_GPIO5_OEN_WIDTH 1 748#define FRF_AB_GPIO4_OEN_LBN 28 749#define FRF_AB_GPIO4_OEN_WIDTH 1 750#define FRF_AB_GPIO3_OEN_LBN 27 751#define FRF_AB_GPIO3_OEN_WIDTH 1 752#define FRF_AB_GPIO2_OEN_LBN 26 753#define FRF_AB_GPIO2_OEN_WIDTH 1 754#define FRF_AB_GPIO1_OEN_LBN 25 755#define FRF_AB_GPIO1_OEN_WIDTH 1 756#define FRF_AB_GPIO0_OEN_LBN 24 757#define FRF_AB_GPIO0_OEN_WIDTH 1 758#define FRF_AB_GPIO5_OUT_LBN 21 759#define FRF_AB_GPIO5_OUT_WIDTH 1 760#define FRF_AB_GPIO4_OUT_LBN 20 761#define FRF_AB_GPIO4_OUT_WIDTH 1 762#define FRF_AB_GPIO3_OUT_LBN 19 763#define FRF_AB_GPIO3_OUT_WIDTH 1 764#define FRF_AB_GPIO2_OUT_LBN 18 765#define FRF_AB_GPIO2_OUT_WIDTH 1 766#define FRF_AB_GPIO1_OUT_LBN 17 767#define FRF_AB_GPIO1_OUT_WIDTH 1 768#define FRF_AB_GPIO0_OUT_LBN 16 769#define FRF_AB_GPIO0_OUT_WIDTH 1 770#define FRF_AB_GPIO5_IN_LBN 13 771#define FRF_AB_GPIO5_IN_WIDTH 1 772#define FRF_AB_GPIO4_IN_LBN 12 773#define FRF_AB_GPIO4_IN_WIDTH 1 774#define FRF_AB_GPIO3_IN_LBN 11 775#define FRF_AB_GPIO3_IN_WIDTH 1 776#define FRF_AB_GPIO2_IN_LBN 10 777#define FRF_AB_GPIO2_IN_WIDTH 1 778#define FRF_AB_GPIO1_IN_LBN 9 779#define FRF_AB_GPIO1_IN_WIDTH 1 780#define FRF_AB_GPIO0_IN_LBN 8 781#define FRF_AB_GPIO0_IN_WIDTH 1 782#define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5 783#define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1 784#define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4 785#define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1 786#define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3 787#define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1 788#define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2 789#define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1 790#define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1 791#define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1 792#define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0 793#define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1 794 795/* 796 * FR_AZ_FATAL_INTR_REG_KER(128bit): 797 * Fatal interrupt register for Kernel 798 */ 799#define FR_AZ_FATAL_INTR_REG_KER_OFST 0x00000230 800/* falcona0,falconb0,sienaa0=net_func_bar2 */ 801 802#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44 803#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1 804#define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43 805#define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1 806#define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43 807#define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1 808#define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42 809#define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1 810#define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41 811#define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1 812#define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40 813#define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1 814#define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39 815#define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1 816#define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38 817#define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1 818#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37 819#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1 820#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36 821#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1 822#define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35 823#define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1 824#define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34 825#define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1 826#define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33 827#define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1 828#define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32 829#define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1 830#define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12 831#define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1 832#define FRF_AB_PCI_BUSERR_INT_KER_LBN 11 833#define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1 834#define FRF_CZ_MBU_PERR_INT_KER_LBN 11 835#define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1 836#define FRF_AZ_SRAM_OOB_INT_KER_LBN 10 837#define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1 838#define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9 839#define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1 840#define FRF_AZ_MEM_PERR_INT_KER_LBN 8 841#define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1 842#define FRF_AZ_RBUF_OWN_INT_KER_LBN 7 843#define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1 844#define FRF_AZ_TBUF_OWN_INT_KER_LBN 6 845#define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1 846#define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5 847#define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1 848#define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4 849#define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1 850#define FRF_AZ_EVQ_OWN_INT_KER_LBN 3 851#define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1 852#define FRF_AZ_EVF_OFLO_INT_KER_LBN 2 853#define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1 854#define FRF_AZ_ILL_ADR_INT_KER_LBN 1 855#define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1 856#define FRF_AZ_SRM_PERR_INT_KER_LBN 0 857#define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1 858 859/* 860 * FR_AZ_FATAL_INTR_REG_CHAR(128bit): 861 * Fatal interrupt register for Char 862 */ 863#define FR_AZ_FATAL_INTR_REG_CHAR_OFST 0x00000240 864/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 865 866#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44 867#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1 868#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_LBN 43 869#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1 870#define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43 871#define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1 872#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_LBN 42 873#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1 874#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_LBN 41 875#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1 876#define FRF_AZ_MEM_PERR_INT_CHAR_EN_LBN 40 877#define FRF_AZ_MEM_PERR_INT_CHAR_EN_WIDTH 1 878#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_LBN 39 879#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1 880#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_LBN 38 881#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1 882#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37 883#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1 884#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36 885#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1 886#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_LBN 35 887#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1 888#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_LBN 34 889#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1 890#define FRF_AZ_ILL_ADR_INT_CHAR_EN_LBN 33 891#define FRF_AZ_ILL_ADR_INT_CHAR_EN_WIDTH 1 892#define FRF_AZ_SRM_PERR_INT_CHAR_EN_LBN 32 893#define FRF_AZ_SRM_PERR_INT_CHAR_EN_WIDTH 1 894#define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12 895#define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1 896#define FRF_AB_PCI_BUSERR_INT_CHAR_LBN 11 897#define FRF_AB_PCI_BUSERR_INT_CHAR_WIDTH 1 898#define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11 899#define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1 900#define FRF_AZ_SRAM_OOB_INT_CHAR_LBN 10 901#define FRF_AZ_SRAM_OOB_INT_CHAR_WIDTH 1 902#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_LBN 9 903#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1 904#define FRF_AZ_MEM_PERR_INT_CHAR_LBN 8 905#define FRF_AZ_MEM_PERR_INT_CHAR_WIDTH 1 906#define FRF_AZ_RBUF_OWN_INT_CHAR_LBN 7 907#define FRF_AZ_RBUF_OWN_INT_CHAR_WIDTH 1 908#define FRF_AZ_TBUF_OWN_INT_CHAR_LBN 6 909#define FRF_AZ_TBUF_OWN_INT_CHAR_WIDTH 1 910#define FRF_AZ_RDESCQ_OWN_INT_CHAR_LBN 5 911#define FRF_AZ_RDESCQ_OWN_INT_CHAR_WIDTH 1 912#define FRF_AZ_TDESCQ_OWN_INT_CHAR_LBN 4 913#define FRF_AZ_TDESCQ_OWN_INT_CHAR_WIDTH 1 914#define FRF_AZ_EVQ_OWN_INT_CHAR_LBN 3 915#define FRF_AZ_EVQ_OWN_INT_CHAR_WIDTH 1 916#define FRF_AZ_EVF_OFLO_INT_CHAR_LBN 2 917#define FRF_AZ_EVF_OFLO_INT_CHAR_WIDTH 1 918#define FRF_AZ_ILL_ADR_INT_CHAR_LBN 1 919#define FRF_AZ_ILL_ADR_INT_CHAR_WIDTH 1 920#define FRF_AZ_SRM_PERR_INT_CHAR_LBN 0 921#define FRF_AZ_SRM_PERR_INT_CHAR_WIDTH 1 922 923/* 924 * FR_AZ_DP_CTRL_REG(128bit): 925 * Datapath control register 926 */ 927#define FR_AZ_DP_CTRL_REG_OFST 0x00000250 928/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 929 930#define FRF_AZ_FLS_EVQ_ID_LBN 0 931#define FRF_AZ_FLS_EVQ_ID_WIDTH 12 932 933/* 934 * FR_AZ_MEM_STAT_REG(128bit): 935 * Memory status register 936 */ 937#define FR_AZ_MEM_STAT_REG_OFST 0x00000260 938/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 939 940#define FRF_AB_MEM_PERR_VEC_LBN 53 941#define FRF_AB_MEM_PERR_VEC_WIDTH 40 942#define FRF_AB_MEM_PERR_VEC_DW0_LBN 53 943#define FRF_AB_MEM_PERR_VEC_DW0_WIDTH 32 944#define FRF_AB_MEM_PERR_VEC_DW1_LBN 85 945#define FRF_AB_MEM_PERR_VEC_DW1_WIDTH 6 946#define FRF_AB_MBIST_CORR_LBN 38 947#define FRF_AB_MBIST_CORR_WIDTH 15 948#define FRF_AB_MBIST_ERR_LBN 0 949#define FRF_AB_MBIST_ERR_WIDTH 40 950#define FRF_AB_MBIST_ERR_DW0_LBN 0 951#define FRF_AB_MBIST_ERR_DW0_WIDTH 32 952#define FRF_AB_MBIST_ERR_DW1_LBN 32 953#define FRF_AB_MBIST_ERR_DW1_WIDTH 6 954#define FRF_CZ_MEM_PERR_VEC_LBN 0 955#define FRF_CZ_MEM_PERR_VEC_WIDTH 35 956#define FRF_CZ_MEM_PERR_VEC_DW0_LBN 0 957#define FRF_CZ_MEM_PERR_VEC_DW0_WIDTH 32 958#define FRF_CZ_MEM_PERR_VEC_DW1_LBN 32 959#define FRF_CZ_MEM_PERR_VEC_DW1_WIDTH 3 960 961/* 962 * FR_PORT0_CS_DEBUG_REG(128bit): 963 * Debug register 964 */ 965 966#define FR_AZ_CS_DEBUG_REG_OFST 0x00000270 967/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 968 969#define FRF_AB_GLB_DEBUG2_SEL_LBN 50 970#define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3 971#define FRF_AB_DEBUG_BLK_SEL2_LBN 47 972#define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3 973#define FRF_AB_DEBUG_BLK_SEL1_LBN 44 974#define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3 975#define FRF_AB_DEBUG_BLK_SEL0_LBN 41 976#define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3 977#define FRF_CZ_CS_PORT_NUM_LBN 40 978#define FRF_CZ_CS_PORT_NUM_WIDTH 2 979#define FRF_AB_MISC_DEBUG_ADDR_LBN 36 980#define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5 981#define FRF_CZ_CS_RESERVED_LBN 36 982#define FRF_CZ_CS_RESERVED_WIDTH 4 983#define FRF_AB_SERDES_DEBUG_ADDR_LBN 31 984#define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5 985#define FRF_CZ_CS_PORT_FPE_DW0_LBN 1 986#define FRF_CZ_CS_PORT_FPE_DW0_WIDTH 32 987#define FRF_CZ_CS_PORT_FPE_DW1_LBN 33 988#define FRF_CZ_CS_PORT_FPE_DW1_WIDTH 3 989#define FRF_CZ_CS_PORT_FPE_LBN 1 990#define FRF_CZ_CS_PORT_FPE_WIDTH 35 991#define FRF_AB_EM_DEBUG_ADDR_LBN 26 992#define FRF_AB_EM_DEBUG_ADDR_WIDTH 5 993#define FRF_AB_SR_DEBUG_ADDR_LBN 21 994#define FRF_AB_SR_DEBUG_ADDR_WIDTH 5 995#define FRF_AB_EV_DEBUG_ADDR_LBN 16 996#define FRF_AB_EV_DEBUG_ADDR_WIDTH 5 997#define FRF_AB_RX_DEBUG_ADDR_LBN 11 998#define FRF_AB_RX_DEBUG_ADDR_WIDTH 5 999#define FRF_AB_TX_DEBUG_ADDR_LBN 6 1000#define FRF_AB_TX_DEBUG_ADDR_WIDTH 5 1001#define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1 1002#define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5 1003#define FRF_AZ_CS_DEBUG_EN_LBN 0 1004#define FRF_AZ_CS_DEBUG_EN_WIDTH 1 1005 1006/* 1007 * FR_AZ_DRIVER_REG(128bit): 1008 * Driver scratch register [0-7] 1009 */ 1010#define FR_AZ_DRIVER_REG_OFST 0x00000280 1011/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1012#define FR_AZ_DRIVER_REG_STEP 16 1013#define FR_AZ_DRIVER_REG_ROWS 8 1014 1015#define FRF_AZ_DRIVER_DW0_LBN 0 1016#define FRF_AZ_DRIVER_DW0_WIDTH 32 1017 1018/* 1019 * FR_AZ_ALTERA_BUILD_REG(128bit): 1020 * Altera build register 1021 */ 1022#define FR_AZ_ALTERA_BUILD_REG_OFST 0x00000300 1023/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1024 1025#define FRF_AZ_ALTERA_BUILD_VER_LBN 0 1026#define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32 1027 1028/* 1029 * FR_AZ_CSR_SPARE_REG(128bit): 1030 * Spare register 1031 */ 1032#define FR_AZ_CSR_SPARE_REG_OFST 0x00000310 1033/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1034 1035#define FRF_AZ_MEM_PERR_EN_TX_DATA_LBN 72 1036#define FRF_AZ_MEM_PERR_EN_TX_DATA_WIDTH 2 1037#define FRF_AZ_MEM_PERR_EN_LBN 64 1038#define FRF_AZ_MEM_PERR_EN_WIDTH 38 1039#define FRF_AZ_MEM_PERR_EN_DW0_LBN 64 1040#define FRF_AZ_MEM_PERR_EN_DW0_WIDTH 32 1041#define FRF_AZ_MEM_PERR_EN_DW1_LBN 96 1042#define FRF_AZ_MEM_PERR_EN_DW1_WIDTH 6 1043#define FRF_AZ_CSR_SPARE_BITS_LBN 0 1044#define FRF_AZ_CSR_SPARE_BITS_WIDTH 32 1045 1046/* 1047 * FR_BZ_DEBUG_DATA_OUT_REG(128bit): 1048 * Live Debug and Debug 2 out ports 1049 */ 1050#define FR_BZ_DEBUG_DATA_OUT_REG_OFST 0x00000350 1051/* falconb0,sienaa0=net_func_bar2 */ 1052 1053#define FRF_BZ_DEBUG2_PORT_LBN 25 1054#define FRF_BZ_DEBUG2_PORT_WIDTH 15 1055#define FRF_BZ_DEBUG1_PORT_LBN 0 1056#define FRF_BZ_DEBUG1_PORT_WIDTH 25 1057 1058/* 1059 * FR_BZ_EVQ_RPTR_REGP0(32bit): 1060 * Event queue read pointer register 1061 */ 1062#define FR_BZ_EVQ_RPTR_REGP0_OFST 0x00000400 1063/* falconb0,sienaa0=net_func_bar2 */ 1064#define FR_BZ_EVQ_RPTR_REGP0_STEP 8192 1065#define FR_BZ_EVQ_RPTR_REGP0_ROWS 1024 1066/* 1067 * FR_AA_EVQ_RPTR_REG_KER(32bit): 1068 * Event queue read pointer register 1069 */ 1070#define FR_AA_EVQ_RPTR_REG_KER_OFST 0x00011b00 1071/* falcona0=net_func_bar2 */ 1072#define FR_AA_EVQ_RPTR_REG_KER_STEP 4 1073#define FR_AA_EVQ_RPTR_REG_KER_ROWS 4 1074/* 1075 * FR_AZ_EVQ_RPTR_REG(32bit): 1076 * Event queue read pointer register 1077 */ 1078#define FR_AZ_EVQ_RPTR_REG_OFST 0x00fa0000 1079/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1080#define FR_AZ_EVQ_RPTR_REG_STEP 16 1081#define FR_AB_EVQ_RPTR_REG_ROWS 4096 1082#define FR_CZ_EVQ_RPTR_REG_ROWS 1024 1083/* 1084 * FR_BB_EVQ_RPTR_REGP123(32bit): 1085 * Event queue read pointer register 1086 */ 1087#define FR_BB_EVQ_RPTR_REGP123_OFST 0x01000400 1088/* falconb0=net_func_bar2 */ 1089#define FR_BB_EVQ_RPTR_REGP123_STEP 8192 1090#define FR_BB_EVQ_RPTR_REGP123_ROWS 3072 1091 1092#define FRF_AZ_EVQ_RPTR_VLD_LBN 15 1093#define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1 1094#define FRF_AZ_EVQ_RPTR_LBN 0 1095#define FRF_AZ_EVQ_RPTR_WIDTH 15 1096 1097/* 1098 * FR_BZ_TIMER_COMMAND_REGP0(128bit): 1099 * Timer Command Registers 1100 */ 1101#define FR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420 1102/* falconb0,sienaa0=net_func_bar2 */ 1103#define FR_BZ_TIMER_COMMAND_REGP0_STEP 8192 1104#define FR_BZ_TIMER_COMMAND_REGP0_ROWS 1024 1105/* 1106 * FR_AA_TIMER_COMMAND_REG_KER(128bit): 1107 * Timer Command Registers 1108 */ 1109#define FR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420 1110/* falcona0=net_func_bar2 */ 1111#define FR_AA_TIMER_COMMAND_REG_KER_STEP 8192 1112#define FR_AA_TIMER_COMMAND_REG_KER_ROWS 4 1113/* 1114 * FR_AB_TIMER_COMMAND_REGP123(128bit): 1115 * Timer Command Registers 1116 */ 1117#define FR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420 1118/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1119#define FR_AB_TIMER_COMMAND_REGP123_STEP 8192 1120#define FR_AB_TIMER_COMMAND_REGP123_ROWS 3072 1121/* 1122 * FR_AA_TIMER_COMMAND_REGP0(128bit): 1123 * Timer Command Registers 1124 */ 1125#define FR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420 1126/* falcona0=char_func_bar0 */ 1127#define FR_AA_TIMER_COMMAND_REGP0_STEP 8192 1128#define FR_AA_TIMER_COMMAND_REGP0_ROWS 1020 1129 1130#define FRF_CZ_TC_TIMER_MODE_LBN 14 1131#define FRF_CZ_TC_TIMER_MODE_WIDTH 2 1132#define FRF_AB_TC_TIMER_MODE_LBN 12 1133#define FRF_AB_TC_TIMER_MODE_WIDTH 2 1134#define FRF_CZ_TC_TIMER_VAL_LBN 0 1135#define FRF_CZ_TC_TIMER_VAL_WIDTH 14 1136#define FRF_AB_TC_TIMER_VAL_LBN 0 1137#define FRF_AB_TC_TIMER_VAL_WIDTH 12 1138 1139/* 1140 * FR_AZ_DRV_EV_REG(128bit): 1141 * Driver generated event register 1142 */ 1143#define FR_AZ_DRV_EV_REG_OFST 0x00000440 1144/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1145 1146#define FRF_AZ_DRV_EV_QID_LBN 64 1147#define FRF_AZ_DRV_EV_QID_WIDTH 12 1148#define FRF_AZ_DRV_EV_DATA_LBN 0 1149#define FRF_AZ_DRV_EV_DATA_WIDTH 64 1150#define FRF_AZ_DRV_EV_DATA_DW0_LBN 0 1151#define FRF_AZ_DRV_EV_DATA_DW0_WIDTH 32 1152#define FRF_AZ_DRV_EV_DATA_DW1_LBN 32 1153#define FRF_AZ_DRV_EV_DATA_DW1_WIDTH 32 1154 1155/* 1156 * FR_AZ_EVQ_CTL_REG(128bit): 1157 * Event queue control register 1158 */ 1159#define FR_AZ_EVQ_CTL_REG_OFST 0x00000450 1160/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1161 1162#define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15 1163#define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10 1164#define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15 1165#define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6 1166#define FRF_AZ_EVQ_OWNERR_CTL_LBN 14 1167#define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1 1168#define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7 1169#define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7 1170#define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0 1171#define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7 1172 1173/* 1174 * FR_AZ_EVQ_CNT1_REG(128bit): 1175 * Event counter 1 register 1176 */ 1177#define FR_AZ_EVQ_CNT1_REG_OFST 0x00000460 1178/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1179 1180#define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120 1181#define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7 1182#define FRF_AZ_EVQ_CNT_TOBIU_LBN 100 1183#define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20 1184#define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80 1185#define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20 1186#define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60 1187#define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20 1188#define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40 1189#define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20 1190#define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20 1191#define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20 1192#define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0 1193#define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20 1194 1195/* 1196 * FR_AZ_EVQ_CNT2_REG(128bit): 1197 * Event counter 2 register 1198 */ 1199#define FR_AZ_EVQ_CNT2_REG_OFST 0x00000470 1200/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1201 1202#define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104 1203#define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20 1204#define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84 1205#define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20 1206#define FRF_AZ_EVQ_RDY_CNT_LBN 80 1207#define FRF_AZ_EVQ_RDY_CNT_WIDTH 4 1208#define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60 1209#define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20 1210#define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40 1211#define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20 1212#define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20 1213#define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20 1214#define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0 1215#define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20 1216 1217/* 1218 * FR_CZ_USR_EV_REG(32bit): 1219 * Event mailbox register 1220 */ 1221#define FR_CZ_USR_EV_REG_OFST 0x00000540 1222/* sienaa0=net_func_bar2 */ 1223#define FR_CZ_USR_EV_REG_STEP 8192 1224#define FR_CZ_USR_EV_REG_ROWS 1024 1225 1226#define FRF_CZ_USR_EV_DATA_LBN 0 1227#define FRF_CZ_USR_EV_DATA_WIDTH 32 1228 1229/* 1230 * FR_AZ_BUF_TBL_CFG_REG(128bit): 1231 * Buffer table configuration register 1232 */ 1233#define FR_AZ_BUF_TBL_CFG_REG_OFST 0x00000600 1234/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1235 1236#define FRF_AZ_BUF_TBL_MODE_LBN 3 1237#define FRF_AZ_BUF_TBL_MODE_WIDTH 1 1238 1239/* 1240 * FR_AZ_SRM_RX_DC_CFG_REG(128bit): 1241 * SRAM receive descriptor cache configuration register 1242 */ 1243#define FR_AZ_SRM_RX_DC_CFG_REG_OFST 0x00000610 1244/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1245 1246#define FRF_AZ_SRM_CLK_TMP_EN_LBN 21 1247#define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1 1248#define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0 1249#define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21 1250 1251/* 1252 * FR_AZ_SRM_TX_DC_CFG_REG(128bit): 1253 * SRAM transmit descriptor cache configuration register 1254 */ 1255#define FR_AZ_SRM_TX_DC_CFG_REG_OFST 0x00000620 1256/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1257 1258#define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0 1259#define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21 1260 1261/* 1262 * FR_AZ_SRM_CFG_REG(128bit): 1263 * SRAM configuration register 1264 */ 1265#define FR_AZ_SRM_CFG_REG_SF_OFST 0x00000380 1266/* falcona0,falconb0=eeprom_flash */ 1267/* 1268 * FR_AZ_SRM_CFG_REG(128bit): 1269 * SRAM configuration register 1270 */ 1271#define FR_AZ_SRM_CFG_REG_OFST 0x00000630 1272/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1273 1274#define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5 1275#define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1 1276#define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4 1277#define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1 1278#define FRF_AZ_SRM_INIT_EN_LBN 3 1279#define FRF_AZ_SRM_INIT_EN_WIDTH 1 1280#define FRF_AZ_SRM_NUM_BANK_LBN 2 1281#define FRF_AZ_SRM_NUM_BANK_WIDTH 1 1282#define FRF_AZ_SRM_BANK_SIZE_LBN 0 1283#define FRF_AZ_SRM_BANK_SIZE_WIDTH 2 1284 1285/* 1286 * FR_AZ_BUF_TBL_UPD_REG(128bit): 1287 * Buffer table update register 1288 */ 1289#define FR_AZ_BUF_TBL_UPD_REG_OFST 0x00000650 1290/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1291 1292#define FRF_AZ_BUF_UPD_CMD_LBN 63 1293#define FRF_AZ_BUF_UPD_CMD_WIDTH 1 1294#define FRF_AZ_BUF_CLR_CMD_LBN 62 1295#define FRF_AZ_BUF_CLR_CMD_WIDTH 1 1296#define FRF_AZ_BUF_CLR_END_ID_LBN 32 1297#define FRF_AZ_BUF_CLR_END_ID_WIDTH 20 1298#define FRF_AZ_BUF_CLR_START_ID_LBN 0 1299#define FRF_AZ_BUF_CLR_START_ID_WIDTH 20 1300 1301/* 1302 * FR_AZ_SRM_UPD_EVQ_REG(128bit): 1303 * Buffer table update register 1304 */ 1305#define FR_AZ_SRM_UPD_EVQ_REG_OFST 0x00000660 1306/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1307 1308#define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0 1309#define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12 1310 1311/* 1312 * FR_AZ_SRAM_PARITY_REG(128bit): 1313 * SRAM parity register. 1314 */ 1315#define FR_AZ_SRAM_PARITY_REG_OFST 0x00000670 1316/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1317 1318#define FRF_CZ_BYPASS_ECC_LBN 3 1319#define FRF_CZ_BYPASS_ECC_WIDTH 1 1320#define FRF_CZ_SEC_INT_LBN 2 1321#define FRF_CZ_SEC_INT_WIDTH 1 1322#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1 1323#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1 1324#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0 1325#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1 1326#define FRF_AB_FORCE_SRAM_PERR_LBN 0 1327#define FRF_AB_FORCE_SRAM_PERR_WIDTH 1 1328 1329/* 1330 * FR_AZ_RX_CFG_REG(128bit): 1331 * Receive configuration register 1332 */ 1333#define FR_AZ_RX_CFG_REG_OFST 0x00000800 1334/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1335 1336#define FRF_CZ_RX_HDR_SPLIT_EN_LBN 71 1337#define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1 1338#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62 1339#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9 1340#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53 1341#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9 1342#define FRF_CZ_RX_PRE_RFF_IPG_LBN 49 1343#define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4 1344#define FRF_BZ_RX_TCP_SUP_LBN 48 1345#define FRF_BZ_RX_TCP_SUP_WIDTH 1 1346#define FRF_BZ_RX_INGR_EN_LBN 47 1347#define FRF_BZ_RX_INGR_EN_WIDTH 1 1348#define FRF_BZ_RX_IP_HASH_LBN 46 1349#define FRF_BZ_RX_IP_HASH_WIDTH 1 1350#define FRF_BZ_RX_HASH_ALG_LBN 45 1351#define FRF_BZ_RX_HASH_ALG_WIDTH 1 1352#define FRF_BZ_RX_HASH_INSRT_HDR_LBN 44 1353#define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1 1354#define FRF_BZ_RX_DESC_PUSH_EN_LBN 43 1355#define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1 1356#define FRF_BZ_RX_RDW_PATCH_EN_LBN 42 1357#define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1 1358#define FRF_BB_RX_PCI_BURST_SIZE_LBN 39 1359#define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3 1360#define FRF_BZ_RX_OWNERR_CTL_LBN 38 1361#define FRF_BZ_RX_OWNERR_CTL_WIDTH 1 1362#define FRF_BZ_RX_XON_TX_TH_LBN 33 1363#define FRF_BZ_RX_XON_TX_TH_WIDTH 5 1364#define FRF_AA_RX_DESC_PUSH_EN_LBN 35 1365#define FRF_AA_RX_DESC_PUSH_EN_WIDTH 1 1366#define FRF_AA_RX_RDW_PATCH_EN_LBN 34 1367#define FRF_AA_RX_RDW_PATCH_EN_WIDTH 1 1368#define FRF_AA_RX_PCI_BURST_SIZE_LBN 31 1369#define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3 1370#define FRF_BZ_RX_XOFF_TX_TH_LBN 28 1371#define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5 1372#define FRF_AA_RX_OWNERR_CTL_LBN 30 1373#define FRF_AA_RX_OWNERR_CTL_WIDTH 1 1374#define FRF_AA_RX_XON_TX_TH_LBN 25 1375#define FRF_AA_RX_XON_TX_TH_WIDTH 5 1376#define FRF_BZ_RX_USR_BUF_SIZE_LBN 19 1377#define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9 1378#define FRF_AA_RX_XOFF_TX_TH_LBN 20 1379#define FRF_AA_RX_XOFF_TX_TH_WIDTH 5 1380#define FRF_AA_RX_USR_BUF_SIZE_LBN 11 1381#define FRF_AA_RX_USR_BUF_SIZE_WIDTH 9 1382#define FRF_BZ_RX_XON_MAC_TH_LBN 10 1383#define FRF_BZ_RX_XON_MAC_TH_WIDTH 9 1384#define FRF_AA_RX_XON_MAC_TH_LBN 6 1385#define FRF_AA_RX_XON_MAC_TH_WIDTH 5 1386#define FRF_BZ_RX_XOFF_MAC_TH_LBN 1 1387#define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9 1388#define FRF_AA_RX_XOFF_MAC_TH_LBN 1 1389#define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5 1390#define FRF_AZ_RX_XOFF_MAC_EN_LBN 0 1391#define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1 1392 1393/* 1394 * FR_AZ_RX_FILTER_CTL_REG(128bit): 1395 * Receive filter control registers 1396 */ 1397#define FR_AZ_RX_FILTER_CTL_REG_OFST 0x00000810 1398/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1399 1400#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94 1401#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8 1402#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86 1403#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8 1404#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85 1405#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1 1406#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69 1407#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16 1408#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57 1409#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12 1410#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56 1411#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1412#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55 1413#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1414#define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43 1415#define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12 1416#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42 1417#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1418#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41 1419#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1420#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40 1421#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1 1422#define FRF_AZ_UDP_FULL_SRCH_LIMIT_LBN 32 1423#define FRF_AZ_UDP_FULL_SRCH_LIMIT_WIDTH 8 1424#define FRF_AZ_NUM_KER_LBN 24 1425#define FRF_AZ_NUM_KER_WIDTH 2 1426#define FRF_AZ_UDP_WILD_SRCH_LIMIT_LBN 16 1427#define FRF_AZ_UDP_WILD_SRCH_LIMIT_WIDTH 8 1428#define FRF_AZ_TCP_WILD_SRCH_LIMIT_LBN 8 1429#define FRF_AZ_TCP_WILD_SRCH_LIMIT_WIDTH 8 1430#define FRF_AZ_TCP_FULL_SRCH_LIMIT_LBN 0 1431#define FRF_AZ_TCP_FULL_SRCH_LIMIT_WIDTH 8 1432 1433/* 1434 * FR_AZ_RX_FLUSH_DESCQ_REG(128bit): 1435 * Receive flush descriptor queue register 1436 */ 1437#define FR_AZ_RX_FLUSH_DESCQ_REG_OFST 0x00000820 1438/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1439 1440#define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24 1441#define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1 1442#define FRF_AZ_RX_FLUSH_DESCQ_LBN 0 1443#define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12 1444 1445/* 1446 * FR_BZ_RX_DESC_UPD_REGP0(128bit): 1447 * Receive descriptor update register. 1448 */ 1449#define FR_BZ_RX_DESC_UPD_REGP0_OFST 0x00000830 1450/* falconb0,sienaa0=net_func_bar2 */ 1451#define FR_BZ_RX_DESC_UPD_REGP0_STEP 8192 1452#define FR_BZ_RX_DESC_UPD_REGP0_ROWS 1024 1453/* 1454 * FR_AA_RX_DESC_UPD_REG_KER(128bit): 1455 * Receive descriptor update register. 1456 */ 1457#define FR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830 1458/* falcona0=net_func_bar2 */ 1459#define FR_AA_RX_DESC_UPD_REG_KER_STEP 8192 1460#define FR_AA_RX_DESC_UPD_REG_KER_ROWS 4 1461/* 1462 * FR_AB_RX_DESC_UPD_REGP123(128bit): 1463 * Receive descriptor update register. 1464 */ 1465#define FR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830 1466/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1467#define FR_AB_RX_DESC_UPD_REGP123_STEP 8192 1468#define FR_AB_RX_DESC_UPD_REGP123_ROWS 3072 1469/* 1470 * FR_AA_RX_DESC_UPD_REGP0(128bit): 1471 * Receive descriptor update register. 1472 */ 1473#define FR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830 1474/* falcona0=char_func_bar0 */ 1475#define FR_AA_RX_DESC_UPD_REGP0_STEP 8192 1476#define FR_AA_RX_DESC_UPD_REGP0_ROWS 1020 1477 1478#define FRF_AZ_RX_DESC_WPTR_LBN 96 1479#define FRF_AZ_RX_DESC_WPTR_WIDTH 12 1480#define FRF_AZ_RX_DESC_PUSH_CMD_LBN 95 1481#define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1 1482#define FRF_AZ_RX_DESC_LBN 0 1483#define FRF_AZ_RX_DESC_WIDTH 64 1484#define FRF_AZ_RX_DESC_DW0_LBN 0 1485#define FRF_AZ_RX_DESC_DW0_WIDTH 32 1486#define FRF_AZ_RX_DESC_DW1_LBN 32 1487#define FRF_AZ_RX_DESC_DW1_WIDTH 32 1488 1489/* 1490 * FR_AZ_RX_DC_CFG_REG(128bit): 1491 * Receive descriptor cache configuration register 1492 */ 1493#define FR_AZ_RX_DC_CFG_REG_OFST 0x00000840 1494/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1495 1496#define FRF_AZ_RX_MAX_PF_LBN 2 1497#define FRF_AZ_RX_MAX_PF_WIDTH 2 1498#define FRF_AZ_RX_DC_SIZE_LBN 0 1499#define FRF_AZ_RX_DC_SIZE_WIDTH 2 1500#define FFE_AZ_RX_DC_SIZE_64 3 1501#define FFE_AZ_RX_DC_SIZE_32 2 1502#define FFE_AZ_RX_DC_SIZE_16 1 1503#define FFE_AZ_RX_DC_SIZE_8 0 1504 1505/* 1506 * FR_AZ_RX_DC_PF_WM_REG(128bit): 1507 * Receive descriptor cache pre-fetch watermark register 1508 */ 1509#define FR_AZ_RX_DC_PF_WM_REG_OFST 0x00000850 1510/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1511 1512#define FRF_AZ_RX_DC_PF_HWM_LBN 6 1513#define FRF_AZ_RX_DC_PF_HWM_WIDTH 6 1514#define FRF_AZ_RX_DC_PF_LWM_LBN 0 1515#define FRF_AZ_RX_DC_PF_LWM_WIDTH 6 1516 1517/* 1518 * FR_BZ_RX_RSS_TKEY_REG(128bit): 1519 * RSS Toeplitz hash key 1520 */ 1521#define FR_BZ_RX_RSS_TKEY_REG_OFST 0x00000860 1522/* falconb0,sienaa0=net_func_bar2 */ 1523 1524#define FRF_BZ_RX_RSS_TKEY_LBN 96 1525#define FRF_BZ_RX_RSS_TKEY_WIDTH 32 1526#define FRF_BZ_RX_RSS_TKEY_DW3_LBN 96 1527#define FRF_BZ_RX_RSS_TKEY_DW3_WIDTH 32 1528#define FRF_BZ_RX_RSS_TKEY_DW2_LBN 64 1529#define FRF_BZ_RX_RSS_TKEY_DW2_WIDTH 32 1530#define FRF_BZ_RX_RSS_TKEY_DW1_LBN 32 1531#define FRF_BZ_RX_RSS_TKEY_DW1_WIDTH 32 1532#define FRF_BZ_RX_RSS_TKEY_DW0_LBN 0 1533#define FRF_BZ_RX_RSS_TKEY_DW0_WIDTH 32 1534 1535/* 1536 * FR_AZ_RX_NODESC_DROP_REG(128bit): 1537 * Receive dropped packet counter register 1538 */ 1539#define FR_AZ_RX_NODESC_DROP_REG_OFST 0x00000880 1540/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1541 1542#define FRF_AZ_RX_NODESC_DROP_CNT_LBN 0 1543#define FRF_AZ_RX_NODESC_DROP_CNT_WIDTH 16 1544 1545/* 1546 * FR_AZ_RX_SELF_RST_REG(128bit): 1547 * Receive self reset register 1548 */ 1549#define FR_AZ_RX_SELF_RST_REG_OFST 0x00000890 1550/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1551 1552#define FRF_AZ_RX_ISCSI_DIS_LBN 17 1553#define FRF_AZ_RX_ISCSI_DIS_WIDTH 1 1554#define FRF_AB_RX_SW_RST_REG_LBN 16 1555#define FRF_AB_RX_SW_RST_REG_WIDTH 1 1556#define FRF_AB_RX_SELF_RST_EN_LBN 8 1557#define FRF_AB_RX_SELF_RST_EN_WIDTH 1 1558#define FRF_AZ_RX_MAX_PF_LAT_LBN 4 1559#define FRF_AZ_RX_MAX_PF_LAT_WIDTH 4 1560#define FRF_AZ_RX_MAX_LU_LAT_LBN 0 1561#define FRF_AZ_RX_MAX_LU_LAT_WIDTH 4 1562 1563/* 1564 * FR_AZ_RX_DEBUG_REG(128bit): 1565 * undocumented register 1566 */ 1567#define FR_AZ_RX_DEBUG_REG_OFST 0x000008a0 1568/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1569 1570#define FRF_AZ_RX_DEBUG_LBN 0 1571#define FRF_AZ_RX_DEBUG_WIDTH 64 1572#define FRF_AZ_RX_DEBUG_DW0_LBN 0 1573#define FRF_AZ_RX_DEBUG_DW0_WIDTH 32 1574#define FRF_AZ_RX_DEBUG_DW1_LBN 32 1575#define FRF_AZ_RX_DEBUG_DW1_WIDTH 32 1576 1577/* 1578 * FR_AZ_RX_PUSH_DROP_REG(128bit): 1579 * Receive descriptor push dropped counter register 1580 */ 1581#define FR_AZ_RX_PUSH_DROP_REG_OFST 0x000008b0 1582/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1583 1584#define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0 1585#define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32 1586 1587/* 1588 * FR_CZ_RX_RSS_IPV6_REG1(128bit): 1589 * IPv6 RSS Toeplitz hash key low bytes 1590 */ 1591#define FR_CZ_RX_RSS_IPV6_REG1_OFST 0x000008d0 1592/* sienaa0=net_func_bar2 */ 1593 1594#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0 1595#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128 1596#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_LBN 0 1597#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_WIDTH 32 1598#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_LBN 32 1599#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_WIDTH 32 1600#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_LBN 64 1601#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_WIDTH 32 1602#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_LBN 96 1603#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_WIDTH 32 1604 1605/* 1606 * FR_CZ_RX_RSS_IPV6_REG2(128bit): 1607 * IPv6 RSS Toeplitz hash key middle bytes 1608 */ 1609#define FR_CZ_RX_RSS_IPV6_REG2_OFST 0x000008e0 1610/* sienaa0=net_func_bar2 */ 1611 1612#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0 1613#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128 1614#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_LBN 0 1615#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_WIDTH 32 1616#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_LBN 32 1617#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_WIDTH 32 1618#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_LBN 64 1619#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_WIDTH 32 1620#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_LBN 96 1621#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_WIDTH 32 1622 1623/* 1624 * FR_CZ_RX_RSS_IPV6_REG3(128bit): 1625 * IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings 1626 */ 1627#define FR_CZ_RX_RSS_IPV6_REG3_OFST 0x000008f0 1628/* sienaa0=net_func_bar2 */ 1629 1630#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66 1631#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1 1632#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65 1633#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1 1634#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64 1635#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1 1636#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0 1637#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64 1638#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_LBN 0 1639#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_WIDTH 32 1640#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_LBN 32 1641#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_WIDTH 32 1642 1643/* 1644 * FR_AZ_TX_FLUSH_DESCQ_REG(128bit): 1645 * Transmit flush descriptor queue register 1646 */ 1647#define FR_AZ_TX_FLUSH_DESCQ_REG_OFST 0x00000a00 1648/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1649 1650#define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12 1651#define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1 1652#define FRF_AZ_TX_FLUSH_DESCQ_LBN 0 1653#define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12 1654 1655/* 1656 * FR_BZ_TX_DESC_UPD_REGP0(128bit): 1657 * Transmit descriptor update register. 1658 */ 1659#define FR_BZ_TX_DESC_UPD_REGP0_OFST 0x00000a10 1660/* falconb0,sienaa0=net_func_bar2 */ 1661#define FR_BZ_TX_DESC_UPD_REGP0_STEP 8192 1662#define FR_BZ_TX_DESC_UPD_REGP0_ROWS 1024 1663/* 1664 * FR_AA_TX_DESC_UPD_REG_KER(128bit): 1665 * Transmit descriptor update register. 1666 */ 1667#define FR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10 1668/* falcona0=net_func_bar2 */ 1669#define FR_AA_TX_DESC_UPD_REG_KER_STEP 8192 1670#define FR_AA_TX_DESC_UPD_REG_KER_ROWS 8 1671/* 1672 * FR_AB_TX_DESC_UPD_REGP123(128bit): 1673 * Transmit descriptor update register. 1674 */ 1675#define FR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10 1676/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1677#define FR_AB_TX_DESC_UPD_REGP123_STEP 8192 1678#define FR_AB_TX_DESC_UPD_REGP123_ROWS 3072 1679/* 1680 * FR_AA_TX_DESC_UPD_REGP0(128bit): 1681 * Transmit descriptor update register. 1682 */ 1683#define FR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10 1684/* falcona0=char_func_bar0 */ 1685#define FR_AA_TX_DESC_UPD_REGP0_STEP 8192 1686#define FR_AA_TX_DESC_UPD_REGP0_ROWS 1020 1687 1688#define FRF_AZ_TX_DESC_WPTR_LBN 96 1689#define FRF_AZ_TX_DESC_WPTR_WIDTH 12 1690#define FRF_AZ_TX_DESC_PUSH_CMD_LBN 95 1691#define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1 1692#define FRF_AZ_TX_DESC_LBN 0 1693#define FRF_AZ_TX_DESC_WIDTH 95 1694#define FRF_AZ_TX_DESC_DW0_LBN 0 1695#define FRF_AZ_TX_DESC_DW0_WIDTH 32 1696#define FRF_AZ_TX_DESC_DW1_LBN 32 1697#define FRF_AZ_TX_DESC_DW1_WIDTH 32 1698#define FRF_AZ_TX_DESC_DW2_LBN 64 1699#define FRF_AZ_TX_DESC_DW2_WIDTH 31 1700 1701/* 1702 * FR_AZ_TX_DC_CFG_REG(128bit): 1703 * Transmit descriptor cache configuration register 1704 */ 1705#define FR_AZ_TX_DC_CFG_REG_OFST 0x00000a20 1706/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1707 1708#define FRF_AZ_TX_DC_SIZE_LBN 0 1709#define FRF_AZ_TX_DC_SIZE_WIDTH 2 1710#define FFE_AZ_TX_DC_SIZE_32 2 1711#define FFE_AZ_TX_DC_SIZE_16 1 1712#define FFE_AZ_TX_DC_SIZE_8 0 1713 1714/* 1715 * FR_AA_TX_CHKSM_CFG_REG(128bit): 1716 * Transmit checksum configuration register 1717 */ 1718#define FR_AA_TX_CHKSM_CFG_REG_OFST 0x00000a30 1719/* falcona0=net_func_bar2,falcona0=char_func_bar0 */ 1720 1721#define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96 1722#define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32 1723#define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64 1724#define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32 1725#define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32 1726#define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32 1727#define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0 1728#define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32 1729 1730/* 1731 * FR_AZ_TX_CFG_REG(128bit): 1732 * Transmit configuration register 1733 */ 1734#define FR_AZ_TX_CFG_REG_OFST 0x00000a50 1735/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1736 1737#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114 1738#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8 1739#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113 1740#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1 1741#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105 1742#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1743#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97 1744#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1745#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89 1746#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1747#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81 1748#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1749#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73 1750#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1751#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65 1752#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1753#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64 1754#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1 1755#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48 1756#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16 1757#define FRF_CZ_TX_FILTER_EN_BIT_LBN 47 1758#define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1 1759#define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16 1760#define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15 1761#define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5 1762#define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1 1763#define FRF_AZ_TX_P1_PRI_EN_LBN 4 1764#define FRF_AZ_TX_P1_PRI_EN_WIDTH 1 1765#define FRF_AZ_TX_OWNERR_CTL_LBN 2 1766#define FRF_AZ_TX_OWNERR_CTL_WIDTH 1 1767#define FRF_AA_TX_NON_IP_DROP_DIS_LBN 1 1768#define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1 1769#define FRF_AZ_TX_IP_ID_REP_EN_LBN 0 1770#define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1 1771 1772/* 1773 * FR_AZ_TX_PUSH_DROP_REG(128bit): 1774 * Transmit push dropped register 1775 */ 1776#define FR_AZ_TX_PUSH_DROP_REG_OFST 0x00000a60 1777/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1778 1779#define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0 1780#define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32 1781 1782/* 1783 * FR_AZ_TX_RESERVED_REG(128bit): 1784 * Transmit configuration register 1785 */ 1786#define FR_AZ_TX_RESERVED_REG_OFST 0x00000a80 1787/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1788 1789#define FRF_AZ_TX_EVT_CNT_LBN 121 1790#define FRF_AZ_TX_EVT_CNT_WIDTH 7 1791#define FRF_AZ_TX_PREF_AGE_CNT_LBN 119 1792#define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2 1793#define FRF_AZ_TX_RD_COMP_TMR_LBN 96 1794#define FRF_AZ_TX_RD_COMP_TMR_WIDTH 23 1795#define FRF_AZ_TX_PUSH_EN_LBN 89 1796#define FRF_AZ_TX_PUSH_EN_WIDTH 1 1797#define FRF_AZ_TX_PUSH_CHK_DIS_LBN 88 1798#define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1 1799#define FRF_AZ_TX_D_FF_FULL_P0_LBN 85 1800#define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1 1801#define FRF_AZ_TX_DMAR_ST_P0_LBN 81 1802#define FRF_AZ_TX_DMAR_ST_P0_WIDTH 1 1803#define FRF_AZ_TX_DMAQ_ST_LBN 78 1804#define FRF_AZ_TX_DMAQ_ST_WIDTH 1 1805#define FRF_AZ_TX_RX_SPACER_LBN 64 1806#define FRF_AZ_TX_RX_SPACER_WIDTH 8 1807#define FRF_AZ_TX_DROP_ABORT_EN_LBN 60 1808#define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1 1809#define FRF_AZ_TX_SOFT_EVT_EN_LBN 59 1810#define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1 1811#define FRF_AZ_TX_PS_EVT_DIS_LBN 58 1812#define FRF_AZ_TX_PS_EVT_DIS_WIDTH 1 1813#define FRF_AZ_TX_RX_SPACER_EN_LBN 57 1814#define FRF_AZ_TX_RX_SPACER_EN_WIDTH 1 1815#define FRF_AZ_TX_XP_TIMER_LBN 52 1816#define FRF_AZ_TX_XP_TIMER_WIDTH 5 1817#define FRF_AZ_TX_PREF_SPACER_LBN 44 1818#define FRF_AZ_TX_PREF_SPACER_WIDTH 8 1819#define FRF_AZ_TX_PREF_WD_TMR_LBN 22 1820#define FRF_AZ_TX_PREF_WD_TMR_WIDTH 22 1821#define FRF_AZ_TX_ONLY1TAG_LBN 21 1822#define FRF_AZ_TX_ONLY1TAG_WIDTH 1 1823#define FRF_AZ_TX_PREF_THRESHOLD_LBN 19 1824#define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2 1825#define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18 1826#define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1 1827#define FRF_AZ_TX_DIS_NON_IP_EV_LBN 17 1828#define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1 1829#define FRF_AA_TX_DMA_FF_THR_LBN 16 1830#define FRF_AA_TX_DMA_FF_THR_WIDTH 1 1831#define FRF_AZ_TX_DMA_SPACER_LBN 8 1832#define FRF_AZ_TX_DMA_SPACER_WIDTH 8 1833#define FRF_AA_TX_TCP_DIS_LBN 7 1834#define FRF_AA_TX_TCP_DIS_WIDTH 1 1835#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7 1836#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1 1837#define FRF_AA_TX_IP_DIS_LBN 6 1838#define FRF_AA_TX_IP_DIS_WIDTH 1 1839#define FRF_AZ_TX_MAX_CPL_LBN 2 1840#define FRF_AZ_TX_MAX_CPL_WIDTH 2 1841#define FFE_AZ_TX_MAX_CPL_16 3 1842#define FFE_AZ_TX_MAX_CPL_8 2 1843#define FFE_AZ_TX_MAX_CPL_4 1 1844#define FFE_AZ_TX_MAX_CPL_NOLIMIT 0 1845#define FRF_AZ_TX_MAX_PREF_LBN 0 1846#define FRF_AZ_TX_MAX_PREF_WIDTH 2 1847#define FFE_AZ_TX_MAX_PREF_32 3 1848#define FFE_AZ_TX_MAX_PREF_16 2 1849#define FFE_AZ_TX_MAX_PREF_8 1 1850#define FFE_AZ_TX_MAX_PREF_OFF 0 1851 1852/* 1853 * FR_BZ_TX_PACE_REG(128bit): 1854 * Transmit pace control register 1855 */ 1856#define FR_BZ_TX_PACE_REG_OFST 0x00000a90 1857/* falconb0,sienaa0=net_func_bar2 */ 1858/* 1859 * FR_AA_TX_PACE_REG(128bit): 1860 * Transmit pace control register 1861 */ 1862#define FR_AA_TX_PACE_REG_OFST 0x00f80000 1863/* falcona0=char_func_bar0 */ 1864 1865#define FRF_AZ_TX_PACE_SB_NOT_AF_LBN 19 1866#define FRF_AZ_TX_PACE_SB_NOT_AF_WIDTH 10 1867#define FRF_AZ_TX_PACE_SB_AF_LBN 9 1868#define FRF_AZ_TX_PACE_SB_AF_WIDTH 10 1869#define FRF_AZ_TX_PACE_FB_BASE_LBN 5 1870#define FRF_AZ_TX_PACE_FB_BASE_WIDTH 4 1871#define FRF_AZ_TX_PACE_BIN_TH_LBN 0 1872#define FRF_AZ_TX_PACE_BIN_TH_WIDTH 5 1873 1874/* 1875 * FR_AZ_TX_PACE_DROP_QID_REG(128bit): 1876 * PACE Drop QID Counter 1877 */ 1878#define FR_AZ_TX_PACE_DROP_QID_REG_OFST 0x00000aa0 1879/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1880 1881#define FRF_AZ_TX_PACE_QID_DRP_CNT_LBN 0 1882#define FRF_AZ_TX_PACE_QID_DRP_CNT_WIDTH 16 1883 1884/* 1885 * FR_AB_TX_VLAN_REG(128bit): 1886 * Transmit VLAN tag register 1887 */ 1888#define FR_AB_TX_VLAN_REG_OFST 0x00000ae0 1889/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1890 1891#define FRF_AB_TX_VLAN_EN_LBN 127 1892#define FRF_AB_TX_VLAN_EN_WIDTH 1 1893#define FRF_AB_TX_VLAN7_PORT1_EN_LBN 125 1894#define FRF_AB_TX_VLAN7_PORT1_EN_WIDTH 1 1895#define FRF_AB_TX_VLAN7_PORT0_EN_LBN 124 1896#define FRF_AB_TX_VLAN7_PORT0_EN_WIDTH 1 1897#define FRF_AB_TX_VLAN7_LBN 112 1898#define FRF_AB_TX_VLAN7_WIDTH 12 1899#define FRF_AB_TX_VLAN6_PORT1_EN_LBN 109 1900#define FRF_AB_TX_VLAN6_PORT1_EN_WIDTH 1 1901#define FRF_AB_TX_VLAN6_PORT0_EN_LBN 108 1902#define FRF_AB_TX_VLAN6_PORT0_EN_WIDTH 1 1903#define FRF_AB_TX_VLAN6_LBN 96 1904#define FRF_AB_TX_VLAN6_WIDTH 12 1905#define FRF_AB_TX_VLAN5_PORT1_EN_LBN 93 1906#define FRF_AB_TX_VLAN5_PORT1_EN_WIDTH 1 1907#define FRF_AB_TX_VLAN5_PORT0_EN_LBN 92 1908#define FRF_AB_TX_VLAN5_PORT0_EN_WIDTH 1 1909#define FRF_AB_TX_VLAN5_LBN 80 1910#define FRF_AB_TX_VLAN5_WIDTH 12 1911#define FRF_AB_TX_VLAN4_PORT1_EN_LBN 77 1912#define FRF_AB_TX_VLAN4_PORT1_EN_WIDTH 1 1913#define FRF_AB_TX_VLAN4_PORT0_EN_LBN 76 1914#define FRF_AB_TX_VLAN4_PORT0_EN_WIDTH 1 1915#define FRF_AB_TX_VLAN4_LBN 64 1916#define FRF_AB_TX_VLAN4_WIDTH 12 1917#define FRF_AB_TX_VLAN3_PORT1_EN_LBN 61 1918#define FRF_AB_TX_VLAN3_PORT1_EN_WIDTH 1 1919#define FRF_AB_TX_VLAN3_PORT0_EN_LBN 60 1920#define FRF_AB_TX_VLAN3_PORT0_EN_WIDTH 1 1921#define FRF_AB_TX_VLAN3_LBN 48 1922#define FRF_AB_TX_VLAN3_WIDTH 12 1923#define FRF_AB_TX_VLAN2_PORT1_EN_LBN 45 1924#define FRF_AB_TX_VLAN2_PORT1_EN_WIDTH 1 1925#define FRF_AB_TX_VLAN2_PORT0_EN_LBN 44 1926#define FRF_AB_TX_VLAN2_PORT0_EN_WIDTH 1 1927#define FRF_AB_TX_VLAN2_LBN 32 1928#define FRF_AB_TX_VLAN2_WIDTH 12 1929#define FRF_AB_TX_VLAN1_PORT1_EN_LBN 29 1930#define FRF_AB_TX_VLAN1_PORT1_EN_WIDTH 1 1931#define FRF_AB_TX_VLAN1_PORT0_EN_LBN 28 1932#define FRF_AB_TX_VLAN1_PORT0_EN_WIDTH 1 1933#define FRF_AB_TX_VLAN1_LBN 16 1934#define FRF_AB_TX_VLAN1_WIDTH 12 1935#define FRF_AB_TX_VLAN0_PORT1_EN_LBN 13 1936#define FRF_AB_TX_VLAN0_PORT1_EN_WIDTH 1 1937#define FRF_AB_TX_VLAN0_PORT0_EN_LBN 12 1938#define FRF_AB_TX_VLAN0_PORT0_EN_WIDTH 1 1939#define FRF_AB_TX_VLAN0_LBN 0 1940#define FRF_AB_TX_VLAN0_WIDTH 12 1941 1942/* 1943 * FR_AZ_TX_IPFIL_PORTEN_REG(128bit): 1944 * Transmit filter control register 1945 */ 1946#define FR_AZ_TX_IPFIL_PORTEN_REG_OFST 0x00000af0 1947/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1948 1949#define FRF_AZ_TX_MADR0_FIL_EN_LBN 64 1950#define FRF_AZ_TX_MADR0_FIL_EN_WIDTH 1 1951#define FRF_AB_TX_IPFIL31_PORT_EN_LBN 62 1952#define FRF_AB_TX_IPFIL31_PORT_EN_WIDTH 1 1953#define FRF_AB_TX_IPFIL30_PORT_EN_LBN 60 1954#define FRF_AB_TX_IPFIL30_PORT_EN_WIDTH 1 1955#define FRF_AB_TX_IPFIL29_PORT_EN_LBN 58 1956#define FRF_AB_TX_IPFIL29_PORT_EN_WIDTH 1 1957#define FRF_AB_TX_IPFIL28_PORT_EN_LBN 56 1958#define FRF_AB_TX_IPFIL28_PORT_EN_WIDTH 1 1959#define FRF_AB_TX_IPFIL27_PORT_EN_LBN 54 1960#define FRF_AB_TX_IPFIL27_PORT_EN_WIDTH 1 1961#define FRF_AB_TX_IPFIL26_PORT_EN_LBN 52 1962#define FRF_AB_TX_IPFIL26_PORT_EN_WIDTH 1 1963#define FRF_AB_TX_IPFIL25_PORT_EN_LBN 50 1964#define FRF_AB_TX_IPFIL25_PORT_EN_WIDTH 1 1965#define FRF_AB_TX_IPFIL24_PORT_EN_LBN 48 1966#define FRF_AB_TX_IPFIL24_PORT_EN_WIDTH 1 1967#define FRF_AB_TX_IPFIL23_PORT_EN_LBN 46 1968#define FRF_AB_TX_IPFIL23_PORT_EN_WIDTH 1 1969#define FRF_AB_TX_IPFIL22_PORT_EN_LBN 44 1970#define FRF_AB_TX_IPFIL22_PORT_EN_WIDTH 1 1971#define FRF_AB_TX_IPFIL21_PORT_EN_LBN 42 1972#define FRF_AB_TX_IPFIL21_PORT_EN_WIDTH 1 1973#define FRF_AB_TX_IPFIL20_PORT_EN_LBN 40 1974#define FRF_AB_TX_IPFIL20_PORT_EN_WIDTH 1 1975#define FRF_AB_TX_IPFIL19_PORT_EN_LBN 38 1976#define FRF_AB_TX_IPFIL19_PORT_EN_WIDTH 1 1977#define FRF_AB_TX_IPFIL18_PORT_EN_LBN 36 1978#define FRF_AB_TX_IPFIL18_PORT_EN_WIDTH 1 1979#define FRF_AB_TX_IPFIL17_PORT_EN_LBN 34 1980#define FRF_AB_TX_IPFIL17_PORT_EN_WIDTH 1 1981#define FRF_AB_TX_IPFIL16_PORT_EN_LBN 32 1982#define FRF_AB_TX_IPFIL16_PORT_EN_WIDTH 1 1983#define FRF_AB_TX_IPFIL15_PORT_EN_LBN 30 1984#define FRF_AB_TX_IPFIL15_PORT_EN_WIDTH 1 1985#define FRF_AB_TX_IPFIL14_PORT_EN_LBN 28 1986#define FRF_AB_TX_IPFIL14_PORT_EN_WIDTH 1 1987#define FRF_AB_TX_IPFIL13_PORT_EN_LBN 26 1988#define FRF_AB_TX_IPFIL13_PORT_EN_WIDTH 1 1989#define FRF_AB_TX_IPFIL12_PORT_EN_LBN 24 1990#define FRF_AB_TX_IPFIL12_PORT_EN_WIDTH 1 1991#define FRF_AB_TX_IPFIL11_PORT_EN_LBN 22 1992#define FRF_AB_TX_IPFIL11_PORT_EN_WIDTH 1 1993#define FRF_AB_TX_IPFIL10_PORT_EN_LBN 20 1994#define FRF_AB_TX_IPFIL10_PORT_EN_WIDTH 1 1995#define FRF_AB_TX_IPFIL9_PORT_EN_LBN 18 1996#define FRF_AB_TX_IPFIL9_PORT_EN_WIDTH 1 1997#define FRF_AB_TX_IPFIL8_PORT_EN_LBN 16 1998#define FRF_AB_TX_IPFIL8_PORT_EN_WIDTH 1 1999#define FRF_AB_TX_IPFIL7_PORT_EN_LBN 14 2000#define FRF_AB_TX_IPFIL7_PORT_EN_WIDTH 1 2001#define FRF_AB_TX_IPFIL6_PORT_EN_LBN 12 2002#define FRF_AB_TX_IPFIL6_PORT_EN_WIDTH 1 2003#define FRF_AB_TX_IPFIL5_PORT_EN_LBN 10 2004#define FRF_AB_TX_IPFIL5_PORT_EN_WIDTH 1 2005#define FRF_AB_TX_IPFIL4_PORT_EN_LBN 8 2006#define FRF_AB_TX_IPFIL4_PORT_EN_WIDTH 1 2007#define FRF_AB_TX_IPFIL3_PORT_EN_LBN 6 2008#define FRF_AB_TX_IPFIL3_PORT_EN_WIDTH 1 2009#define FRF_AB_TX_IPFIL2_PORT_EN_LBN 4 2010#define FRF_AB_TX_IPFIL2_PORT_EN_WIDTH 1 2011#define FRF_AB_TX_IPFIL1_PORT_EN_LBN 2 2012#define FRF_AB_TX_IPFIL1_PORT_EN_WIDTH 1 2013#define FRF_AB_TX_IPFIL0_PORT_EN_LBN 0 2014#define FRF_AB_TX_IPFIL0_PORT_EN_WIDTH 1 2015 2016/* 2017 * FR_AB_TX_IPFIL_TBL(128bit): 2018 * Transmit IP source address filter table 2019 */ 2020#define FR_AB_TX_IPFIL_TBL_OFST 0x00000b00 2021/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2022#define FR_AB_TX_IPFIL_TBL_STEP 16 2023#define FR_AB_TX_IPFIL_TBL_ROWS 16 2024 2025#define FRF_AB_TX_IPFIL_MASK_1_LBN 96 2026#define FRF_AB_TX_IPFIL_MASK_1_WIDTH 32 2027#define FRF_AB_TX_IP_SRC_ADR_1_LBN 64 2028#define FRF_AB_TX_IP_SRC_ADR_1_WIDTH 32 2029#define FRF_AB_TX_IPFIL_MASK_0_LBN 32 2030#define FRF_AB_TX_IPFIL_MASK_0_WIDTH 32 2031#define FRF_AB_TX_IP_SRC_ADR_0_LBN 0 2032#define FRF_AB_TX_IP_SRC_ADR_0_WIDTH 32 2033 2034/* 2035 * FR_AB_MD_TXD_REG(128bit): 2036 * PHY management transmit data register 2037 */ 2038#define FR_AB_MD_TXD_REG_OFST 0x00000c00 2039/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2040 2041#define FRF_AB_MD_TXD_LBN 0 2042#define FRF_AB_MD_TXD_WIDTH 16 2043 2044/* 2045 * FR_AB_MD_RXD_REG(128bit): 2046 * PHY management receive data register 2047 */ 2048#define FR_AB_MD_RXD_REG_OFST 0x00000c10 2049/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2050 2051#define FRF_AB_MD_RXD_LBN 0 2052#define FRF_AB_MD_RXD_WIDTH 16 2053 2054/* 2055 * FR_AB_MD_CS_REG(128bit): 2056 * PHY management configuration & status register 2057 */ 2058#define FR_AB_MD_CS_REG_OFST 0x00000c20 2059/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2060 2061#define FRF_AB_MD_RD_EN_LBN 15 2062#define FRF_AB_MD_RD_EN_WIDTH 1 2063#define FRF_AB_MD_WR_EN_LBN 14 2064#define FRF_AB_MD_WR_EN_WIDTH 1 2065#define FRF_AB_MD_ADDR_CMD_LBN 13 2066#define FRF_AB_MD_ADDR_CMD_WIDTH 1 2067#define FRF_AB_MD_PT_LBN 7 2068#define FRF_AB_MD_PT_WIDTH 3 2069#define FRF_AB_MD_PL_LBN 6 2070#define FRF_AB_MD_PL_WIDTH 1 2071#define FRF_AB_MD_INT_CLR_LBN 5 2072#define FRF_AB_MD_INT_CLR_WIDTH 1 2073#define FRF_AB_MD_GC_LBN 4 2074#define FRF_AB_MD_GC_WIDTH 1 2075#define FRF_AB_MD_PRSP_LBN 3 2076#define FRF_AB_MD_PRSP_WIDTH 1 2077#define FRF_AB_MD_RIC_LBN 2 2078#define FRF_AB_MD_RIC_WIDTH 1 2079#define FRF_AB_MD_RDC_LBN 1 2080#define FRF_AB_MD_RDC_WIDTH 1 2081#define FRF_AB_MD_WRC_LBN 0 2082#define FRF_AB_MD_WRC_WIDTH 1 2083 2084/* 2085 * FR_AB_MD_PHY_ADR_REG(128bit): 2086 * PHY management PHY address register 2087 */ 2088#define FR_AB_MD_PHY_ADR_REG_OFST 0x00000c30 2089/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2090 2091#define FRF_AB_MD_PHY_ADR_LBN 0 2092#define FRF_AB_MD_PHY_ADR_WIDTH 16 2093 2094/* 2095 * FR_AB_MD_ID_REG(128bit): 2096 * PHY management ID register 2097 */ 2098#define FR_AB_MD_ID_REG_OFST 0x00000c40 2099/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2100 2101#define FRF_AB_MD_PRT_ADR_LBN 11 2102#define FRF_AB_MD_PRT_ADR_WIDTH 5 2103#define FRF_AB_MD_DEV_ADR_LBN 6 2104#define FRF_AB_MD_DEV_ADR_WIDTH 5 2105 2106/* 2107 * FR_AB_MD_STAT_REG(128bit): 2108 * PHY management status & mask register 2109 */ 2110#define FR_AB_MD_STAT_REG_OFST 0x00000c50 2111/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2112 2113#define FRF_AB_MD_PINT_LBN 4 2114#define FRF_AB_MD_PINT_WIDTH 1 2115#define FRF_AB_MD_DONE_LBN 3 2116#define FRF_AB_MD_DONE_WIDTH 1 2117#define FRF_AB_MD_BSERR_LBN 2 2118#define FRF_AB_MD_BSERR_WIDTH 1 2119#define FRF_AB_MD_LNFL_LBN 1 2120#define FRF_AB_MD_LNFL_WIDTH 1 2121#define FRF_AB_MD_BSY_LBN 0 2122#define FRF_AB_MD_BSY_WIDTH 1 2123 2124/* 2125 * FR_AB_MAC_STAT_DMA_REG(128bit): 2126 * Port MAC statistical counter DMA register 2127 */ 2128#define FR_AB_MAC_STAT_DMA_REG_OFST 0x00000c60 2129/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2130 2131#define FRF_AB_MAC_STAT_DMA_CMD_LBN 48 2132#define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1 2133#define FRF_AB_MAC_STAT_DMA_ADR_LBN 0 2134#define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48 2135#define FRF_AB_MAC_STAT_DMA_ADR_DW0_LBN 0 2136#define FRF_AB_MAC_STAT_DMA_ADR_DW0_WIDTH 32 2137#define FRF_AB_MAC_STAT_DMA_ADR_DW1_LBN 32 2138#define FRF_AB_MAC_STAT_DMA_ADR_DW1_WIDTH 16 2139 2140/* 2141 * FR_AB_MAC_CTRL_REG(128bit): 2142 * Port MAC control register 2143 */ 2144#define FR_AB_MAC_CTRL_REG_OFST 0x00000c80 2145/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2146 2147#define FRF_AB_MAC_XOFF_VAL_LBN 16 2148#define FRF_AB_MAC_XOFF_VAL_WIDTH 16 2149#define FRF_BB_TXFIFO_DRAIN_EN_LBN 7 2150#define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1 2151#define FRF_AB_MAC_XG_DISTXCRC_LBN 5 2152#define FRF_AB_MAC_XG_DISTXCRC_WIDTH 1 2153#define FRF_AB_MAC_BCAD_ACPT_LBN 4 2154#define FRF_AB_MAC_BCAD_ACPT_WIDTH 1 2155#define FRF_AB_MAC_UC_PROM_LBN 3 2156#define FRF_AB_MAC_UC_PROM_WIDTH 1 2157#define FRF_AB_MAC_LINK_STATUS_LBN 2 2158#define FRF_AB_MAC_LINK_STATUS_WIDTH 1 2159#define FRF_AB_MAC_SPEED_LBN 0 2160#define FRF_AB_MAC_SPEED_WIDTH 2 2161#define FRF_AB_MAC_SPEED_10M 0 2162#define FRF_AB_MAC_SPEED_100M 1 2163#define FRF_AB_MAC_SPEED_1G 2 2164#define FRF_AB_MAC_SPEED_10G 3 2165 2166/* 2167 * FR_BB_GEN_MODE_REG(128bit): 2168 * General Purpose mode register (external interrupt mask) 2169 */ 2170#define FR_BB_GEN_MODE_REG_OFST 0x00000c90 2171/* falconb0=net_func_bar2 */ 2172 2173#define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3 2174#define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1 2175#define FRF_BB_XG_PHY_INT_POL_SEL_LBN 2 2176#define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1 2177#define FRF_BB_XFP_PHY_INT_MASK_LBN 1 2178#define FRF_BB_XFP_PHY_INT_MASK_WIDTH 1 2179#define FRF_BB_XG_PHY_INT_MASK_LBN 0 2180#define FRF_BB_XG_PHY_INT_MASK_WIDTH 1 2181 2182/* 2183 * FR_AB_MAC_MC_HASH_REG0(128bit): 2184 * Multicast address hash table 2185 */ 2186#define FR_AB_MAC_MC_HASH0_REG_OFST 0x00000ca0 2187/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2188 2189#define FRF_AB_MAC_MCAST_HASH0_LBN 0 2190#define FRF_AB_MAC_MCAST_HASH0_WIDTH 128 2191#define FRF_AB_MAC_MCAST_HASH0_DW0_LBN 0 2192#define FRF_AB_MAC_MCAST_HASH0_DW0_WIDTH 32 2193#define FRF_AB_MAC_MCAST_HASH0_DW1_LBN 32 2194#define FRF_AB_MAC_MCAST_HASH0_DW1_WIDTH 32 2195#define FRF_AB_MAC_MCAST_HASH0_DW2_LBN 64 2196#define FRF_AB_MAC_MCAST_HASH0_DW2_WIDTH 32 2197#define FRF_AB_MAC_MCAST_HASH0_DW3_LBN 96 2198#define FRF_AB_MAC_MCAST_HASH0_DW3_WIDTH 32 2199 2200/* 2201 * FR_AB_MAC_MC_HASH_REG1(128bit): 2202 * Multicast address hash table 2203 */ 2204#define FR_AB_MAC_MC_HASH1_REG_OFST 0x00000cb0 2205/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2206 2207#define FRF_AB_MAC_MCAST_HASH1_LBN 0 2208#define FRF_AB_MAC_MCAST_HASH1_WIDTH 128 2209#define FRF_AB_MAC_MCAST_HASH1_DW0_LBN 0 2210#define FRF_AB_MAC_MCAST_HASH1_DW0_WIDTH 32 2211#define FRF_AB_MAC_MCAST_HASH1_DW1_LBN 32 2212#define FRF_AB_MAC_MCAST_HASH1_DW1_WIDTH 32 2213#define FRF_AB_MAC_MCAST_HASH1_DW2_LBN 64 2214#define FRF_AB_MAC_MCAST_HASH1_DW2_WIDTH 32 2215#define FRF_AB_MAC_MCAST_HASH1_DW3_LBN 96 2216#define FRF_AB_MAC_MCAST_HASH1_DW3_WIDTH 32 2217 2218/* 2219 * FR_AB_GM_CFG1_REG(32bit): 2220 * GMAC configuration register 1 2221 */ 2222#define FR_AB_GM_CFG1_REG_OFST 0x00000e00 2223/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2224 2225#define FRF_AB_GM_SW_RST_LBN 31 2226#define FRF_AB_GM_SW_RST_WIDTH 1 2227#define FRF_AB_GM_SIM_RST_LBN 30 2228#define FRF_AB_GM_SIM_RST_WIDTH 1 2229#define FRF_AB_GM_RST_RX_MAC_CTL_LBN 19 2230#define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1 2231#define FRF_AB_GM_RST_TX_MAC_CTL_LBN 18 2232#define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1 2233#define FRF_AB_GM_RST_RX_FUNC_LBN 17 2234#define FRF_AB_GM_RST_RX_FUNC_WIDTH 1 2235#define FRF_AB_GM_RST_TX_FUNC_LBN 16 2236#define FRF_AB_GM_RST_TX_FUNC_WIDTH 1 2237#define FRF_AB_GM_LOOP_LBN 8 2238#define FRF_AB_GM_LOOP_WIDTH 1 2239#define FRF_AB_GM_RX_FC_EN_LBN 5 2240#define FRF_AB_GM_RX_FC_EN_WIDTH 1 2241#define FRF_AB_GM_TX_FC_EN_LBN 4 2242#define FRF_AB_GM_TX_FC_EN_WIDTH 1 2243#define FRF_AB_GM_SYNC_RXEN_LBN 3 2244#define FRF_AB_GM_SYNC_RXEN_WIDTH 1 2245#define FRF_AB_GM_RX_EN_LBN 2 2246#define FRF_AB_GM_RX_EN_WIDTH 1 2247#define FRF_AB_GM_SYNC_TXEN_LBN 1 2248#define FRF_AB_GM_SYNC_TXEN_WIDTH 1 2249#define FRF_AB_GM_TX_EN_LBN 0 2250#define FRF_AB_GM_TX_EN_WIDTH 1 2251 2252/* 2253 * FR_AB_GM_CFG2_REG(32bit): 2254 * GMAC configuration register 2 2255 */ 2256#define FR_AB_GM_CFG2_REG_OFST 0x00000e10 2257/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2258 2259#define FRF_AB_GM_PAMBL_LEN_LBN 12 2260#define FRF_AB_GM_PAMBL_LEN_WIDTH 4 2261#define FRF_AB_GM_IF_MODE_LBN 8 2262#define FRF_AB_GM_IF_MODE_WIDTH 2 2263#define FRF_AB_GM_IF_MODE_BYTE_MODE 2 2264#define FRF_AB_GM_IF_MODE_NIBBLE_MODE 1 2265#define FRF_AB_GM_HUGE_FRM_EN_LBN 5 2266#define FRF_AB_GM_HUGE_FRM_EN_WIDTH 1 2267#define FRF_AB_GM_LEN_CHK_LBN 4 2268#define FRF_AB_GM_LEN_CHK_WIDTH 1 2269#define FRF_AB_GM_PAD_CRC_EN_LBN 2 2270#define FRF_AB_GM_PAD_CRC_EN_WIDTH 1 2271#define FRF_AB_GM_CRC_EN_LBN 1 2272#define FRF_AB_GM_CRC_EN_WIDTH 1 2273#define FRF_AB_GM_FD_LBN 0 2274#define FRF_AB_GM_FD_WIDTH 1 2275 2276/* 2277 * FR_AB_GM_IPG_REG(32bit): 2278 * GMAC IPG register 2279 */ 2280#define FR_AB_GM_IPG_REG_OFST 0x00000e20 2281/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2282 2283#define FRF_AB_GM_NONB2B_IPG1_LBN 24 2284#define FRF_AB_GM_NONB2B_IPG1_WIDTH 7 2285#define FRF_AB_GM_NONB2B_IPG2_LBN 16 2286#define FRF_AB_GM_NONB2B_IPG2_WIDTH 7 2287#define FRF_AB_GM_MIN_IPG_ENF_LBN 8 2288#define FRF_AB_GM_MIN_IPG_ENF_WIDTH 8 2289#define FRF_AB_GM_B2B_IPG_LBN 0 2290#define FRF_AB_GM_B2B_IPG_WIDTH 7 2291 2292/* 2293 * FR_AB_GM_HD_REG(32bit): 2294 * GMAC half duplex register 2295 */ 2296#define FR_AB_GM_HD_REG_OFST 0x00000e30 2297/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2298 2299#define FRF_AB_GM_ALT_BOFF_VAL_LBN 20 2300#define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4 2301#define FRF_AB_GM_ALT_BOFF_EN_LBN 19 2302#define FRF_AB_GM_ALT_BOFF_EN_WIDTH 1 2303#define FRF_AB_GM_BP_NO_BOFF_LBN 18 2304#define FRF_AB_GM_BP_NO_BOFF_WIDTH 1 2305#define FRF_AB_GM_DIS_BOFF_LBN 17 2306#define FRF_AB_GM_DIS_BOFF_WIDTH 1 2307#define FRF_AB_GM_EXDEF_TX_EN_LBN 16 2308#define FRF_AB_GM_EXDEF_TX_EN_WIDTH 1 2309#define FRF_AB_GM_RTRY_LIMIT_LBN 12 2310#define FRF_AB_GM_RTRY_LIMIT_WIDTH 4 2311#define FRF_AB_GM_COL_WIN_LBN 0 2312#define FRF_AB_GM_COL_WIN_WIDTH 10 2313 2314/* 2315 * FR_AB_GM_MAX_FLEN_REG(32bit): 2316 * GMAC maximum frame length register 2317 */ 2318#define FR_AB_GM_MAX_FLEN_REG_OFST 0x00000e40 2319/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2320 2321#define FRF_AB_GM_MAX_FLEN_LBN 0 2322#define FRF_AB_GM_MAX_FLEN_WIDTH 16 2323 2324/* 2325 * FR_AB_GM_TEST_REG(32bit): 2326 * GMAC test register 2327 */ 2328#define FR_AB_GM_TEST_REG_OFST 0x00000e70 2329/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2330 2331#define FRF_AB_GM_MAX_BOFF_LBN 3 2332#define FRF_AB_GM_MAX_BOFF_WIDTH 1 2333#define FRF_AB_GM_REG_TX_FLOW_EN_LBN 2 2334#define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1 2335#define FRF_AB_GM_TEST_PAUSE_LBN 1 2336#define FRF_AB_GM_TEST_PAUSE_WIDTH 1 2337#define FRF_AB_GM_SHORT_SLOT_LBN 0 2338#define FRF_AB_GM_SHORT_SLOT_WIDTH 1 2339 2340/* 2341 * FR_AB_GM_ADR1_REG(32bit): 2342 * GMAC station address register 1 2343 */ 2344#define FR_AB_GM_ADR1_REG_OFST 0x00000f00 2345/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2346 2347#define FRF_AB_GM_ADR_B0_LBN 24 2348#define FRF_AB_GM_ADR_B0_WIDTH 8 2349#define FRF_AB_GM_ADR_B1_LBN 16 2350#define FRF_AB_GM_ADR_B1_WIDTH 8 2351#define FRF_AB_GM_ADR_B2_LBN 8 2352#define FRF_AB_GM_ADR_B2_WIDTH 8 2353#define FRF_AB_GM_ADR_B3_LBN 0 2354#define FRF_AB_GM_ADR_B3_WIDTH 8 2355 2356/* 2357 * FR_AB_GM_ADR2_REG(32bit): 2358 * GMAC station address register 2 2359 */ 2360#define FR_AB_GM_ADR2_REG_OFST 0x00000f10 2361/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2362 2363#define FRF_AB_GM_ADR_B4_LBN 24 2364#define FRF_AB_GM_ADR_B4_WIDTH 8 2365#define FRF_AB_GM_ADR_B5_LBN 16 2366#define FRF_AB_GM_ADR_B5_WIDTH 8 2367 2368/* 2369 * FR_AB_GMF_CFG0_REG(32bit): 2370 * GMAC FIFO configuration register 0 2371 */ 2372#define FR_AB_GMF_CFG0_REG_OFST 0x00000f20 2373/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2374 2375#define FRF_AB_GMF_FTFENRPLY_LBN 20 2376#define FRF_AB_GMF_FTFENRPLY_WIDTH 1 2377#define FRF_AB_GMF_STFENRPLY_LBN 19 2378#define FRF_AB_GMF_STFENRPLY_WIDTH 1 2379#define FRF_AB_GMF_FRFENRPLY_LBN 18 2380#define FRF_AB_GMF_FRFENRPLY_WIDTH 1 2381#define FRF_AB_GMF_SRFENRPLY_LBN 17 2382#define FRF_AB_GMF_SRFENRPLY_WIDTH 1 2383#define FRF_AB_GMF_WTMENRPLY_LBN 16 2384#define FRF_AB_GMF_WTMENRPLY_WIDTH 1 2385#define FRF_AB_GMF_FTFENREQ_LBN 12 2386#define FRF_AB_GMF_FTFENREQ_WIDTH 1 2387#define FRF_AB_GMF_STFENREQ_LBN 11 2388#define FRF_AB_GMF_STFENREQ_WIDTH 1 2389#define FRF_AB_GMF_FRFENREQ_LBN 10 2390#define FRF_AB_GMF_FRFENREQ_WIDTH 1 2391#define FRF_AB_GMF_SRFENREQ_LBN 9 2392#define FRF_AB_GMF_SRFENREQ_WIDTH 1 2393#define FRF_AB_GMF_WTMENREQ_LBN 8 2394#define FRF_AB_GMF_WTMENREQ_WIDTH 1 2395#define FRF_AB_GMF_HSTRSTFT_LBN 4 2396#define FRF_AB_GMF_HSTRSTFT_WIDTH 1 2397#define FRF_AB_GMF_HSTRSTST_LBN 3 2398#define FRF_AB_GMF_HSTRSTST_WIDTH 1 2399#define FRF_AB_GMF_HSTRSTFR_LBN 2 2400#define FRF_AB_GMF_HSTRSTFR_WIDTH 1 2401#define FRF_AB_GMF_HSTRSTSR_LBN 1 2402#define FRF_AB_GMF_HSTRSTSR_WIDTH 1 2403#define FRF_AB_GMF_HSTRSTWT_LBN 0 2404#define FRF_AB_GMF_HSTRSTWT_WIDTH 1 2405 2406/* 2407 * FR_AB_GMF_CFG1_REG(32bit): 2408 * GMAC FIFO configuration register 1 2409 */ 2410#define FR_AB_GMF_CFG1_REG_OFST 0x00000f30 2411/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2412 2413#define FRF_AB_GMF_CFGFRTH_LBN 16 2414#define FRF_AB_GMF_CFGFRTH_WIDTH 5 2415#define FRF_AB_GMF_CFGXOFFRTX_LBN 0 2416#define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16 2417 2418/* 2419 * FR_AB_GMF_CFG2_REG(32bit): 2420 * GMAC FIFO configuration register 2 2421 */ 2422#define FR_AB_GMF_CFG2_REG_OFST 0x00000f40 2423/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2424 2425#define FRF_AB_GMF_CFGHWM_LBN 16 2426#define FRF_AB_GMF_CFGHWM_WIDTH 6 2427#define FRF_AB_GMF_CFGLWM_LBN 0 2428#define FRF_AB_GMF_CFGLWM_WIDTH 6 2429 2430/* 2431 * FR_AB_GMF_CFG3_REG(32bit): 2432 * GMAC FIFO configuration register 3 2433 */ 2434#define FR_AB_GMF_CFG3_REG_OFST 0x00000f50 2435/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2436 2437#define FRF_AB_GMF_CFGHWMFT_LBN 16 2438#define FRF_AB_GMF_CFGHWMFT_WIDTH 6 2439#define FRF_AB_GMF_CFGFTTH_LBN 0 2440#define FRF_AB_GMF_CFGFTTH_WIDTH 6 2441 2442/* 2443 * FR_AB_GMF_CFG4_REG(32bit): 2444 * GMAC FIFO configuration register 4 2445 */ 2446#define FR_AB_GMF_CFG4_REG_OFST 0x00000f60 2447/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2448 2449#define FRF_AB_GMF_HSTFLTRFRM_LBN 0 2450#define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18 2451 2452/* 2453 * FR_AB_GMF_CFG5_REG(32bit): 2454 * GMAC FIFO configuration register 5 2455 */ 2456#define FR_AB_GMF_CFG5_REG_OFST 0x00000f70 2457/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2458 2459#define FRF_AB_GMF_CFGHDPLX_LBN 22 2460#define FRF_AB_GMF_CFGHDPLX_WIDTH 1 2461#define FRF_AB_GMF_SRFULL_LBN 21 2462#define FRF_AB_GMF_SRFULL_WIDTH 1 2463#define FRF_AB_GMF_HSTSRFULLCLR_LBN 20 2464#define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1 2465#define FRF_AB_GMF_CFGBYTMODE_LBN 19 2466#define FRF_AB_GMF_CFGBYTMODE_WIDTH 1 2467#define FRF_AB_GMF_HSTDRPLT64_LBN 18 2468#define FRF_AB_GMF_HSTDRPLT64_WIDTH 1 2469#define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0 2470#define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18 2471 2472/* 2473 * FR_BB_TX_SRC_MAC_TBL(128bit): 2474 * Transmit IP source address filter table 2475 */ 2476#define FR_BB_TX_SRC_MAC_TBL_OFST 0x00001000 2477/* falconb0=net_func_bar2 */ 2478#define FR_BB_TX_SRC_MAC_TBL_STEP 16 2479#define FR_BB_TX_SRC_MAC_TBL_ROWS 16 2480 2481#define FRF_BB_TX_SRC_MAC_ADR_1_LBN 64 2482#define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48 2483#define FRF_BB_TX_SRC_MAC_ADR_1_DW0_LBN 64 2484#define FRF_BB_TX_SRC_MAC_ADR_1_DW0_WIDTH 32 2485#define FRF_BB_TX_SRC_MAC_ADR_1_DW1_LBN 96 2486#define FRF_BB_TX_SRC_MAC_ADR_1_DW1_WIDTH 16 2487#define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0 2488#define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48 2489#define FRF_BB_TX_SRC_MAC_ADR_0_DW0_LBN 0 2490#define FRF_BB_TX_SRC_MAC_ADR_0_DW0_WIDTH 32 2491#define FRF_BB_TX_SRC_MAC_ADR_0_DW1_LBN 32 2492#define FRF_BB_TX_SRC_MAC_ADR_0_DW1_WIDTH 16 2493 2494/* 2495 * FR_BB_TX_SRC_MAC_CTL_REG(128bit): 2496 * Transmit MAC source address filter control 2497 */ 2498#define FR_BB_TX_SRC_MAC_CTL_REG_OFST 0x00001100 2499/* falconb0=net_func_bar2 */ 2500 2501#define FRF_BB_TX_SRC_DROP_CTR_LBN 16 2502#define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16 2503#define FRF_BB_TX_SRC_FLTR_EN_LBN 15 2504#define FRF_BB_TX_SRC_FLTR_EN_WIDTH 1 2505#define FRF_BB_TX_DROP_CTR_CLR_LBN 12 2506#define FRF_BB_TX_DROP_CTR_CLR_WIDTH 1 2507#define FRF_BB_TX_MAC_QID_SEL_LBN 0 2508#define FRF_BB_TX_MAC_QID_SEL_WIDTH 3 2509 2510/* 2511 * FR_AB_XM_ADR_LO_REG(128bit): 2512 * XGMAC address register low 2513 */ 2514#define FR_AB_XM_ADR_LO_REG_OFST 0x00001200 2515/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2516 2517#define FRF_AB_XM_ADR_LO_LBN 0 2518#define FRF_AB_XM_ADR_LO_WIDTH 32 2519 2520/* 2521 * FR_AB_XM_ADR_HI_REG(128bit): 2522 * XGMAC address register high 2523 */ 2524#define FR_AB_XM_ADR_HI_REG_OFST 0x00001210 2525/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2526 2527#define FRF_AB_XM_ADR_HI_LBN 0 2528#define FRF_AB_XM_ADR_HI_WIDTH 16 2529 2530/* 2531 * FR_AB_XM_GLB_CFG_REG(128bit): 2532 * XGMAC global configuration 2533 */ 2534#define FR_AB_XM_GLB_CFG_REG_OFST 0x00001220 2535/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2536 2537#define FRF_AB_XM_RMTFLT_GEN_LBN 17 2538#define FRF_AB_XM_RMTFLT_GEN_WIDTH 1 2539#define FRF_AB_XM_DEBUG_MODE_LBN 16 2540#define FRF_AB_XM_DEBUG_MODE_WIDTH 1 2541#define FRF_AB_XM_RX_STAT_EN_LBN 11 2542#define FRF_AB_XM_RX_STAT_EN_WIDTH 1 2543#define FRF_AB_XM_TX_STAT_EN_LBN 10 2544#define FRF_AB_XM_TX_STAT_EN_WIDTH 1 2545#define FRF_AB_XM_RX_JUMBO_MODE_LBN 6 2546#define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1 2547#define FRF_AB_XM_WAN_MODE_LBN 5 2548#define FRF_AB_XM_WAN_MODE_WIDTH 1 2549#define FRF_AB_XM_INTCLR_MODE_LBN 3 2550#define FRF_AB_XM_INTCLR_MODE_WIDTH 1 2551#define FRF_AB_XM_CORE_RST_LBN 0 2552#define FRF_AB_XM_CORE_RST_WIDTH 1 2553 2554/* 2555 * FR_AB_XM_TX_CFG_REG(128bit): 2556 * XGMAC transmit configuration 2557 */ 2558#define FR_AB_XM_TX_CFG_REG_OFST 0x00001230 2559/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2560 2561#define FRF_AB_XM_TX_PROG_LBN 24 2562#define FRF_AB_XM_TX_PROG_WIDTH 1 2563#define FRF_AB_XM_IPG_LBN 16 2564#define FRF_AB_XM_IPG_WIDTH 4 2565#define FRF_AB_XM_FCNTL_LBN 10 2566#define FRF_AB_XM_FCNTL_WIDTH 1 2567#define FRF_AB_XM_TXCRC_LBN 8 2568#define FRF_AB_XM_TXCRC_WIDTH 1 2569#define FRF_AB_XM_EDRC_LBN 6 2570#define FRF_AB_XM_EDRC_WIDTH 1 2571#define FRF_AB_XM_AUTO_PAD_LBN 5 2572#define FRF_AB_XM_AUTO_PAD_WIDTH 1 2573#define FRF_AB_XM_TX_PRMBL_LBN 2 2574#define FRF_AB_XM_TX_PRMBL_WIDTH 1 2575#define FRF_AB_XM_TXEN_LBN 1 2576#define FRF_AB_XM_TXEN_WIDTH 1 2577#define FRF_AB_XM_TX_RST_LBN 0 2578#define FRF_AB_XM_TX_RST_WIDTH 1 2579 2580/* 2581 * FR_AB_XM_RX_CFG_REG(128bit): 2582 * XGMAC receive configuration 2583 */ 2584#define FR_AB_XM_RX_CFG_REG_OFST 0x00001240 2585/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2586 2587#define FRF_AB_XM_PASS_LENERR_LBN 26 2588#define FRF_AB_XM_PASS_LENERR_WIDTH 1 2589#define FRF_AB_XM_PASS_CRC_ERR_LBN 25 2590#define FRF_AB_XM_PASS_CRC_ERR_WIDTH 1 2591#define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24 2592#define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1 2593#define FRF_AB_XM_REJ_BCAST_LBN 20 2594#define FRF_AB_XM_REJ_BCAST_WIDTH 1 2595#define FRF_AB_XM_ACPT_ALL_MCAST_LBN 11 2596#define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1 2597#define FRF_AB_XM_ACPT_ALL_UCAST_LBN 9 2598#define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1 2599#define FRF_AB_XM_AUTO_DEPAD_LBN 8 2600#define FRF_AB_XM_AUTO_DEPAD_WIDTH 1 2601#define FRF_AB_XM_RXCRC_LBN 3 2602#define FRF_AB_XM_RXCRC_WIDTH 1 2603#define FRF_AB_XM_RX_PRMBL_LBN 2 2604#define FRF_AB_XM_RX_PRMBL_WIDTH 1 2605#define FRF_AB_XM_RXEN_LBN 1 2606#define FRF_AB_XM_RXEN_WIDTH 1 2607#define FRF_AB_XM_RX_RST_LBN 0 2608#define FRF_AB_XM_RX_RST_WIDTH 1 2609 2610/* 2611 * FR_AB_XM_MGT_INT_MASK(128bit): 2612 * documentation to be written for sum_XM_MGT_INT_MASK 2613 */ 2614#define FR_AB_XM_MGT_INT_MASK_OFST 0x00001250 2615/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2616 2617#define FRF_AB_XM_MSK_STA_INTR_LBN 16 2618#define FRF_AB_XM_MSK_STA_INTR_WIDTH 1 2619#define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9 2620#define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1 2621#define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8 2622#define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1 2623#define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2 2624#define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1 2625#define FRF_AB_XM_MSK_RMTFLT_LBN 1 2626#define FRF_AB_XM_MSK_RMTFLT_WIDTH 1 2627#define FRF_AB_XM_MSK_LCLFLT_LBN 0 2628#define FRF_AB_XM_MSK_LCLFLT_WIDTH 1 2629 2630/* 2631 * FR_AB_XM_FC_REG(128bit): 2632 * XGMAC flow control register 2633 */ 2634#define FR_AB_XM_FC_REG_OFST 0x00001270 2635/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2636 2637#define FRF_AB_XM_PAUSE_TIME_LBN 16 2638#define FRF_AB_XM_PAUSE_TIME_WIDTH 16 2639#define FRF_AB_XM_RX_MAC_STAT_LBN 11 2640#define FRF_AB_XM_RX_MAC_STAT_WIDTH 1 2641#define FRF_AB_XM_TX_MAC_STAT_LBN 10 2642#define FRF_AB_XM_TX_MAC_STAT_WIDTH 1 2643#define FRF_AB_XM_MCNTL_PASS_LBN 8 2644#define FRF_AB_XM_MCNTL_PASS_WIDTH 2 2645#define FRF_AB_XM_REJ_CNTL_UCAST_LBN 6 2646#define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1 2647#define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5 2648#define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1 2649#define FRF_AB_XM_ZPAUSE_LBN 2 2650#define FRF_AB_XM_ZPAUSE_WIDTH 1 2651#define FRF_AB_XM_XMIT_PAUSE_LBN 1 2652#define FRF_AB_XM_XMIT_PAUSE_WIDTH 1 2653#define FRF_AB_XM_DIS_FCNTL_LBN 0 2654#define FRF_AB_XM_DIS_FCNTL_WIDTH 1 2655 2656/* 2657 * FR_AB_XM_PAUSE_TIME_REG(128bit): 2658 * XGMAC pause time register 2659 */ 2660#define FR_AB_XM_PAUSE_TIME_REG_OFST 0x00001290 2661/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2662 2663#define FRF_AB_XM_TX_PAUSE_CNT_LBN 16 2664#define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16 2665#define FRF_AB_XM_RX_PAUSE_CNT_LBN 0 2666#define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16 2667 2668/* 2669 * FR_AB_XM_TX_PARAM_REG(128bit): 2670 * XGMAC transmit parameter register 2671 */ 2672#define FR_AB_XM_TX_PARAM_REG_OFST 0x000012d0 2673/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2674 2675#define FRF_AB_XM_TX_JUMBO_MODE_LBN 31 2676#define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1 2677#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19 2678#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11 2679#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16 2680#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3 2681#define FRF_AB_XM_PAD_CHAR_LBN 0 2682#define FRF_AB_XM_PAD_CHAR_WIDTH 8 2683 2684/* 2685 * FR_AB_XM_RX_PARAM_REG(128bit): 2686 * XGMAC receive parameter register 2687 */ 2688#define FR_AB_XM_RX_PARAM_REG_OFST 0x000012e0 2689/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2690 2691#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3 2692#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11 2693#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0 2694#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3 2695 2696/* 2697 * FR_AB_XM_MGT_INT_MSK_REG(128bit): 2698 * XGMAC management interrupt mask register 2699 */ 2700#define FR_AB_XM_MGT_INT_REG_OFST 0x000012f0 2701/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2702 2703#define FRF_AB_XM_STAT_CNTR_OF_LBN 9 2704#define FRF_AB_XM_STAT_CNTR_OF_WIDTH 1 2705#define FRF_AB_XM_STAT_CNTR_HF_LBN 8 2706#define FRF_AB_XM_STAT_CNTR_HF_WIDTH 1 2707#define FRF_AB_XM_PRMBLE_ERR_LBN 2 2708#define FRF_AB_XM_PRMBLE_ERR_WIDTH 1 2709#define FRF_AB_XM_RMTFLT_LBN 1 2710#define FRF_AB_XM_RMTFLT_WIDTH 1 2711#define FRF_AB_XM_LCLFLT_LBN 0 2712#define FRF_AB_XM_LCLFLT_WIDTH 1 2713 2714/* 2715 * FR_AB_XX_PWR_RST_REG(128bit): 2716 * XGXS/XAUI powerdown/reset register 2717 */ 2718#define FR_AB_XX_PWR_RST_REG_OFST 0x00001300 2719/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2720 2721#define FRF_AB_XX_PWRDND_SIG_LBN 31 2722#define FRF_AB_XX_PWRDND_SIG_WIDTH 1 2723#define FRF_AB_XX_PWRDNC_SIG_LBN 30 2724#define FRF_AB_XX_PWRDNC_SIG_WIDTH 1 2725#define FRF_AB_XX_PWRDNB_SIG_LBN 29 2726#define FRF_AB_XX_PWRDNB_SIG_WIDTH 1 2727#define FRF_AB_XX_PWRDNA_SIG_LBN 28 2728#define FRF_AB_XX_PWRDNA_SIG_WIDTH 1 2729#define FRF_AB_XX_SIM_MODE_LBN 27 2730#define FRF_AB_XX_SIM_MODE_WIDTH 1 2731#define FRF_AB_XX_RSTPLLCD_SIG_LBN 25 2732#define FRF_AB_XX_RSTPLLCD_SIG_WIDTH 1 2733#define FRF_AB_XX_RSTPLLAB_SIG_LBN 24 2734#define FRF_AB_XX_RSTPLLAB_SIG_WIDTH 1 2735#define FRF_AB_XX_RESETD_SIG_LBN 23 2736#define FRF_AB_XX_RESETD_SIG_WIDTH 1 2737#define FRF_AB_XX_RESETC_SIG_LBN 22 2738#define FRF_AB_XX_RESETC_SIG_WIDTH 1 2739#define FRF_AB_XX_RESETB_SIG_LBN 21 2740#define FRF_AB_XX_RESETB_SIG_WIDTH 1 2741#define FRF_AB_XX_RESETA_SIG_LBN 20 2742#define FRF_AB_XX_RESETA_SIG_WIDTH 1 2743#define FRF_AB_XX_RSTXGXSRX_SIG_LBN 18 2744#define FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1 2745#define FRF_AB_XX_RSTXGXSTX_SIG_LBN 17 2746#define FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1 2747#define FRF_AB_XX_SD_RST_ACT_LBN 16 2748#define FRF_AB_XX_SD_RST_ACT_WIDTH 1 2749#define FRF_AB_XX_PWRDND_EN_LBN 15 2750#define FRF_AB_XX_PWRDND_EN_WIDTH 1 2751#define FRF_AB_XX_PWRDNC_EN_LBN 14 2752#define FRF_AB_XX_PWRDNC_EN_WIDTH 1 2753#define FRF_AB_XX_PWRDNB_EN_LBN 13 2754#define FRF_AB_XX_PWRDNB_EN_WIDTH 1 2755#define FRF_AB_XX_PWRDNA_EN_LBN 12 2756#define FRF_AB_XX_PWRDNA_EN_WIDTH 1 2757#define FRF_AB_XX_RSTPLLCD_EN_LBN 9 2758#define FRF_AB_XX_RSTPLLCD_EN_WIDTH 1 2759#define FRF_AB_XX_RSTPLLAB_EN_LBN 8 2760#define FRF_AB_XX_RSTPLLAB_EN_WIDTH 1 2761#define FRF_AB_XX_RESETD_EN_LBN 7 2762#define FRF_AB_XX_RESETD_EN_WIDTH 1 2763#define FRF_AB_XX_RESETC_EN_LBN 6 2764#define FRF_AB_XX_RESETC_EN_WIDTH 1 2765#define FRF_AB_XX_RESETB_EN_LBN 5 2766#define FRF_AB_XX_RESETB_EN_WIDTH 1 2767#define FRF_AB_XX_RESETA_EN_LBN 4 2768#define FRF_AB_XX_RESETA_EN_WIDTH 1 2769#define FRF_AB_XX_RSTXGXSRX_EN_LBN 2 2770#define FRF_AB_XX_RSTXGXSRX_EN_WIDTH 1 2771#define FRF_AB_XX_RSTXGXSTX_EN_LBN 1 2772#define FRF_AB_XX_RSTXGXSTX_EN_WIDTH 1 2773#define FRF_AB_XX_RST_XX_EN_LBN 0 2774#define FRF_AB_XX_RST_XX_EN_WIDTH 1 2775 2776/* 2777 * FR_AB_XX_SD_CTL_REG(128bit): 2778 * XGXS/XAUI powerdown/reset control register 2779 */ 2780#define FR_AB_XX_SD_CTL_REG_OFST 0x00001310 2781/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2782 2783#define FRF_AB_XX_TERMADJ1_LBN 17 2784#define FRF_AB_XX_TERMADJ1_WIDTH 1 2785#define FRF_AB_XX_TERMADJ0_LBN 16 2786#define FRF_AB_XX_TERMADJ0_WIDTH 1 2787#define FRF_AB_XX_HIDRVD_LBN 15 2788#define FRF_AB_XX_HIDRVD_WIDTH 1 2789#define FRF_AB_XX_LODRVD_LBN 14 2790#define FRF_AB_XX_LODRVD_WIDTH 1 2791#define FRF_AB_XX_HIDRVC_LBN 13 2792#define FRF_AB_XX_HIDRVC_WIDTH 1 2793#define FRF_AB_XX_LODRVC_LBN 12 2794#define FRF_AB_XX_LODRVC_WIDTH 1 2795#define FRF_AB_XX_HIDRVB_LBN 11 2796#define FRF_AB_XX_HIDRVB_WIDTH 1 2797#define FRF_AB_XX_LODRVB_LBN 10 2798#define FRF_AB_XX_LODRVB_WIDTH 1 2799#define FRF_AB_XX_HIDRVA_LBN 9 2800#define FRF_AB_XX_HIDRVA_WIDTH 1 2801#define FRF_AB_XX_LODRVA_LBN 8 2802#define FRF_AB_XX_LODRVA_WIDTH 1 2803#define FRF_AB_XX_LPBKD_LBN 3 2804#define FRF_AB_XX_LPBKD_WIDTH 1 2805#define FRF_AB_XX_LPBKC_LBN 2 2806#define FRF_AB_XX_LPBKC_WIDTH 1 2807#define FRF_AB_XX_LPBKB_LBN 1 2808#define FRF_AB_XX_LPBKB_WIDTH 1 2809#define FRF_AB_XX_LPBKA_LBN 0 2810#define FRF_AB_XX_LPBKA_WIDTH 1 2811 2812/* 2813 * FR_AB_XX_TXDRV_CTL_REG(128bit): 2814 * XAUI SerDes transmit drive control register 2815 */ 2816#define FR_AB_XX_TXDRV_CTL_REG_OFST 0x00001320 2817/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2818 2819#define FRF_AB_XX_DEQD_LBN 28 2820#define FRF_AB_XX_DEQD_WIDTH 4 2821#define FRF_AB_XX_DEQC_LBN 24 2822#define FRF_AB_XX_DEQC_WIDTH 4 2823#define FRF_AB_XX_DEQB_LBN 20 2824#define FRF_AB_XX_DEQB_WIDTH 4 2825#define FRF_AB_XX_DEQA_LBN 16 2826#define FRF_AB_XX_DEQA_WIDTH 4 2827#define FRF_AB_XX_DTXD_LBN 12 2828#define FRF_AB_XX_DTXD_WIDTH 4 2829#define FRF_AB_XX_DTXC_LBN 8 2830#define FRF_AB_XX_DTXC_WIDTH 4 2831#define FRF_AB_XX_DTXB_LBN 4 2832#define FRF_AB_XX_DTXB_WIDTH 4 2833#define FRF_AB_XX_DTXA_LBN 0 2834#define FRF_AB_XX_DTXA_WIDTH 4 2835 2836/* 2837 * FR_AB_XX_PRBS_CTL_REG(128bit): 2838 * documentation to be written for sum_XX_PRBS_CTL_REG 2839 */ 2840#define FR_AB_XX_PRBS_CTL_REG_OFST 0x00001330 2841/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2842 2843#define FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30 2844#define FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2 2845#define FRF_AB_XX_CH3_RX_PRBS_INV_LBN 29 2846#define FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1 2847#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28 2848#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1 2849#define FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26 2850#define FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2 2851#define FRF_AB_XX_CH2_RX_PRBS_INV_LBN 25 2852#define FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1 2853#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24 2854#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1 2855#define FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22 2856#define FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2 2857#define FRF_AB_XX_CH1_RX_PRBS_INV_LBN 21 2858#define FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1 2859#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20 2860#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1 2861#define FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18 2862#define FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2 2863#define FRF_AB_XX_CH0_RX_PRBS_INV_LBN 17 2864#define FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1 2865#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16 2866#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1 2867#define FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14 2868#define FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2 2869#define FRF_AB_XX_CH3_TX_PRBS_INV_LBN 13 2870#define FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1 2871#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12 2872#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1 2873#define FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10 2874#define FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2 2875#define FRF_AB_XX_CH2_TX_PRBS_INV_LBN 9 2876#define FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1 2877#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8 2878#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1 2879#define FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6 2880#define FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2 2881#define FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5 2882#define FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1 2883#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4 2884#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1 2885#define FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2 2886#define FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2 2887#define FRF_AB_XX_CH0_TX_PRBS_INV_LBN 1 2888#define FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1 2889#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0 2890#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1 2891 2892/* 2893 * FR_AB_XX_PRBS_CHK_REG(128bit): 2894 * documentation to be written for sum_XX_PRBS_CHK_REG 2895 */ 2896#define FR_AB_XX_PRBS_CHK_REG_OFST 0x00001340 2897/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2898 2899#define FRF_AB_XX_REV_LB_EN_LBN 16 2900#define FRF_AB_XX_REV_LB_EN_WIDTH 1 2901#define FRF_AB_XX_CH3_DEG_DET_LBN 15 2902#define FRF_AB_XX_CH3_DEG_DET_WIDTH 1 2903#define FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14 2904#define FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1 2905#define FRF_AB_XX_CH3_PRBS_FRUN_LBN 13 2906#define FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1 2907#define FRF_AB_XX_CH3_ERR_CHK_LBN 12 2908#define FRF_AB_XX_CH3_ERR_CHK_WIDTH 1 2909#define FRF_AB_XX_CH2_DEG_DET_LBN 11 2910#define FRF_AB_XX_CH2_DEG_DET_WIDTH 1 2911#define FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10 2912#define FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1 2913#define FRF_AB_XX_CH2_PRBS_FRUN_LBN 9 2914#define FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1 2915#define FRF_AB_XX_CH2_ERR_CHK_LBN 8 2916#define FRF_AB_XX_CH2_ERR_CHK_WIDTH 1 2917#define FRF_AB_XX_CH1_DEG_DET_LBN 7 2918#define FRF_AB_XX_CH1_DEG_DET_WIDTH 1 2919#define FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6 2920#define FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1 2921#define FRF_AB_XX_CH1_PRBS_FRUN_LBN 5 2922#define FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1 2923#define FRF_AB_XX_CH1_ERR_CHK_LBN 4 2924#define FRF_AB_XX_CH1_ERR_CHK_WIDTH 1 2925#define FRF_AB_XX_CH0_DEG_DET_LBN 3 2926#define FRF_AB_XX_CH0_DEG_DET_WIDTH 1 2927#define FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2 2928#define FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1 2929#define FRF_AB_XX_CH0_PRBS_FRUN_LBN 1 2930#define FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1 2931#define FRF_AB_XX_CH0_ERR_CHK_LBN 0 2932#define FRF_AB_XX_CH0_ERR_CHK_WIDTH 1 2933 2934/* 2935 * FR_AB_XX_PRBS_ERR_REG(128bit): 2936 * documentation to be written for sum_XX_PRBS_ERR_REG 2937 */ 2938#define FR_AB_XX_PRBS_ERR_REG_OFST 0x00001350 2939/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2940 2941#define FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24 2942#define FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8 2943#define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16 2944#define FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8 2945#define FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8 2946#define FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8 2947#define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0 2948#define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8 2949 2950/* 2951 * FR_AB_XX_CORE_STAT_REG(128bit): 2952 * XAUI XGXS core status register 2953 */ 2954#define FR_AB_XX_CORE_STAT_REG_OFST 0x00001360 2955/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2956 2957#define FRF_AB_XX_FORCE_SIG3_LBN 31 2958#define FRF_AB_XX_FORCE_SIG3_WIDTH 1 2959#define FRF_AB_XX_FORCE_SIG3_VAL_LBN 30 2960#define FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1 2961#define FRF_AB_XX_FORCE_SIG2_LBN 29 2962#define FRF_AB_XX_FORCE_SIG2_WIDTH 1 2963#define FRF_AB_XX_FORCE_SIG2_VAL_LBN 28 2964#define FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1 2965#define FRF_AB_XX_FORCE_SIG1_LBN 27 2966#define FRF_AB_XX_FORCE_SIG1_WIDTH 1 2967#define FRF_AB_XX_FORCE_SIG1_VAL_LBN 26 2968#define FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1 2969#define FRF_AB_XX_FORCE_SIG0_LBN 25 2970#define FRF_AB_XX_FORCE_SIG0_WIDTH 1 2971#define FRF_AB_XX_FORCE_SIG0_VAL_LBN 24 2972#define FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1 2973#define FRF_AB_XX_XGXS_LB_EN_LBN 23 2974#define FRF_AB_XX_XGXS_LB_EN_WIDTH 1 2975#define FRF_AB_XX_XGMII_LB_EN_LBN 22 2976#define FRF_AB_XX_XGMII_LB_EN_WIDTH 1 2977#define FRF_AB_XX_MATCH_FAULT_LBN 21 2978#define FRF_AB_XX_MATCH_FAULT_WIDTH 1 2979#define FRF_AB_XX_ALIGN_DONE_LBN 20 2980#define FRF_AB_XX_ALIGN_DONE_WIDTH 1 2981#define FRF_AB_XX_SYNC_STAT3_LBN 19 2982#define FRF_AB_XX_SYNC_STAT3_WIDTH 1 2983#define FRF_AB_XX_SYNC_STAT2_LBN 18 2984#define FRF_AB_XX_SYNC_STAT2_WIDTH 1 2985#define FRF_AB_XX_SYNC_STAT1_LBN 17 2986#define FRF_AB_XX_SYNC_STAT1_WIDTH 1 2987#define FRF_AB_XX_SYNC_STAT0_LBN 16 2988#define FRF_AB_XX_SYNC_STAT0_WIDTH 1 2989#define FRF_AB_XX_COMMA_DET_CH3_LBN 15 2990#define FRF_AB_XX_COMMA_DET_CH3_WIDTH 1 2991#define FRF_AB_XX_COMMA_DET_CH2_LBN 14 2992#define FRF_AB_XX_COMMA_DET_CH2_WIDTH 1 2993#define FRF_AB_XX_COMMA_DET_CH1_LBN 13 2994#define FRF_AB_XX_COMMA_DET_CH1_WIDTH 1 2995#define FRF_AB_XX_COMMA_DET_CH0_LBN 12 2996#define FRF_AB_XX_COMMA_DET_CH0_WIDTH 1 2997#define FRF_AB_XX_CGRP_ALIGN_CH3_LBN 11 2998#define FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1 2999#define FRF_AB_XX_CGRP_ALIGN_CH2_LBN 10 3000#define FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1 3001#define FRF_AB_XX_CGRP_ALIGN_CH1_LBN 9 3002#define FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1 3003#define FRF_AB_XX_CGRP_ALIGN_CH0_LBN 8 3004#define FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1 3005#define FRF_AB_XX_CHAR_ERR_CH3_LBN 7 3006#define FRF_AB_XX_CHAR_ERR_CH3_WIDTH 1 3007#define FRF_AB_XX_CHAR_ERR_CH2_LBN 6 3008#define FRF_AB_XX_CHAR_ERR_CH2_WIDTH 1 3009#define FRF_AB_XX_CHAR_ERR_CH1_LBN 5 3010#define FRF_AB_XX_CHAR_ERR_CH1_WIDTH 1 3011#define FRF_AB_XX_CHAR_ERR_CH0_LBN 4 3012#define FRF_AB_XX_CHAR_ERR_CH0_WIDTH 1 3013#define FRF_AB_XX_DISPERR_CH3_LBN 3 3014#define FRF_AB_XX_DISPERR_CH3_WIDTH 1 3015#define FRF_AB_XX_DISPERR_CH2_LBN 2 3016#define FRF_AB_XX_DISPERR_CH2_WIDTH 1 3017#define FRF_AB_XX_DISPERR_CH1_LBN 1 3018#define FRF_AB_XX_DISPERR_CH1_WIDTH 1 3019#define FRF_AB_XX_DISPERR_CH0_LBN 0 3020#define FRF_AB_XX_DISPERR_CH0_WIDTH 1 3021 3022/* 3023 * FR_AA_RX_DESC_PTR_TBL_KER(128bit): 3024 * Receive descriptor pointer table 3025 */ 3026#define FR_AA_RX_DESC_PTR_TBL_KER_OFST 0x00011800 3027/* falcona0=net_func_bar2 */ 3028#define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16 3029#define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4 3030/* 3031 * FR_AZ_RX_DESC_PTR_TBL(128bit): 3032 * Receive descriptor pointer table 3033 */ 3034#define FR_AZ_RX_DESC_PTR_TBL_OFST 0x00f40000 3035/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3036#define FR_AZ_RX_DESC_PTR_TBL_STEP 16 3037#define FR_CZ_RX_DESC_PTR_TBL_ROWS 1024 3038#define FR_AB_RX_DESC_PTR_TBL_ROWS 4096 3039 3040#define FRF_CZ_RX_HDR_SPLIT_LBN 90 3041#define FRF_CZ_RX_HDR_SPLIT_WIDTH 1 3042#define FRF_AZ_RX_RESET_LBN 89 3043#define FRF_AZ_RX_RESET_WIDTH 1 3044#define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88 3045#define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1 3046#define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87 3047#define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1 3048#define FRF_AZ_RX_DESC_PREF_ACT_LBN 86 3049#define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1 3050#define FRF_AZ_RX_DC_HW_RPTR_LBN 80 3051#define FRF_AZ_RX_DC_HW_RPTR_WIDTH 6 3052#define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68 3053#define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12 3054#define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56 3055#define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12 3056#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36 3057#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20 3058#define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24 3059#define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12 3060#define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10 3061#define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14 3062#define FRF_AZ_RX_DESCQ_LABEL_LBN 5 3063#define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5 3064#define FRF_AZ_RX_DESCQ_SIZE_LBN 3 3065#define FRF_AZ_RX_DESCQ_SIZE_WIDTH 2 3066#define FFE_AZ_RX_DESCQ_SIZE_4K 3 3067#define FFE_AZ_RX_DESCQ_SIZE_2K 2 3068#define FFE_AZ_RX_DESCQ_SIZE_1K 1 3069#define FFE_AZ_RX_DESCQ_SIZE_512 0 3070#define FRF_AZ_RX_DESCQ_TYPE_LBN 2 3071#define FRF_AZ_RX_DESCQ_TYPE_WIDTH 1 3072#define FRF_AZ_RX_DESCQ_JUMBO_LBN 1 3073#define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1 3074#define FRF_AZ_RX_DESCQ_EN_LBN 0 3075#define FRF_AZ_RX_DESCQ_EN_WIDTH 1 3076 3077/* 3078 * FR_AA_TX_DESC_PTR_TBL_KER(128bit): 3079 * Transmit descriptor pointer 3080 */ 3081#define FR_AA_TX_DESC_PTR_TBL_KER_OFST 0x00011900 3082/* falcona0=net_func_bar2 */ 3083#define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16 3084#define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8 3085/* 3086 * FR_AZ_TX_DESC_PTR_TBL(128bit): 3087 * Transmit descriptor pointer 3088 */ 3089#define FR_AZ_TX_DESC_PTR_TBL_OFST 0x00f50000 3090/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 3091#define FR_AZ_TX_DESC_PTR_TBL_STEP 16 3092#define FR_AB_TX_DESC_PTR_TBL_ROWS 4096 3093#define FR_CZ_TX_DESC_PTR_TBL_ROWS 1024 3094 3095#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94 3096#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2 3097#define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93 3098#define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1 3099#define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92 3100#define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1 3101#define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91 3102#define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1 3103#define FRF_BZ_TX_IP_CHKSM_DIS_LBN 90 3104#define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1 3105#define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89 3106#define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1 3107#define FRF_AZ_TX_DESCQ_EN_LBN 88 3108#define FRF_AZ_TX_DESCQ_EN_WIDTH 1 3109#define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87 3110#define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1 3111#define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86 3112#define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1 3113#define FRF_AZ_TX_DC_HW_RPTR_LBN 80 3114#define FRF_AZ_TX_DC_HW_RPTR_WIDTH 6 3115#define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68 3116#define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12 3117#define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56 3118#define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12 3119#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36 3120#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20 3121#define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24 3122#define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12 3123#define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10 3124#define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14 3125#define FRF_AZ_TX_DESCQ_LABEL_LBN 5 3126#define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5 3127#define FRF_AZ_TX_DESCQ_SIZE_LBN 3 3128#define FRF_AZ_TX_DESCQ_SIZE_WIDTH 2 3129#define FFE_AZ_TX_DESCQ_SIZE_4K 3 3130#define FFE_AZ_TX_DESCQ_SIZE_2K 2 3131#define FFE_AZ_TX_DESCQ_SIZE_1K 1 3132#define FFE_AZ_TX_DESCQ_SIZE_512 0 3133#define FRF_AZ_TX_DESCQ_TYPE_LBN 1 3134#define FRF_AZ_TX_DESCQ_TYPE_WIDTH 2 3135#define FRF_AZ_TX_DESCQ_FLUSH_LBN 0 3136#define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1 3137 3138/* 3139 * FR_AA_EVQ_PTR_TBL_KER(128bit): 3140 * Event queue pointer table 3141 */ 3142#define FR_AA_EVQ_PTR_TBL_KER_OFST 0x00011a00 3143/* falcona0=net_func_bar2 */ 3144#define FR_AA_EVQ_PTR_TBL_KER_STEP 16 3145#define FR_AA_EVQ_PTR_TBL_KER_ROWS 4 3146/* 3147 * FR_AZ_EVQ_PTR_TBL(128bit): 3148 * Event queue pointer table 3149 */ 3150#define FR_AZ_EVQ_PTR_TBL_OFST 0x00f60000 3151/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3152#define FR_AZ_EVQ_PTR_TBL_STEP 16 3153#define FR_CZ_EVQ_PTR_TBL_ROWS 1024 3154#define FR_AB_EVQ_PTR_TBL_ROWS 4096 3155 3156#define FRF_BZ_EVQ_RPTR_IGN_LBN 40 3157#define FRF_BZ_EVQ_RPTR_IGN_WIDTH 1 3158#define FRF_AZ_EVQ_WKUP_OR_INT_EN_LBN 39 3159#define FRF_AZ_EVQ_WKUP_OR_INT_EN_WIDTH 1 3160#define FRF_AZ_EVQ_NXT_WPTR_LBN 24 3161#define FRF_AZ_EVQ_NXT_WPTR_WIDTH 15 3162#define FRF_AZ_EVQ_EN_LBN 23 3163#define FRF_AZ_EVQ_EN_WIDTH 1 3164#define FRF_AZ_EVQ_SIZE_LBN 20 3165#define FRF_AZ_EVQ_SIZE_WIDTH 3 3166#define FFE_AZ_EVQ_SIZE_32K 6 3167#define FFE_AZ_EVQ_SIZE_16K 5 3168#define FFE_AZ_EVQ_SIZE_8K 4 3169#define FFE_AZ_EVQ_SIZE_4K 3 3170#define FFE_AZ_EVQ_SIZE_2K 2 3171#define FFE_AZ_EVQ_SIZE_1K 1 3172#define FFE_AZ_EVQ_SIZE_512 0 3173#define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0 3174#define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20 3175 3176/* 3177 * FR_AA_BUF_HALF_TBL_KER(64bit): 3178 * Buffer table in half buffer table mode direct access by driver 3179 */ 3180#define FR_AA_BUF_HALF_TBL_KER_OFST 0x00018000 3181/* falcona0=net_func_bar2 */ 3182#define FR_AA_BUF_HALF_TBL_KER_STEP 8 3183#define FR_AA_BUF_HALF_TBL_KER_ROWS 4096 3184/* 3185 * FR_AZ_BUF_HALF_TBL(64bit): 3186 * Buffer table in half buffer table mode direct access by driver 3187 */ 3188#define FR_AZ_BUF_HALF_TBL_OFST 0x00800000 3189/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3190#define FR_AZ_BUF_HALF_TBL_STEP 8 3191#define FR_CZ_BUF_HALF_TBL_ROWS 147456 3192#define FR_AB_BUF_HALF_TBL_ROWS 524288 3193 3194#define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44 3195#define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20 3196#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32 3197#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12 3198#define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12 3199#define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20 3200#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0 3201#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12 3202 3203/* 3204 * FR_AA_BUF_FULL_TBL_KER(64bit): 3205 * Buffer table in full buffer table mode direct access by driver 3206 */ 3207#define FR_AA_BUF_FULL_TBL_KER_OFST 0x00018000 3208/* falcona0=net_func_bar2 */ 3209#define FR_AA_BUF_FULL_TBL_KER_STEP 8 3210#define FR_AA_BUF_FULL_TBL_KER_ROWS 4096 3211/* 3212 * FR_AZ_BUF_FULL_TBL(64bit): 3213 * Buffer table in full buffer table mode direct access by driver 3214 */ 3215#define FR_AZ_BUF_FULL_TBL_OFST 0x00800000 3216/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3217#define FR_AZ_BUF_FULL_TBL_STEP 8 3218 3219#define FR_CZ_BUF_FULL_TBL_ROWS 147456 3220#define FR_AB_BUF_FULL_TBL_ROWS 917504 3221 3222#define FRF_AZ_BUF_FULL_UNUSED_LBN 51 3223#define FRF_AZ_BUF_FULL_UNUSED_WIDTH 13 3224#define FRF_AZ_IP_DAT_BUF_SIZE_LBN 50 3225#define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1 3226#define FRF_AZ_BUF_ADR_REGION_LBN 48 3227#define FRF_AZ_BUF_ADR_REGION_WIDTH 2 3228#define FFE_AZ_BUF_ADR_REGN3 3 3229#define FFE_AZ_BUF_ADR_REGN2 2 3230#define FFE_AZ_BUF_ADR_REGN1 1 3231#define FFE_AZ_BUF_ADR_REGN0 0 3232#define FRF_AZ_BUF_ADR_FBUF_LBN 14 3233#define FRF_AZ_BUF_ADR_FBUF_WIDTH 34 3234#define FRF_AZ_BUF_ADR_FBUF_DW0_LBN 14 3235#define FRF_AZ_BUF_ADR_FBUF_DW0_WIDTH 32 3236#define FRF_AZ_BUF_ADR_FBUF_DW1_LBN 46 3237#define FRF_AZ_BUF_ADR_FBUF_DW1_WIDTH 2 3238#define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0 3239#define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14 3240 3241/* 3242 * FR_AZ_RX_FILTER_TBL0(128bit): 3243 * TCP/IPv4 Receive filter table 3244 */ 3245#define FR_AZ_RX_FILTER_TBL0_OFST 0x00f00000 3246/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 3247#define FR_AZ_RX_FILTER_TBL0_STEP 32 3248#define FR_AZ_RX_FILTER_TBL0_ROWS 8192 3249/* 3250 * FR_AB_RX_FILTER_TBL1(128bit): 3251 * TCP/IPv4 Receive filter table 3252 */ 3253#define FR_AB_RX_FILTER_TBL1_OFST 0x00f00010 3254/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3255#define FR_AB_RX_FILTER_TBL1_STEP 32 3256#define FR_AB_RX_FILTER_TBL1_ROWS 8192 3257 3258#define FRF_BZ_RSS_EN_LBN 110 3259#define FRF_BZ_RSS_EN_WIDTH 1 3260#define FRF_BZ_SCATTER_EN_LBN 109 3261#define FRF_BZ_SCATTER_EN_WIDTH 1 3262#define FRF_AZ_TCP_UDP_LBN 108 3263#define FRF_AZ_TCP_UDP_WIDTH 1 3264#define FRF_AZ_RXQ_ID_LBN 96 3265#define FRF_AZ_RXQ_ID_WIDTH 12 3266#define FRF_AZ_DEST_IP_LBN 64 3267#define FRF_AZ_DEST_IP_WIDTH 32 3268#define FRF_AZ_DEST_PORT_TCP_LBN 48 3269#define FRF_AZ_DEST_PORT_TCP_WIDTH 16 3270#define FRF_AZ_SRC_IP_LBN 16 3271#define FRF_AZ_SRC_IP_WIDTH 32 3272#define FRF_AZ_SRC_TCP_DEST_UDP_LBN 0 3273#define FRF_AZ_SRC_TCP_DEST_UDP_WIDTH 16 3274 3275/* 3276 * FR_CZ_RX_MAC_FILTER_TBL0(128bit): 3277 * Receive Ethernet filter table 3278 */ 3279#define FR_CZ_RX_MAC_FILTER_TBL0_OFST 0x00f00010 3280/* sienaa0=net_func_bar2 */ 3281#define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32 3282#define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512 3283 3284#define FRF_CZ_RMFT_RSS_EN_LBN 75 3285#define FRF_CZ_RMFT_RSS_EN_WIDTH 1 3286#define FRF_CZ_RMFT_SCATTER_EN_LBN 74 3287#define FRF_CZ_RMFT_SCATTER_EN_WIDTH 1 3288#define FRF_CZ_RMFT_IP_OVERRIDE_LBN 73 3289#define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1 3290#define FRF_CZ_RMFT_RXQ_ID_LBN 61 3291#define FRF_CZ_RMFT_RXQ_ID_WIDTH 12 3292#define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60 3293#define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1 3294#define FRF_CZ_RMFT_DEST_MAC_LBN 12 3295#define FRF_CZ_RMFT_DEST_MAC_WIDTH 48 3296#define FRF_CZ_RMFT_DEST_MAC_DW0_LBN 12 3297#define FRF_CZ_RMFT_DEST_MAC_DW0_WIDTH 32 3298#define FRF_CZ_RMFT_DEST_MAC_DW1_LBN 44 3299#define FRF_CZ_RMFT_DEST_MAC_DW1_WIDTH 16 3300#define FRF_CZ_RMFT_VLAN_ID_LBN 0 3301#define FRF_CZ_RMFT_VLAN_ID_WIDTH 12 3302 3303/* 3304 * FR_AZ_TIMER_TBL(128bit): 3305 * Timer table 3306 */ 3307#define FR_AZ_TIMER_TBL_OFST 0x00f70000 3308/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3309#define FR_AZ_TIMER_TBL_STEP 16 3310#define FR_CZ_TIMER_TBL_ROWS 1024 3311#define FR_AB_TIMER_TBL_ROWS 4096 3312 3313#define FRF_CZ_TIMER_Q_EN_LBN 33 3314#define FRF_CZ_TIMER_Q_EN_WIDTH 1 3315#define FRF_CZ_INT_ARMD_LBN 32 3316#define FRF_CZ_INT_ARMD_WIDTH 1 3317#define FRF_CZ_INT_PEND_LBN 31 3318#define FRF_CZ_INT_PEND_WIDTH 1 3319#define FRF_CZ_HOST_NOTIFY_MODE_LBN 30 3320#define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1 3321#define FRF_CZ_RELOAD_TIMER_VAL_LBN 16 3322#define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14 3323#define FRF_CZ_TIMER_MODE_LBN 14 3324#define FRF_CZ_TIMER_MODE_WIDTH 2 3325#define FFE_CZ_TIMER_MODE_INT_HLDOFF 3 3326#define FFE_CZ_TIMER_MODE_TRIG_START 2 3327#define FFE_CZ_TIMER_MODE_IMMED_START 1 3328#define FFE_CZ_TIMER_MODE_DIS 0 3329#define FRF_AB_TIMER_MODE_LBN 12 3330#define FRF_AB_TIMER_MODE_WIDTH 2 3331#define FFE_AB_TIMER_MODE_INT_HLDOFF 2 3332#define FFE_AB_TIMER_MODE_TRIG_START 2 3333#define FFE_AB_TIMER_MODE_IMMED_START 1 3334#define FFE_AB_TIMER_MODE_DIS 0 3335#define FRF_CZ_TIMER_VAL_LBN 0 3336#define FRF_CZ_TIMER_VAL_WIDTH 14 3337#define FRF_AB_TIMER_VAL_LBN 0 3338#define FRF_AB_TIMER_VAL_WIDTH 12 3339 3340/* 3341 * FR_BZ_TX_PACE_TBL(128bit): 3342 * Transmit pacing table 3343 */ 3344#define FR_BZ_TX_PACE_TBL_OFST 0x00f80000 3345/* sienaa0=net_func_bar2,falconb0=net_func_bar2 */ 3346#define FR_AZ_TX_PACE_TBL_STEP 16 3347#define FR_CZ_TX_PACE_TBL_ROWS 1024 3348#define FR_BB_TX_PACE_TBL_ROWS 4096 3349/* 3350 * FR_AA_TX_PACE_TBL(128bit): 3351 * Transmit pacing table 3352 */ 3353#define FR_AA_TX_PACE_TBL_OFST 0x00f80040 3354/* falcona0=char_func_bar0 */ 3355/* FR_AZ_TX_PACE_TBL_STEP 16 */ 3356#define FR_AA_TX_PACE_TBL_ROWS 4092 3357 3358#define FRF_AZ_TX_PACE_LBN 0 3359#define FRF_AZ_TX_PACE_WIDTH 5 3360 3361/* 3362 * FR_BZ_RX_INDIRECTION_TBL(7bit): 3363 * RX Indirection Table 3364 */ 3365#define FR_BZ_RX_INDIRECTION_TBL_OFST 0x00fb0000 3366/* falconb0,sienaa0=net_func_bar2 */ 3367#define FR_BZ_RX_INDIRECTION_TBL_STEP 16 3368#define FR_BZ_RX_INDIRECTION_TBL_ROWS 128 3369 3370#define FRF_BZ_IT_QUEUE_LBN 0 3371#define FRF_BZ_IT_QUEUE_WIDTH 6 3372 3373/* 3374 * FR_CZ_TX_FILTER_TBL0(128bit): 3375 * TCP/IPv4 Transmit filter table 3376 */ 3377#define FR_CZ_TX_FILTER_TBL0_OFST 0x00fc0000 3378/* sienaa0=net_func_bar2 */ 3379#define FR_CZ_TX_FILTER_TBL0_STEP 16 3380#define FR_CZ_TX_FILTER_TBL0_ROWS 8192 3381 3382#define FRF_CZ_TIFT_TCP_UDP_LBN 108 3383#define FRF_CZ_TIFT_TCP_UDP_WIDTH 1 3384#define FRF_CZ_TIFT_TXQ_ID_LBN 96 3385#define FRF_CZ_TIFT_TXQ_ID_WIDTH 12 3386#define FRF_CZ_TIFT_DEST_IP_LBN 64 3387#define FRF_CZ_TIFT_DEST_IP_WIDTH 32 3388#define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48 3389#define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16 3390#define FRF_CZ_TIFT_SRC_IP_LBN 16 3391#define FRF_CZ_TIFT_SRC_IP_WIDTH 32 3392#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0 3393#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16 3394 3395/* 3396 * FR_CZ_TX_MAC_FILTER_TBL0(128bit): 3397 * Transmit Ethernet filter table 3398 */ 3399#define FR_CZ_TX_MAC_FILTER_TBL0_OFST 0x00fe0000 3400/* sienaa0=net_func_bar2 */ 3401#define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16 3402#define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512 3403 3404#define FRF_CZ_TMFT_TXQ_ID_LBN 61 3405#define FRF_CZ_TMFT_TXQ_ID_WIDTH 12 3406#define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60 3407#define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1 3408#define FRF_CZ_TMFT_SRC_MAC_LBN 12 3409#define FRF_CZ_TMFT_SRC_MAC_WIDTH 48 3410#define FRF_CZ_TMFT_SRC_MAC_DW0_LBN 12 3411#define FRF_CZ_TMFT_SRC_MAC_DW0_WIDTH 32 3412#define FRF_CZ_TMFT_SRC_MAC_DW1_LBN 44 3413#define FRF_CZ_TMFT_SRC_MAC_DW1_WIDTH 16 3414#define FRF_CZ_TMFT_VLAN_ID_LBN 0 3415#define FRF_CZ_TMFT_VLAN_ID_WIDTH 12 3416 3417/* 3418 * FR_CZ_MC_TREG_SMEM(32bit): 3419 * MC Shared Memory 3420 */ 3421#define FR_CZ_MC_TREG_SMEM_OFST 0x00ff0000 3422/* sienaa0=net_func_bar2 */ 3423#define FR_CZ_MC_TREG_SMEM_STEP 4 3424#define FR_CZ_MC_TREG_SMEM_ROWS 512 3425 3426#define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0 3427#define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32 3428 3429/* 3430 * FR_BB_MSIX_VECTOR_TABLE(128bit): 3431 * MSIX Vector Table 3432 */ 3433#define FR_BB_MSIX_VECTOR_TABLE_OFST 0x00ff0000 3434/* falconb0=net_func_bar2 */ 3435#define FR_BZ_MSIX_VECTOR_TABLE_STEP 16 3436#define FR_BB_MSIX_VECTOR_TABLE_ROWS 64 3437/* 3438 * FR_CZ_MSIX_VECTOR_TABLE(128bit): 3439 * MSIX Vector Table 3440 */ 3441#define FR_CZ_MSIX_VECTOR_TABLE_OFST 0x00000000 3442/* sienaa0=pci_f0_bar4 */ 3443/* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */ 3444#define FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024 3445 3446#define FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97 3447#define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31 3448#define FRF_BZ_MSIX_VECTOR_MASK_LBN 96 3449#define FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1 3450#define FRF_BZ_MSIX_MESSAGE_DATA_LBN 64 3451#define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32 3452#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32 3453#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32 3454#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0 3455#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32 3456 3457/* 3458 * FR_BB_MSIX_PBA_TABLE(32bit): 3459 * MSIX Pending Bit Array 3460 */ 3461#define FR_BB_MSIX_PBA_TABLE_OFST 0x00ff2000 3462/* falconb0=net_func_bar2 */ 3463#define FR_BZ_MSIX_PBA_TABLE_STEP 4 3464#define FR_BB_MSIX_PBA_TABLE_ROWS 2 3465/* 3466 * FR_CZ_MSIX_PBA_TABLE(32bit): 3467 * MSIX Pending Bit Array 3468 */ 3469#define FR_CZ_MSIX_PBA_TABLE_OFST 0x00008000 3470/* sienaa0=pci_f0_bar4 */ 3471/* FR_BZ_MSIX_PBA_TABLE_STEP 4 */ 3472#define FR_CZ_MSIX_PBA_TABLE_ROWS 32 3473 3474#define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0 3475#define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32 3476 3477/* 3478 * FR_AZ_SRM_DBG_REG(64bit): 3479 * SRAM debug access 3480 */ 3481#define FR_AZ_SRM_DBG_REG_OFST 0x03000000 3482/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3483#define FR_AZ_SRM_DBG_REG_STEP 8 3484 3485#define FR_CZ_SRM_DBG_REG_ROWS 262144 3486#define FR_AB_SRM_DBG_REG_ROWS 2097152 3487 3488#define FRF_AZ_SRM_DBG_LBN 0 3489#define FRF_AZ_SRM_DBG_WIDTH 64 3490#define FRF_AZ_SRM_DBG_DW0_LBN 0 3491#define FRF_AZ_SRM_DBG_DW0_WIDTH 32 3492#define FRF_AZ_SRM_DBG_DW1_LBN 32 3493#define FRF_AZ_SRM_DBG_DW1_WIDTH 32 3494 3495/* 3496 * FR_AA_INT_ACK_CHAR(32bit): 3497 * CHAR interrupt acknowledge register 3498 */ 3499#define FR_AA_INT_ACK_CHAR_OFST 0x00000060 3500/* falcona0=char_func_bar0 */ 3501 3502#define FRF_AA_INT_ACK_CHAR_FIELD_LBN 0 3503#define FRF_AA_INT_ACK_CHAR_FIELD_WIDTH 32 3504 3505/* FS_DRIVER_EV */ 3506#define FSF_AZ_DRIVER_EV_SUBCODE_LBN 56 3507#define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4 3508#define FSE_AZ_TX_DSC_ERROR_EV 15 3509#define FSE_AZ_RX_DSC_ERROR_EV 14 3510#define FSE_AZ_RX_RECOVER_EV 11 3511#define FSE_AZ_TIMER_EV 10 3512#define FSE_AZ_TX_PKT_NON_TCP_UDP 9 3513#define FSE_AZ_WAKE_UP_EV 6 3514#define FSE_AZ_SRM_UPD_DONE_EV 5 3515#define FSE_AZ_EVQ_NOT_EN_EV 3 3516#define FSE_AZ_EVQ_INIT_DONE_EV 2 3517#define FSE_AZ_RX_DESCQ_FLS_DONE_EV 1 3518#define FSE_AZ_TX_DESCQ_FLS_DONE_EV 0 3519#define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0 3520#define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14 3521 3522/* FS_EVENT_ENTRY */ 3523#define FSF_AZ_EV_CODE_LBN 60 3524#define FSF_AZ_EV_CODE_WIDTH 4 3525#define FSE_AZ_EV_CODE_USER_EV 8 3526#define FSE_AZ_EV_CODE_DRV_GEN_EV 7 3527#define FSE_AZ_EV_CODE_GLOBAL_EV 6 3528#define FSE_AZ_EV_CODE_DRIVER_EV 5 3529#define FSE_AZ_EV_CODE_TX_EV 2 3530#define FSE_AZ_EV_CODE_RX_EV 0 3531#define FSF_AZ_EV_DATA_LBN 0 3532#define FSF_AZ_EV_DATA_WIDTH 60 3533#define FSF_AZ_EV_DATA_DW0_LBN 0 3534#define FSF_AZ_EV_DATA_DW0_WIDTH 32 3535#define FSF_AZ_EV_DATA_DW1_LBN 32 3536#define FSF_AZ_EV_DATA_DW1_WIDTH 28 3537 3538/* FS_GLOBAL_EV */ 3539#define FSF_AA_GLB_EV_RX_RECOVERY_LBN 12 3540#define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1 3541#define FSF_BZ_GLB_EV_XG_MNT_INTR_LBN 11 3542#define FSF_BZ_GLB_EV_XG_MNT_INTR_WIDTH 1 3543#define FSF_AZ_GLB_EV_XFP_PHY0_INTR_LBN 10 3544#define FSF_AZ_GLB_EV_XFP_PHY0_INTR_WIDTH 1 3545#define FSF_AZ_GLB_EV_XG_PHY0_INTR_LBN 9 3546#define FSF_AZ_GLB_EV_XG_PHY0_INTR_WIDTH 1 3547#define FSF_AZ_GLB_EV_G_PHY0_INTR_LBN 7 3548#define FSF_AZ_GLB_EV_G_PHY0_INTR_WIDTH 1 3549 3550/* FS_RX_EV */ 3551#define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58 3552#define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1 3553#define FSF_CZ_RX_EV_IPV6_PKT_LBN 57 3554#define FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1 3555#define FSF_AZ_RX_EV_PKT_OK_LBN 56 3556#define FSF_AZ_RX_EV_PKT_OK_WIDTH 1 3557#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55 3558#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1 3559#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54 3560#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1 3561#define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53 3562#define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1 3563#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52 3564#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1 3565#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51 3566#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1 3567#define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50 3568#define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1 3569#define FSF_AZ_RX_EV_FRM_TRUNC_LBN 49 3570#define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1 3571#define FSF_AZ_RX_EV_TOBE_DISC_LBN 47 3572#define FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1 3573#define FSF_AZ_RX_EV_PKT_TYPE_LBN 44 3574#define FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3 3575#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5 3576#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4 3577#define FSE_AZ_RX_EV_PKT_TYPE_VLAN 3 3578#define FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2 3579#define FSE_AZ_RX_EV_PKT_TYPE_LLC 1 3580#define FSE_AZ_RX_EV_PKT_TYPE_ETH 0 3581#define FSF_AZ_RX_EV_HDR_TYPE_LBN 42 3582#define FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2 3583#define FSE_AZ_RX_EV_HDR_TYPE_OTHER 3 3584#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_OTHER 2 3585#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2 3586#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_UDP 1 3587#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1 3588#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_TCP 0 3589#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0 3590#define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41 3591#define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1 3592#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40 3593#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1 3594#define FSF_AZ_RX_EV_MCAST_PKT_LBN 39 3595#define FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1 3596#define FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37 3597#define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1 3598#define FSF_AZ_RX_EV_Q_LABEL_LBN 32 3599#define FSF_AZ_RX_EV_Q_LABEL_WIDTH 5 3600#define FSF_AZ_RX_EV_JUMBO_CONT_LBN 31 3601#define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1 3602#define FSF_AZ_RX_EV_PORT_LBN 30 3603#define FSF_AZ_RX_EV_PORT_WIDTH 1 3604#define FSF_AZ_RX_EV_BYTE_CNT_LBN 16 3605#define FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14 3606#define FSF_AZ_RX_EV_SOP_LBN 15 3607#define FSF_AZ_RX_EV_SOP_WIDTH 1 3608#define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14 3609#define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1 3610#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13 3611#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1 3612#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12 3613#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1 3614#define FSF_AZ_RX_EV_DESC_PTR_LBN 0 3615#define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12 3616 3617/* FS_RX_KER_DESC */ 3618#define FSF_AZ_RX_KER_BUF_SIZE_LBN 48 3619#define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14 3620#define FSF_AZ_RX_KER_BUF_REGION_LBN 46 3621#define FSF_AZ_RX_KER_BUF_REGION_WIDTH 2 3622#define FSF_AZ_RX_KER_BUF_ADDR_LBN 0 3623#define FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46 3624#define FSF_AZ_RX_KER_BUF_ADDR_DW0_LBN 0 3625#define FSF_AZ_RX_KER_BUF_ADDR_DW0_WIDTH 32 3626#define FSF_AZ_RX_KER_BUF_ADDR_DW1_LBN 32 3627#define FSF_AZ_RX_KER_BUF_ADDR_DW1_WIDTH 14 3628 3629/* FS_RX_USER_DESC */ 3630#define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20 3631#define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12 3632#define FSF_AZ_RX_USER_BUF_ID_LBN 0 3633#define FSF_AZ_RX_USER_BUF_ID_WIDTH 20 3634 3635/* FS_TX_EV */ 3636#define FSF_AZ_TX_EV_PKT_ERR_LBN 38 3637#define FSF_AZ_TX_EV_PKT_ERR_WIDTH 1 3638#define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37 3639#define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1 3640#define FSF_AZ_TX_EV_Q_LABEL_LBN 32 3641#define FSF_AZ_TX_EV_Q_LABEL_WIDTH 5 3642#define FSF_AZ_TX_EV_PORT_LBN 16 3643#define FSF_AZ_TX_EV_PORT_WIDTH 1 3644#define FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15 3645#define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1 3646#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14 3647#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1 3648#define FSF_AZ_TX_EV_COMP_LBN 12 3649#define FSF_AZ_TX_EV_COMP_WIDTH 1 3650#define FSF_AZ_TX_EV_DESC_PTR_LBN 0 3651#define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12 3652 3653/* FS_TX_KER_DESC */ 3654#define FSF_AZ_TX_KER_CONT_LBN 62 3655#define FSF_AZ_TX_KER_CONT_WIDTH 1 3656#define FSF_AZ_TX_KER_BYTE_COUNT_LBN 48 3657#define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14 3658#define FSF_AZ_TX_KER_BUF_REGION_LBN 46 3659#define FSF_AZ_TX_KER_BUF_REGION_WIDTH 2 3660#define FSF_AZ_TX_KER_BUF_ADDR_LBN 0 3661#define FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46 3662#define FSF_AZ_TX_KER_BUF_ADDR_DW0_LBN 0 3663#define FSF_AZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 3664#define FSF_AZ_TX_KER_BUF_ADDR_DW1_LBN 32 3665#define FSF_AZ_TX_KER_BUF_ADDR_DW1_WIDTH 14 3666 3667/* FS_TX_USER_DESC */ 3668#define FSF_AZ_TX_USER_SW_EV_EN_LBN 48 3669#define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1 3670#define FSF_AZ_TX_USER_CONT_LBN 46 3671#define FSF_AZ_TX_USER_CONT_WIDTH 1 3672#define FSF_AZ_TX_USER_BYTE_CNT_LBN 33 3673#define FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13 3674#define FSF_AZ_TX_USER_BUF_ID_LBN 13 3675#define FSF_AZ_TX_USER_BUF_ID_WIDTH 20 3676#define FSF_AZ_TX_USER_BYTE_OFS_LBN 0 3677#define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13 3678 3679/* FS_USER_EV */ 3680#define FSF_CZ_USER_QID_LBN 32 3681#define FSF_CZ_USER_QID_WIDTH 10 3682#define FSF_CZ_USER_EV_REG_VALUE_LBN 0 3683#define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32 3684 3685/* FS_NET_IVEC */ 3686#define FSF_AZ_NET_IVEC_FATAL_INT_LBN 64 3687#define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1 3688#define FSF_AZ_NET_IVEC_INT_Q_LBN 40 3689#define FSF_AZ_NET_IVEC_INT_Q_WIDTH 4 3690#define FSF_AZ_NET_IVEC_INT_FLAG_LBN 32 3691#define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1 3692#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1 3693#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1 3694#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0 3695#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1 3696 3697/* DRIVER_EV */ 3698/* Sub-fields of an RX flush completion event */ 3699#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12 3700#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1 3701#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0 3702#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12 3703 3704/************************************************************************** 3705 * 3706 * Falcon non-volatile configuration 3707 * 3708 ************************************************************************** 3709 */ 3710 3711#define FR_AZ_TX_PACE_TBL_OFST FR_BZ_TX_PACE_TBL_OFST 3712 3713#ifdef __cplusplus 3714} 3715#endif 3716 3717#endif /* _SYS_EFX_REGS_H */ 3718