1169689Skan/*- 2169689Skan * SPDX-License-Identifier: BSD-2-Clause 3169689Skan * 4169689Skan * Copyright (c) 2006-2016 Solarflare Communications Inc. 5169689Skan * All rights reserved. 6169689Skan * 7169689Skan * Redistribution and use in source and binary forms, with or without 8169689Skan * modification, are permitted provided that the following conditions are met: 9169689Skan * 10169689Skan * 1. Redistributions of source code must retain the above copyright notice, 11169689Skan * this list of conditions and the following disclaimer. 12169689Skan * 2. Redistributions in binary form must reproduce the above copyright notice, 13169689Skan * this list of conditions and the following disclaimer in the documentation 14169689Skan * and/or other materials provided with the distribution. 15169689Skan * 16169689Skan * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17169689Skan * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18169689Skan * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19169689Skan * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20169689Skan * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21169689Skan * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22169689Skan * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23169689Skan * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24169689Skan * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25169689Skan * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26169689Skan * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27169689Skan * 28169689Skan * The views and conclusions contained in the software and documentation are 29169689Skan * those of the authors and should not be interpreted as representing official 30169689Skan * policies, either expressed or implied, of the FreeBSD Project. 31169689Skan */ 32169689Skan 33169689Skan#ifndef _SYS_EFX_H 34169689Skan#define _SYS_EFX_H 35169689Skan 36169689Skan#include "efx_annote.h" 37169689Skan#include "efsys.h" 38169689Skan#include "efx_check.h" 39169689Skan#include "efx_phy_ids.h" 40169689Skan 41169689Skan#ifdef __cplusplus 42169689Skanextern "C" { 43169689Skan#endif 44169689Skan 45169689Skan#define EFX_STATIC_ASSERT(_cond) \ 46169689Skan ((void)sizeof (char[(_cond) ? 1 : -1])) 47169689Skan 48169689Skan#define EFX_ARRAY_SIZE(_array) \ 49169689Skan (sizeof (_array) / sizeof ((_array)[0])) 50169689Skan 51169689Skan#define EFX_FIELD_OFFSET(_type, _field) \ 52169689Skan ((size_t)&(((_type *)0)->_field)) 53169689Skan 54169689Skan/* The macro expands divider twice */ 55169689Skan#define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d)) 56169689Skan 57169689Skan/* Round value up to the nearest power of two. */ 58169689Skan#define EFX_P2ROUNDUP(_type, _value, _align) \ 59169689Skan (-(-(_type)(_value) & -(_type)(_align))) 60169689Skan 61169689Skan/* Align value down to the nearest power of two. */ 62169689Skan#define EFX_P2ALIGN(_type, _value, _align) \ 63169689Skan ((_type)(_value) & -(_type)(_align)) 64169689Skan 65169689Skan/* Test if value is power of 2 aligned. */ 66169689Skan#define EFX_IS_P2ALIGNED(_type, _value, _align) \ 67169689Skan ((((_type)(_value)) & ((_type)(_align) - 1)) == 0) 68169689Skan 69169689Skan/* Return codes */ 70169689Skan 71169689Skantypedef __success(return == 0) int efx_rc_t; 72169689Skan 73169689Skan/* Chip families */ 74169689Skan 75169689Skantypedef enum efx_family_e { 76169689Skan EFX_FAMILY_INVALID, 77169689Skan EFX_FAMILY_FALCON, /* Obsolete and not supported */ 78169689Skan EFX_FAMILY_SIENA, 79169689Skan EFX_FAMILY_HUNTINGTON, 80169689Skan EFX_FAMILY_MEDFORD, 81169689Skan EFX_FAMILY_MEDFORD2, 82169689Skan EFX_FAMILY_NTYPES 83169689Skan} efx_family_t; 84169689Skan 85169689Skanextern __checkReturn efx_rc_t 86169689Skanefx_family( 87169689Skan __in uint16_t venid, 88169689Skan __in uint16_t devid, 89169689Skan __out efx_family_t *efp, 90169689Skan __out unsigned int *membarp); 91169689Skan 92169689Skan#define EFX_PCI_VENID_SFC 0x1924 93169689Skan 94169689Skan#define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 95169689Skan 96169689Skan#define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 97169689Skan#define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 98169689Skan#define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 99169689Skan 100169689Skan#define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 101169689Skan#define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 102169689Skan#define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 103169689Skan 104169689Skan#define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 105169689Skan#define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 106169689Skan 107169689Skan#define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 108169689Skan#define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 109169689Skan#define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 110169689Skan 111169689Skan#define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13 112169689Skan#define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */ 113169689Skan#define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */ 114169689Skan 115169689Skan#define EFX_MEM_BAR_SIENA 2 116169689Skan 117169689Skan#define EFX_MEM_BAR_HUNTINGTON_PF 2 118169689Skan#define EFX_MEM_BAR_HUNTINGTON_VF 0 119220150Smm 120220150Smm#define EFX_MEM_BAR_MEDFORD_PF 2 121220150Smm#define EFX_MEM_BAR_MEDFORD_VF 0 122169689Skan 123169689Skan#define EFX_MEM_BAR_MEDFORD2 0 124169689Skan 125169689Skan/* Error codes */ 126169689Skan 127169689Skanenum { 128169689Skan EFX_ERR_INVALID, 129169689Skan EFX_ERR_SRAM_OOB, 130169689Skan EFX_ERR_BUFID_DC_OOB, 131169689Skan EFX_ERR_MEM_PERR, 132169689Skan EFX_ERR_RBUF_OWN, 133169689Skan EFX_ERR_TBUF_OWN, 134169689Skan EFX_ERR_RDESQ_OWN, 135169689Skan EFX_ERR_TDESQ_OWN, 136169689Skan EFX_ERR_EVQ_OWN, 137169689Skan EFX_ERR_EVFF_OFLO, 138169689Skan EFX_ERR_ILL_ADDR, 139169689Skan EFX_ERR_SRAM_PERR, 140169689Skan EFX_ERR_NCODES 141169689Skan}; 142169689Skan 143169689Skan/* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 144169689Skanextern __checkReturn uint32_t 145169689Skanefx_crc32_calculate( 146169689Skan __in uint32_t crc_init, 147169689Skan __in_ecount(length) uint8_t const *input, 148169689Skan __in int length); 149169689Skan 150169689Skan/* Type prototypes */ 151169689Skan 152169689Skantypedef struct efx_rxq_s efx_rxq_t; 153169689Skan 154169689Skan/* NIC */ 155169689Skan 156169689Skantypedef struct efx_nic_s efx_nic_t; 157169689Skan 158169689Skanextern __checkReturn efx_rc_t 159169689Skanefx_nic_create( 160169689Skan __in efx_family_t family, 161169689Skan __in efsys_identifier_t *esip, 162169689Skan __in efsys_bar_t *esbp, 163169689Skan __in efsys_lock_t *eslp, 164169689Skan __deref_out efx_nic_t **enpp); 165169689Skan 166169689Skan/* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */ 167169689Skantypedef enum efx_fw_variant_e { 168169689Skan EFX_FW_VARIANT_FULL_FEATURED, 169169689Skan EFX_FW_VARIANT_LOW_LATENCY, 170169689Skan EFX_FW_VARIANT_PACKED_STREAM, 171169689Skan EFX_FW_VARIANT_HIGH_TX_RATE, 172169689Skan EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1, 173169689Skan EFX_FW_VARIANT_RULES_ENGINE, 174169689Skan EFX_FW_VARIANT_DPDK, 175169689Skan EFX_FW_VARIANT_DONT_CARE = 0xffffffff 176169689Skan} efx_fw_variant_t; 177169689Skan 178169689Skanextern __checkReturn efx_rc_t 179169689Skanefx_nic_probe( 180169689Skan __in efx_nic_t *enp, 181169689Skan __in efx_fw_variant_t efv); 182169689Skan 183169689Skanextern __checkReturn efx_rc_t 184169689Skanefx_nic_init( 185169689Skan __in efx_nic_t *enp); 186169689Skan 187169689Skanextern __checkReturn efx_rc_t 188169689Skanefx_nic_reset( 189169689Skan __in efx_nic_t *enp); 190169689Skan 191169689Skanextern __checkReturn boolean_t 192169689Skanefx_nic_hw_unavailable( 193169689Skan __in efx_nic_t *enp); 194169689Skan 195169689Skanextern void 196169689Skanefx_nic_set_hw_unavailable( 197169689Skan __in efx_nic_t *enp); 198169689Skan 199169689Skan#if EFSYS_OPT_DIAG 200169689Skan 201169689Skanextern __checkReturn efx_rc_t 202169689Skanefx_nic_register_test( 203169689Skan __in efx_nic_t *enp); 204169689Skan 205169689Skan#endif /* EFSYS_OPT_DIAG */ 206169689Skan 207169689Skanextern void 208169689Skanefx_nic_fini( 209169689Skan __in efx_nic_t *enp); 210169689Skan 211169689Skanextern void 212169689Skanefx_nic_unprobe( 213169689Skan __in efx_nic_t *enp); 214169689Skan 215169689Skanextern void 216169689Skanefx_nic_destroy( 217169689Skan __in efx_nic_t *enp); 218169689Skan 219169689Skan#define EFX_PCIE_LINK_SPEED_GEN1 1 220169689Skan#define EFX_PCIE_LINK_SPEED_GEN2 2 221169689Skan#define EFX_PCIE_LINK_SPEED_GEN3 3 222169689Skan 223169689Skantypedef enum efx_pcie_link_performance_e { 224169689Skan EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH, 225169689Skan EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH, 226169689Skan EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY, 227169689Skan EFX_PCIE_LINK_PERFORMANCE_OPTIMAL 228169689Skan} efx_pcie_link_performance_t; 229169689Skan 230169689Skanextern __checkReturn efx_rc_t 231169689Skanefx_nic_calculate_pcie_link_bandwidth( 232169689Skan __in uint32_t pcie_link_width, 233169689Skan __in uint32_t pcie_link_gen, 234169689Skan __out uint32_t *bandwidth_mbpsp); 235169689Skan 236169689Skanextern __checkReturn efx_rc_t 237169689Skanefx_nic_check_pcie_link_speed( 238169689Skan __in efx_nic_t *enp, 239169689Skan __in uint32_t pcie_link_width, 240169689Skan __in uint32_t pcie_link_gen, 241169689Skan __out efx_pcie_link_performance_t *resultp); 242169689Skan 243169689Skan#if EFSYS_OPT_MCDI 244169689Skan 245169689Skan#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 246169689Skan/* Huntington and Medford require MCDIv2 commands */ 247169689Skan#define WITH_MCDI_V2 1 248169689Skan#endif 249169689Skan 250169689Skantypedef struct efx_mcdi_req_s efx_mcdi_req_t; 251169689Skan 252169689Skantypedef enum efx_mcdi_exception_e { 253169689Skan EFX_MCDI_EXCEPTION_MC_REBOOT, 254169689Skan EFX_MCDI_EXCEPTION_MC_BADASSERT, 255169689Skan} efx_mcdi_exception_t; 256169689Skan 257169689Skan#if EFSYS_OPT_MCDI_LOGGING 258169689Skantypedef enum efx_log_msg_e { 259169689Skan EFX_LOG_INVALID, 260169689Skan EFX_LOG_MCDI_REQUEST, 261169689Skan EFX_LOG_MCDI_RESPONSE, 262169689Skan} efx_log_msg_t; 263169689Skan#endif /* EFSYS_OPT_MCDI_LOGGING */ 264169689Skan 265169689Skantypedef struct efx_mcdi_transport_s { 266169689Skan void *emt_context; 267169689Skan efsys_mem_t *emt_dma_mem; 268169689Skan void (*emt_execute)(void *, efx_mcdi_req_t *); 269169689Skan void (*emt_ev_cpl)(void *); 270169689Skan void (*emt_exception)(void *, efx_mcdi_exception_t); 271169689Skan#if EFSYS_OPT_MCDI_LOGGING 272169689Skan void (*emt_logger)(void *, efx_log_msg_t, 273169689Skan void *, size_t, void *, size_t); 274169689Skan#endif /* EFSYS_OPT_MCDI_LOGGING */ 275169689Skan#if EFSYS_OPT_MCDI_PROXY_AUTH 276169689Skan void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 277169689Skan#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 278169689Skan} efx_mcdi_transport_t; 279169689Skan 280169689Skanextern __checkReturn efx_rc_t 281169689Skanefx_mcdi_init( 282169689Skan __in efx_nic_t *enp, 283169689Skan __in const efx_mcdi_transport_t *mtp); 284169689Skan 285169689Skanextern __checkReturn efx_rc_t 286169689Skanefx_mcdi_reboot( 287169689Skan __in efx_nic_t *enp); 288169689Skan 289 void 290efx_mcdi_new_epoch( 291 __in efx_nic_t *enp); 292 293extern void 294efx_mcdi_get_timeout( 295 __in efx_nic_t *enp, 296 __in efx_mcdi_req_t *emrp, 297 __out uint32_t *usec_timeoutp); 298 299extern void 300efx_mcdi_request_start( 301 __in efx_nic_t *enp, 302 __in efx_mcdi_req_t *emrp, 303 __in boolean_t ev_cpl); 304 305extern __checkReturn boolean_t 306efx_mcdi_request_poll( 307 __in efx_nic_t *enp); 308 309extern __checkReturn boolean_t 310efx_mcdi_request_abort( 311 __in efx_nic_t *enp); 312 313extern void 314efx_mcdi_fini( 315 __in efx_nic_t *enp); 316 317#endif /* EFSYS_OPT_MCDI */ 318 319/* INTR */ 320 321#define EFX_NINTR_SIENA 1024 322 323typedef enum efx_intr_type_e { 324 EFX_INTR_INVALID = 0, 325 EFX_INTR_LINE, 326 EFX_INTR_MESSAGE, 327 EFX_INTR_NTYPES 328} efx_intr_type_t; 329 330#define EFX_INTR_SIZE (sizeof (efx_oword_t)) 331 332extern __checkReturn efx_rc_t 333efx_intr_init( 334 __in efx_nic_t *enp, 335 __in efx_intr_type_t type, 336 __in_opt efsys_mem_t *esmp); 337 338extern void 339efx_intr_enable( 340 __in efx_nic_t *enp); 341 342extern void 343efx_intr_disable( 344 __in efx_nic_t *enp); 345 346extern void 347efx_intr_disable_unlocked( 348 __in efx_nic_t *enp); 349 350#define EFX_INTR_NEVQS 32 351 352extern __checkReturn efx_rc_t 353efx_intr_trigger( 354 __in efx_nic_t *enp, 355 __in unsigned int level); 356 357extern void 358efx_intr_status_line( 359 __in efx_nic_t *enp, 360 __out boolean_t *fatalp, 361 __out uint32_t *maskp); 362 363extern void 364efx_intr_status_message( 365 __in efx_nic_t *enp, 366 __in unsigned int message, 367 __out boolean_t *fatalp); 368 369extern void 370efx_intr_fatal( 371 __in efx_nic_t *enp); 372 373extern void 374efx_intr_fini( 375 __in efx_nic_t *enp); 376 377/* MAC */ 378 379#if EFSYS_OPT_MAC_STATS 380 381/* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */ 382typedef enum efx_mac_stat_e { 383 EFX_MAC_RX_OCTETS, 384 EFX_MAC_RX_PKTS, 385 EFX_MAC_RX_UNICST_PKTS, 386 EFX_MAC_RX_MULTICST_PKTS, 387 EFX_MAC_RX_BRDCST_PKTS, 388 EFX_MAC_RX_PAUSE_PKTS, 389 EFX_MAC_RX_LE_64_PKTS, 390 EFX_MAC_RX_65_TO_127_PKTS, 391 EFX_MAC_RX_128_TO_255_PKTS, 392 EFX_MAC_RX_256_TO_511_PKTS, 393 EFX_MAC_RX_512_TO_1023_PKTS, 394 EFX_MAC_RX_1024_TO_15XX_PKTS, 395 EFX_MAC_RX_GE_15XX_PKTS, 396 EFX_MAC_RX_ERRORS, 397 EFX_MAC_RX_FCS_ERRORS, 398 EFX_MAC_RX_DROP_EVENTS, 399 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 400 EFX_MAC_RX_SYMBOL_ERRORS, 401 EFX_MAC_RX_ALIGN_ERRORS, 402 EFX_MAC_RX_INTERNAL_ERRORS, 403 EFX_MAC_RX_JABBER_PKTS, 404 EFX_MAC_RX_LANE0_CHAR_ERR, 405 EFX_MAC_RX_LANE1_CHAR_ERR, 406 EFX_MAC_RX_LANE2_CHAR_ERR, 407 EFX_MAC_RX_LANE3_CHAR_ERR, 408 EFX_MAC_RX_LANE0_DISP_ERR, 409 EFX_MAC_RX_LANE1_DISP_ERR, 410 EFX_MAC_RX_LANE2_DISP_ERR, 411 EFX_MAC_RX_LANE3_DISP_ERR, 412 EFX_MAC_RX_MATCH_FAULT, 413 EFX_MAC_RX_NODESC_DROP_CNT, 414 EFX_MAC_TX_OCTETS, 415 EFX_MAC_TX_PKTS, 416 EFX_MAC_TX_UNICST_PKTS, 417 EFX_MAC_TX_MULTICST_PKTS, 418 EFX_MAC_TX_BRDCST_PKTS, 419 EFX_MAC_TX_PAUSE_PKTS, 420 EFX_MAC_TX_LE_64_PKTS, 421 EFX_MAC_TX_65_TO_127_PKTS, 422 EFX_MAC_TX_128_TO_255_PKTS, 423 EFX_MAC_TX_256_TO_511_PKTS, 424 EFX_MAC_TX_512_TO_1023_PKTS, 425 EFX_MAC_TX_1024_TO_15XX_PKTS, 426 EFX_MAC_TX_GE_15XX_PKTS, 427 EFX_MAC_TX_ERRORS, 428 EFX_MAC_TX_SGL_COL_PKTS, 429 EFX_MAC_TX_MULT_COL_PKTS, 430 EFX_MAC_TX_EX_COL_PKTS, 431 EFX_MAC_TX_LATE_COL_PKTS, 432 EFX_MAC_TX_DEF_PKTS, 433 EFX_MAC_TX_EX_DEF_PKTS, 434 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 435 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 436 EFX_MAC_PM_TRUNC_VFIFO_FULL, 437 EFX_MAC_PM_DISCARD_VFIFO_FULL, 438 EFX_MAC_PM_TRUNC_QBB, 439 EFX_MAC_PM_DISCARD_QBB, 440 EFX_MAC_PM_DISCARD_MAPPING, 441 EFX_MAC_RXDP_Q_DISABLED_PKTS, 442 EFX_MAC_RXDP_DI_DROPPED_PKTS, 443 EFX_MAC_RXDP_STREAMING_PKTS, 444 EFX_MAC_RXDP_HLB_FETCH, 445 EFX_MAC_RXDP_HLB_WAIT, 446 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 447 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 448 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 449 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 450 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 451 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 452 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 453 EFX_MAC_VADAPTER_RX_BAD_BYTES, 454 EFX_MAC_VADAPTER_RX_OVERFLOW, 455 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 456 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 457 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 458 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 459 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 460 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 461 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 462 EFX_MAC_VADAPTER_TX_BAD_BYTES, 463 EFX_MAC_VADAPTER_TX_OVERFLOW, 464 EFX_MAC_FEC_UNCORRECTED_ERRORS, 465 EFX_MAC_FEC_CORRECTED_ERRORS, 466 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0, 467 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1, 468 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2, 469 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3, 470 EFX_MAC_CTPIO_VI_BUSY_FALLBACK, 471 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS, 472 EFX_MAC_CTPIO_MISSING_DBELL_FAIL, 473 EFX_MAC_CTPIO_OVERFLOW_FAIL, 474 EFX_MAC_CTPIO_UNDERFLOW_FAIL, 475 EFX_MAC_CTPIO_TIMEOUT_FAIL, 476 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL, 477 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL, 478 EFX_MAC_CTPIO_INVALID_WR_FAIL, 479 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK, 480 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK, 481 EFX_MAC_CTPIO_RUNT_FALLBACK, 482 EFX_MAC_CTPIO_SUCCESS, 483 EFX_MAC_CTPIO_FALLBACK, 484 EFX_MAC_CTPIO_POISON, 485 EFX_MAC_CTPIO_ERASE, 486 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC, 487 EFX_MAC_RXDP_HLB_IDLE, 488 EFX_MAC_RXDP_HLB_TIMEOUT, 489 EFX_MAC_NSTATS 490} efx_mac_stat_t; 491 492/* END MKCONFIG GENERATED EfxHeaderMacBlock */ 493 494#endif /* EFSYS_OPT_MAC_STATS */ 495 496typedef enum efx_link_mode_e { 497 EFX_LINK_UNKNOWN = 0, 498 EFX_LINK_DOWN, 499 EFX_LINK_10HDX, 500 EFX_LINK_10FDX, 501 EFX_LINK_100HDX, 502 EFX_LINK_100FDX, 503 EFX_LINK_1000HDX, 504 EFX_LINK_1000FDX, 505 EFX_LINK_10000FDX, 506 EFX_LINK_40000FDX, 507 EFX_LINK_25000FDX, 508 EFX_LINK_50000FDX, 509 EFX_LINK_100000FDX, 510 EFX_LINK_NMODES 511} efx_link_mode_t; 512 513#define EFX_MAC_ADDR_LEN 6 514 515#define EFX_VNI_OR_VSID_LEN 3 516 517#define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01) 518 519#define EFX_MAC_MULTICAST_LIST_MAX 256 520 521#define EFX_MAC_SDU_MAX 9202 522 523#define EFX_MAC_PDU_ADJUSTMENT \ 524 (/* EtherII */ 14 \ 525 + /* VLAN */ 4 \ 526 + /* CRC */ 4 \ 527 + /* bug16011 */ 16) \ 528 529#define EFX_MAC_PDU(_sdu) \ 530 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) 531 532/* 533 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give 534 * the SDU rounded up slightly. 535 */ 536#define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) 537 538#define EFX_MAC_PDU_MIN 60 539#define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 540 541extern __checkReturn efx_rc_t 542efx_mac_pdu_get( 543 __in efx_nic_t *enp, 544 __out size_t *pdu); 545 546extern __checkReturn efx_rc_t 547efx_mac_pdu_set( 548 __in efx_nic_t *enp, 549 __in size_t pdu); 550 551extern __checkReturn efx_rc_t 552efx_mac_addr_set( 553 __in efx_nic_t *enp, 554 __in uint8_t *addr); 555 556extern __checkReturn efx_rc_t 557efx_mac_filter_set( 558 __in efx_nic_t *enp, 559 __in boolean_t all_unicst, 560 __in boolean_t mulcst, 561 __in boolean_t all_mulcst, 562 __in boolean_t brdcst); 563 564extern __checkReturn efx_rc_t 565efx_mac_multicast_list_set( 566 __in efx_nic_t *enp, 567 __in_ecount(6*count) uint8_t const *addrs, 568 __in int count); 569 570extern __checkReturn efx_rc_t 571efx_mac_filter_default_rxq_set( 572 __in efx_nic_t *enp, 573 __in efx_rxq_t *erp, 574 __in boolean_t using_rss); 575 576extern void 577efx_mac_filter_default_rxq_clear( 578 __in efx_nic_t *enp); 579 580extern __checkReturn efx_rc_t 581efx_mac_drain( 582 __in efx_nic_t *enp, 583 __in boolean_t enabled); 584 585extern __checkReturn efx_rc_t 586efx_mac_up( 587 __in efx_nic_t *enp, 588 __out boolean_t *mac_upp); 589 590#define EFX_FCNTL_RESPOND 0x00000001 591#define EFX_FCNTL_GENERATE 0x00000002 592 593extern __checkReturn efx_rc_t 594efx_mac_fcntl_set( 595 __in efx_nic_t *enp, 596 __in unsigned int fcntl, 597 __in boolean_t autoneg); 598 599extern void 600efx_mac_fcntl_get( 601 __in efx_nic_t *enp, 602 __out unsigned int *fcntl_wantedp, 603 __out unsigned int *fcntl_linkp); 604 605#if EFSYS_OPT_MAC_STATS 606 607#if EFSYS_OPT_NAMES 608 609extern __checkReturn const char * 610efx_mac_stat_name( 611 __in efx_nic_t *enp, 612 __in unsigned int id); 613 614#endif /* EFSYS_OPT_NAMES */ 615 616#define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t)) 617 618#define EFX_MAC_STATS_MASK_NPAGES \ 619 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \ 620 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ 621 EFX_MAC_STATS_MASK_BITS_PER_PAGE) 622 623/* 624 * Get mask of MAC statistics supported by the hardware. 625 * 626 * If mask_size is insufficient to return the mask, EINVAL error is 627 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page 628 * (which is sizeof (uint32_t)) is sufficient. 629 */ 630extern __checkReturn efx_rc_t 631efx_mac_stats_get_mask( 632 __in efx_nic_t *enp, 633 __out_bcount(mask_size) uint32_t *maskp, 634 __in size_t mask_size); 635 636#define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \ 637 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \ 638 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1)))) 639 640extern __checkReturn efx_rc_t 641efx_mac_stats_clear( 642 __in efx_nic_t *enp); 643 644/* 645 * Upload mac statistics supported by the hardware into the given buffer. 646 * 647 * The DMA buffer must be 4Kbyte aligned and sized to hold at least 648 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters. 649 * 650 * The hardware will only DMA statistics that it understands (of course). 651 * Drivers should not make any assumptions about which statistics are 652 * supported, especially when the statistics are generated by firmware. 653 * 654 * Thus, drivers should zero this buffer before use, so that not-understood 655 * statistics read back as zero. 656 */ 657extern __checkReturn efx_rc_t 658efx_mac_stats_upload( 659 __in efx_nic_t *enp, 660 __in efsys_mem_t *esmp); 661 662extern __checkReturn efx_rc_t 663efx_mac_stats_periodic( 664 __in efx_nic_t *enp, 665 __in efsys_mem_t *esmp, 666 __in uint16_t period_ms, 667 __in boolean_t events); 668 669extern __checkReturn efx_rc_t 670efx_mac_stats_update( 671 __in efx_nic_t *enp, 672 __in efsys_mem_t *esmp, 673 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 674 __inout_opt uint32_t *generationp); 675 676#endif /* EFSYS_OPT_MAC_STATS */ 677 678/* MON */ 679 680typedef enum efx_mon_type_e { 681 EFX_MON_INVALID = 0, 682 EFX_MON_SFC90X0, 683 EFX_MON_SFC91X0, 684 EFX_MON_SFC92X0, 685 EFX_MON_NTYPES 686} efx_mon_type_t; 687 688#if EFSYS_OPT_NAMES 689 690extern const char * 691efx_mon_name( 692 __in efx_nic_t *enp); 693 694#endif /* EFSYS_OPT_NAMES */ 695 696extern __checkReturn efx_rc_t 697efx_mon_init( 698 __in efx_nic_t *enp); 699 700#if EFSYS_OPT_MON_STATS 701 702#define EFX_MON_STATS_PAGE_SIZE 0x100 703#define EFX_MON_MASK_ELEMENT_SIZE 32 704 705/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */ 706typedef enum efx_mon_stat_e { 707 EFX_MON_STAT_CONTROLLER_TEMP, 708 EFX_MON_STAT_PHY_COMMON_TEMP, 709 EFX_MON_STAT_CONTROLLER_COOLING, 710 EFX_MON_STAT_PHY0_TEMP, 711 EFX_MON_STAT_PHY0_COOLING, 712 EFX_MON_STAT_PHY1_TEMP, 713 EFX_MON_STAT_PHY1_COOLING, 714 EFX_MON_STAT_IN_1V0, 715 EFX_MON_STAT_IN_1V2, 716 EFX_MON_STAT_IN_1V8, 717 EFX_MON_STAT_IN_2V5, 718 EFX_MON_STAT_IN_3V3, 719 EFX_MON_STAT_IN_12V0, 720 EFX_MON_STAT_IN_1V2A, 721 EFX_MON_STAT_IN_VREF, 722 EFX_MON_STAT_OUT_VAOE, 723 EFX_MON_STAT_AOE_TEMP, 724 EFX_MON_STAT_PSU_AOE_TEMP, 725 EFX_MON_STAT_PSU_TEMP, 726 EFX_MON_STAT_FAN_0, 727 EFX_MON_STAT_FAN_1, 728 EFX_MON_STAT_FAN_2, 729 EFX_MON_STAT_FAN_3, 730 EFX_MON_STAT_FAN_4, 731 EFX_MON_STAT_IN_VAOE, 732 EFX_MON_STAT_OUT_IAOE, 733 EFX_MON_STAT_IN_IAOE, 734 EFX_MON_STAT_NIC_POWER, 735 EFX_MON_STAT_IN_0V9, 736 EFX_MON_STAT_IN_I0V9, 737 EFX_MON_STAT_IN_I1V2, 738 EFX_MON_STAT_IN_0V9_ADC, 739 EFX_MON_STAT_CONTROLLER_2_TEMP, 740 EFX_MON_STAT_VREG_INTERNAL_TEMP, 741 EFX_MON_STAT_VREG_0V9_TEMP, 742 EFX_MON_STAT_VREG_1V2_TEMP, 743 EFX_MON_STAT_CONTROLLER_VPTAT, 744 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP, 745 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC, 746 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC, 747 EFX_MON_STAT_AMBIENT_TEMP, 748 EFX_MON_STAT_AIRFLOW, 749 EFX_MON_STAT_VDD08D_VSS08D_CSR, 750 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 751 EFX_MON_STAT_HOTPOINT_TEMP, 752 EFX_MON_STAT_PHY_POWER_PORT0, 753 EFX_MON_STAT_PHY_POWER_PORT1, 754 EFX_MON_STAT_MUM_VCC, 755 EFX_MON_STAT_IN_0V9_A, 756 EFX_MON_STAT_IN_I0V9_A, 757 EFX_MON_STAT_VREG_0V9_A_TEMP, 758 EFX_MON_STAT_IN_0V9_B, 759 EFX_MON_STAT_IN_I0V9_B, 760 EFX_MON_STAT_VREG_0V9_B_TEMP, 761 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 762 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC, 763 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 764 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC, 765 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 766 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 767 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC, 768 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC, 769 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 770 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 771 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC, 772 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC, 773 EFX_MON_STAT_SODIMM_VOUT, 774 EFX_MON_STAT_SODIMM_0_TEMP, 775 EFX_MON_STAT_SODIMM_1_TEMP, 776 EFX_MON_STAT_PHY0_VCC, 777 EFX_MON_STAT_PHY1_VCC, 778 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 779 EFX_MON_STAT_BOARD_FRONT_TEMP, 780 EFX_MON_STAT_BOARD_BACK_TEMP, 781 EFX_MON_STAT_IN_I1V8, 782 EFX_MON_STAT_IN_I2V5, 783 EFX_MON_STAT_IN_I3V3, 784 EFX_MON_STAT_IN_I12V0, 785 EFX_MON_STAT_IN_1V3, 786 EFX_MON_STAT_IN_I1V3, 787 EFX_MON_NSTATS 788} efx_mon_stat_t; 789 790/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 791 792typedef enum efx_mon_stat_state_e { 793 EFX_MON_STAT_STATE_OK = 0, 794 EFX_MON_STAT_STATE_WARNING = 1, 795 EFX_MON_STAT_STATE_FATAL = 2, 796 EFX_MON_STAT_STATE_BROKEN = 3, 797 EFX_MON_STAT_STATE_NO_READING = 4, 798} efx_mon_stat_state_t; 799 800typedef enum efx_mon_stat_unit_e { 801 EFX_MON_STAT_UNIT_UNKNOWN = 0, 802 EFX_MON_STAT_UNIT_BOOL, 803 EFX_MON_STAT_UNIT_TEMP_C, 804 EFX_MON_STAT_UNIT_VOLTAGE_MV, 805 EFX_MON_STAT_UNIT_CURRENT_MA, 806 EFX_MON_STAT_UNIT_POWER_W, 807 EFX_MON_STAT_UNIT_RPM, 808 EFX_MON_NUNITS 809} efx_mon_stat_unit_t; 810 811typedef struct efx_mon_stat_value_s { 812 uint16_t emsv_value; 813 efx_mon_stat_state_t emsv_state; 814 efx_mon_stat_unit_t emsv_unit; 815} efx_mon_stat_value_t; 816 817typedef struct efx_mon_limit_value_s { 818 uint16_t emlv_warning_min; 819 uint16_t emlv_warning_max; 820 uint16_t emlv_fatal_min; 821 uint16_t emlv_fatal_max; 822} efx_mon_stat_limits_t; 823 824typedef enum efx_mon_stat_portmask_e { 825 EFX_MON_STAT_PORTMAP_NONE = 0, 826 EFX_MON_STAT_PORTMAP_PORT0 = 1, 827 EFX_MON_STAT_PORTMAP_PORT1 = 2, 828 EFX_MON_STAT_PORTMAP_PORT2 = 3, 829 EFX_MON_STAT_PORTMAP_PORT3 = 4, 830 EFX_MON_STAT_PORTMAP_ALL = (-1), 831 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2) 832} efx_mon_stat_portmask_t; 833 834#if EFSYS_OPT_NAMES 835 836extern const char * 837efx_mon_stat_name( 838 __in efx_nic_t *enp, 839 __in efx_mon_stat_t id); 840 841extern const char * 842efx_mon_stat_description( 843 __in efx_nic_t *enp, 844 __in efx_mon_stat_t id); 845 846#endif /* EFSYS_OPT_NAMES */ 847 848extern __checkReturn boolean_t 849efx_mon_mcdi_to_efx_stat( 850 __in int mcdi_index, 851 __out efx_mon_stat_t *statp); 852 853extern __checkReturn boolean_t 854efx_mon_get_stat_unit( 855 __in efx_mon_stat_t stat, 856 __out efx_mon_stat_unit_t *unitp); 857 858extern __checkReturn boolean_t 859efx_mon_get_stat_portmap( 860 __in efx_mon_stat_t stat, 861 __out efx_mon_stat_portmask_t *maskp); 862 863extern __checkReturn efx_rc_t 864efx_mon_stats_update( 865 __in efx_nic_t *enp, 866 __in efsys_mem_t *esmp, 867 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 868 869extern __checkReturn efx_rc_t 870efx_mon_limits_update( 871 __in efx_nic_t *enp, 872 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values); 873 874#endif /* EFSYS_OPT_MON_STATS */ 875 876extern void 877efx_mon_fini( 878 __in efx_nic_t *enp); 879 880/* PHY */ 881 882extern __checkReturn efx_rc_t 883efx_phy_verify( 884 __in efx_nic_t *enp); 885 886#if EFSYS_OPT_PHY_LED_CONTROL 887 888typedef enum efx_phy_led_mode_e { 889 EFX_PHY_LED_DEFAULT = 0, 890 EFX_PHY_LED_OFF, 891 EFX_PHY_LED_ON, 892 EFX_PHY_LED_FLASH, 893 EFX_PHY_LED_NMODES 894} efx_phy_led_mode_t; 895 896extern __checkReturn efx_rc_t 897efx_phy_led_set( 898 __in efx_nic_t *enp, 899 __in efx_phy_led_mode_t mode); 900 901#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 902 903extern __checkReturn efx_rc_t 904efx_port_init( 905 __in efx_nic_t *enp); 906 907#if EFSYS_OPT_LOOPBACK 908 909typedef enum efx_loopback_type_e { 910 EFX_LOOPBACK_OFF = 0, 911 EFX_LOOPBACK_DATA = 1, 912 EFX_LOOPBACK_GMAC = 2, 913 EFX_LOOPBACK_XGMII = 3, 914 EFX_LOOPBACK_XGXS = 4, 915 EFX_LOOPBACK_XAUI = 5, 916 EFX_LOOPBACK_GMII = 6, 917 EFX_LOOPBACK_SGMII = 7, 918 EFX_LOOPBACK_XGBR = 8, 919 EFX_LOOPBACK_XFI = 9, 920 EFX_LOOPBACK_XAUI_FAR = 10, 921 EFX_LOOPBACK_GMII_FAR = 11, 922 EFX_LOOPBACK_SGMII_FAR = 12, 923 EFX_LOOPBACK_XFI_FAR = 13, 924 EFX_LOOPBACK_GPHY = 14, 925 EFX_LOOPBACK_PHY_XS = 15, 926 EFX_LOOPBACK_PCS = 16, 927 EFX_LOOPBACK_PMA_PMD = 17, 928 EFX_LOOPBACK_XPORT = 18, 929 EFX_LOOPBACK_XGMII_WS = 19, 930 EFX_LOOPBACK_XAUI_WS = 20, 931 EFX_LOOPBACK_XAUI_WS_FAR = 21, 932 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 933 EFX_LOOPBACK_GMII_WS = 23, 934 EFX_LOOPBACK_XFI_WS = 24, 935 EFX_LOOPBACK_XFI_WS_FAR = 25, 936 EFX_LOOPBACK_PHYXS_WS = 26, 937 EFX_LOOPBACK_PMA_INT = 27, 938 EFX_LOOPBACK_SD_NEAR = 28, 939 EFX_LOOPBACK_SD_FAR = 29, 940 EFX_LOOPBACK_PMA_INT_WS = 30, 941 EFX_LOOPBACK_SD_FEP2_WS = 31, 942 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 943 EFX_LOOPBACK_SD_FEP_WS = 33, 944 EFX_LOOPBACK_SD_FES_WS = 34, 945 EFX_LOOPBACK_AOE_INT_NEAR = 35, 946 EFX_LOOPBACK_DATA_WS = 36, 947 EFX_LOOPBACK_FORCE_EXT_LINK = 37, 948 EFX_LOOPBACK_NTYPES 949} efx_loopback_type_t; 950 951typedef enum efx_loopback_kind_e { 952 EFX_LOOPBACK_KIND_OFF = 0, 953 EFX_LOOPBACK_KIND_ALL, 954 EFX_LOOPBACK_KIND_MAC, 955 EFX_LOOPBACK_KIND_PHY, 956 EFX_LOOPBACK_NKINDS 957} efx_loopback_kind_t; 958 959extern void 960efx_loopback_mask( 961 __in efx_loopback_kind_t loopback_kind, 962 __out efx_qword_t *maskp); 963 964extern __checkReturn efx_rc_t 965efx_port_loopback_set( 966 __in efx_nic_t *enp, 967 __in efx_link_mode_t link_mode, 968 __in efx_loopback_type_t type); 969 970#if EFSYS_OPT_NAMES 971 972extern __checkReturn const char * 973efx_loopback_type_name( 974 __in efx_nic_t *enp, 975 __in efx_loopback_type_t type); 976 977#endif /* EFSYS_OPT_NAMES */ 978 979#endif /* EFSYS_OPT_LOOPBACK */ 980 981extern __checkReturn efx_rc_t 982efx_port_poll( 983 __in efx_nic_t *enp, 984 __out_opt efx_link_mode_t *link_modep); 985 986extern void 987efx_port_fini( 988 __in efx_nic_t *enp); 989 990typedef enum efx_phy_cap_type_e { 991 EFX_PHY_CAP_INVALID = 0, 992 EFX_PHY_CAP_10HDX, 993 EFX_PHY_CAP_10FDX, 994 EFX_PHY_CAP_100HDX, 995 EFX_PHY_CAP_100FDX, 996 EFX_PHY_CAP_1000HDX, 997 EFX_PHY_CAP_1000FDX, 998 EFX_PHY_CAP_10000FDX, 999 EFX_PHY_CAP_PAUSE, 1000 EFX_PHY_CAP_ASYM, 1001 EFX_PHY_CAP_AN, 1002 EFX_PHY_CAP_40000FDX, 1003 EFX_PHY_CAP_DDM, 1004 EFX_PHY_CAP_100000FDX, 1005 EFX_PHY_CAP_25000FDX, 1006 EFX_PHY_CAP_50000FDX, 1007 EFX_PHY_CAP_BASER_FEC, 1008 EFX_PHY_CAP_BASER_FEC_REQUESTED, 1009 EFX_PHY_CAP_RS_FEC, 1010 EFX_PHY_CAP_RS_FEC_REQUESTED, 1011 EFX_PHY_CAP_25G_BASER_FEC, 1012 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED, 1013 EFX_PHY_CAP_NTYPES 1014} efx_phy_cap_type_t; 1015 1016#define EFX_PHY_CAP_CURRENT 0x00000000 1017#define EFX_PHY_CAP_DEFAULT 0x00000001 1018#define EFX_PHY_CAP_PERM 0x00000002 1019 1020extern void 1021efx_phy_adv_cap_get( 1022 __in efx_nic_t *enp, 1023 __in uint32_t flag, 1024 __out uint32_t *maskp); 1025 1026extern __checkReturn efx_rc_t 1027efx_phy_adv_cap_set( 1028 __in efx_nic_t *enp, 1029 __in uint32_t mask); 1030 1031extern void 1032efx_phy_lp_cap_get( 1033 __in efx_nic_t *enp, 1034 __out uint32_t *maskp); 1035 1036extern __checkReturn efx_rc_t 1037efx_phy_oui_get( 1038 __in efx_nic_t *enp, 1039 __out uint32_t *ouip); 1040 1041typedef enum efx_phy_media_type_e { 1042 EFX_PHY_MEDIA_INVALID = 0, 1043 EFX_PHY_MEDIA_XAUI, 1044 EFX_PHY_MEDIA_CX4, 1045 EFX_PHY_MEDIA_KX4, 1046 EFX_PHY_MEDIA_XFP, 1047 EFX_PHY_MEDIA_SFP_PLUS, 1048 EFX_PHY_MEDIA_BASE_T, 1049 EFX_PHY_MEDIA_QSFP_PLUS, 1050 EFX_PHY_MEDIA_NTYPES 1051} efx_phy_media_type_t; 1052 1053/* 1054 * Get the type of medium currently used. If the board has ports for 1055 * modules, a module is present, and we recognise the media type of 1056 * the module, then this will be the media type of the module. 1057 * Otherwise it will be the media type of the port. 1058 */ 1059extern void 1060efx_phy_media_type_get( 1061 __in efx_nic_t *enp, 1062 __out efx_phy_media_type_t *typep); 1063 1064/* 1065 * 2-wire device address of the base information in accordance with SFF-8472 1066 * Diagnostic Monitoring Interface for Optical Transceivers section 1067 * 4 Memory Organization. 1068 */ 1069#define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0 1070 1071/* 1072 * 2-wire device address of the digital diagnostics monitoring interface 1073 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical 1074 * Transceivers section 4 Memory Organization. 1075 */ 1076#define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2 1077 1078/* 1079 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436 1080 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and 1081 * Operation. 1082 */ 1083#define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0 1084 1085/* 1086 * Maximum accessible data offset for PHY module information. 1087 */ 1088#define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100 1089 1090extern __checkReturn efx_rc_t 1091efx_phy_module_get_info( 1092 __in efx_nic_t *enp, 1093 __in uint8_t dev_addr, 1094 __in size_t offset, 1095 __in size_t len, 1096 __out_bcount(len) uint8_t *data); 1097 1098#if EFSYS_OPT_PHY_STATS 1099 1100/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 1101typedef enum efx_phy_stat_e { 1102 EFX_PHY_STAT_OUI, 1103 EFX_PHY_STAT_PMA_PMD_LINK_UP, 1104 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 1105 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 1106 EFX_PHY_STAT_PMA_PMD_REV_A, 1107 EFX_PHY_STAT_PMA_PMD_REV_B, 1108 EFX_PHY_STAT_PMA_PMD_REV_C, 1109 EFX_PHY_STAT_PMA_PMD_REV_D, 1110 EFX_PHY_STAT_PCS_LINK_UP, 1111 EFX_PHY_STAT_PCS_RX_FAULT, 1112 EFX_PHY_STAT_PCS_TX_FAULT, 1113 EFX_PHY_STAT_PCS_BER, 1114 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 1115 EFX_PHY_STAT_PHY_XS_LINK_UP, 1116 EFX_PHY_STAT_PHY_XS_RX_FAULT, 1117 EFX_PHY_STAT_PHY_XS_TX_FAULT, 1118 EFX_PHY_STAT_PHY_XS_ALIGN, 1119 EFX_PHY_STAT_PHY_XS_SYNC_A, 1120 EFX_PHY_STAT_PHY_XS_SYNC_B, 1121 EFX_PHY_STAT_PHY_XS_SYNC_C, 1122 EFX_PHY_STAT_PHY_XS_SYNC_D, 1123 EFX_PHY_STAT_AN_LINK_UP, 1124 EFX_PHY_STAT_AN_MASTER, 1125 EFX_PHY_STAT_AN_LOCAL_RX_OK, 1126 EFX_PHY_STAT_AN_REMOTE_RX_OK, 1127 EFX_PHY_STAT_CL22EXT_LINK_UP, 1128 EFX_PHY_STAT_SNR_A, 1129 EFX_PHY_STAT_SNR_B, 1130 EFX_PHY_STAT_SNR_C, 1131 EFX_PHY_STAT_SNR_D, 1132 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 1133 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 1134 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 1135 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 1136 EFX_PHY_STAT_AN_COMPLETE, 1137 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 1138 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 1139 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 1140 EFX_PHY_STAT_PCS_FW_VERSION_0, 1141 EFX_PHY_STAT_PCS_FW_VERSION_1, 1142 EFX_PHY_STAT_PCS_FW_VERSION_2, 1143 EFX_PHY_STAT_PCS_FW_VERSION_3, 1144 EFX_PHY_STAT_PCS_FW_BUILD_YY, 1145 EFX_PHY_STAT_PCS_FW_BUILD_MM, 1146 EFX_PHY_STAT_PCS_FW_BUILD_DD, 1147 EFX_PHY_STAT_PCS_OP_MODE, 1148 EFX_PHY_NSTATS 1149} efx_phy_stat_t; 1150 1151/* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 1152 1153#if EFSYS_OPT_NAMES 1154 1155extern const char * 1156efx_phy_stat_name( 1157 __in efx_nic_t *enp, 1158 __in efx_phy_stat_t stat); 1159 1160#endif /* EFSYS_OPT_NAMES */ 1161 1162#define EFX_PHY_STATS_SIZE 0x100 1163 1164extern __checkReturn efx_rc_t 1165efx_phy_stats_update( 1166 __in efx_nic_t *enp, 1167 __in efsys_mem_t *esmp, 1168 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 1169 1170#endif /* EFSYS_OPT_PHY_STATS */ 1171 1172#if EFSYS_OPT_BIST 1173 1174typedef enum efx_bist_type_e { 1175 EFX_BIST_TYPE_UNKNOWN, 1176 EFX_BIST_TYPE_PHY_NORMAL, 1177 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1178 EFX_BIST_TYPE_PHY_CABLE_LONG, 1179 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1180 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */ 1181 EFX_BIST_TYPE_REG, /* Test the register memories */ 1182 EFX_BIST_TYPE_NTYPES, 1183} efx_bist_type_t; 1184 1185typedef enum efx_bist_result_e { 1186 EFX_BIST_RESULT_UNKNOWN, 1187 EFX_BIST_RESULT_RUNNING, 1188 EFX_BIST_RESULT_PASSED, 1189 EFX_BIST_RESULT_FAILED, 1190} efx_bist_result_t; 1191 1192typedef enum efx_phy_cable_status_e { 1193 EFX_PHY_CABLE_STATUS_OK, 1194 EFX_PHY_CABLE_STATUS_INVALID, 1195 EFX_PHY_CABLE_STATUS_OPEN, 1196 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1197 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1198 EFX_PHY_CABLE_STATUS_BUSY, 1199} efx_phy_cable_status_t; 1200 1201typedef enum efx_bist_value_e { 1202 EFX_BIST_PHY_CABLE_LENGTH_A, 1203 EFX_BIST_PHY_CABLE_LENGTH_B, 1204 EFX_BIST_PHY_CABLE_LENGTH_C, 1205 EFX_BIST_PHY_CABLE_LENGTH_D, 1206 EFX_BIST_PHY_CABLE_STATUS_A, 1207 EFX_BIST_PHY_CABLE_STATUS_B, 1208 EFX_BIST_PHY_CABLE_STATUS_C, 1209 EFX_BIST_PHY_CABLE_STATUS_D, 1210 EFX_BIST_FAULT_CODE, 1211 /* 1212 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1213 * response. 1214 */ 1215 EFX_BIST_MEM_TEST, 1216 EFX_BIST_MEM_ADDR, 1217 EFX_BIST_MEM_BUS, 1218 EFX_BIST_MEM_EXPECT, 1219 EFX_BIST_MEM_ACTUAL, 1220 EFX_BIST_MEM_ECC, 1221 EFX_BIST_MEM_ECC_PARITY, 1222 EFX_BIST_MEM_ECC_FATAL, 1223 EFX_BIST_NVALUES, 1224} efx_bist_value_t; 1225 1226extern __checkReturn efx_rc_t 1227efx_bist_enable_offline( 1228 __in efx_nic_t *enp); 1229 1230extern __checkReturn efx_rc_t 1231efx_bist_start( 1232 __in efx_nic_t *enp, 1233 __in efx_bist_type_t type); 1234 1235extern __checkReturn efx_rc_t 1236efx_bist_poll( 1237 __in efx_nic_t *enp, 1238 __in efx_bist_type_t type, 1239 __out efx_bist_result_t *resultp, 1240 __out_opt uint32_t *value_maskp, 1241 __out_ecount_opt(count) unsigned long *valuesp, 1242 __in size_t count); 1243 1244extern void 1245efx_bist_stop( 1246 __in efx_nic_t *enp, 1247 __in efx_bist_type_t type); 1248 1249#endif /* EFSYS_OPT_BIST */ 1250 1251#define EFX_FEATURE_IPV6 0x00000001 1252#define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1253#define EFX_FEATURE_LINK_EVENTS 0x00000004 1254#define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1255#define EFX_FEATURE_MCDI 0x00000020 1256#define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1257#define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1258#define EFX_FEATURE_TURBO 0x00000100 1259#define EFX_FEATURE_MCDI_DMA 0x00000200 1260#define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1261#define EFX_FEATURE_PIO_BUFFERS 0x00000800 1262#define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1263#define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 1264#define EFX_FEATURE_PACKED_STREAM 0x00004000 1265#define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000 1266 1267typedef enum efx_tunnel_protocol_e { 1268 EFX_TUNNEL_PROTOCOL_NONE = 0, 1269 EFX_TUNNEL_PROTOCOL_VXLAN, 1270 EFX_TUNNEL_PROTOCOL_GENEVE, 1271 EFX_TUNNEL_PROTOCOL_NVGRE, 1272 EFX_TUNNEL_NPROTOS 1273} efx_tunnel_protocol_t; 1274 1275typedef enum efx_vi_window_shift_e { 1276 EFX_VI_WINDOW_SHIFT_INVALID = 0, 1277 EFX_VI_WINDOW_SHIFT_8K = 13, 1278 EFX_VI_WINDOW_SHIFT_16K = 14, 1279 EFX_VI_WINDOW_SHIFT_64K = 16, 1280} efx_vi_window_shift_t; 1281 1282typedef struct efx_nic_cfg_s { 1283 uint32_t enc_board_type; 1284 uint32_t enc_phy_type; 1285#if EFSYS_OPT_NAMES 1286 char enc_phy_name[21]; 1287#endif 1288 char enc_phy_revision[21]; 1289 efx_mon_type_t enc_mon_type; 1290#if EFSYS_OPT_MON_STATS 1291 uint32_t enc_mon_stat_dma_buf_size; 1292 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1293#endif 1294 unsigned int enc_features; 1295 efx_vi_window_shift_t enc_vi_window_shift; 1296 uint8_t enc_mac_addr[6]; 1297 uint8_t enc_port; /* PHY port number */ 1298 uint32_t enc_intr_vec_base; 1299 uint32_t enc_intr_limit; 1300 uint32_t enc_evq_limit; 1301 uint32_t enc_txq_limit; 1302 uint32_t enc_rxq_limit; 1303 uint32_t enc_txq_max_ndescs; 1304 uint32_t enc_buftbl_limit; 1305 uint32_t enc_piobuf_limit; 1306 uint32_t enc_piobuf_size; 1307 uint32_t enc_piobuf_min_alloc_size; 1308 uint32_t enc_evq_timer_quantum_ns; 1309 uint32_t enc_evq_timer_max_us; 1310 uint32_t enc_clk_mult; 1311 uint32_t enc_rx_prefix_size; 1312 uint32_t enc_rx_buf_align_start; 1313 uint32_t enc_rx_buf_align_end; 1314#if EFSYS_OPT_RX_SCALE 1315 uint32_t enc_rx_scale_max_exclusive_contexts; 1316 /* 1317 * Mask of supported hash algorithms. 1318 * Hash algorithm types are used as the bit indices. 1319 */ 1320 uint32_t enc_rx_scale_hash_alg_mask; 1321 /* 1322 * Indicates whether port numbers can be included to the 1323 * input data for hash computation. 1324 */ 1325 boolean_t enc_rx_scale_l4_hash_supported; 1326 boolean_t enc_rx_scale_additional_modes_supported; 1327#endif /* EFSYS_OPT_RX_SCALE */ 1328#if EFSYS_OPT_LOOPBACK 1329 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1330#endif /* EFSYS_OPT_LOOPBACK */ 1331#if EFSYS_OPT_PHY_FLAGS 1332 uint32_t enc_phy_flags_mask; 1333#endif /* EFSYS_OPT_PHY_FLAGS */ 1334#if EFSYS_OPT_PHY_LED_CONTROL 1335 uint32_t enc_led_mask; 1336#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1337#if EFSYS_OPT_PHY_STATS 1338 uint64_t enc_phy_stat_mask; 1339#endif /* EFSYS_OPT_PHY_STATS */ 1340#if EFSYS_OPT_MCDI 1341 uint8_t enc_mcdi_mdio_channel; 1342#if EFSYS_OPT_PHY_STATS 1343 uint32_t enc_mcdi_phy_stat_mask; 1344#endif /* EFSYS_OPT_PHY_STATS */ 1345#if EFSYS_OPT_MON_STATS 1346 uint32_t *enc_mcdi_sensor_maskp; 1347 uint32_t enc_mcdi_sensor_mask_size; 1348#endif /* EFSYS_OPT_MON_STATS */ 1349#endif /* EFSYS_OPT_MCDI */ 1350#if EFSYS_OPT_BIST 1351 uint32_t enc_bist_mask; 1352#endif /* EFSYS_OPT_BIST */ 1353#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 1354 uint32_t enc_pf; 1355 uint32_t enc_vf; 1356 uint32_t enc_privilege_mask; 1357#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ 1358 boolean_t enc_bug26807_workaround; 1359 boolean_t enc_bug35388_workaround; 1360 boolean_t enc_bug41750_workaround; 1361 boolean_t enc_bug61265_workaround; 1362 boolean_t enc_bug61297_workaround; 1363 boolean_t enc_rx_batching_enabled; 1364 /* Maximum number of descriptors completed in an rx event. */ 1365 uint32_t enc_rx_batch_max; 1366 /* Number of rx descriptors the hardware requires for a push. */ 1367 uint32_t enc_rx_push_align; 1368 /* Maximum amount of data in DMA descriptor */ 1369 uint32_t enc_tx_dma_desc_size_max; 1370 /* 1371 * Boundary which DMA descriptor data must not cross or 0 if no 1372 * limitation. 1373 */ 1374 uint32_t enc_tx_dma_desc_boundary; 1375 /* 1376 * Maximum number of bytes into the packet the TCP header can start for 1377 * the hardware to apply TSO packet edits. 1378 */ 1379 uint32_t enc_tx_tso_tcp_header_offset_limit; 1380 boolean_t enc_fw_assisted_tso_enabled; 1381 boolean_t enc_fw_assisted_tso_v2_enabled; 1382 boolean_t enc_fw_assisted_tso_v2_encap_enabled; 1383 /* Number of TSO contexts on the NIC (FATSOv2) */ 1384 uint32_t enc_fw_assisted_tso_v2_n_contexts; 1385 boolean_t enc_hw_tx_insert_vlan_enabled; 1386 /* Number of PFs on the NIC */ 1387 uint32_t enc_hw_pf_count; 1388 /* Datapath firmware vadapter/vport/vswitch support */ 1389 boolean_t enc_datapath_cap_evb; 1390 boolean_t enc_rx_disable_scatter_supported; 1391 boolean_t enc_allow_set_mac_with_installed_filters; 1392 boolean_t enc_enhanced_set_mac_supported; 1393 boolean_t enc_init_evq_v2_supported; 1394 boolean_t enc_rx_packed_stream_supported; 1395 boolean_t enc_rx_var_packed_stream_supported; 1396 boolean_t enc_rx_es_super_buffer_supported; 1397 boolean_t enc_fw_subvariant_no_tx_csum_supported; 1398 boolean_t enc_pm_and_rxdp_counters; 1399 boolean_t enc_mac_stats_40g_tx_size_bins; 1400 uint32_t enc_tunnel_encapsulations_supported; 1401 /* 1402 * NIC global maximum for unique UDP tunnel ports shared by all 1403 * functions. 1404 */ 1405 uint32_t enc_tunnel_config_udp_entries_max; 1406 /* External port identifier */ 1407 uint8_t enc_external_port; 1408 uint32_t enc_mcdi_max_payload_length; 1409 /* VPD may be per-PF or global */ 1410 boolean_t enc_vpd_is_global; 1411 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */ 1412 uint32_t enc_required_pcie_bandwidth_mbps; 1413 uint32_t enc_max_pcie_link_gen; 1414 /* Firmware verifies integrity of NVRAM updates */ 1415 uint32_t enc_nvram_update_verify_result_supported; 1416 /* Firmware support for extended MAC_STATS buffer */ 1417 uint32_t enc_mac_stats_nstats; 1418 boolean_t enc_fec_counters; 1419 boolean_t enc_hlb_counters; 1420 /* Firmware support for "FLAG" and "MARK" filter actions */ 1421 boolean_t enc_filter_action_flag_supported; 1422 boolean_t enc_filter_action_mark_supported; 1423 uint32_t enc_filter_action_mark_max; 1424} efx_nic_cfg_t; 1425 1426#define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) 1427#define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) 1428 1429#define EFX_PCI_FUNCTION(_encp) \ 1430 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1431 1432#define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1433 1434extern const efx_nic_cfg_t * 1435efx_nic_cfg_get( 1436 __in efx_nic_t *enp); 1437 1438/* RxDPCPU firmware id values by which FW variant can be identified */ 1439#define EFX_RXDP_FULL_FEATURED_FW_ID 0x0 1440#define EFX_RXDP_LOW_LATENCY_FW_ID 0x1 1441#define EFX_RXDP_PACKED_STREAM_FW_ID 0x2 1442#define EFX_RXDP_RULES_ENGINE_FW_ID 0x5 1443#define EFX_RXDP_DPDK_FW_ID 0x6 1444 1445typedef struct efx_nic_fw_info_s { 1446 /* Basic FW version information */ 1447 uint16_t enfi_mc_fw_version[4]; 1448 /* 1449 * If datapath capabilities can be detected, 1450 * additional FW information is to be shown 1451 */ 1452 boolean_t enfi_dpcpu_fw_ids_valid; 1453 /* Rx and Tx datapath CPU FW IDs */ 1454 uint16_t enfi_rx_dpcpu_fw_id; 1455 uint16_t enfi_tx_dpcpu_fw_id; 1456} efx_nic_fw_info_t; 1457 1458extern __checkReturn efx_rc_t 1459efx_nic_get_fw_version( 1460 __in efx_nic_t *enp, 1461 __out efx_nic_fw_info_t *enfip); 1462 1463/* Driver resource limits (minimum required/maximum usable). */ 1464typedef struct efx_drv_limits_s { 1465 uint32_t edl_min_evq_count; 1466 uint32_t edl_max_evq_count; 1467 1468 uint32_t edl_min_rxq_count; 1469 uint32_t edl_max_rxq_count; 1470 1471 uint32_t edl_min_txq_count; 1472 uint32_t edl_max_txq_count; 1473 1474 /* PIO blocks (sub-allocated from piobuf) */ 1475 uint32_t edl_min_pio_alloc_size; 1476 uint32_t edl_max_pio_alloc_count; 1477} efx_drv_limits_t; 1478 1479extern __checkReturn efx_rc_t 1480efx_nic_set_drv_limits( 1481 __inout efx_nic_t *enp, 1482 __in efx_drv_limits_t *edlp); 1483 1484typedef enum efx_nic_region_e { 1485 EFX_REGION_VI, /* Memory BAR UC mapping */ 1486 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1487} efx_nic_region_t; 1488 1489extern __checkReturn efx_rc_t 1490efx_nic_get_bar_region( 1491 __in efx_nic_t *enp, 1492 __in efx_nic_region_t region, 1493 __out uint32_t *offsetp, 1494 __out size_t *sizep); 1495 1496extern __checkReturn efx_rc_t 1497efx_nic_get_vi_pool( 1498 __in efx_nic_t *enp, 1499 __out uint32_t *evq_countp, 1500 __out uint32_t *rxq_countp, 1501 __out uint32_t *txq_countp); 1502 1503#if EFSYS_OPT_VPD 1504 1505typedef enum efx_vpd_tag_e { 1506 EFX_VPD_ID = 0x02, 1507 EFX_VPD_END = 0x0f, 1508 EFX_VPD_RO = 0x10, 1509 EFX_VPD_RW = 0x11, 1510} efx_vpd_tag_t; 1511 1512typedef uint16_t efx_vpd_keyword_t; 1513 1514typedef struct efx_vpd_value_s { 1515 efx_vpd_tag_t evv_tag; 1516 efx_vpd_keyword_t evv_keyword; 1517 uint8_t evv_length; 1518 uint8_t evv_value[0x100]; 1519} efx_vpd_value_t; 1520 1521#define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1522 1523extern __checkReturn efx_rc_t 1524efx_vpd_init( 1525 __in efx_nic_t *enp); 1526 1527extern __checkReturn efx_rc_t 1528efx_vpd_size( 1529 __in efx_nic_t *enp, 1530 __out size_t *sizep); 1531 1532extern __checkReturn efx_rc_t 1533efx_vpd_read( 1534 __in efx_nic_t *enp, 1535 __out_bcount(size) caddr_t data, 1536 __in size_t size); 1537 1538extern __checkReturn efx_rc_t 1539efx_vpd_verify( 1540 __in efx_nic_t *enp, 1541 __in_bcount(size) caddr_t data, 1542 __in size_t size); 1543 1544extern __checkReturn efx_rc_t 1545efx_vpd_reinit( 1546 __in efx_nic_t *enp, 1547 __in_bcount(size) caddr_t data, 1548 __in size_t size); 1549 1550extern __checkReturn efx_rc_t 1551efx_vpd_get( 1552 __in efx_nic_t *enp, 1553 __in_bcount(size) caddr_t data, 1554 __in size_t size, 1555 __inout efx_vpd_value_t *evvp); 1556 1557extern __checkReturn efx_rc_t 1558efx_vpd_set( 1559 __in efx_nic_t *enp, 1560 __inout_bcount(size) caddr_t data, 1561 __in size_t size, 1562 __in efx_vpd_value_t *evvp); 1563 1564extern __checkReturn efx_rc_t 1565efx_vpd_next( 1566 __in efx_nic_t *enp, 1567 __inout_bcount(size) caddr_t data, 1568 __in size_t size, 1569 __out efx_vpd_value_t *evvp, 1570 __inout unsigned int *contp); 1571 1572extern __checkReturn efx_rc_t 1573efx_vpd_write( 1574 __in efx_nic_t *enp, 1575 __in_bcount(size) caddr_t data, 1576 __in size_t size); 1577 1578extern void 1579efx_vpd_fini( 1580 __in efx_nic_t *enp); 1581 1582#endif /* EFSYS_OPT_VPD */ 1583 1584/* NVRAM */ 1585 1586#if EFSYS_OPT_NVRAM 1587 1588typedef enum efx_nvram_type_e { 1589 EFX_NVRAM_INVALID = 0, 1590 EFX_NVRAM_BOOTROM, 1591 EFX_NVRAM_BOOTROM_CFG, 1592 EFX_NVRAM_MC_FIRMWARE, 1593 EFX_NVRAM_MC_GOLDEN, 1594 EFX_NVRAM_PHY, 1595 EFX_NVRAM_NULLPHY, 1596 EFX_NVRAM_FPGA, 1597 EFX_NVRAM_FCFW, 1598 EFX_NVRAM_CPLD, 1599 EFX_NVRAM_FPGA_BACKUP, 1600 EFX_NVRAM_DYNAMIC_CFG, 1601 EFX_NVRAM_LICENSE, 1602 EFX_NVRAM_UEFIROM, 1603 EFX_NVRAM_MUM_FIRMWARE, 1604 EFX_NVRAM_DYNCONFIG_DEFAULTS, 1605 EFX_NVRAM_ROMCONFIG_DEFAULTS, 1606 EFX_NVRAM_NTYPES, 1607} efx_nvram_type_t; 1608 1609extern __checkReturn efx_rc_t 1610efx_nvram_init( 1611 __in efx_nic_t *enp); 1612 1613#if EFSYS_OPT_DIAG 1614 1615extern __checkReturn efx_rc_t 1616efx_nvram_test( 1617 __in efx_nic_t *enp); 1618 1619#endif /* EFSYS_OPT_DIAG */ 1620 1621extern __checkReturn efx_rc_t 1622efx_nvram_size( 1623 __in efx_nic_t *enp, 1624 __in efx_nvram_type_t type, 1625 __out size_t *sizep); 1626 1627extern __checkReturn efx_rc_t 1628efx_nvram_rw_start( 1629 __in efx_nic_t *enp, 1630 __in efx_nvram_type_t type, 1631 __out_opt size_t *pref_chunkp); 1632 1633extern __checkReturn efx_rc_t 1634efx_nvram_rw_finish( 1635 __in efx_nic_t *enp, 1636 __in efx_nvram_type_t type, 1637 __out_opt uint32_t *verify_resultp); 1638 1639extern __checkReturn efx_rc_t 1640efx_nvram_get_version( 1641 __in efx_nic_t *enp, 1642 __in efx_nvram_type_t type, 1643 __out uint32_t *subtypep, 1644 __out_ecount(4) uint16_t version[4]); 1645 1646extern __checkReturn efx_rc_t 1647efx_nvram_read_chunk( 1648 __in efx_nic_t *enp, 1649 __in efx_nvram_type_t type, 1650 __in unsigned int offset, 1651 __out_bcount(size) caddr_t data, 1652 __in size_t size); 1653 1654extern __checkReturn efx_rc_t 1655efx_nvram_read_backup( 1656 __in efx_nic_t *enp, 1657 __in efx_nvram_type_t type, 1658 __in unsigned int offset, 1659 __out_bcount(size) caddr_t data, 1660 __in size_t size); 1661 1662extern __checkReturn efx_rc_t 1663efx_nvram_set_version( 1664 __in efx_nic_t *enp, 1665 __in efx_nvram_type_t type, 1666 __in_ecount(4) uint16_t version[4]); 1667 1668extern __checkReturn efx_rc_t 1669efx_nvram_validate( 1670 __in efx_nic_t *enp, 1671 __in efx_nvram_type_t type, 1672 __in_bcount(partn_size) caddr_t partn_data, 1673 __in size_t partn_size); 1674 1675extern __checkReturn efx_rc_t 1676efx_nvram_erase( 1677 __in efx_nic_t *enp, 1678 __in efx_nvram_type_t type); 1679 1680extern __checkReturn efx_rc_t 1681efx_nvram_write_chunk( 1682 __in efx_nic_t *enp, 1683 __in efx_nvram_type_t type, 1684 __in unsigned int offset, 1685 __in_bcount(size) caddr_t data, 1686 __in size_t size); 1687 1688extern void 1689efx_nvram_fini( 1690 __in efx_nic_t *enp); 1691 1692#endif /* EFSYS_OPT_NVRAM */ 1693 1694#if EFSYS_OPT_BOOTCFG 1695 1696/* Report size and offset of bootcfg sector in NVRAM partition. */ 1697extern __checkReturn efx_rc_t 1698efx_bootcfg_sector_info( 1699 __in efx_nic_t *enp, 1700 __in uint32_t pf, 1701 __out_opt uint32_t *sector_countp, 1702 __out size_t *offsetp, 1703 __out size_t *max_sizep); 1704 1705/* 1706 * Copy bootcfg sector data to a target buffer which may differ in size. 1707 * Optionally corrects format errors in source buffer. 1708 */ 1709extern efx_rc_t 1710efx_bootcfg_copy_sector( 1711 __in efx_nic_t *enp, 1712 __inout_bcount(sector_length) 1713 uint8_t *sector, 1714 __in size_t sector_length, 1715 __out_bcount(data_size) uint8_t *data, 1716 __in size_t data_size, 1717 __in boolean_t handle_format_errors); 1718 1719extern efx_rc_t 1720efx_bootcfg_read( 1721 __in efx_nic_t *enp, 1722 __out_bcount(size) uint8_t *data, 1723 __in size_t size); 1724 1725extern efx_rc_t 1726efx_bootcfg_write( 1727 __in efx_nic_t *enp, 1728 __in_bcount(size) uint8_t *data, 1729 __in size_t size); 1730 1731/* 1732 * Processing routines for buffers arranged in the DHCP/BOOTP option format 1733 * (see https://tools.ietf.org/html/rfc1533) 1734 * 1735 * Summarising the format: the buffer is a sequence of options. All options 1736 * begin with a tag octet, which uniquely identifies the option. Fixed- 1737 * length options without data consist of only a tag octet. Only options PAD 1738 * (0) and END (255) are fixed length. All other options are variable-length 1739 * with a length octet following the tag octet. The value of the length 1740 * octet does not include the two octets specifying the tag and length. The 1741 * length octet is followed by "length" octets of data. 1742 * 1743 * Option data may be a sequence of sub-options in the same format. The data 1744 * content of the encapsulating option is one or more encapsulated sub-options, 1745 * with no terminating END tag is required. 1746 * 1747 * To be valid, the top-level sequence of options should be terminated by an 1748 * END tag. The buffer should be padded with the PAD byte. 1749 * 1750 * When stored to NVRAM, the DHCP option format buffer is preceded by a 1751 * checksum octet. The full buffer (including after the END tag) contributes 1752 * to the checksum, hence the need to fill the buffer to the end with PAD. 1753 */ 1754 1755#define EFX_DHCP_END ((uint8_t)0xff) 1756#define EFX_DHCP_PAD ((uint8_t)0) 1757 1758#define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \ 1759 (uint16_t)(((encapsulator) << 8) | (encapsulated)) 1760 1761extern __checkReturn uint8_t 1762efx_dhcp_csum( 1763 __in_bcount(size) uint8_t const *data, 1764 __in size_t size); 1765 1766extern __checkReturn efx_rc_t 1767efx_dhcp_verify( 1768 __in_bcount(size) uint8_t const *data, 1769 __in size_t size, 1770 __out_opt size_t *usedp); 1771 1772extern __checkReturn efx_rc_t 1773efx_dhcp_find_tag( 1774 __in_bcount(buffer_length) uint8_t *bufferp, 1775 __in size_t buffer_length, 1776 __in uint16_t opt, 1777 __deref_out uint8_t **valuepp, 1778 __out size_t *value_lengthp); 1779 1780extern __checkReturn efx_rc_t 1781efx_dhcp_find_end( 1782 __in_bcount(buffer_length) uint8_t *bufferp, 1783 __in size_t buffer_length, 1784 __deref_out uint8_t **endpp); 1785 1786extern __checkReturn efx_rc_t 1787efx_dhcp_delete_tag( 1788 __inout_bcount(buffer_length) uint8_t *bufferp, 1789 __in size_t buffer_length, 1790 __in uint16_t opt); 1791 1792extern __checkReturn efx_rc_t 1793efx_dhcp_add_tag( 1794 __inout_bcount(buffer_length) uint8_t *bufferp, 1795 __in size_t buffer_length, 1796 __in uint16_t opt, 1797 __in_bcount_opt(value_length) uint8_t *valuep, 1798 __in size_t value_length); 1799 1800extern __checkReturn efx_rc_t 1801efx_dhcp_update_tag( 1802 __inout_bcount(buffer_length) uint8_t *bufferp, 1803 __in size_t buffer_length, 1804 __in uint16_t opt, 1805 __in uint8_t *value_locationp, 1806 __in_bcount_opt(value_length) uint8_t *valuep, 1807 __in size_t value_length); 1808 1809#endif /* EFSYS_OPT_BOOTCFG */ 1810 1811#if EFSYS_OPT_IMAGE_LAYOUT 1812 1813#include "ef10_signed_image_layout.h" 1814 1815/* 1816 * Image header used in unsigned and signed image layouts (see SF-102785-PS). 1817 * 1818 * NOTE: 1819 * The image header format is extensible. However, older drivers require an 1820 * exact match of image header version and header length when validating and 1821 * writing firmware images. 1822 * 1823 * To avoid breaking backward compatibility, we use the upper bits of the 1824 * controller version fields to contain an extra version number used for 1825 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM 1826 * version). See bug39254 and SF-102785-PS for details. 1827 */ 1828typedef struct efx_image_header_s { 1829 uint32_t eih_magic; 1830 uint32_t eih_version; 1831 uint32_t eih_type; 1832 uint32_t eih_subtype; 1833 uint32_t eih_code_size; 1834 uint32_t eih_size; 1835 union { 1836 uint32_t eih_controller_version_min; 1837 struct { 1838 uint16_t eih_controller_version_min_short; 1839 uint8_t eih_extra_version_a; 1840 uint8_t eih_extra_version_b; 1841 }; 1842 }; 1843 union { 1844 uint32_t eih_controller_version_max; 1845 struct { 1846 uint16_t eih_controller_version_max_short; 1847 uint8_t eih_extra_version_c; 1848 uint8_t eih_extra_version_d; 1849 }; 1850 }; 1851 uint16_t eih_code_version_a; 1852 uint16_t eih_code_version_b; 1853 uint16_t eih_code_version_c; 1854 uint16_t eih_code_version_d; 1855} efx_image_header_t; 1856 1857#define EFX_IMAGE_HEADER_SIZE (40) 1858#define EFX_IMAGE_HEADER_VERSION (4) 1859#define EFX_IMAGE_HEADER_MAGIC (0x106F1A5) 1860 1861typedef struct efx_image_trailer_s { 1862 uint32_t eit_crc; 1863} efx_image_trailer_t; 1864 1865#define EFX_IMAGE_TRAILER_SIZE (4) 1866 1867typedef enum efx_image_format_e { 1868 EFX_IMAGE_FORMAT_NO_IMAGE, 1869 EFX_IMAGE_FORMAT_INVALID, 1870 EFX_IMAGE_FORMAT_UNSIGNED, 1871 EFX_IMAGE_FORMAT_SIGNED, 1872} efx_image_format_t; 1873 1874typedef struct efx_image_info_s { 1875 efx_image_format_t eii_format; 1876 uint8_t * eii_imagep; 1877 size_t eii_image_size; 1878 efx_image_header_t * eii_headerp; 1879} efx_image_info_t; 1880 1881extern __checkReturn efx_rc_t 1882efx_check_reflash_image( 1883 __in void *bufferp, 1884 __in uint32_t buffer_size, 1885 __out efx_image_info_t *infop); 1886 1887extern __checkReturn efx_rc_t 1888efx_build_signed_image_write_buffer( 1889 __out_bcount(buffer_size) 1890 uint8_t *bufferp, 1891 __in uint32_t buffer_size, 1892 __in efx_image_info_t *infop, 1893 __out efx_image_header_t **headerpp); 1894 1895#endif /* EFSYS_OPT_IMAGE_LAYOUT */ 1896 1897#if EFSYS_OPT_DIAG 1898 1899typedef enum efx_pattern_type_t { 1900 EFX_PATTERN_BYTE_INCREMENT = 0, 1901 EFX_PATTERN_ALL_THE_SAME, 1902 EFX_PATTERN_BIT_ALTERNATE, 1903 EFX_PATTERN_BYTE_ALTERNATE, 1904 EFX_PATTERN_BYTE_CHANGING, 1905 EFX_PATTERN_BIT_SWEEP, 1906 EFX_PATTERN_NTYPES 1907} efx_pattern_type_t; 1908 1909typedef void 1910(*efx_sram_pattern_fn_t)( 1911 __in size_t row, 1912 __in boolean_t negate, 1913 __out efx_qword_t *eqp); 1914 1915extern __checkReturn efx_rc_t 1916efx_sram_test( 1917 __in efx_nic_t *enp, 1918 __in efx_pattern_type_t type); 1919 1920#endif /* EFSYS_OPT_DIAG */ 1921 1922extern __checkReturn efx_rc_t 1923efx_sram_buf_tbl_set( 1924 __in efx_nic_t *enp, 1925 __in uint32_t id, 1926 __in efsys_mem_t *esmp, 1927 __in size_t n); 1928 1929extern void 1930efx_sram_buf_tbl_clear( 1931 __in efx_nic_t *enp, 1932 __in uint32_t id, 1933 __in size_t n); 1934 1935#define EFX_BUF_TBL_SIZE 0x20000 1936 1937#define EFX_BUF_SIZE 4096 1938 1939/* EV */ 1940 1941typedef struct efx_evq_s efx_evq_t; 1942 1943#if EFSYS_OPT_QSTATS 1944 1945/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */ 1946typedef enum efx_ev_qstat_e { 1947 EV_ALL, 1948 EV_RX, 1949 EV_RX_OK, 1950 EV_RX_FRM_TRUNC, 1951 EV_RX_TOBE_DISC, 1952 EV_RX_PAUSE_FRM_ERR, 1953 EV_RX_BUF_OWNER_ID_ERR, 1954 EV_RX_IPV4_HDR_CHKSUM_ERR, 1955 EV_RX_TCP_UDP_CHKSUM_ERR, 1956 EV_RX_ETH_CRC_ERR, 1957 EV_RX_IP_FRAG_ERR, 1958 EV_RX_MCAST_PKT, 1959 EV_RX_MCAST_HASH_MATCH, 1960 EV_RX_TCP_IPV4, 1961 EV_RX_TCP_IPV6, 1962 EV_RX_UDP_IPV4, 1963 EV_RX_UDP_IPV6, 1964 EV_RX_OTHER_IPV4, 1965 EV_RX_OTHER_IPV6, 1966 EV_RX_NON_IP, 1967 EV_RX_BATCH, 1968 EV_TX, 1969 EV_TX_WQ_FF_FULL, 1970 EV_TX_PKT_ERR, 1971 EV_TX_PKT_TOO_BIG, 1972 EV_TX_UNEXPECTED, 1973 EV_GLOBAL, 1974 EV_GLOBAL_MNT, 1975 EV_DRIVER, 1976 EV_DRIVER_SRM_UPD_DONE, 1977 EV_DRIVER_TX_DESCQ_FLS_DONE, 1978 EV_DRIVER_RX_DESCQ_FLS_DONE, 1979 EV_DRIVER_RX_DESCQ_FLS_FAILED, 1980 EV_DRIVER_RX_DSC_ERROR, 1981 EV_DRIVER_TX_DSC_ERROR, 1982 EV_DRV_GEN, 1983 EV_MCDI_RESPONSE, 1984 EV_NQSTATS 1985} efx_ev_qstat_t; 1986 1987/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 1988 1989#endif /* EFSYS_OPT_QSTATS */ 1990 1991extern __checkReturn efx_rc_t 1992efx_ev_init( 1993 __in efx_nic_t *enp); 1994 1995extern void 1996efx_ev_fini( 1997 __in efx_nic_t *enp); 1998 1999#define EFX_EVQ_MAXNEVS 32768 2000#define EFX_EVQ_MINNEVS 512 2001 2002#define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) 2003#define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) 2004 2005#define EFX_EVQ_FLAGS_TYPE_MASK (0x3) 2006#define EFX_EVQ_FLAGS_TYPE_AUTO (0x0) 2007#define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1) 2008#define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2) 2009 2010#define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC) 2011#define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */ 2012#define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */ 2013 2014extern __checkReturn efx_rc_t 2015efx_ev_qcreate( 2016 __in efx_nic_t *enp, 2017 __in unsigned int index, 2018 __in efsys_mem_t *esmp, 2019 __in size_t ndescs, 2020 __in uint32_t id, 2021 __in uint32_t us, 2022 __in uint32_t flags, 2023 __deref_out efx_evq_t **eepp); 2024 2025extern void 2026efx_ev_qpost( 2027 __in efx_evq_t *eep, 2028 __in uint16_t data); 2029 2030typedef __checkReturn boolean_t 2031(*efx_initialized_ev_t)( 2032 __in_opt void *arg); 2033 2034#define EFX_PKT_UNICAST 0x0004 2035#define EFX_PKT_START 0x0008 2036 2037#define EFX_PKT_VLAN_TAGGED 0x0010 2038#define EFX_CKSUM_TCPUDP 0x0020 2039#define EFX_CKSUM_IPV4 0x0040 2040#define EFX_PKT_CONT 0x0080 2041 2042#define EFX_CHECK_VLAN 0x0100 2043#define EFX_PKT_TCP 0x0200 2044#define EFX_PKT_UDP 0x0400 2045#define EFX_PKT_IPV4 0x0800 2046 2047#define EFX_PKT_IPV6 0x1000 2048#define EFX_PKT_PREFIX_LEN 0x2000 2049#define EFX_ADDR_MISMATCH 0x4000 2050#define EFX_DISCARD 0x8000 2051 2052/* 2053 * The following flags are used only for packed stream 2054 * mode. The values for the flags are reused to fit into 16 bit, 2055 * since EFX_PKT_START and EFX_PKT_CONT are never used in 2056 * packed stream mode 2057 */ 2058#define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START 2059#define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT 2060 2061#define EFX_EV_RX_NLABELS 32 2062#define EFX_EV_TX_NLABELS 32 2063 2064typedef __checkReturn boolean_t 2065(*efx_rx_ev_t)( 2066 __in_opt void *arg, 2067 __in uint32_t label, 2068 __in uint32_t id, 2069 __in uint32_t size, 2070 __in uint16_t flags); 2071 2072#if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2073 2074/* 2075 * Packed stream mode is documented in SF-112241-TC. 2076 * The general idea is that, instead of putting each incoming 2077 * packet into a separate buffer which is specified in a RX 2078 * descriptor, a large buffer is provided to the hardware and 2079 * packets are put there in a continuous stream. 2080 * The main advantage of such an approach is that RX queue refilling 2081 * happens much less frequently. 2082 * 2083 * Equal stride packed stream mode is documented in SF-119419-TC. 2084 * The general idea is to utilize advantages of the packed stream, 2085 * but avoid indirection in packets representation. 2086 * The main advantage of such an approach is that RX queue refilling 2087 * happens much less frequently and packets buffers are independent 2088 * from upper layers point of view. 2089 */ 2090 2091typedef __checkReturn boolean_t 2092(*efx_rx_ps_ev_t)( 2093 __in_opt void *arg, 2094 __in uint32_t label, 2095 __in uint32_t id, 2096 __in uint32_t pkt_count, 2097 __in uint16_t flags); 2098 2099#endif 2100 2101typedef __checkReturn boolean_t 2102(*efx_tx_ev_t)( 2103 __in_opt void *arg, 2104 __in uint32_t label, 2105 __in uint32_t id); 2106 2107#define EFX_EXCEPTION_RX_RECOVERY 0x00000001 2108#define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 2109#define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 2110#define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 2111#define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 2112#define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 2113#define EFX_EXCEPTION_RX_ERROR 0x00000007 2114#define EFX_EXCEPTION_TX_ERROR 0x00000008 2115#define EFX_EXCEPTION_EV_ERROR 0x00000009 2116 2117typedef __checkReturn boolean_t 2118(*efx_exception_ev_t)( 2119 __in_opt void *arg, 2120 __in uint32_t label, 2121 __in uint32_t data); 2122 2123typedef __checkReturn boolean_t 2124(*efx_rxq_flush_done_ev_t)( 2125 __in_opt void *arg, 2126 __in uint32_t rxq_index); 2127 2128typedef __checkReturn boolean_t 2129(*efx_rxq_flush_failed_ev_t)( 2130 __in_opt void *arg, 2131 __in uint32_t rxq_index); 2132 2133typedef __checkReturn boolean_t 2134(*efx_txq_flush_done_ev_t)( 2135 __in_opt void *arg, 2136 __in uint32_t txq_index); 2137 2138typedef __checkReturn boolean_t 2139(*efx_software_ev_t)( 2140 __in_opt void *arg, 2141 __in uint16_t magic); 2142 2143typedef __checkReturn boolean_t 2144(*efx_sram_ev_t)( 2145 __in_opt void *arg, 2146 __in uint32_t code); 2147 2148#define EFX_SRAM_CLEAR 0 2149#define EFX_SRAM_UPDATE 1 2150#define EFX_SRAM_ILLEGAL_CLEAR 2 2151 2152typedef __checkReturn boolean_t 2153(*efx_wake_up_ev_t)( 2154 __in_opt void *arg, 2155 __in uint32_t label); 2156 2157typedef __checkReturn boolean_t 2158(*efx_timer_ev_t)( 2159 __in_opt void *arg, 2160 __in uint32_t label); 2161 2162typedef __checkReturn boolean_t 2163(*efx_link_change_ev_t)( 2164 __in_opt void *arg, 2165 __in efx_link_mode_t link_mode); 2166 2167#if EFSYS_OPT_MON_STATS 2168 2169typedef __checkReturn boolean_t 2170(*efx_monitor_ev_t)( 2171 __in_opt void *arg, 2172 __in efx_mon_stat_t id, 2173 __in efx_mon_stat_value_t value); 2174 2175#endif /* EFSYS_OPT_MON_STATS */ 2176 2177#if EFSYS_OPT_MAC_STATS 2178 2179typedef __checkReturn boolean_t 2180(*efx_mac_stats_ev_t)( 2181 __in_opt void *arg, 2182 __in uint32_t generation); 2183 2184#endif /* EFSYS_OPT_MAC_STATS */ 2185 2186typedef struct efx_ev_callbacks_s { 2187 efx_initialized_ev_t eec_initialized; 2188 efx_rx_ev_t eec_rx; 2189#if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2190 efx_rx_ps_ev_t eec_rx_ps; 2191#endif 2192 efx_tx_ev_t eec_tx; 2193 efx_exception_ev_t eec_exception; 2194 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 2195 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 2196 efx_txq_flush_done_ev_t eec_txq_flush_done; 2197 efx_software_ev_t eec_software; 2198 efx_sram_ev_t eec_sram; 2199 efx_wake_up_ev_t eec_wake_up; 2200 efx_timer_ev_t eec_timer; 2201 efx_link_change_ev_t eec_link_change; 2202#if EFSYS_OPT_MON_STATS 2203 efx_monitor_ev_t eec_monitor; 2204#endif /* EFSYS_OPT_MON_STATS */ 2205#if EFSYS_OPT_MAC_STATS 2206 efx_mac_stats_ev_t eec_mac_stats; 2207#endif /* EFSYS_OPT_MAC_STATS */ 2208} efx_ev_callbacks_t; 2209 2210extern __checkReturn boolean_t 2211efx_ev_qpending( 2212 __in efx_evq_t *eep, 2213 __in unsigned int count); 2214 2215#if EFSYS_OPT_EV_PREFETCH 2216 2217extern void 2218efx_ev_qprefetch( 2219 __in efx_evq_t *eep, 2220 __in unsigned int count); 2221 2222#endif /* EFSYS_OPT_EV_PREFETCH */ 2223 2224extern void 2225efx_ev_qpoll( 2226 __in efx_evq_t *eep, 2227 __inout unsigned int *countp, 2228 __in const efx_ev_callbacks_t *eecp, 2229 __in_opt void *arg); 2230 2231extern __checkReturn efx_rc_t 2232efx_ev_usecs_to_ticks( 2233 __in efx_nic_t *enp, 2234 __in unsigned int usecs, 2235 __out unsigned int *ticksp); 2236 2237extern __checkReturn efx_rc_t 2238efx_ev_qmoderate( 2239 __in efx_evq_t *eep, 2240 __in unsigned int us); 2241 2242extern __checkReturn efx_rc_t 2243efx_ev_qprime( 2244 __in efx_evq_t *eep, 2245 __in unsigned int count); 2246 2247#if EFSYS_OPT_QSTATS 2248 2249#if EFSYS_OPT_NAMES 2250 2251extern const char * 2252efx_ev_qstat_name( 2253 __in efx_nic_t *enp, 2254 __in unsigned int id); 2255 2256#endif /* EFSYS_OPT_NAMES */ 2257 2258extern void 2259efx_ev_qstats_update( 2260 __in efx_evq_t *eep, 2261 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 2262 2263#endif /* EFSYS_OPT_QSTATS */ 2264 2265extern void 2266efx_ev_qdestroy( 2267 __in efx_evq_t *eep); 2268 2269/* RX */ 2270 2271extern __checkReturn efx_rc_t 2272efx_rx_init( 2273 __inout efx_nic_t *enp); 2274 2275extern void 2276efx_rx_fini( 2277 __in efx_nic_t *enp); 2278 2279#if EFSYS_OPT_RX_SCATTER 2280 __checkReturn efx_rc_t 2281efx_rx_scatter_enable( 2282 __in efx_nic_t *enp, 2283 __in unsigned int buf_size); 2284#endif /* EFSYS_OPT_RX_SCATTER */ 2285 2286/* Handle to represent use of the default RSS context. */ 2287#define EFX_RSS_CONTEXT_DEFAULT 0xffffffff 2288 2289#if EFSYS_OPT_RX_SCALE 2290 2291typedef enum efx_rx_hash_alg_e { 2292 EFX_RX_HASHALG_LFSR = 0, 2293 EFX_RX_HASHALG_TOEPLITZ, 2294 EFX_RX_HASHALG_PACKED_STREAM, 2295 EFX_RX_NHASHALGS 2296} efx_rx_hash_alg_t; 2297 2298/* 2299 * Legacy hash type flags. 2300 * 2301 * They represent standard tuples for distinct traffic classes. 2302 */ 2303#define EFX_RX_HASH_IPV4 (1U << 0) 2304#define EFX_RX_HASH_TCPIPV4 (1U << 1) 2305#define EFX_RX_HASH_IPV6 (1U << 2) 2306#define EFX_RX_HASH_TCPIPV6 (1U << 3) 2307 2308#define EFX_RX_HASH_LEGACY_MASK \ 2309 (EFX_RX_HASH_IPV4 | \ 2310 EFX_RX_HASH_TCPIPV4 | \ 2311 EFX_RX_HASH_IPV6 | \ 2312 EFX_RX_HASH_TCPIPV6) 2313 2314/* 2315 * The type of the argument used by efx_rx_scale_mode_set() to 2316 * provide a means for the client drivers to configure hashing. 2317 * 2318 * A properly constructed value can either be: 2319 * - a combination of legacy flags 2320 * - a combination of EFX_RX_HASH() flags 2321 */ 2322typedef uint32_t efx_rx_hash_type_t; 2323 2324typedef enum efx_rx_hash_support_e { 2325 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 2326 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 2327} efx_rx_hash_support_t; 2328 2329#define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */ 2330#define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 2331#define EFX_MAXRSS 64 /* RX indirection entry range */ 2332#define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 2333 2334typedef enum efx_rx_scale_context_type_e { 2335 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */ 2336 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 2337 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 2338} efx_rx_scale_context_type_t; 2339 2340/* 2341 * Traffic classes eligible for hash computation. 2342 * 2343 * Select packet headers used in computing the receive hash. 2344 * This uses the same encoding as the RSS_MODES field of 2345 * MC_CMD_RSS_CONTEXT_SET_FLAGS. 2346 */ 2347#define EFX_RX_CLASS_IPV4_TCP_LBN 8 2348#define EFX_RX_CLASS_IPV4_TCP_WIDTH 4 2349#define EFX_RX_CLASS_IPV4_UDP_LBN 12 2350#define EFX_RX_CLASS_IPV4_UDP_WIDTH 4 2351#define EFX_RX_CLASS_IPV4_LBN 16 2352#define EFX_RX_CLASS_IPV4_WIDTH 4 2353#define EFX_RX_CLASS_IPV6_TCP_LBN 20 2354#define EFX_RX_CLASS_IPV6_TCP_WIDTH 4 2355#define EFX_RX_CLASS_IPV6_UDP_LBN 24 2356#define EFX_RX_CLASS_IPV6_UDP_WIDTH 4 2357#define EFX_RX_CLASS_IPV6_LBN 28 2358#define EFX_RX_CLASS_IPV6_WIDTH 4 2359 2360#define EFX_RX_NCLASSES 6 2361 2362/* 2363 * Ancillary flags used to construct generic hash tuples. 2364 * This uses the same encoding as RSS_MODE_HASH_SELECTOR. 2365 */ 2366#define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0) 2367#define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1) 2368#define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2) 2369#define EFX_RX_CLASS_HASH_DST_PORT (1U << 3) 2370 2371/* 2372 * Generic hash tuples. 2373 * 2374 * They express combinations of packet fields 2375 * which can contribute to the hash value for 2376 * a particular traffic class. 2377 */ 2378#define EFX_RX_CLASS_HASH_DISABLE 0 2379 2380#define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR 2381#define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR 2382 2383#define EFX_RX_CLASS_HASH_2TUPLE \ 2384 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2385 EFX_RX_CLASS_HASH_DST_ADDR) 2386 2387#define EFX_RX_CLASS_HASH_2TUPLE_SRC \ 2388 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2389 EFX_RX_CLASS_HASH_SRC_PORT) 2390 2391#define EFX_RX_CLASS_HASH_2TUPLE_DST \ 2392 (EFX_RX_CLASS_HASH_DST_ADDR | \ 2393 EFX_RX_CLASS_HASH_DST_PORT) 2394 2395#define EFX_RX_CLASS_HASH_4TUPLE \ 2396 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2397 EFX_RX_CLASS_HASH_DST_ADDR | \ 2398 EFX_RX_CLASS_HASH_SRC_PORT | \ 2399 EFX_RX_CLASS_HASH_DST_PORT) 2400 2401#define EFX_RX_CLASS_HASH_NTUPLES 7 2402 2403/* 2404 * Hash flag constructor. 2405 * 2406 * Resulting flags encode hash tuples for specific traffic classes. 2407 * The client drivers are encouraged to use these flags to form 2408 * a hash type value. 2409 */ 2410#define EFX_RX_HASH(_class, _tuple) \ 2411 EFX_INSERT_FIELD_NATIVE32(0, 31, \ 2412 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple) 2413 2414/* 2415 * The maximum number of EFX_RX_HASH() flags. 2416 */ 2417#define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES) 2418 2419extern __checkReturn efx_rc_t 2420efx_rx_scale_hash_flags_get( 2421 __in efx_nic_t *enp, 2422 __in efx_rx_hash_alg_t hash_alg, 2423 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp, 2424 __in unsigned int max_nflags, 2425 __out unsigned int *nflagsp); 2426 2427extern __checkReturn efx_rc_t 2428efx_rx_hash_default_support_get( 2429 __in efx_nic_t *enp, 2430 __out efx_rx_hash_support_t *supportp); 2431 2432extern __checkReturn efx_rc_t 2433efx_rx_scale_default_support_get( 2434 __in efx_nic_t *enp, 2435 __out efx_rx_scale_context_type_t *typep); 2436 2437extern __checkReturn efx_rc_t 2438efx_rx_scale_context_alloc( 2439 __in efx_nic_t *enp, 2440 __in efx_rx_scale_context_type_t type, 2441 __in uint32_t num_queues, 2442 __out uint32_t *rss_contextp); 2443 2444extern __checkReturn efx_rc_t 2445efx_rx_scale_context_free( 2446 __in efx_nic_t *enp, 2447 __in uint32_t rss_context); 2448 2449extern __checkReturn efx_rc_t 2450efx_rx_scale_mode_set( 2451 __in efx_nic_t *enp, 2452 __in uint32_t rss_context, 2453 __in efx_rx_hash_alg_t alg, 2454 __in efx_rx_hash_type_t type, 2455 __in boolean_t insert); 2456 2457extern __checkReturn efx_rc_t 2458efx_rx_scale_tbl_set( 2459 __in efx_nic_t *enp, 2460 __in uint32_t rss_context, 2461 __in_ecount(n) unsigned int *table, 2462 __in size_t n); 2463 2464extern __checkReturn efx_rc_t 2465efx_rx_scale_key_set( 2466 __in efx_nic_t *enp, 2467 __in uint32_t rss_context, 2468 __in_ecount(n) uint8_t *key, 2469 __in size_t n); 2470 2471extern __checkReturn uint32_t 2472efx_pseudo_hdr_hash_get( 2473 __in efx_rxq_t *erp, 2474 __in efx_rx_hash_alg_t func, 2475 __in uint8_t *buffer); 2476 2477#endif /* EFSYS_OPT_RX_SCALE */ 2478 2479extern __checkReturn efx_rc_t 2480efx_pseudo_hdr_pkt_length_get( 2481 __in efx_rxq_t *erp, 2482 __in uint8_t *buffer, 2483 __out uint16_t *pkt_lengthp); 2484 2485#define EFX_RXQ_MAXNDESCS 4096 2486#define EFX_RXQ_MINNDESCS 512 2487 2488#define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 2489#define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2490#define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2491#define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize) 2492 2493typedef enum efx_rxq_type_e { 2494 EFX_RXQ_TYPE_DEFAULT, 2495 EFX_RXQ_TYPE_PACKED_STREAM, 2496 EFX_RXQ_TYPE_ES_SUPER_BUFFER, 2497 EFX_RXQ_NTYPES 2498} efx_rxq_type_t; 2499 2500/* 2501 * Dummy flag to be used instead of 0 to make it clear that the argument 2502 * is receive queue flags. 2503 */ 2504#define EFX_RXQ_FLAG_NONE 0x0 2505#define EFX_RXQ_FLAG_SCATTER 0x1 2506/* 2507 * If tunnels are supported and Rx event can provide information about 2508 * either outer or inner packet classes (e.g. SFN8xxx adapters with 2509 * full-feature firmware variant running), outer classes are requested by 2510 * default. However, if the driver supports tunnels, the flag allows to 2511 * request inner classes which are required to be able to interpret inner 2512 * Rx checksum offload results. 2513 */ 2514#define EFX_RXQ_FLAG_INNER_CLASSES 0x2 2515 2516extern __checkReturn efx_rc_t 2517efx_rx_qcreate( 2518 __in efx_nic_t *enp, 2519 __in unsigned int index, 2520 __in unsigned int label, 2521 __in efx_rxq_type_t type, 2522 __in efsys_mem_t *esmp, 2523 __in size_t ndescs, 2524 __in uint32_t id, 2525 __in unsigned int flags, 2526 __in efx_evq_t *eep, 2527 __deref_out efx_rxq_t **erpp); 2528 2529#if EFSYS_OPT_RX_PACKED_STREAM 2530 2531#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024) 2532#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024) 2533#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024) 2534#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024) 2535#define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024) 2536 2537extern __checkReturn efx_rc_t 2538efx_rx_qcreate_packed_stream( 2539 __in efx_nic_t *enp, 2540 __in unsigned int index, 2541 __in unsigned int label, 2542 __in uint32_t ps_buf_size, 2543 __in efsys_mem_t *esmp, 2544 __in size_t ndescs, 2545 __in efx_evq_t *eep, 2546 __deref_out efx_rxq_t **erpp); 2547 2548#endif 2549 2550#if EFSYS_OPT_RX_ES_SUPER_BUFFER 2551 2552/* Maximum head-of-line block timeout in nanoseconds */ 2553#define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000) 2554 2555extern __checkReturn efx_rc_t 2556efx_rx_qcreate_es_super_buffer( 2557 __in efx_nic_t *enp, 2558 __in unsigned int index, 2559 __in unsigned int label, 2560 __in uint32_t n_bufs_per_desc, 2561 __in uint32_t max_dma_len, 2562 __in uint32_t buf_stride, 2563 __in uint32_t hol_block_timeout, 2564 __in efsys_mem_t *esmp, 2565 __in size_t ndescs, 2566 __in unsigned int flags, 2567 __in efx_evq_t *eep, 2568 __deref_out efx_rxq_t **erpp); 2569 2570#endif 2571 2572typedef struct efx_buffer_s { 2573 efsys_dma_addr_t eb_addr; 2574 size_t eb_size; 2575 boolean_t eb_eop; 2576} efx_buffer_t; 2577 2578typedef struct efx_desc_s { 2579 efx_qword_t ed_eq; 2580} efx_desc_t; 2581 2582extern void 2583efx_rx_qpost( 2584 __in efx_rxq_t *erp, 2585 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 2586 __in size_t size, 2587 __in unsigned int ndescs, 2588 __in unsigned int completed, 2589 __in unsigned int added); 2590 2591extern void 2592efx_rx_qpush( 2593 __in efx_rxq_t *erp, 2594 __in unsigned int added, 2595 __inout unsigned int *pushedp); 2596 2597#if EFSYS_OPT_RX_PACKED_STREAM 2598 2599extern void 2600efx_rx_qpush_ps_credits( 2601 __in efx_rxq_t *erp); 2602 2603extern __checkReturn uint8_t * 2604efx_rx_qps_packet_info( 2605 __in efx_rxq_t *erp, 2606 __in uint8_t *buffer, 2607 __in uint32_t buffer_length, 2608 __in uint32_t current_offset, 2609 __out uint16_t *lengthp, 2610 __out uint32_t *next_offsetp, 2611 __out uint32_t *timestamp); 2612#endif 2613 2614extern __checkReturn efx_rc_t 2615efx_rx_qflush( 2616 __in efx_rxq_t *erp); 2617 2618extern void 2619efx_rx_qenable( 2620 __in efx_rxq_t *erp); 2621 2622extern void 2623efx_rx_qdestroy( 2624 __in efx_rxq_t *erp); 2625 2626/* TX */ 2627 2628typedef struct efx_txq_s efx_txq_t; 2629 2630#if EFSYS_OPT_QSTATS 2631 2632/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 2633typedef enum efx_tx_qstat_e { 2634 TX_POST, 2635 TX_POST_PIO, 2636 TX_NQSTATS 2637} efx_tx_qstat_t; 2638 2639/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 2640 2641#endif /* EFSYS_OPT_QSTATS */ 2642 2643extern __checkReturn efx_rc_t 2644efx_tx_init( 2645 __in efx_nic_t *enp); 2646 2647extern void 2648efx_tx_fini( 2649 __in efx_nic_t *enp); 2650 2651#define EFX_TXQ_MINNDESCS 512 2652 2653#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 2654#define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 2655#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2656 2657#define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ 2658 2659#define EFX_TXQ_CKSUM_IPV4 0x0001 2660#define EFX_TXQ_CKSUM_TCPUDP 0x0002 2661#define EFX_TXQ_FATSOV2 0x0004 2662#define EFX_TXQ_CKSUM_INNER_IPV4 0x0008 2663#define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010 2664 2665extern __checkReturn efx_rc_t 2666efx_tx_qcreate( 2667 __in efx_nic_t *enp, 2668 __in unsigned int index, 2669 __in unsigned int label, 2670 __in efsys_mem_t *esmp, 2671 __in size_t n, 2672 __in uint32_t id, 2673 __in uint16_t flags, 2674 __in efx_evq_t *eep, 2675 __deref_out efx_txq_t **etpp, 2676 __out unsigned int *addedp); 2677 2678extern __checkReturn efx_rc_t 2679efx_tx_qpost( 2680 __in efx_txq_t *etp, 2681 __in_ecount(ndescs) efx_buffer_t *eb, 2682 __in unsigned int ndescs, 2683 __in unsigned int completed, 2684 __inout unsigned int *addedp); 2685 2686extern __checkReturn efx_rc_t 2687efx_tx_qpace( 2688 __in efx_txq_t *etp, 2689 __in unsigned int ns); 2690 2691extern void 2692efx_tx_qpush( 2693 __in efx_txq_t *etp, 2694 __in unsigned int added, 2695 __in unsigned int pushed); 2696 2697extern __checkReturn efx_rc_t 2698efx_tx_qflush( 2699 __in efx_txq_t *etp); 2700 2701extern void 2702efx_tx_qenable( 2703 __in efx_txq_t *etp); 2704 2705extern __checkReturn efx_rc_t 2706efx_tx_qpio_enable( 2707 __in efx_txq_t *etp); 2708 2709extern void 2710efx_tx_qpio_disable( 2711 __in efx_txq_t *etp); 2712 2713extern __checkReturn efx_rc_t 2714efx_tx_qpio_write( 2715 __in efx_txq_t *etp, 2716 __in_ecount(buf_length) uint8_t *buffer, 2717 __in size_t buf_length, 2718 __in size_t pio_buf_offset); 2719 2720extern __checkReturn efx_rc_t 2721efx_tx_qpio_post( 2722 __in efx_txq_t *etp, 2723 __in size_t pkt_length, 2724 __in unsigned int completed, 2725 __inout unsigned int *addedp); 2726 2727extern __checkReturn efx_rc_t 2728efx_tx_qdesc_post( 2729 __in efx_txq_t *etp, 2730 __in_ecount(n) efx_desc_t *ed, 2731 __in unsigned int n, 2732 __in unsigned int completed, 2733 __inout unsigned int *addedp); 2734 2735extern void 2736efx_tx_qdesc_dma_create( 2737 __in efx_txq_t *etp, 2738 __in efsys_dma_addr_t addr, 2739 __in size_t size, 2740 __in boolean_t eop, 2741 __out efx_desc_t *edp); 2742 2743extern void 2744efx_tx_qdesc_tso_create( 2745 __in efx_txq_t *etp, 2746 __in uint16_t ipv4_id, 2747 __in uint32_t tcp_seq, 2748 __in uint8_t tcp_flags, 2749 __out efx_desc_t *edp); 2750 2751/* Number of FATSOv2 option descriptors */ 2752#define EFX_TX_FATSOV2_OPT_NDESCS 2 2753 2754/* Maximum number of DMA segments per TSO packet (not superframe) */ 2755#define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24 2756 2757extern void 2758efx_tx_qdesc_tso2_create( 2759 __in efx_txq_t *etp, 2760 __in uint16_t ipv4_id, 2761 __in uint16_t outer_ipv4_id, 2762 __in uint32_t tcp_seq, 2763 __in uint16_t tcp_mss, 2764 __out_ecount(count) efx_desc_t *edp, 2765 __in int count); 2766 2767extern void 2768efx_tx_qdesc_vlantci_create( 2769 __in efx_txq_t *etp, 2770 __in uint16_t tci, 2771 __out efx_desc_t *edp); 2772 2773extern void 2774efx_tx_qdesc_checksum_create( 2775 __in efx_txq_t *etp, 2776 __in uint16_t flags, 2777 __out efx_desc_t *edp); 2778 2779#if EFSYS_OPT_QSTATS 2780 2781#if EFSYS_OPT_NAMES 2782 2783extern const char * 2784efx_tx_qstat_name( 2785 __in efx_nic_t *etp, 2786 __in unsigned int id); 2787 2788#endif /* EFSYS_OPT_NAMES */ 2789 2790extern void 2791efx_tx_qstats_update( 2792 __in efx_txq_t *etp, 2793 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 2794 2795#endif /* EFSYS_OPT_QSTATS */ 2796 2797extern void 2798efx_tx_qdestroy( 2799 __in efx_txq_t *etp); 2800 2801/* FILTER */ 2802 2803#if EFSYS_OPT_FILTER 2804 2805#define EFX_ETHER_TYPE_IPV4 0x0800 2806#define EFX_ETHER_TYPE_IPV6 0x86DD 2807 2808#define EFX_IPPROTO_TCP 6 2809#define EFX_IPPROTO_UDP 17 2810#define EFX_IPPROTO_GRE 47 2811 2812/* Use RSS to spread across multiple queues */ 2813#define EFX_FILTER_FLAG_RX_RSS 0x01 2814/* Enable RX scatter */ 2815#define EFX_FILTER_FLAG_RX_SCATTER 0x02 2816/* 2817 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO). 2818 * May only be set by the filter implementation for each type. 2819 * A removal request will restore the automatic filter in its place. 2820 */ 2821#define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04 2822/* Filter is for RX */ 2823#define EFX_FILTER_FLAG_RX 0x08 2824/* Filter is for TX */ 2825#define EFX_FILTER_FLAG_TX 0x10 2826/* Set match flag on the received packet */ 2827#define EFX_FILTER_FLAG_ACTION_FLAG 0x20 2828/* Set match mark on the received packet */ 2829#define EFX_FILTER_FLAG_ACTION_MARK 0x40 2830 2831typedef uint8_t efx_filter_flags_t; 2832 2833/* 2834 * Flags which specify the fields to match on. The values are the same as in the 2835 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands. 2836 */ 2837 2838/* Match by remote IP host address */ 2839#define EFX_FILTER_MATCH_REM_HOST 0x00000001 2840/* Match by local IP host address */ 2841#define EFX_FILTER_MATCH_LOC_HOST 0x00000002 2842/* Match by remote MAC address */ 2843#define EFX_FILTER_MATCH_REM_MAC 0x00000004 2844/* Match by remote TCP/UDP port */ 2845#define EFX_FILTER_MATCH_REM_PORT 0x00000008 2846/* Match by remote TCP/UDP port */ 2847#define EFX_FILTER_MATCH_LOC_MAC 0x00000010 2848/* Match by local TCP/UDP port */ 2849#define EFX_FILTER_MATCH_LOC_PORT 0x00000020 2850/* Match by Ether-type */ 2851#define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040 2852/* Match by inner VLAN ID */ 2853#define EFX_FILTER_MATCH_INNER_VID 0x00000080 2854/* Match by outer VLAN ID */ 2855#define EFX_FILTER_MATCH_OUTER_VID 0x00000100 2856/* Match by IP transport protocol */ 2857#define EFX_FILTER_MATCH_IP_PROTO 0x00000200 2858/* Match by VNI or VSID */ 2859#define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800 2860/* For encapsulated packets, match by inner frame local MAC address */ 2861#define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000 2862/* For encapsulated packets, match all multicast inner frames */ 2863#define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000 2864/* For encapsulated packets, match all unicast inner frames */ 2865#define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000 2866/* 2867 * Match by encap type, this flag does not correspond to 2868 * the MCDI match flags and any unoccupied value may be used 2869 */ 2870#define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000 2871/* Match otherwise-unmatched multicast and broadcast packets */ 2872#define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000 2873/* Match otherwise-unmatched unicast packets */ 2874#define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000 2875 2876typedef uint32_t efx_filter_match_flags_t; 2877 2878typedef enum efx_filter_priority_s { 2879 EFX_FILTER_PRI_HINT = 0, /* Performance hint */ 2880 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device 2881 * address list or hardware 2882 * requirements. This may only be used 2883 * by the filter implementation for 2884 * each NIC type. */ 2885 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 2886 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the 2887 * client (e.g. SR-IOV, HyperV VMQ etc.) 2888 */ 2889} efx_filter_priority_t; 2890 2891/* 2892 * FIXME: All these fields are assumed to be in little-endian byte order. 2893 * It may be better for some to be big-endian. See bug42804. 2894 */ 2895 2896typedef struct efx_filter_spec_s { 2897 efx_filter_match_flags_t efs_match_flags; 2898 uint8_t efs_priority; 2899 efx_filter_flags_t efs_flags; 2900 uint16_t efs_dmaq_id; 2901 uint32_t efs_rss_context; 2902 uint32_t efs_mark; 2903 /* Fields below here are hashed for software filter lookup */ 2904 uint16_t efs_outer_vid; 2905 uint16_t efs_inner_vid; 2906 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 2907 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 2908 uint16_t efs_ether_type; 2909 uint8_t efs_ip_proto; 2910 efx_tunnel_protocol_t efs_encap_type; 2911 uint16_t efs_loc_port; 2912 uint16_t efs_rem_port; 2913 efx_oword_t efs_rem_host; 2914 efx_oword_t efs_loc_host; 2915 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN]; 2916 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN]; 2917} efx_filter_spec_t; 2918 2919/* Default values for use in filter specifications */ 2920#define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 2921#define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 2922 2923extern __checkReturn efx_rc_t 2924efx_filter_init( 2925 __in efx_nic_t *enp); 2926 2927extern void 2928efx_filter_fini( 2929 __in efx_nic_t *enp); 2930 2931extern __checkReturn efx_rc_t 2932efx_filter_insert( 2933 __in efx_nic_t *enp, 2934 __inout efx_filter_spec_t *spec); 2935 2936extern __checkReturn efx_rc_t 2937efx_filter_remove( 2938 __in efx_nic_t *enp, 2939 __inout efx_filter_spec_t *spec); 2940 2941extern __checkReturn efx_rc_t 2942efx_filter_restore( 2943 __in efx_nic_t *enp); 2944 2945extern __checkReturn efx_rc_t 2946efx_filter_supported_filters( 2947 __in efx_nic_t *enp, 2948 __out_ecount(buffer_length) uint32_t *buffer, 2949 __in size_t buffer_length, 2950 __out size_t *list_lengthp); 2951 2952extern void 2953efx_filter_spec_init_rx( 2954 __out efx_filter_spec_t *spec, 2955 __in efx_filter_priority_t priority, 2956 __in efx_filter_flags_t flags, 2957 __in efx_rxq_t *erp); 2958 2959extern void 2960efx_filter_spec_init_tx( 2961 __out efx_filter_spec_t *spec, 2962 __in efx_txq_t *etp); 2963 2964extern __checkReturn efx_rc_t 2965efx_filter_spec_set_ipv4_local( 2966 __inout efx_filter_spec_t *spec, 2967 __in uint8_t proto, 2968 __in uint32_t host, 2969 __in uint16_t port); 2970 2971extern __checkReturn efx_rc_t 2972efx_filter_spec_set_ipv4_full( 2973 __inout efx_filter_spec_t *spec, 2974 __in uint8_t proto, 2975 __in uint32_t lhost, 2976 __in uint16_t lport, 2977 __in uint32_t rhost, 2978 __in uint16_t rport); 2979 2980extern __checkReturn efx_rc_t 2981efx_filter_spec_set_eth_local( 2982 __inout efx_filter_spec_t *spec, 2983 __in uint16_t vid, 2984 __in const uint8_t *addr); 2985 2986extern void 2987efx_filter_spec_set_ether_type( 2988 __inout efx_filter_spec_t *spec, 2989 __in uint16_t ether_type); 2990 2991extern __checkReturn efx_rc_t 2992efx_filter_spec_set_uc_def( 2993 __inout efx_filter_spec_t *spec); 2994 2995extern __checkReturn efx_rc_t 2996efx_filter_spec_set_mc_def( 2997 __inout efx_filter_spec_t *spec); 2998 2999typedef enum efx_filter_inner_frame_match_e { 3000 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0, 3001 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST, 3002 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST 3003} efx_filter_inner_frame_match_t; 3004 3005extern __checkReturn efx_rc_t 3006efx_filter_spec_set_encap_type( 3007 __inout efx_filter_spec_t *spec, 3008 __in efx_tunnel_protocol_t encap_type, 3009 __in efx_filter_inner_frame_match_t inner_frame_match); 3010 3011extern __checkReturn efx_rc_t 3012efx_filter_spec_set_vxlan( 3013 __inout efx_filter_spec_t *spec, 3014 __in const uint8_t *vni, 3015 __in const uint8_t *inner_addr, 3016 __in const uint8_t *outer_addr); 3017 3018extern __checkReturn efx_rc_t 3019efx_filter_spec_set_geneve( 3020 __inout efx_filter_spec_t *spec, 3021 __in const uint8_t *vni, 3022 __in const uint8_t *inner_addr, 3023 __in const uint8_t *outer_addr); 3024 3025extern __checkReturn efx_rc_t 3026efx_filter_spec_set_nvgre( 3027 __inout efx_filter_spec_t *spec, 3028 __in const uint8_t *vsid, 3029 __in const uint8_t *inner_addr, 3030 __in const uint8_t *outer_addr); 3031 3032#if EFSYS_OPT_RX_SCALE 3033extern __checkReturn efx_rc_t 3034efx_filter_spec_set_rss_context( 3035 __inout efx_filter_spec_t *spec, 3036 __in uint32_t rss_context); 3037#endif 3038#endif /* EFSYS_OPT_FILTER */ 3039 3040/* HASH */ 3041 3042extern __checkReturn uint32_t 3043efx_hash_dwords( 3044 __in_ecount(count) uint32_t const *input, 3045 __in size_t count, 3046 __in uint32_t init); 3047 3048extern __checkReturn uint32_t 3049efx_hash_bytes( 3050 __in_ecount(length) uint8_t const *input, 3051 __in size_t length, 3052 __in uint32_t init); 3053 3054#if EFSYS_OPT_LICENSING 3055 3056/* LICENSING */ 3057 3058typedef struct efx_key_stats_s { 3059 uint32_t eks_valid; 3060 uint32_t eks_invalid; 3061 uint32_t eks_blacklisted; 3062 uint32_t eks_unverifiable; 3063 uint32_t eks_wrong_node; 3064 uint32_t eks_licensed_apps_lo; 3065 uint32_t eks_licensed_apps_hi; 3066 uint32_t eks_licensed_features_lo; 3067 uint32_t eks_licensed_features_hi; 3068} efx_key_stats_t; 3069 3070extern __checkReturn efx_rc_t 3071efx_lic_init( 3072 __in efx_nic_t *enp); 3073 3074extern void 3075efx_lic_fini( 3076 __in efx_nic_t *enp); 3077 3078extern __checkReturn boolean_t 3079efx_lic_check_support( 3080 __in efx_nic_t *enp); 3081 3082extern __checkReturn efx_rc_t 3083efx_lic_update_licenses( 3084 __in efx_nic_t *enp); 3085 3086extern __checkReturn efx_rc_t 3087efx_lic_get_key_stats( 3088 __in efx_nic_t *enp, 3089 __out efx_key_stats_t *ksp); 3090 3091extern __checkReturn efx_rc_t 3092efx_lic_app_state( 3093 __in efx_nic_t *enp, 3094 __in uint64_t app_id, 3095 __out boolean_t *licensedp); 3096 3097extern __checkReturn efx_rc_t 3098efx_lic_get_id( 3099 __in efx_nic_t *enp, 3100 __in size_t buffer_size, 3101 __out uint32_t *typep, 3102 __out size_t *lengthp, 3103 __out_opt uint8_t *bufferp); 3104 3105extern __checkReturn efx_rc_t 3106efx_lic_find_start( 3107 __in efx_nic_t *enp, 3108 __in_bcount(buffer_size) 3109 caddr_t bufferp, 3110 __in size_t buffer_size, 3111 __out uint32_t *startp); 3112 3113extern __checkReturn efx_rc_t 3114efx_lic_find_end( 3115 __in efx_nic_t *enp, 3116 __in_bcount(buffer_size) 3117 caddr_t bufferp, 3118 __in size_t buffer_size, 3119 __in uint32_t offset, 3120 __out uint32_t *endp); 3121 3122extern __checkReturn __success(return != B_FALSE) boolean_t 3123efx_lic_find_key( 3124 __in efx_nic_t *enp, 3125 __in_bcount(buffer_size) 3126 caddr_t bufferp, 3127 __in size_t buffer_size, 3128 __in uint32_t offset, 3129 __out uint32_t *startp, 3130 __out uint32_t *lengthp); 3131 3132extern __checkReturn __success(return != B_FALSE) boolean_t 3133efx_lic_validate_key( 3134 __in efx_nic_t *enp, 3135 __in_bcount(length) caddr_t keyp, 3136 __in uint32_t length); 3137 3138extern __checkReturn efx_rc_t 3139efx_lic_read_key( 3140 __in efx_nic_t *enp, 3141 __in_bcount(buffer_size) 3142 caddr_t bufferp, 3143 __in size_t buffer_size, 3144 __in uint32_t offset, 3145 __in uint32_t length, 3146 __out_bcount_part(key_max_size, *lengthp) 3147 caddr_t keyp, 3148 __in size_t key_max_size, 3149 __out uint32_t *lengthp); 3150 3151extern __checkReturn efx_rc_t 3152efx_lic_write_key( 3153 __in efx_nic_t *enp, 3154 __in_bcount(buffer_size) 3155 caddr_t bufferp, 3156 __in size_t buffer_size, 3157 __in uint32_t offset, 3158 __in_bcount(length) caddr_t keyp, 3159 __in uint32_t length, 3160 __out uint32_t *lengthp); 3161 3162 __checkReturn efx_rc_t 3163efx_lic_delete_key( 3164 __in efx_nic_t *enp, 3165 __in_bcount(buffer_size) 3166 caddr_t bufferp, 3167 __in size_t buffer_size, 3168 __in uint32_t offset, 3169 __in uint32_t length, 3170 __in uint32_t end, 3171 __out uint32_t *deltap); 3172 3173extern __checkReturn efx_rc_t 3174efx_lic_create_partition( 3175 __in efx_nic_t *enp, 3176 __in_bcount(buffer_size) 3177 caddr_t bufferp, 3178 __in size_t buffer_size); 3179 3180extern __checkReturn efx_rc_t 3181efx_lic_finish_partition( 3182 __in efx_nic_t *enp, 3183 __in_bcount(buffer_size) 3184 caddr_t bufferp, 3185 __in size_t buffer_size); 3186 3187#endif /* EFSYS_OPT_LICENSING */ 3188 3189/* TUNNEL */ 3190 3191#if EFSYS_OPT_TUNNEL 3192 3193extern __checkReturn efx_rc_t 3194efx_tunnel_init( 3195 __in efx_nic_t *enp); 3196 3197extern void 3198efx_tunnel_fini( 3199 __in efx_nic_t *enp); 3200 3201/* 3202 * For overlay network encapsulation using UDP, the firmware needs to know 3203 * the configured UDP port for the overlay so it can decode encapsulated 3204 * frames correctly. 3205 * The UDP port/protocol list is global. 3206 */ 3207 3208extern __checkReturn efx_rc_t 3209efx_tunnel_config_udp_add( 3210 __in efx_nic_t *enp, 3211 __in uint16_t port /* host/cpu-endian */, 3212 __in efx_tunnel_protocol_t protocol); 3213 3214extern __checkReturn efx_rc_t 3215efx_tunnel_config_udp_remove( 3216 __in efx_nic_t *enp, 3217 __in uint16_t port /* host/cpu-endian */, 3218 __in efx_tunnel_protocol_t protocol); 3219 3220extern void 3221efx_tunnel_config_clear( 3222 __in efx_nic_t *enp); 3223 3224/** 3225 * Apply tunnel UDP ports configuration to hardware. 3226 * 3227 * EAGAIN is returned if hardware will be reset (datapath and management CPU 3228 * reboot). 3229 */ 3230extern __checkReturn efx_rc_t 3231efx_tunnel_reconfigure( 3232 __in efx_nic_t *enp); 3233 3234#endif /* EFSYS_OPT_TUNNEL */ 3235 3236#if EFSYS_OPT_FW_SUBVARIANT_AWARE 3237 3238/** 3239 * Firmware subvariant choice options. 3240 * 3241 * It may be switched to no Tx checksum if attached drivers are either 3242 * preboot or firmware subvariant aware and no VIS are allocated. 3243 * If may be always switched to default explicitly using set request or 3244 * implicitly if unaware driver is attaching. If switching is done when 3245 * a driver is attached, it gets MC_REBOOT event and should recreate its 3246 * datapath. 3247 * 3248 * See SF-119419-TC DPDK Firmware Driver Interface and 3249 * SF-109306-TC EF10 for Driver Writers for details. 3250 */ 3251typedef enum efx_nic_fw_subvariant_e { 3252 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0, 3253 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1, 3254 EFX_NIC_FW_SUBVARIANT_NTYPES 3255} efx_nic_fw_subvariant_t; 3256 3257extern __checkReturn efx_rc_t 3258efx_nic_get_fw_subvariant( 3259 __in efx_nic_t *enp, 3260 __out efx_nic_fw_subvariant_t *subvariantp); 3261 3262extern __checkReturn efx_rc_t 3263efx_nic_set_fw_subvariant( 3264 __in efx_nic_t *enp, 3265 __in efx_nic_fw_subvariant_t subvariant); 3266 3267#endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ 3268 3269typedef enum efx_phy_fec_type_e { 3270 EFX_PHY_FEC_NONE = 0, 3271 EFX_PHY_FEC_BASER, 3272 EFX_PHY_FEC_RS 3273} efx_phy_fec_type_t; 3274 3275extern __checkReturn efx_rc_t 3276efx_phy_fec_type_get( 3277 __in efx_nic_t *enp, 3278 __out efx_phy_fec_type_t *typep); 3279 3280typedef struct efx_phy_link_state_s { 3281 uint32_t epls_adv_cap_mask; 3282 uint32_t epls_lp_cap_mask; 3283 uint32_t epls_ld_cap_mask; 3284 unsigned int epls_fcntl; 3285 efx_phy_fec_type_t epls_fec; 3286 efx_link_mode_t epls_link_mode; 3287} efx_phy_link_state_t; 3288 3289extern __checkReturn efx_rc_t 3290efx_phy_link_state_get( 3291 __in efx_nic_t *enp, 3292 __out efx_phy_link_state_t *eplsp); 3293 3294#ifdef __cplusplus 3295} 3296#endif 3297 3298#endif /* _SYS_EFX_H */ 3299