1/*-
2 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#ifndef R12A_RX_DESC_H
28#define R12A_RX_DESC_H
29
30#include <dev/rtwn/rtl8192c/r92c_rx_desc.h>
31
32/* Rx MAC descriptor defines (chip-specific). */
33/* Rx dword 1 */
34#define R12A_RXDW1_AMSDU	0x00002000
35#define R12A_RXDW1_AMPDU	0x00008000
36#define R12A_RXDW1_CKSUM_ERR	0x00100000
37#define R12A_RXDW1_IPV6		0x00200000
38#define R12A_RXDW1_UDP		0x00400000
39#define R12A_RXDW1_CKSUM	0x00800000
40/* Rx dword 2 */
41#define R12A_RXDW2_RPT_C2H	0x10000000
42/* Rx dword 3 */
43#define R12A_RXDW3_RATE_M	0x0000007f
44#define R12A_RXDW3_RATE_S	0
45/* Rx dword 4 */
46#define R12A_RXDW4_SPLCP	0x00000001
47#define R12A_RXDW4_LDPC		0x00000002
48#define R12A_RXDW4_STBC		0x00000004
49#define R12A_RXDW4_BW_M		0x00000030
50#define R12A_RXDW4_BW_S		4
51#define R12A_RXDW4_BW20		0
52#define R12A_RXDW4_BW40		1
53#define R12A_RXDW4_BW80		2
54#define R12A_RXDW4_BW160	3
55
56/* Rx PHY descriptor. */
57struct r12a_rx_phystat {
58	uint8_t		gain_trsw[2];
59	uint16_t	phyw1;
60#define R12A_PHYW1_CHAN_M	0x03ff
61#define R12A_PHYW1_CHAN_S	0
62#define R12A_PHYW1_CHAN_EXT_M	0x3c00
63#define R12A_PHYW1_CHAN_EXT_S	10
64#define R12A_PHYW1_RFMOD_M	0xc000
65#define R12A_PHYW1_RFMOD_S	14
66
67	uint8_t		pwdb_all;
68	uint8_t		cfosho[4];
69	uint8_t		cfotail[4];
70	uint8_t		rxevm[2];
71	uint8_t		rxsnr[2];
72	uint8_t		pcts_msk_rpt[2];
73	uint8_t		pdsnr[2];
74	uint8_t		csi_current[2];
75	uint8_t		rx_gain_c;
76	uint8_t		rx_gain_d;
77	uint8_t		sigevm;
78	uint16_t	phyw13;
79#define R12A_PHYW13_ANTIDX_A_M	0x0700
80#define R12A_PHYW13_ANTIDX_A_S	8
81#define R12A_PHYW13_ANTIDX_B_M	0x3800
82#define R12A_PHYW13_ANTIDX_B_S	11
83} __packed;
84
85#endif	/* R12A_RX_DESC_H */
86