1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2020 Henri Hennebert <hlh@restart.be> 7 * All rights reserved. 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#ifndef _RTSXREG_H_ 27#define _RTSXREG_H_ 28 29/* Host command buffer control register. */ 30#define RTSX_HCBAR 0x00 31#define RTSX_HCBCTLR 0x04 32#define RTSX_START_CMD (1U << 31) 33#define RTSX_HW_AUTO_RSP (1U << 30) 34#define RTSX_STOP_CMD (1U << 28) 35 36/* Host data buffer control register. */ 37#define RTSX_HDBAR 0x08 38#define RTSX_HDBCTLR 0x0C 39#define RTSX_TRIG_DMA (1U << 31) 40#define RTSX_DMA_READ (1U << 29) 41#define RTSX_STOP_DMA (1U << 28) 42#define RTSX_ADMA_MODE (2U << 26) 43 44/* Interrupt pending register. */ 45#define RTSX_BIPR 0x14 46#define RTSX_CMD_DONE_INT (1U << 31) 47#define RTSX_DATA_DONE_INT (1U << 30) 48#define RTSX_TRANS_OK_INT (1U << 29) 49#define RTSX_TRANS_FAIL_INT (1U << 28) 50#define RTSX_XD_INT (1U << 27) 51#define RTSX_MS_INT (1U << 26) 52#define RTSX_SD_INT (1U << 25) 53#define RTSX_DELINK_INT (1U << 24) 54#define RTSX_SD_WRITE_PROTECT (1U << 19) 55#define RTSX_XD_EXIST (1U << 18) 56#define RTSX_MS_EXIST (1U << 17) 57#define RTSX_SD_EXIST (1U << 16) 58#define RTSX_CARD_EXIST (RTSX_XD_EXIST|RTSX_MS_EXIST|RTSX_SD_EXIST) 59#define RTSX_CARD_INT (RTSX_XD_INT|RTSX_MS_INT|RTSX_SD_INT) 60 61/* Chip register access. */ 62#define RTSX_HAIMR 0x10 63#define RTSX_HAIMR_WRITE 0x40000000 64#define RTSX_HAIMR_BUSY 0x80000000 65 66/* Interrupt enable register. */ 67#define RTSX_BIER 0x18 68#define RTSX_CMD_DONE_INT_EN (1U << 31) 69#define RTSX_DATA_DONE_INT_EN (1U << 30) 70#define RTSX_TRANS_OK_INT_EN (1U << 29) 71#define RTSX_TRANS_FAIL_INT_EN (1U << 28) 72#define RTSX_XD_INT_EN (1U << 27) 73#define RTSX_MS_INT_EN (1U << 26) 74#define RTSX_SD_INT_EN (1U << 25) 75#define RTSX_GPIO0_INT_EN (1U << 24) 76#define RTSX_MS_OC_INT_EN (1U << 23) 77#define RTSX_SD_OC_INT_EN (1U << 22) 78 79/* Power on/off. */ 80#define RTSX_FPDCTL 0xFC00 81#define RTSX_SSC_POWER_DOWN 0x01 82#define RTSX_SD_OC_POWER_DOWN 0x02 83#define RTSX_MS_OC_POWER_DOWN 0x04 84#define RTSX_ALL_POWER_DOWN 0x07 85#define RTSX_OC_POWER_DOWN 0x06 86 87/* Card power control register. */ 88#define RTSX_CARD_PWR_CTL 0xFD50 89#define RTSX_SD_PWR_ON 0x00 90#define RTSX_SD_PARTIAL_PWR_ON 0x01 91#define RTSX_SD_PWR_OFF 0x03 92#define RTSX_SD_PWR_MASK 0x03 93 94#define RTSX_PMOS_STRG_MASK 0x10 95#define RTSX_PMOS_STRG_400mA 0x00 96#define RTSX_PMOS_STRG_800mA 0x10 97 98#define RTSX_BPP_POWER_MASK 0x0F 99#define RTSX_BPP_POWER_OFF 0x0F 100#define RTSX_BPP_POWER_5_PERCENT_ON 0x0E 101#define RTSX_BPP_POWER_10_PERCENT_ON 0x0C 102#define RTSX_BPP_POWER_15_PERCENT_ON 0x08 103#define RTSX_BPP_POWER_ON 0x00 104 105#define RTSX_MS_PWR_OFF 0x0C 106#define RTSX_MS_PWR_ON 0x00 107#define RTSX_MS_PARTIAL_PWR_ON 0x04 108 109#define RTSX_RTL8411B_PACKAGE 0xFD51 110#define RTSX_RTL8411B_QFN48 0x02 111 112#define RTSX_CARD_SHARE_MODE 0xFD52 113#define RTSX_CARD_SHARE_MASK 0x0F 114#define RTSX_CARD_SHARE_48_XD 0x02 115#define RTSX_CARD_SHARE_48_SD 0x04 116#define RTSX_CARD_SHARE_48_MS 0x08 117 118#define RTSX_CARD_DRIVE_SEL 0xFD53 119#define RTSX_MS_DRIVE_8mA (0x01 << 6) 120#define RTSX_MMC_DRIVE_8mA (0x01 << 4) 121#define RTSX_XD_DRIVE_8mA (0x01 << 2) 122#define RTSX_GPIO_DRIVE_8mA 0x01 123#define RTSX_CARD_DRIVE_DEFAULT (RTSX_MS_DRIVE_8mA | RTSX_GPIO_DRIVE_8mA) 124#define RTSX_RTS5209_CARD_DRIVE_DEFAULT (RTSX_MS_DRIVE_8mA | RTSX_MMC_DRIVE_8mA | \ 125 RTSX_XD_DRIVE_8mA | RTSX_GPIO_DRIVE_8mA) 126#define RTSX_RTL8411_CARD_DRIVE_DEFAULT (RTSX_MS_DRIVE_8mA | RTSX_MMC_DRIVE_8mA | \ 127 RTSX_XD_DRIVE_8mA) 128 129#define RTSX_CARD_STOP 0xFD54 130#define RTSX_SPI_STOP 0x01 131#define RTSX_XD_STOP 0x02 132#define RTSX_SD_STOP 0x04 133#define RTSX_MS_STOP 0x08 134#define RTSX_SPI_CLR_ERR 0x10 135#define RTSX_XD_CLR_ERR 0x20 136#define RTSX_SD_CLR_ERR 0x40 137#define RTSX_MS_CLR_ERR 0x80 138#define RTSX_ALL_STOP 0x0F 139#define RTSX_ALL_CLR_ERR 0xF0 140 141#define RTSX_CARD_OE 0xFD55 142#define RTSX_XD_OUTPUT_EN 0x02 143#define RTSX_SD_OUTPUT_EN 0x04 144#define RTSX_MS_OUTPUT_EN 0x08 145#define RTSX_SPI_OUTPUT_EN 0x10 146#define RTSX_CARD_OUTPUT_EN (RTSX_XD_OUTPUT_EN|RTSX_SD_OUTPUT_EN|\ 147 RTSX_MS_OUTPUT_EN) 148 149#define RTSX_CARD_GPIO_DIR 0xFD57 150#define RTSX_CARD_GPIO 0xFD58 151#define RTSX_CARD_GPIO_LED_OFF 0x01 152 153#define RTSX_SD30_CLK_DRIVE_SEL 0xFD5A 154#define RTSX_DRIVER_TYPE_A 0x05 155#define RTSX_DRIVER_TYPE_B 0x03 156#define RTSX_DRIVER_TYPE_C 0x02 157#define RTSX_DRIVER_TYPE_D 0x01 158 159#define RTSX_CARD_DATA_SOURCE 0xFD5B 160#define RTSX_RING_BUFFER 0x00 161#define RTSX_PINGPONG_BUFFER 0x01 162 163#define RTSX_CARD_SELECT 0xFD5C 164#define RTSX_XD_MOD_SEL 0x01 165#define RTSX_SD_MOD_SEL 0x02 166#define RTSX_MS_MOD_SEL 0x03 167#define RTSX_SPI_MOD_SEL 0x04 168 169#define RTSX_SD30_CMD_DRIVE_SEL 0xFD5E /* was 0xFE5E in OpenBSD */ 170#define RTSX_CFG_DRIVER_TYPE_A 0x02 171#define RTSX_CFG_DRIVER_TYPE_B 0x03 172#define RTSX_CFG_DRIVER_TYPE_C 0x01 173#define RTSX_CFG_DRIVER_TYPE_D 0x00 174#define RTSX_SD30_DRIVE_SEL_MASK 0x07 175 176#define RTSX_SD30_DAT_DRIVE_SEL 0xFD5F 177 178/* Card clock. */ 179#define RTSX_CARD_CLK_EN 0xFD69 180#define RTSX_XD_CLK_EN 0x02 181#define RTSX_SD_CLK_EN 0x04 182#define RTSX_MS_CLK_EN 0x08 183#define RTSX_SPI_CLK_EN 0x10 184#define RTSX_CARD_CLK_EN_ALL (RTSX_XD_CLK_EN|RTSX_SD_CLK_EN|\ 185 RTSX_MS_CLK_EN|RTSX_SPI_CLK_EN) 186 187#define RTSX_SDIO_CTRL 0xFD6B 188#define RTSX_SDIO_BUS_CTRL 0x01 189#define RTSX_SDIO_CD_CTRL 0x02 190 191#define RTSX_CARD_PAD_CTL 0xFD73 192#define RTSX_CD_DISABLE_MASK 0x07 193#define RTSX_CD_AUTO_DISABLE 0x40 194#define RTSX_CD_ENABLE 0x00 195 196/* Internal clock. */ 197#define RTSX_CLK_CTL 0xFC02 198#define RTSX_CHANGE_CLK 0x01 199#define RTSX_CLK_LOW_FREQ 0x01 200 201/* Internal clock divisor values. */ 202#define RTSX_CLK_DIV 0xFC03 203#define RTSX_CLK_DIV_1 0x01 204#define RTSX_CLK_DIV_2 0x02 205#define RTSX_CLK_DIV_4 0x03 206#define RTSX_CLK_DIV_8 0x04 207 208/* Internal clock selection. */ 209#define RTSX_CLK_SEL 0xFC04 210#define RTSX_SSC_80 0 211#define RTSX_SSC_100 1 212#define RTSX_SSC_120 2 213#define RTSX_SSC_150 3 214#define RTSX_SSC_200 4 215 216#define RTSX_SSC_DIV_N_0 0xFC0F 217 218#define RTSX_SSC_CTL1 0xFC11 219#define RTSX_RSTB 0x80 220#define RTSX_SSC_8X_EN 0x40 221#define RTSX_SSC_FIX_FRAC 0x20 222#define RTSX_SSC_SEL_1M 0x00 223#define RTSX_SSC_SEL_2M 0x08 224#define RTSX_SSC_SEL_2M 0x08 225#define RTSX_SSC_SEL_4M 0x10 226#define RTSX_SSC_SEL_8M 0x18 227 228#define RTSX_SSC_CTL2 0xFC12 229#define RTSX_SSC_DEPTH_MASK 0x07 230#define RTSX_SSC_DEPTH_4M 0x01 231#define RTSX_SSC_DEPTH_2M 0x02 232#define RTSX_SSC_DEPTH_1M 0x03 233#define RTSX_SSC_DEPTH_500K 0x04 234#define RTSX_SSC_DEPTH_250K 0x05 235 236/* RC oscillator, default is 2M */ 237#define RTSX_RCCTL 0xFC14 238#define RTSX_RCCTL_F_400K 0x00 239#define RTSX_RCCTL_F_2M 0x01 240 241/* RTS5229-only. */ 242#define RTSX_OLT_LED_CTL 0xFC1E 243#define RTSX_OLT_LED_PERIOD 0x02 244#define RTSX_OLT_LED_AUTOBLINK 0x08 245 246#define RTSX_LDO_CTL 0xFC1E 247#define RTSX_BPP_ASIC_3V3 0x07 248#define RTSX_BPP_ASIC_MASK 0x07 249#define RTSX_BPP_PAD_3V3 0x04 250#define RTSX_BPP_PAD_1V8 0x00 251#define RTSX_BPP_PAD_MASK 0x04 252#define RTSX_BPP_LDO_POWB 0x03 253#define RTSX_BPP_LDO_ON 0x00 254#define RTSX_BPP_LDO_SUSPEND 0x02 255#define RTSX_BPP_LDO_OFF 0x03 256#define RTSX_BPP_SHIFT_8402 5 257#define RTSX_BPP_SHIFT_8411 4 258 259#define RTSX_GPIO_CTL 0xFC1F 260#define RTSX_GPIO_LED_ON 0x02 261 262#define RTSX_SD_VPCLK0_CTL 0xFC2A 263#define RTSX_SD_VPCLK1_CTL 0xFC2B 264#define RTSX_PHASE_SELECT_MASK 0x1F 265#define RTSX_PHASE_NOT_RESET 0x40 266 267/* Host controller commands. */ 268#define RTSX_READ_REG_CMD 0 269#define RTSX_WRITE_REG_CMD 1 270#define RTSX_CHECK_REG_CMD 2 271 272#define RTSX_OCPCTL 0xFC15 273#define RTSX_OCPSTAT 0xFC16 274#define RTSX_OCPGLITCH 0xFC17 275#define RTSX_OCPPARA1 0xFC18 276#define RTSX_OCPPARA2 0xFC19 277 278/* FPGA */ 279#define RTSX_FPGA_PULL_CTL 0xFC1D 280#define RTSX_FPGA_MS_PULL_CTL_BIT 0x10 281#define RTSX_FPGA_SD_PULL_CTL_BIT 0x08 282 283/* Clock source configuration register. */ 284#define RTSX_CARD_CLK_SOURCE 0xFC2E 285#define RTSX_CRC_FIX_CLK (0x00 << 0) 286#define RTSX_CRC_VAR_CLK0 (0x01 << 0) 287#define RTSX_CRC_VAR_CLK1 (0x02 << 0) 288#define RTSX_SD30_FIX_CLK (0x00 << 2) 289#define RTSX_SD30_VAR_CLK0 (0x01 << 2) 290#define RTSX_SD30_VAR_CLK1 (0x02 << 2) 291#define RTSX_SAMPLE_FIX_CLK (0x00 << 4) 292#define RTSX_SAMPLE_VAR_CLK0 (0x01 << 4) 293#define RTSX_SAMPLE_VAR_CLK1 (0x02 << 4) 294 295 296/* ASIC */ 297#define RTSX_CARD_PULL_CTL1 0xFD60 298#define RTSX_CARD_PULL_CTL2 0xFD61 299#define RTSX_CARD_PULL_CTL3 0xFD62 300#define RTSX_CARD_PULL_CTL4 0xFD63 301#define RTSX_CARD_PULL_CTL5 0xFD64 302#define RTSX_CARD_PULL_CTL6 0xFD65 303 304#define RTSX_PULL_CTL_DISABLE12 0x55 305#define RTSX_PULL_CTL_DISABLE3 0xD5 306#define RTSX_PULL_CTL_DISABLE3_TYPE_C 0xE5 307#define RTSX_PULL_CTL_ENABLE12 0xAA 308#define RTSX_PULL_CTL_ENABLE3 0xE9 309#define RTSX_PULL_CTL_ENABLE3_TYPE_C 0xD9 310 311/* SD configuration register 1 (clock divider, bus mode and width). */ 312#define RTSX_SD_CFG1 0xFDA0 313#define RTSX_CLK_DIVIDE_0 0x00 314#define RTSX_CLK_DIVIDE_128 0x80 315#define RTSX_CLK_DIVIDE_256 0xC0 316#define RTSX_CLK_DIVIDE_MASK 0xC0 317#define RTSX_SD20_MODE 0x00 318#define RTSX_SDDDR_MODE 0x04 319#define RTSX_SD30_MODE 0x08 320#define RTSX_SD_MODE_MASK 0x0C 321#define RTSX_BUS_WIDTH_1 0x00 322#define RTSX_BUS_WIDTH_4 0x01 323#define RTSX_BUS_WIDTH_8 0x02 324#define RTSX_SD_ASYNC_FIFO_NOT_RST 0x10 325#define RTSX_BUS_WIDTH_MASK 0x03 326 327/* SD configuration register 2 (SD command response flags). */ 328#define RTSX_SD_CFG2 0xFDA1 329#define RTSX_SD_CALCULATE_CRC7 0x00 330#define RTSX_SD_NO_CALCULATE_CRC7 0x80 331#define RTSX_SD_CHECK_CRC16 0x00 332#define RTSX_SD_NO_CHECK_CRC16 0x40 333#define RTSX_SD_NO_CHECK_WAIT_CRC_TO 0x20 334#define RTSX_SD_WAIT_BUSY_END 0x08 335#define RTSX_SD_NO_WAIT_BUSY_END 0x00 336#define RTSX_SD_CHECK_CRC7 0x00 337#define RTSX_SD_NO_CHECK_CRC7 0x04 338#define RTSX_SD_RSP_LEN_0 0x00 339#define RTSX_SD_RSP_LEN_6 0x01 340#define RTSX_SD_RSP_LEN_17 0x02 341/* SD command response types. */ 342#define RTSX_SD_RSP_TYPE_R0 0x04 343#define RTSX_SD_RSP_TYPE_R1 0x01 344#define RTSX_SD_RSP_TYPE_R1B 0x09 345#define RTSX_SD_RSP_TYPE_R2 0x02 346#define RTSX_SD_RSP_TYPE_R3 0x05 347#define RTSX_SD_RSP_TYPE_R4 0x05 348#define RTSX_SD_RSP_TYPE_R5 0x01 349#define RTSX_SD_RSP_TYPE_R6 0x01 350#define RTSX_SD_RSP_TYPE_R7 0x01 351 352#define RTSX_SD_CFG3 0xFDA2 353#define RTSX_SD30_CLK_END_EN 0x10 354#define RTSX_SD_RSP_80CLK_TIMEOUT_EN 0x01 355 356#define RTSX_SD_STAT1 0xFDA3 357#define RTSX_SD_CRC7_ERR 0x80 358#define RTSX_SD_CRC16_ERR 0x40 359#define RTSX_SD_CRC_WRITE_ERR 0x20 360#define RTSX_SD_CRC_WRITE_ERR_MASK 0x1C 361#define RTSX_GET_CRC_TIME_OUT 0x02 362#define RTSX_SD_TUNING_COMPARE_ERR 0x01 363 364#define RTSX_SD_STAT2 0xFDA4 365#define RTSX_SD_RSP_80CLK_TIMEOUT 0x01 366 367#define RTSX_SD_CRC_ERR (RTSX_SD_CRC7_ERR|RTSX_SD_CRC16_ERR|RTSX_SD_CRC_WRITE_ERR) 368 369/* SD bus status register. */ 370#define RTSX_SD_BUS_STAT 0xFDA5 371#define RTSX_SD_CLK_TOGGLE_EN 0x80 372#define RTSX_SD_CLK_FORCE_STOP 0x40 373#define RTSX_SD_DAT3_STATUS 0x10 374#define RTSX_SD_DAT2_STATUS 0x08 375#define RTSX_SD_DAT1_STATUS 0x04 376#define RTSX_SD_DAT0_STATUS 0x02 377#define RTSX_SD_CMD_STATUS 0x01 378 379#define RTSX_SD_PAD_CTL 0xFDA6 380#define RTSX_SD_IO_USING_1V8 0x80 381 382/* Sample point control register. */ 383#define RTSX_SD_SAMPLE_POINT_CTL 0xFDA7 384#define RTSX_DDR_FIX_RX_DAT 0x00 385#define RTSX_DDR_VAR_RX_DAT 0x80 386#define RTSX_DDR_FIX_RX_DAT_EDGE 0x00 387#define RTSX_DDR_FIX_RX_DAT_14_DELAY 0x40 388#define RTSX_DDR_FIX_RX_CMD 0x00 389#define RTSX_DDR_VAR_RX_CMD 0x20 390#define RTSX_DDR_FIX_RX_CMD_POS_EDGE 0x00 391#define RTSX_DDR_FIX_RX_CMD_14_DELAY 0x10 392#define RTSX_SD20_RX_POS_EDGE 0x00 393#define RTSX_SD20_RX_14_DELAY 0x08 394#define RTSX_SD20_RX_SEL_MASK 0x08 395 396#define RTSX_SD_PUSH_POINT_CTL 0xFDA8 397#define RTSX_SD20_TX_NEG_EDGE 0x00 398#define RTSX_SD20_TX_SEL_MASK 0x10 399#define RTSX_SD20_TX_14_AHEAD 0x10 400 401#define RTSX_SD_CMD0 0xFDA9 402#define RTSX_SD_CMD_START 0x40 403#define RTSX_SD_CMD1 0xFDAA 404#define RTSX_SD_CMD2 0xFDAB 405#define RTSX_SD_CMD3 0xFDAC 406#define RTSX_SD_CMD4 0xFDAD 407 408#define RTSX_SD_CMD5 0xFDAE 409#define RTSX_SD_BYTE_CNT_L 0xFDAF 410#define RTSX_SD_BYTE_CNT_H 0xFDB0 411#define RTSX_SD_BLOCK_CNT_L 0xFDB1 412#define RTSX_SD_BLOCK_CNT_H 0xFDB2 413 414/* 415 * Transfer modes. 416 */ 417#define RTSX_SD_TRANSFER 0xFDB3 418 419/* Write one or two bytes from SD_CMD2 and SD_CMD3 to the card. */ 420#define RTSX_TM_NORMAL_WRITE 0x00 421 422/* Write (SD_BYTE_CNT * SD_BLOCK_COUNTS) bytes from ring buffer to card. */ 423#define RTSX_TM_AUTO_WRITE3 0x01 424 425/* Like AUTO_WRITE3, plus automatically send CMD 12 when done. 426 * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 427#define RTSX_TM_AUTO_WRITE4 0x02 428 429/* Read (SD_BYTE_CNT * SD_BLOCK_CNT) bytes from card into ring buffer. */ 430#define RTSX_TM_AUTO_READ3 0x05 431 432/* Like AUTO_READ3, plus automatically send CMD 12 when done. 433 * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 434#define RTSX_TM_AUTO_READ4 0x06 435 436/* Send an SD command described in SD_CMD{0,1,2,3,4} to the card and put 437 * the response into SD_CMD{0,1,2,3,4}. Long responses (17 byte) are put 438 * into ping-pong buffer 2 instead. */ 439#define RTSX_TM_CMD_RSP 0x08 440 441/* Send write command, get response from the card, write data from ring 442 * buffer to card, and send CMD 12 when done. 443 * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 444#define RTSX_TM_AUTO_WRITE1 0x09 445 446/* Like AUTO_WRITE1 except no CMD 12 is sent. */ 447#define RTSX_TM_AUTO_WRITE2 0x0A 448 449/* Send read command, read up to 512 bytes (SD_BYTE_CNT * SD_BLOCK_CNT) 450 * from the card into the ring buffer or ping-pong buffer 2. */ 451#define RTSX_TM_NORMAL_READ 0x0C 452 453/* Same as WRITE1, except data is read from the card to the ring buffer. */ 454#define RTSX_TM_AUTO_READ1 0x0D 455 456/* Same as WRITE2, except data is read from the card to the ring buffer. */ 457#define RTSX_TM_AUTO_READ2 0x0E 458 459/* Send CMD 19 and receive response and tuning pattern from card and 460 * report the result. */ 461#define RTSX_TM_AUTO_TUNING 0x0F 462 463/* transfer control */ 464#define RTSX_SD_TRANSFER_START 0x80 465#define RTSX_SD_TRANSFER_END 0x40 466#define RTSX_SD_STAT_IDLE 0x20 467#define RTSX_SD_TRANSFER_ERR 0x10 468 469#define RTSX_SD_CMD_STATE 0xFDB5 470#define RTSX_SD_CMD_IDLE 0x80 471 472#define RTSX_SD_DATA_STATE 0xFDB6 473#define RTSX_SD_DATA_IDLE 0x80 474 475#define RTSX_REG_SD_STOP_SDCLK_CFG 0xFDB8 476#define RTSX_SD30_CLK_STOP_CFG_EN 0x04 477#define RTSX_SD30_CLK_STOP_CFG0 0x01 478#define RTSX_SD30_CLK_STOP_CFG1 0x02 479 480#define RTSX_REG_PRE_RW_MODE 0xFD70 481#define RTSX_EN_INFINITE_MODE 0x01 482 483/* ping-pong buffer 2 */ 484#define RTSX_PPBUF_BASE2 0xFA00 485#define RTSX_PPBUF_SIZE 256 486 487#define RTSX_SUPPORTED_VOLTAGE (MMC_OCR_300_310|MMC_OCR_310_320|\ 488 MMC_OCR_320_330|MMC_OCR_330_340) 489 490#define RTSX_CFG_PCI 0x1C 491#define RTSX_CFG_ASIC 0x10 492 493#define RTSX_IRQEN0 0xFE20 494#define RTSX_LINK_DOWN_INT_EN 0x10 495#define RTSX_LINK_READY_INT_EN 0x20 496#define RTSX_SUSPEND_INT_EN 0x40 497#define RTSX_DMA_DONE_INT_EN 0x80 498 499#define RTSX_IRQSTAT0 0xFE21 500#define RTSX_LINK_DOWN_INT 0x10 501#define RTSX_LINK_READY_INT 0x20 502#define RTSX_SUSPEND_INT 0x40 503#define RTSX_DMA_DONE_INT 0x80 504 505#define RTSX_DMATC0 0xFE28 506#define RTSX_DMATC1 0xFE29 507#define RTSX_DMATC2 0xFE2A 508#define RTSX_DMATC3 0xFE2B 509 510#define RTSX_DMACTL 0xFE2C 511#define RTSX_DMA_EN 0x01 512#define RTSX_DMA_DIR 0x02 513#define RTSX_DMA_DIR_TO_CARD 0x00 514#define RTSX_DMA_DIR_FROM_CARD 0x02 515#define RTSX_DMA_BUSY 0x04 516#define RTSX_DMA_RST 0x80 517#define RTSX_DMA_128 (0 << 4) 518#define RTSX_DMA_256 (1 << 4) 519#define RTSX_DMA_512 (2 << 4) 520#define RTSX_DMA_1024 (3 << 4) 521#define RTSX_DMA_PACK_SIZE_MASK 0x30 522 523#define RTSX_RBCTL 0xFE34 524#define RTSX_RB_FLUSH 0x80 525#define RTSX_U_AUTO_DMA_EN_MASK 0x20 526#define RTSX_U_AUTO_DMA_DISABLE 0x00 527 528#define RTSX_CFGADDR0 0xFE35 529#define RTSX_CFGADDR1 0xFE36 530#define RTSX_CFGDATA0 0xFE37 531#define RTSX_CFGDATA1 0xFE38 532#define RTSX_CFGDATA2 0xFE39 533#define RTSX_CFGDATA3 0xFE3A 534#define RTSX_CFGRWCTL 0xFE3B 535#define RTSX_CFG_WRITE_DATA0 0x01 536#define RTSX_CFG_WRITE_DATA1 0x02 537#define RTSX_CFG_WRITE_DATA2 0x04 538#define RTSX_CFG_WRITE_DATA3 0x08 539#define RTSX_CFG_BUSY 0x80 540 541#define RTSX_LTR_CTL 0xFE4A 542 543#define RTSX_OBFF_CFG 0xFE4C 544#define RTSX_OBFF_EN_MASK 0x03 545#define RTSX_OBFF_DISABLE 0x00 546#define RTSX_OBFF_ENABLE 0x03 547 548#define RTSX_SDIOCFG_REG 0x724 549#define RTSX_SDIOCFG_NO_BYPASS_SDIO 0x02 550#define RTSX_SDIOCFG_HAVE_SDIO 0x04 551#define RTSX_SDIOCFG_SINGLE_LUN 0x08 552#define RTSX_SDIOCFG_SDIO_ONLY 0x80 553 554#define RTSX_HOST_SLEEP_STATE 0xFE60 555#define RTSX_HOST_ENTER_S1 0x01 556#define RTSX_HOST_ENTER_S3 0x02 557 558#define RTSX_SDIO_CFG 0xFE70 559#define RTSX_SDIO_BUS_AUTO_SWITCH 0x10 560 561#define RTSX_NFTS_TX_CTRL 0xFE72 562#define RTSX_INT_READ_CLR 0x02 563 564#define RTSX_PWR_GATE_CTRL 0xFE75 565#define RTSX_PWR_GATE_EN 0x01 566#define RTSX_LDO3318_PWR_MASK 0x06 567#define RTSX_LDO3318_ON 0x00 568#define RTSX_LDO3318_SUSPEND 0x04 569#define RTSX_LDO3318_OFF 0x06 570#define RTSX_LDO3318_VCC1 0x02 571#define RTSX_LDO3318_VCC2 0x04 572#define RTSX_PWD_SUSPEND_EN 0xFE76 573#define RTSX_LDO_PWR_SEL 0xFE78 574#define RTSX_LDO_PWR_SEL_3V3 0x01 575#define RTSX_LDO_PWR_SEL_DV33 0x03 576 577#define RTSX_PHY_RWCTL 0xFE3C 578#define RTSX_PHY_READ 0x00 579#define RTSX_PHY_WRITE 0x01 580#define RTSX_PHY_BUSY 0x80 581#define RTSX_PHY_DATA0 0xFE3D 582#define RTSX_PHY_DATA1 0xFE3E 583#define RTSX_PHY_ADDR 0xFE3F 584 585#define RTSX_PHY_PCR 0x00 586#define RTSX_PHY_PCR_FORCE_CODE 0xB000 587#define RTSX_PHY_PCR_OOBS_CALI_50 0x0800 588#define RTSX_PHY_PCR_OOBS_VCM_08 0x0200 589#define RTSX_PHY_PCR_OOBS_SEN_90 0x0040 590#define RTSX_PHY_PCR_RSSI_EN 0x0002 591#define RTSX_PHY_PCR_RX10K 0x0001 592 593#define RTSX_PHY_RCR1 0x02 594#define RTSX_PHY_RCR1_ADP_TIME_4 0x0400 595#define RTSX_PHY_RCR1_VCO_COARSE 0x001F 596#define RTSX_PHY_RCR1_INIT_27S 0x0A1F 597 598#define RTSX_PHY_RCR2 0x03 599#define RTSX_PHY_RCR2_EMPHASE_EN 0x8000 600#define RTSX_PHY_RCR2_NADJR 0x4000 601#define RTSX_PHY_RCR2_CDR_SR_2 0x0100 602#define RTSX_PHY_RCR2_FREQSEL_12 0x0040 603#define RTSX_PHY_RCR2_CDR_SC_12P 0x0010 604#define RTSX_PHY_RCR2_CALIB_LATE 0x0002 605#define RTSX_PHY_RCR2_INIT_27S 0xC152 606 607#define RTSX__PHY_ANA03 0x03 608#define RTSX__PHY_ANA03_TIMER_MAX 0x2700 609#define RTSX__PHY_ANA03_OOBS_DEB_EN 0x0040 610#define RTSX__PHY_CMU_DEBUG_EN 0x0008 611 612#define RTSX_PHY_RDR 0x05 613#define RTSX_PHY_RDR_RXDSEL_1_9 0x4000 614#define RTSX_PHY_SSC_AUTO_PWD 0x0600 615 616#define RTSX_PHY_TUNE 0x08 617#define RTSX_PHY_TUNE_TUNEREF_1_0 0x4000 618#define RTSX_PHY_TUNE_VBGSEL_1252 0x0C00 619#define RTSX_PHY_TUNE_SDBUS_33 0x0200 620#define RTSX_PHY_TUNE_TUNED18 0x01C0 621#define RTSX_PHY_TUNE_TUNED12 0X0020 622#define RTSX_PHY_TUNE_TUNEA12 0x0004 623#define RTSX_PHY_TUNE_VOLTAGE_MASK 0xFC3F 624#define RTSX_PHY_TUNE_VOLTAGE_3V3 0x03C0 625#define RTSX_PHY_TUNE_D18_1V8 0x0100 626#define RTSX_PHY_TUNE_D18_1V7 0x0080 627 628#define RTSX_PHY_BPCR 0x0A 629#define RTSX_PHY_BPCR_IBRXSEL 0x0400 630#define RTSX_PHY_BPCR_IBTXSEL 0x0100 631#define RTSX_PHY_BPCR_IB_FILTER 0x0080 632#define RTSX_PHY_BPCR_CMIRROR_EN 0x0040 633 634#define RTSX_PHY_REV 0x19 635#define RTSX_PHY_REV_RESV 0xE000 636#define RTSX_PHY_REV_RXIDLE_LATCHED 0x1000 637#define RTSX_PHY_REV_P1_EN 0x0800 638#define RTSX_PHY_REV_RXIDLE_EN 0x0400 639#define RTSX_PHY_REV_CLKREQ_TX_EN 0x0200 640#define RTSX_PHY_REV_CLKREQ_RX_EN 0x0100 641#define RTSX_PHY_REV_CLKREQ_DT_1_0 0x0040 642#define RTSX_PHY_REV_STOP_CLKRD 0x0020 643#define RTSX_PHY_REV_RX_PWST 0x0008 644#define RTSX_PHY_REV_STOP_CLKWR 0x0004 645 646 647#define RTSX__PHY_REV0 0x19 648#define RTSX__PHY_REV0_FILTER_OUT 0x3800 649#define RTSX__PHY_REV0_CDR_BYPASS_PFD 0x0100 650#define RTSX__PHY_REV0_CDR_RX_IDLE_BYPASS 0x0002 651 652#define RTSX_PHY_FLD0 0x1A 653#define RTSX_PHY_FLD0_INIT_27S 0x2546 654 655#define RTSX_PHY_FLD3 0x1D 656#define RTSX_PHY_FLD3_TIMER_4 0x0800 657#define RTSX_PHY_FLD3_TIMER_6 0x0020 658#define RTSX_PHY_FLD3_RXDELINK 0x0004 659#define RTSX_PHY_FLD3_INIT_27S 0x0004 660 661#define RTSX__PHY_FLD0 0x1D 662#define RTSX__PHY_FLD0_CLK_REQ_20C 0x8000 663#define RTSX__PHY_FLD0_RX_IDLE_EN 0x1000 664#define RTSX__PHY_FLD0_BIT_ERR_RSTN 0x0800 665#define RTSX__PHY_FLD0_BER_COUNT 0x01E0 666#define RTSX__PHY_FLD0_BER_TIMER 0x001E 667#define RTSX__PHY_FLD0_CHECK_EN 0x0001 668 669#define RTSX_PHY_FLD4 0x1E 670#define RTSX_PHY_FLD4_FLDEN_SEL 0x4000 671#define RTSX_PHY_FLD4_REQ_REF 0x2000 672#define RTSX_PHY_FLD4_RXAMP_OFF 0x1000 673#define RTSX_PHY_FLD4_REQ_ADDA 0x0800 674#define RTSX_PHY_FLD4_BER_COUNT 0x00E0 675#define RTSX_PHY_FLD4_BER_TIMER 0x000A 676#define RTSX_PHY_FLD4_BER_CHK_EN 0x0001 677#define RTSX_PHY_FLD4_INIT_27S 0x5C7F 678 679#define RTSX_CARD_AUTO_BLINK 0xFD56 680#define RTSX_LED_BLINK_EN 0x08 681#define RTSX_LED_BLINK_SPEED 0x05 682 683#define RTSX_PCLK_CTL 0xFE55 684#define RTSX_PCLK_MODE_SEL 0x20 685 686#define RTSX_PME_FORCE_CTL 0xFE56 687 688#define RTSX_ASPM_FORCE_CTL 0xFE57 689#define RTSX_ASPM_FORCE_MASK 0x3F 690#define RTSX_FORCE_ASPM_NO_ASPM 0x00 691 692#define RTSX_PM_CLK_FORCE_CTL 0xFE58 693#define RTSX_CLK_PM_EN 0x01 694 695#define RTSX_FUNC_FORCE_CTL 0xFE59 696#define RTSX_FUNC_FORCE_UPME_XMT_DBG 0x02 697 698#define RTSX_CHANGE_LINK_STATE 0xFE5B 699#define RTSX_CD_RST_CORE_EN 0x01 700#define RTSX_FORCE_RST_CORE_EN 0x02 701#define RTSX_NON_STICKY_RST_N_DBG 0x08 702#define RTSX_MAC_PHY_RST_N_DBG 0x10 703 704#define RTSX_PERST_GLITCH_WIDTH 0xFE5C 705 706#define RTSX_EFUSE_CONTENT 0xFE5F 707 708#define RTSX_PM_EVENT_DEBUG 0xFE71 709#define RTSX_PME_DEBUG_0 0x08 710 711#define RTSX_L1SUB_CONFIG1 0xFE8D 712#define RTSX_AUX_CLK_ACTIVE_SEL_MASK 0x01 713#define RTSX_MAC_CKSW_DONE 0x00 714 715#define RTSX_L1SUB_CONFIG2 0xFE8E 716#define RTSX_L1SUB_AUTO_CFG 0x02 717 718#define RTSX_L1SUB_CONFIG3 0xFE8F 719 720#define RTSX_DUMMY_REG 0xFE90 721 722#define RTSX_REG_VREF 0xFE97 723#define RTSX_PWD_SUSPND_EN 0x10 724 725#define RTSX_RTS5260_DMA_RST_CTL_0 0xFEBF 726#define RTSX_RTS5260_DMA_RST 0x80 727#define RTSX_RTS5260_ADMA3_RST 0x40 728 729#define RTSX_PETXCFG 0xFF03 /* was 0xFE49 in OpenBSD */ 730#define RTSX_FORCE_CLKREQ_DELINK_MASK 0x80 731#define RTSX_FORCE_CLKREQ_LOW 0x80 732 733#define RTSX_RREF_CFG 0xFF6C 734#define RTSX_RREF_VBGSEL_MASK 0x38 735#define RTSX_RREF_VBGSEL_1V25 0x28 736 737#define RTSX_PM_CTRL3 0xFF46 738#define RTSX_RTS522A_PM_CTRL3 0xFF7E 739#define RTSX_D3_DELINK_MODE_EN 0x10 740#define RTSX_PM_WAKE_EN 0x01 741 742#define RTSX_OOBS_CONFIG 0xFF6E 743#define RTSX_OOBS_AUTOK_DIS 0x80 744#define RTSX_OOBS_VAL_MASK 0x1F 745 746#define RTSX_LDO_DV18_CFG 0xFF70 747#define RTSX_DV331812_MASK 0x70 748#define RTSX_DV331812_33 0x70 749 750#define RTSX_LDO_CONFIG2 0xFF71 751#define RTSX_LDO_D3318_MASK 0x07 752#define RTSX_LDO_D3318_33V 0x07 753#define RTSX_LDO_D3318_18V 0x02 754#define RTSX_DV331812_VDD1 0x04 755#define RTSX_DV331812_POWERON 0x08 756#define RTSX_DV331812_POWEROFF 0x00 757 758#define RTSX_LDO_VCC_CFG0 0xFF72 759#define RTSX_LDO_VCC_LMTVTH_MASK 0x30 760#define RTSX_LDO_VCC_LMTVTH_2A 0x10 761#define RTSX_RTS5260_DVCC_TUNE_MASK 0x70 762#define RTSX_RTS5260_DVCC_33 0x70 763 764#define RTSX_LDO_VCC_CFG1 0xFF73 765#define RTSX_LDO_VCC_REF_TUNE_MASK 0x30 766#define RTSX_LDO_VCC_REF_1V2 0x20 767#define RTSX_LDO_VCC_TUNE_MASK 0x07 768#define RTSX_LDO_VCC_1V8 0x04 769#define RTSX_LDO_VCC_3V3 0x07 770#define RTSX_LDO_VCC_LMT_EN 0x08 771/*RTS5260*/ 772#define RTSX_LDO_POW_SDVDD1_MASK 0x08 773#define RTSX_LDO_POW_SDVDD1_ON 0x08 774#define RTSX_LDO_POW_SDVDD1_OFF 0x00 775 776#define RTSX_RTS5260_DVCC_CTRL 0xFF73 777#define RTSX_RTS5260_DVCC_OCP_EN (0x01 << 7) 778#define RTSX_RTS5260_DVCC_OCP_THD_MASK (0x07 << 4) 779#define RTSX_RTS5260_DVCC_POWERON (0x01 << 3) 780#define RTSX_RTS5260_DVCC_OCP_CL_EN (0x01 << 2) 781 782#define RTSX_LDO_VIO_CFG 0xFF75 783#define RTSX_LDO_VIO_TUNE_MASK 0x07 784#define RTSX_LDO_VIO_1V7 0x03 785 786#define RTSX_LDO_DV12S_CFG 0xFF76 787#define RTSX_LDO_D12_TUNE_MASK 0x07 788#define RTSX_LDO_D12_TUNE_DF 0x04 789 790#define RTSX_LDO_AV12S_CFG 0xFF77 791#define RTSX_LDO_AV12S_TUNE_MASK 0x07 792#define RTSX_LDO_AV12S_TUNE_DF 0x04 793 794#define RTSX_SG_INT 0x04 795#define RTSX_SG_END 0x02 796#define RTSX_SG_VALID 0x01 797 798#define RTSX_SG_NO_OP 0x00 799#define RTSX_SG_TRANS_DATA (0x02 << 4) 800#define RTSX_SG_LINK_DESC (0x03 << 4) 801 802#define RTSX_IC_VERSION_A 0x00 803#define RTSX_IC_VERSION_B 0x01 804#define RTSX_IC_VERSION_C 0x02 805#define RTSX_IC_VERSION_D 0x03 806 807#define RTSX_RTS5260_AUTOLOAD_CFG4 0xFF7F 808#define RTSX_RTS5260_MIMO_DISABLE 0x8A 809 810#define RTSX_PCR_SETTING_REG1 0x724 811#define RTSX_PCR_SETTING_REG2 0x814 812#define RTSX_PCR_SETTING_REG3 0x747 813 814#define RTSX_RX_PHASE_MAX 32 815#define RTSX_RX_TUNING_CNT 3 816#endif 817