1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013-2014 Qlogic Corporation
5 * All rights reserved.
6 *
7 *  Redistribution and use in source and binary forms, with or without
8 *  modification, are permitted provided that the following conditions
9 *  are met:
10 *
11 *  1. Redistributions of source code must retain the above copyright
12 *     notice, this list of conditions and the following disclaimer.
13 *  2. Redistributions in binary form must reproduce the above copyright
14 *     notice, this list of conditions and the following disclaimer in the
15 *     documentation and/or other materials provided with the distribution.
16 *
17 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 *  POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * File: qls_def.h
32 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
33 */
34
35#ifndef _QLS_DEF_H_
36#define _QLS_DEF_H_
37
38/*
39 * structure encapsulating a DMA buffer
40 */
41struct qla_dma {
42        bus_size_t              alignment;
43        uint32_t                size;
44        void                    *dma_b;
45        bus_addr_t              dma_addr;
46        bus_dmamap_t            dma_map;
47        bus_dma_tag_t           dma_tag;
48};
49typedef struct qla_dma qla_dma_t;
50
51/*
52 * structure encapsulating interrupt vectors
53 */
54struct qla_ivec {
55	uint32_t		cq_idx;
56	void			*ha;
57	struct resource		*irq;
58	void			*handle;
59	int			irq_rid;
60};
61typedef struct qla_ivec qla_ivec_t;
62
63/*
64 * Transmit Related Definitions
65 */
66
67#define MAX_TX_RINGS		1
68#define NUM_TX_DESCRIPTORS	1024
69
70#define QLA_MAX_SEGMENTS	64	/* maximum # of segs in a sg list */
71#define QLA_OAL_BLK_SIZE	(sizeof (q81_txb_desc_t) * QLA_MAX_SEGMENTS)
72
73#define QLA_TX_OALB_TOTAL_SIZE	(NUM_TX_DESCRIPTORS * QLA_OAL_BLK_SIZE)
74
75#define QLA_TX_PRIVATE_BSIZE	((QLA_TX_OALB_TOTAL_SIZE + \
76					PAGE_SIZE + \
77					(PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
78
79#define QLA_MAX_MTU		9000
80#define QLA_STD_FRAME_SIZE	1514
81#define QLA_MAX_TSO_FRAME_SIZE	((64 * 1024 - 1) + 22)
82
83#define QL_FRAME_HDR_SIZE	(ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\
84                sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16)
85
86struct qla_tx_buf {
87	struct mbuf	*m_head;
88	bus_dmamap_t	map;
89
90	/* The number of entries in the OAL is determined by QLA_MAX_SEGMENTS */
91	bus_addr_t      oal_paddr;
92	void		*oal_vaddr;
93};
94typedef struct qla_tx_buf qla_tx_buf_t;
95
96struct qla_tx_ring {
97	volatile struct {
98		uint32_t	wq_dma:1,
99				privb_dma:1;
100	} flags;
101
102	qla_dma_t		privb_dma;
103	qla_dma_t		wq_dma;
104
105	qla_tx_buf_t		tx_buf[NUM_TX_DESCRIPTORS];
106	uint64_t		count;
107
108	struct resource         *wq_db_addr;
109	uint32_t		wq_db_offset;
110
111	q81_tx_cmd_t		*wq_vaddr;
112	bus_addr_t		wq_paddr;
113
114	void			*wq_icb_vaddr;
115	bus_addr_t		wq_icb_paddr;
116
117	uint32_t		*txr_cons_vaddr;
118	bus_addr_t		txr_cons_paddr;
119
120	volatile uint32_t	txr_free; /* # of free entries in tx ring */
121	volatile uint32_t	txr_next; /* # next available tx ring entry */
122	volatile uint32_t	txr_done;
123
124	uint64_t		tx_frames;
125	uint64_t		tx_tso_frames;
126	uint64_t		tx_vlan_frames;
127};
128typedef struct qla_tx_ring qla_tx_ring_t;
129
130/*
131 * Receive Related Definitions
132 */
133
134#define MAX_RX_RINGS		MAX_TX_RINGS
135
136#define NUM_RX_DESCRIPTORS	1024
137#define NUM_CQ_ENTRIES		NUM_RX_DESCRIPTORS
138
139#define QLA_LGB_SIZE		(12 * 1024)
140#define QLA_NUM_LGB_ENTRIES	32
141
142#define QLA_LBQ_SIZE		(QLA_NUM_LGB_ENTRIES * sizeof(q81_bq_addr_e_t))
143
144#define QLA_LGBQ_AND_TABLE_SIZE	\
145	((QLA_LBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
146
147/* Please note that Small Buffer size is determined by max mtu size */
148#define QLA_NUM_SMB_ENTRIES	NUM_RX_DESCRIPTORS
149
150#define QLA_SBQ_SIZE		(QLA_NUM_SMB_ENTRIES * sizeof(q81_bq_addr_e_t))
151
152#define QLA_SMBQ_AND_TABLE_SIZE	\
153	((QLA_SBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
154
155struct qla_rx_buf {
156	struct mbuf	*m_head;
157	bus_dmamap_t	map;
158	bus_addr_t      paddr;
159	void		*next;
160};
161typedef struct qla_rx_buf qla_rx_buf_t;
162
163struct qla_rx_ring {
164	volatile struct {
165		uint32_t	cq_dma:1,
166				lbq_dma:1,
167				sbq_dma:1,
168				lb_dma:1;
169	} flags;
170
171	qla_dma_t		cq_dma;
172	qla_dma_t		lbq_dma;
173	qla_dma_t		sbq_dma;
174	qla_dma_t		lb_dma;
175
176	struct lro_ctrl		lro;
177
178	qla_rx_buf_t		rx_buf[NUM_RX_DESCRIPTORS];
179	qla_rx_buf_t		*rxb_free;
180	uint32_t		rx_free;
181	uint32_t		rx_next;
182
183	uint32_t		cq_db_offset;
184
185	void			*cq_icb_vaddr;
186	bus_addr_t		cq_icb_paddr;
187
188	uint32_t		*cqi_vaddr;
189	bus_addr_t		cqi_paddr;
190
191	void			*cq_base_vaddr;
192	bus_addr_t		cq_base_paddr;
193	uint32_t		cq_next; /* next cq entry to process */
194
195	void			*lbq_addr_tbl_vaddr;
196	bus_addr_t		lbq_addr_tbl_paddr;
197
198	void			*lbq_vaddr;
199	bus_addr_t		lbq_paddr;
200	uint32_t		lbq_next; /* next entry in LBQ to process */
201	uint32_t		lbq_free;/* # of entries in LBQ to arm */
202	uint32_t		lbq_in; /* next entry in LBQ to arm */
203
204	void			*lb_vaddr;
205	bus_addr_t		lb_paddr;
206
207	void			*sbq_addr_tbl_vaddr;
208	bus_addr_t		sbq_addr_tbl_paddr;
209
210	void			*sbq_vaddr;
211	bus_addr_t		sbq_paddr;
212	uint32_t		sbq_next; /* next entry in SBQ to process */
213	uint32_t		sbq_free;/* # of entries in SBQ to arm */
214	uint32_t		sbq_in; /* next entry in SBQ to arm */
215
216	uint64_t		rx_int;
217	uint64_t		rss_int;
218};
219typedef struct qla_rx_ring qla_rx_ring_t;
220
221#define QLA_WATCHDOG_CALLOUT_TICKS	1
222
223/*
224 * Multicast Definitions
225 */
226typedef struct _qla_mcast {
227	uint16_t	rsrvd;
228	uint8_t		addr[6];
229} __packed qla_mcast_t;
230
231/*
232 * Misc. definitions
233 */
234#define QLA_PAGE_SIZE		4096
235
236/*
237 * Adapter structure contains the hardware independent information of the
238 * pci function.
239 */
240struct qla_host {
241        volatile struct {
242                volatile uint32_t
243			mpi_dma			:1,
244			rss_dma			:1,
245			intr_enable		:1,
246			qla_callout_init	:1,
247			qla_watchdog_active	:1,
248			qla_watchdog_exit	:1,
249			qla_watchdog_pause	:1,
250			lro_init		:1,
251			parent_tag		:1,
252			lock_init		:1;
253        } flags;
254
255	volatile uint32_t	hw_init;
256
257	volatile uint32_t	qla_watchdog_exited;
258	volatile uint32_t	qla_watchdog_paused;
259	volatile uint32_t	qla_initiate_recovery;
260
261	device_t		pci_dev;
262
263	uint8_t			pci_func;
264	uint16_t		watchdog_ticks;
265	uint8_t			resvd;
266
267        /* ioctl related */
268        struct cdev             *ioctl_dev;
269
270	/* register mapping */
271	struct resource		*pci_reg;
272	int			reg_rid;
273
274	struct resource		*pci_reg1;
275	int			reg_rid1;
276
277	int			msix_count;
278	qla_ivec_t              irq_vec[MAX_RX_RINGS];
279
280	/* parent dma tag */
281	bus_dma_tag_t           parent_tag;
282
283	/* interface to o.s */
284	if_t ifp;
285
286	struct ifmedia		media;
287	uint16_t		max_frame_size;
288	uint16_t		rsrvd0;
289	uint32_t		msize;
290	int			if_flags;
291
292	/* hardware access lock */
293	struct mtx		hw_lock;
294	volatile uint32_t	hw_lock_held;
295
296	uint32_t		vm_pgsize;
297	/* transmit related */
298	uint32_t		num_tx_rings;
299	qla_tx_ring_t		tx_ring[MAX_TX_RINGS];
300
301	bus_dma_tag_t		tx_tag;
302	struct task		tx_task;
303	struct taskqueue	*tx_tq;
304	struct callout		tx_callout;
305	struct mtx		tx_lock;
306
307	/* receive related */
308	uint32_t		num_rx_rings;
309	qla_rx_ring_t		rx_ring[MAX_RX_RINGS];
310	bus_dma_tag_t		rx_tag;
311
312	/* stats */
313	uint32_t		err_m_getcl;
314	uint32_t		err_m_getjcl;
315	uint32_t		err_tx_dmamap_create;
316	uint32_t		err_tx_dmamap_load;
317	uint32_t		err_tx_defrag;
318
319	/* mac address related */
320	uint8_t			mac_rcv_mode;
321	uint8_t			mac_addr[ETHER_ADDR_LEN];
322	uint32_t		nmcast;
323	qla_mcast_t		mcast[Q8_MAX_NUM_MULTICAST_ADDRS];
324
325	/* Link Related */
326        uint8_t			link_up;
327	uint32_t		link_status;
328	uint32_t		link_down_info;
329	uint32_t		link_hw_info;
330	uint32_t		link_dcbx_counters;
331	uint32_t		link_change_counters;
332
333	/* Flash Related */
334	q81_flash_t		flash;
335
336	/* debug stuff */
337	volatile const char 	*qla_lock;
338	volatile const char	*qla_unlock;
339
340	/* Error Recovery Related */
341	uint32_t		err_inject;
342	struct task		err_task;
343	struct taskqueue	*err_tq;
344
345	/* Chip related */
346	uint32_t		rev_id;
347
348	/* mailbox completions */
349	uint32_t		aen[Q81_NUM_AEN_REGISTERS];
350	uint32_t		mbox[Q81_NUM_MBX_REGISTERS];
351	volatile uint32_t       mbx_done;
352
353	/* mpi dump related */
354	qla_dma_t		mpi_dma;
355	qla_dma_t		rss_dma;
356
357};
358typedef struct qla_host qla_host_t;
359
360/* note that align has to be a power of 2 */
361#define QL_ALIGN(size, align) (((size) + ((align) - 1)) & (~((align) - 1)))
362#define QL_MIN(x, y) ((x < y) ? x : y)
363
364#define QL_RUNNING(ifp) \
365		((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == \
366			IFF_DRV_RUNNING)
367
368/* Return 0, if identical, else 1 */
369
370#define QL_MAC_CMP(mac1, mac2)    \
371	((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \
372	(*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1)
373
374#endif /* #ifndef _QLS_DEF_H_ */
375