1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013-2016 Qlogic Corporation
5 * All rights reserved.
6 *
7 *  Redistribution and use in source and binary forms, with or without
8 *  modification, are permitted provided that the following conditions
9 *  are met:
10 *
11 *  1. Redistributions of source code must retain the above copyright
12 *     notice, this list of conditions and the following disclaimer.
13 *  2. Redistributions in binary form must reproduce the above copyright
14 *     notice, this list of conditions and the following disclaimer in the
15 *     documentation and/or other materials provided with the distribution.
16 *
17 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 *  POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * File: ql_def.h
32 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
33 */
34
35#ifndef _QL_DEF_H_
36#define _QL_DEF_H_
37
38#define BIT_0                   (0x1 << 0)
39#define BIT_1                   (0x1 << 1)
40#define BIT_2                   (0x1 << 2)
41#define BIT_3                   (0x1 << 3)
42#define BIT_4                   (0x1 << 4)
43#define BIT_5                   (0x1 << 5)
44#define BIT_6                   (0x1 << 6)
45#define BIT_7                   (0x1 << 7)
46#define BIT_8                   (0x1 << 8)
47#define BIT_9                   (0x1 << 9)
48#define BIT_10                  (0x1 << 10)
49#define BIT_11                  (0x1 << 11)
50#define BIT_12                  (0x1 << 12)
51#define BIT_13                  (0x1 << 13)
52#define BIT_14                  (0x1 << 14)
53#define BIT_15                  (0x1 << 15)
54#define BIT_16                  (0x1 << 16)
55#define BIT_17                  (0x1 << 17)
56#define BIT_18                  (0x1 << 18)
57#define BIT_19                  (0x1 << 19)
58#define BIT_20                  (0x1 << 20)
59#define BIT_21                  (0x1 << 21)
60#define BIT_22                  (0x1 << 22)
61#define BIT_23                  (0x1 << 23)
62#define BIT_24                  (0x1 << 24)
63#define BIT_25                  (0x1 << 25)
64#define BIT_26                  (0x1 << 26)
65#define BIT_27                  (0x1 << 27)
66#define BIT_28                  (0x1 << 28)
67#define BIT_29                  (0x1 << 29)
68#define BIT_30                  (0x1 << 30)
69#define BIT_31                  (0x1 << 31)
70
71struct qla_rx_buf {
72	struct mbuf	*m_head;
73	bus_dmamap_t	map;
74	bus_addr_t      paddr;
75	uint32_t	handle;
76	void		*next;
77};
78typedef struct qla_rx_buf qla_rx_buf_t;
79
80struct qla_rx_ring {
81	qla_rx_buf_t	rx_buf[NUM_RX_DESCRIPTORS];
82};
83typedef struct qla_rx_ring qla_rx_ring_t;
84
85struct qla_tx_buf {
86	struct mbuf	*m_head;
87	bus_dmamap_t	map;
88};
89typedef struct qla_tx_buf qla_tx_buf_t;
90
91#define QLA_MAX_SEGMENTS	62	/* maximum # of segs in a sg list */
92#define QLA_MAX_MTU		9000
93#define QLA_STD_FRAME_SIZE	1514
94#define QLA_MAX_TSO_FRAME_SIZE	((64 * 1024 - 1) + 22)
95
96/* Number of MSIX/MSI Vectors required */
97
98struct qla_ivec {
99	uint32_t		sds_idx;
100	void			*ha;
101	struct resource		*irq;
102	void			*handle;
103	int			irq_rid;
104};
105
106typedef struct qla_ivec qla_ivec_t;
107
108#define QLA_WATCHDOG_CALLOUT_TICKS	2
109
110typedef struct _qla_tx_ring {
111	qla_tx_buf_t	tx_buf[NUM_TX_DESCRIPTORS];
112	uint64_t	count;
113	uint64_t	iscsi_pkt_count;
114} qla_tx_ring_t;
115
116typedef struct _qla_tx_fp {
117	struct mtx		tx_mtx;
118	char			tx_mtx_name[32];
119	struct buf_ring		*tx_br;
120	struct task		fp_task;
121	struct taskqueue	*fp_taskqueue;
122	void			*ha;
123	uint32_t		txr_idx;
124} qla_tx_fp_t;
125
126/*
127 * Adapter structure contains the hardware independent information of the
128 * pci function.
129 */
130struct qla_host {
131        volatile struct {
132                volatile uint32_t
133			qla_callout_init	:1,
134			qla_watchdog_active	:1,
135			parent_tag		:1,
136			lock_init		:1;
137        } flags;
138
139	volatile uint32_t	qla_interface_up;
140	volatile uint32_t	stop_rcv;
141	volatile uint32_t	qla_watchdog_exit;
142	volatile uint32_t	qla_watchdog_exited;
143	volatile uint32_t	qla_watchdog_pause;
144	volatile uint32_t	qla_watchdog_paused;
145	volatile uint32_t	qla_initiate_recovery;
146	volatile uint32_t	qla_detach_active;
147	volatile uint32_t	offline;
148
149	device_t		pci_dev;
150
151	volatile uint16_t	watchdog_ticks;
152	uint8_t			pci_func;
153
154        /* ioctl related */
155        struct cdev             *ioctl_dev;
156
157	/* register mapping */
158	struct resource		*pci_reg;
159	int			reg_rid;
160	struct resource		*pci_reg1;
161	int			reg_rid1;
162
163	/* interrupts */
164	struct resource         *mbx_irq;
165	void			*mbx_handle;
166	int			mbx_irq_rid;
167
168	int			msix_count;
169
170	qla_ivec_t		irq_vec[MAX_SDS_RINGS];
171
172	/* parent dma tag */
173	bus_dma_tag_t           parent_tag;
174
175	/* interface to o.s */
176	if_t			ifp;
177
178	struct ifmedia		media;
179	uint16_t		max_frame_size;
180	uint16_t		rsrvd0;
181	int			if_flags;
182
183	/* hardware access lock */
184
185	struct mtx		sp_log_lock;
186	struct mtx		hw_lock;
187	volatile uint32_t	hw_lock_held;
188	uint64_t		hw_lock_failed;
189
190	/* transmit and receive buffers */
191	uint32_t		txr_idx; /* index of the current tx ring */
192	qla_tx_ring_t		tx_ring[NUM_TX_RINGS];
193
194	bus_dma_tag_t		tx_tag;
195	struct callout		tx_callout;
196
197	qla_tx_fp_t		tx_fp[MAX_SDS_RINGS];
198
199	qla_rx_ring_t		rx_ring[MAX_RDS_RINGS];
200	bus_dma_tag_t		rx_tag;
201	uint32_t		std_replenish;
202
203	qla_rx_buf_t		*rxb_free;
204	uint32_t		rxb_free_count;
205
206	/* stats */
207	uint32_t		err_m_getcl;
208	uint32_t		err_m_getjcl;
209	uint32_t		err_tx_dmamap_create;
210	uint32_t		err_tx_dmamap_load;
211	uint32_t		err_tx_defrag;
212
213	uint64_t		rx_frames;
214	uint64_t		rx_bytes;
215
216	uint64_t		lro_pkt_count;
217	uint64_t		lro_bytes;
218
219	uint64_t		ipv4_lro;
220	uint64_t		ipv6_lro;
221
222	uint64_t		tx_frames;
223	uint64_t		tx_bytes;
224	uint64_t		tx_tso_frames;
225	uint64_t		hw_vlan_tx_frames;
226
227	struct task             stats_task;
228	struct taskqueue	*stats_tq;
229
230        uint32_t                fw_ver_major;
231        uint32_t                fw_ver_minor;
232        uint32_t                fw_ver_sub;
233        uint32_t                fw_ver_build;
234
235	/* hardware specific */
236	qla_hw_t		hw;
237
238	/* debug stuff */
239	volatile const char 	*qla_lock;
240	volatile const char	*qla_unlock;
241	uint32_t		dbg_level;
242	uint32_t		enable_minidump;
243	uint32_t		enable_driverstate_dump;
244	uint32_t		enable_error_recovery;
245	uint32_t		ms_delay_after_init;
246
247	uint8_t			fw_ver_str[32];
248
249	/* Error Injection Related */
250	uint32_t		err_inject;
251	struct task		err_task;
252	struct taskqueue	*err_tq;
253
254	/* Async Event Related */
255	uint32_t                async_event;
256	struct task             async_event_task;
257	struct taskqueue        *async_event_tq;
258
259	/* Peer Device */
260	device_t		peer_dev;
261
262	volatile uint32_t	msg_from_peer;
263#define QL_PEER_MSG_RESET	0x01
264#define QL_PEER_MSG_ACK		0x02
265
266};
267typedef struct qla_host qla_host_t;
268
269/* note that align has to be a power of 2 */
270#define QL_ALIGN(size, align) (((size) + ((align) - 1)) & (~((align) - 1)))
271#define QL_MIN(x, y) ((x < y) ? x : y)
272
273#define QL_RUNNING(ifp) (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
274
275/* Return 0, if identical, else 1 */
276#define QL_MAC_CMP(mac1, mac2)    \
277	((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \
278	(*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1)
279
280#define QL_INITIATE_RECOVERY(ha) qla_set_error_recovery(ha)
281
282#endif /* #ifndef _QL_DEF_H_ */
283