1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011-2013 Qlogic Corporation
5 * All rights reserved.
6 *
7 *  Redistribution and use in source and binary forms, with or without
8 *  modification, are permitted provided that the following conditions
9 *  are met:
10 *
11 *  1. Redistributions of source code must retain the above copyright
12 *     notice, this list of conditions and the following disclaimer.
13 *  2. Redistributions in binary form must reproduce the above copyright
14 *     notice, this list of conditions and the following disclaimer in the
15 *     documentation and/or other materials provided with the distribution.
16 *
17 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 *  POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * File: qla_isr.c
32 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
33 */
34
35#include <sys/cdefs.h>
36#include "qla_os.h"
37#include "qla_reg.h"
38#include "qla_hw.h"
39#include "qla_def.h"
40#include "qla_inline.h"
41#include "qla_ver.h"
42#include "qla_glbl.h"
43#include "qla_dbg.h"
44
45static void qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp);
46static void qla_replenish_jumbo_rx(qla_host_t *ha, qla_sds_t *sdsp);
47
48/*
49 * Name: qla_rx_intr
50 * Function: Handles normal ethernet frames received
51 */
52static void
53qla_rx_intr(qla_host_t *ha, uint64_t data, uint32_t sds_idx,
54	struct lro_ctrl *lro)
55{
56	uint32_t idx, length, status, ring;
57	qla_rx_buf_t *rxb;
58	struct mbuf *mp;
59	if_t ifp = ha->ifp;
60	qla_sds_t *sdsp;
61	struct ether_vlan_header *eh;
62
63	sdsp = &ha->hw.sds[sds_idx];
64
65	ring = (uint32_t)Q8_STAT_DESC_TYPE(data);
66	idx = (uint32_t)Q8_STAT_DESC_HANDLE(data);
67	length = (uint32_t)Q8_STAT_DESC_TOTAL_LENGTH(data);
68	status = (uint32_t)Q8_STAT_DESC_STATUS(data);
69
70	if (ring == 0) {
71		if ((idx >= NUM_RX_DESCRIPTORS) || (length > MCLBYTES)) {
72			device_printf(ha->pci_dev, "%s: ring[%d] index[0x%08x]"
73				" len[0x%08x] invalid\n",
74				__func__, ring, idx, length);
75			return;
76		}
77	} else {
78		if ((idx >= NUM_RX_JUMBO_DESCRIPTORS)||(length > MJUM9BYTES)) {
79			device_printf(ha->pci_dev, "%s: ring[%d] index[0x%08x]"
80				" len[0x%08x] invalid\n",
81				__func__, ring, idx, length);
82			return;
83		}
84	}
85
86	if (ring == 0)
87		rxb = &ha->rx_buf[idx];
88	else
89		rxb = &ha->rx_jbuf[idx];
90
91	QL_ASSERT((rxb != NULL),\
92		("%s: [r, i, sds_idx]=[%d, 0x%x, %d] rxb != NULL\n",\
93		 __func__, ring, idx, sds_idx));
94
95	mp = rxb->m_head;
96
97	QL_ASSERT((mp != NULL),\
98		("%s: [r,i,rxb, sds_idx]=[%d, 0x%x, %p, %d] mp != NULL\n",\
99		 __func__, ring, idx, rxb, sds_idx));
100
101	bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_POSTREAD);
102
103	if (ring == 0) {
104		rxb->m_head = NULL;
105		rxb->next = sdsp->rxb_free;
106		sdsp->rxb_free = rxb;
107		sdsp->rx_free++;
108	} else {
109		rxb->m_head = NULL;
110		rxb->next = sdsp->rxjb_free;
111		sdsp->rxjb_free = rxb;
112		sdsp->rxj_free++;
113	}
114
115	mp->m_len = length;
116	mp->m_pkthdr.len = length;
117	mp->m_pkthdr.rcvif = ifp;
118
119	eh = mtod(mp, struct ether_vlan_header *);
120
121	if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
122		uint32_t *data = (uint32_t *)eh;
123
124		mp->m_pkthdr.ether_vtag = ntohs(eh->evl_tag);
125		mp->m_flags |= M_VLANTAG;
126
127		*(data + 3) = *(data + 2);
128		*(data + 2) = *(data + 1);
129		*(data + 1) = *data;
130
131		m_adj(mp, ETHER_VLAN_ENCAP_LEN);
132	}
133
134	if (status == Q8_STAT_DESC_STATUS_CHKSUM_OK) {
135		mp->m_pkthdr.csum_flags = (CSUM_IP_CHECKED | CSUM_IP_VALID);
136	} else {
137		mp->m_pkthdr.csum_flags = 0;
138	}
139
140#if defined(INET) || defined(INET6)
141	if (lro->lro_cnt && (tcp_lro_rx(lro, mp, 0) == 0)) {
142		/* LRO packet has been successfully queued */
143	} else
144#endif
145	{
146		if_input(ifp, mp);
147	}
148
149	if (sdsp->rx_free > std_replenish)
150		qla_replenish_normal_rx(ha, sdsp);
151
152	if (sdsp->rxj_free > jumbo_replenish)
153		qla_replenish_jumbo_rx(ha, sdsp);
154
155	return;
156}
157
158static void
159qla_replenish_jumbo_rx(qla_host_t *ha, qla_sds_t *sdsp)
160{
161	qla_rx_buf_t *rxb;
162	int count = jumbo_replenish;
163	uint32_t rxj_next;
164
165	if (!mtx_trylock(&ha->rxj_lock))
166		return;
167
168	rxj_next = ha->hw.rxj_next;
169
170	while (count--) {
171		rxb = sdsp->rxjb_free;
172
173		if (rxb == NULL)
174			break;
175
176		sdsp->rxjb_free = rxb->next;
177		sdsp->rxj_free--;
178
179		if (qla_get_mbuf(ha, rxb, NULL, RDS_RING_INDEX_JUMBO) == 0) {
180			qla_set_hw_rcv_desc(ha, RDS_RING_INDEX_JUMBO,
181				ha->hw.rxj_in, rxb->handle, rxb->paddr,
182				(rxb->m_head)->m_pkthdr.len);
183			ha->hw.rxj_in++;
184			if (ha->hw.rxj_in == NUM_RX_JUMBO_DESCRIPTORS)
185				ha->hw.rxj_in = 0;
186			ha->hw.rxj_next++;
187			if (ha->hw.rxj_next == NUM_RX_JUMBO_DESCRIPTORS)
188				ha->hw.rxj_next = 0;
189		} else {
190			device_printf(ha->pci_dev,
191				"%s: qla_get_mbuf [1,(%d),(%d)] failed\n",
192				__func__, ha->hw.rxj_in, rxb->handle);
193
194			rxb->m_head = NULL;
195			rxb->next = sdsp->rxjb_free;
196			sdsp->rxjb_free = rxb;
197			sdsp->rxj_free++;
198
199			break;
200		}
201	}
202
203	if (rxj_next != ha->hw.rxj_next) {
204		QL_UPDATE_RDS_PRODUCER_INDEX(ha, 1, ha->hw.rxj_next);
205	}
206	mtx_unlock(&ha->rxj_lock);
207}
208
209static void
210qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp)
211{
212	qla_rx_buf_t *rxb;
213	int count = std_replenish;
214	uint32_t rx_next;
215
216	if (!mtx_trylock(&ha->rx_lock))
217		return;
218
219	rx_next = ha->hw.rx_next;
220
221	while (count--) {
222		rxb = sdsp->rxb_free;
223
224		if (rxb == NULL)
225			break;
226
227		sdsp->rxb_free = rxb->next;
228		sdsp->rx_free--;
229
230		if (qla_get_mbuf(ha, rxb, NULL, RDS_RING_INDEX_NORMAL) == 0) {
231			qla_set_hw_rcv_desc(ha, RDS_RING_INDEX_NORMAL,
232				ha->hw.rx_in, rxb->handle, rxb->paddr,
233				(rxb->m_head)->m_pkthdr.len);
234			ha->hw.rx_in++;
235			if (ha->hw.rx_in == NUM_RX_DESCRIPTORS)
236				ha->hw.rx_in = 0;
237			ha->hw.rx_next++;
238			if (ha->hw.rx_next == NUM_RX_DESCRIPTORS)
239				ha->hw.rx_next = 0;
240		} else {
241			device_printf(ha->pci_dev,
242				"%s: qla_get_mbuf [0,(%d),(%d)] failed\n",
243				__func__, ha->hw.rx_in, rxb->handle);
244
245			rxb->m_head = NULL;
246			rxb->next = sdsp->rxb_free;
247			sdsp->rxb_free = rxb;
248			sdsp->rx_free++;
249
250			break;
251		}
252	}
253
254	if (rx_next != ha->hw.rx_next) {
255		QL_UPDATE_RDS_PRODUCER_INDEX(ha, 0, ha->hw.rx_next);
256	}
257	mtx_unlock(&ha->rx_lock);
258}
259
260/*
261 * Name: qla_isr
262 * Function: Main Interrupt Service Routine
263 */
264static uint32_t
265qla_rcv_isr(qla_host_t *ha, uint32_t sds_idx, uint32_t count)
266{
267	device_t dev;
268	qla_hw_t *hw;
269	uint32_t comp_idx, desc_count;
270	q80_stat_desc_t *sdesc;
271	struct lro_ctrl *lro;
272	uint32_t ret = 0;
273
274	dev = ha->pci_dev;
275	hw = &ha->hw;
276
277	hw->sds[sds_idx].rcv_active = 1;
278	if (ha->flags.stop_rcv) {
279		hw->sds[sds_idx].rcv_active = 0;
280		return 0;
281	}
282
283	QL_DPRINT2((dev, "%s: [%d]enter\n", __func__, sds_idx));
284
285	/*
286	 * receive interrupts
287	 */
288	comp_idx = hw->sds[sds_idx].sdsr_next;
289	lro = &hw->sds[sds_idx].lro;
290
291	while (count--) {
292		sdesc = (q80_stat_desc_t *)
293				&hw->sds[sds_idx].sds_ring_base[comp_idx];
294
295		if (Q8_STAT_DESC_OWNER((sdesc->data[0])) !=
296			Q8_STAT_DESC_OWNER_HOST) {
297			QL_DPRINT2((dev, "%s:  data %p sdsr_next 0x%08x\n",
298				__func__, (void *)sdesc->data[0], comp_idx));
299			break;
300		}
301
302		desc_count = Q8_STAT_DESC_COUNT((sdesc->data[0]));
303
304		switch (Q8_STAT_DESC_OPCODE((sdesc->data[0]))) {
305		case Q8_STAT_DESC_OPCODE_RCV_PKT:
306		case Q8_STAT_DESC_OPCODE_SYN_OFFLOAD:
307			qla_rx_intr(ha, (sdesc->data[0]), sds_idx, lro);
308
309			break;
310
311		default:
312			device_printf(dev, "%s: default 0x%llx!\n", __func__,
313					(long long unsigned int)sdesc->data[0]);
314			break;
315		}
316
317		while (desc_count--) {
318			sdesc->data[0] =
319				Q8_STAT_DESC_SET_OWNER(Q8_STAT_DESC_OWNER_FW);
320			comp_idx = (comp_idx + 1) & (NUM_STATUS_DESCRIPTORS-1);
321			sdesc = (q80_stat_desc_t *)
322				&hw->sds[sds_idx].sds_ring_base[comp_idx];
323		}
324	}
325
326#if defined(INET) || defined(INET6)
327	tcp_lro_flush_all(lro);
328#endif
329
330	if (hw->sds[sds_idx].sdsr_next != comp_idx) {
331		QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx, comp_idx);
332	}
333	hw->sds[sds_idx].sdsr_next = comp_idx;
334
335	sdesc = (q80_stat_desc_t *)&hw->sds[sds_idx].sds_ring_base[comp_idx];
336	if ((sds_idx == 0) && (Q8_STAT_DESC_OWNER((sdesc->data[0])) ==
337					Q8_STAT_DESC_OWNER_HOST)) {
338		ret = -1;
339	}
340
341	hw->sds[sds_idx].rcv_active = 0;
342	return (ret);
343}
344
345void
346qla_isr(void *arg)
347{
348	qla_ivec_t *ivec = arg;
349	qla_host_t *ha;
350	uint32_t sds_idx;
351	uint32_t ret;
352
353	ha = ivec->ha;
354	sds_idx = ivec->irq_rid - 1;
355
356	if (sds_idx >= ha->hw.num_sds_rings) {
357		device_printf(ha->pci_dev, "%s: bogus sds_idx 0x%x\n", __func__,
358			sds_idx);
359
360		return;
361	}
362
363	if (sds_idx == 0)
364		taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
365
366	ret = qla_rcv_isr(ha, sds_idx, rcv_pkt_thres);
367
368	if (sds_idx == 0)
369		taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
370
371	if (ret) {
372		taskqueue_enqueue(ha->irq_vec[sds_idx].rcv_tq,
373			&ha->irq_vec[sds_idx].rcv_task);
374	} else {
375		QL_ENABLE_INTERRUPTS(ha, sds_idx);
376	}
377}
378
379void
380qla_rcv(void *context, int pending)
381{
382	qla_ivec_t *ivec = context;
383	qla_host_t *ha;
384	qla_hw_t *hw;
385	uint32_t sds_idx;
386	uint32_t ret;
387	if_t ifp;
388
389	ha = ivec->ha;
390	hw = &ha->hw;
391	sds_idx = ivec->irq_rid - 1;
392	ifp = ha->ifp;
393
394	do {
395		if (sds_idx == 0) {
396			if (qla_le32_to_host(*(hw->tx_cons)) != hw->txr_comp) {
397				taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
398			} else if (!if_sendq_empty(ifp) &&
399					QL_RUNNING(ifp)) {
400				taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
401			}
402		}
403		ret = qla_rcv_isr(ha, sds_idx, rcv_pkt_thres_d);
404	} while (ret);
405
406	if (sds_idx == 0)
407		taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
408
409	QL_ENABLE_INTERRUPTS(ha, sds_idx);
410}
411