1/* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29#ifndef __ECORE_MCP_API_H__ 30#define __ECORE_MCP_API_H__ 31 32#include "ecore_status.h" 33 34struct ecore_mcp_link_speed_params { 35 bool autoneg; 36 u32 advertised_speeds; /* bitmask of DRV_SPEED_CAPABILITY */ 37 u32 forced_speed; /* In Mb/s */ 38}; 39 40struct ecore_mcp_link_pause_params { 41 bool autoneg; 42 bool forced_rx; 43 bool forced_tx; 44}; 45 46enum ecore_mcp_eee_mode { 47 ECORE_MCP_EEE_DISABLED, 48 ECORE_MCP_EEE_ENABLED, 49 ECORE_MCP_EEE_UNSUPPORTED 50}; 51 52#ifndef __EXTRACT__LINUX__ 53struct ecore_link_eee_params { 54 u32 tx_lpi_timer; 55#define ECORE_EEE_1G_ADV (1 << 0) 56#define ECORE_EEE_10G_ADV (1 << 1) 57 /* Capabilities are represented using ECORE_EEE_*_ADV values */ 58 u8 adv_caps; 59 u8 lp_adv_caps; 60 bool enable; 61 bool tx_lpi_enable; 62}; 63#endif 64 65struct ecore_mcp_link_params { 66 struct ecore_mcp_link_speed_params speed; 67 struct ecore_mcp_link_pause_params pause; 68 u32 loopback_mode; /* in PMM_LOOPBACK values */ 69 struct ecore_link_eee_params eee; 70}; 71 72struct ecore_mcp_link_capabilities { 73 u32 speed_capabilities; 74 bool default_speed_autoneg; /* In Mb/s */ 75 u32 default_speed; /* In Mb/s */ /* __LINUX__THROW__ */ 76 enum ecore_mcp_eee_mode default_eee; 77 u32 eee_lpi_timer; 78 u8 eee_speed_caps; 79}; 80 81struct ecore_mcp_link_state { 82 bool link_up; 83 84 u32 min_pf_rate; /* In Mb/s */ 85 86 /* Actual link speed in Mb/s */ 87 u32 line_speed; 88 89 /* PF max speed in MB/s, deduced from line_speed 90 * according to PF max bandwidth configuration. 91 */ 92 u32 speed; 93 bool full_duplex; 94 95 bool an; 96 bool an_complete; 97 bool parallel_detection; 98 bool pfc_enabled; 99 100#define ECORE_LINK_PARTNER_SPEED_1G_HD (1 << 0) 101#define ECORE_LINK_PARTNER_SPEED_1G_FD (1 << 1) 102#define ECORE_LINK_PARTNER_SPEED_10G (1 << 2) 103#define ECORE_LINK_PARTNER_SPEED_20G (1 << 3) 104#define ECORE_LINK_PARTNER_SPEED_25G (1 << 4) 105#define ECORE_LINK_PARTNER_SPEED_40G (1 << 5) 106#define ECORE_LINK_PARTNER_SPEED_50G (1 << 6) 107#define ECORE_LINK_PARTNER_SPEED_100G (1 << 7) 108 u32 partner_adv_speed; 109 110 bool partner_tx_flow_ctrl_en; 111 bool partner_rx_flow_ctrl_en; 112 113#define ECORE_LINK_PARTNER_SYMMETRIC_PAUSE (1) 114#define ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE (2) 115#define ECORE_LINK_PARTNER_BOTH_PAUSE (3) 116 u8 partner_adv_pause; 117 118 bool sfp_tx_fault; 119 120 bool eee_active; 121 u8 eee_adv_caps; 122 u8 eee_lp_adv_caps; 123}; 124 125struct ecore_mcp_function_info { 126 u8 pause_on_host; 127 128 enum ecore_pci_personality protocol; 129 130 u8 bandwidth_min; 131 u8 bandwidth_max; 132 133 u8 mac[ETH_ALEN]; 134 135 u64 wwn_port; 136 u64 wwn_node; 137 138#define ECORE_MCP_VLAN_UNSET (0xffff) 139 u16 ovlan; 140 141 u16 mtu; 142}; 143 144#ifndef __EXTRACT__LINUX__ 145enum ecore_nvm_images { 146 ECORE_NVM_IMAGE_ISCSI_CFG, 147 ECORE_NVM_IMAGE_FCOE_CFG, 148 ECORE_NVM_IMAGE_MDUMP, 149}; 150#endif 151 152struct ecore_mcp_drv_version { 153 u32 version; 154 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 155}; 156 157struct ecore_mcp_lan_stats { 158 u64 ucast_rx_pkts; 159 u64 ucast_tx_pkts; 160 u32 fcs_err; 161}; 162 163#ifndef ECORE_PROTO_STATS 164#define ECORE_PROTO_STATS 165struct ecore_mcp_fcoe_stats { 166 u64 rx_pkts; 167 u64 tx_pkts; 168 u32 fcs_err; 169 u32 login_failure; 170}; 171 172struct ecore_mcp_iscsi_stats { 173 u64 rx_pdus; 174 u64 tx_pdus; 175 u64 rx_bytes; 176 u64 tx_bytes; 177}; 178 179struct ecore_mcp_rdma_stats { 180 u64 rx_pkts; 181 u64 tx_pkts; 182 u64 rx_bytes; 183 u64 tx_byts; 184}; 185 186enum ecore_mcp_protocol_type { 187 ECORE_MCP_LAN_STATS, 188 ECORE_MCP_FCOE_STATS, 189 ECORE_MCP_ISCSI_STATS, 190 ECORE_MCP_RDMA_STATS 191}; 192 193union ecore_mcp_protocol_stats { 194 struct ecore_mcp_lan_stats lan_stats; 195 struct ecore_mcp_fcoe_stats fcoe_stats; 196 struct ecore_mcp_iscsi_stats iscsi_stats; 197 struct ecore_mcp_rdma_stats rdma_stats; 198}; 199#endif 200 201enum ecore_ov_client { 202 ECORE_OV_CLIENT_DRV, 203 ECORE_OV_CLIENT_USER, 204 ECORE_OV_CLIENT_VENDOR_SPEC 205}; 206 207enum ecore_ov_driver_state { 208 ECORE_OV_DRIVER_STATE_NOT_LOADED, 209 ECORE_OV_DRIVER_STATE_DISABLED, 210 ECORE_OV_DRIVER_STATE_ACTIVE 211}; 212 213enum ecore_ov_wol { 214 ECORE_OV_WOL_DEFAULT, 215 ECORE_OV_WOL_DISABLED, 216 ECORE_OV_WOL_ENABLED 217}; 218 219#ifndef __EXTRACT__LINUX__ 220#define ECORE_MAX_NPIV_ENTRIES 128 221#define ECORE_WWN_SIZE 8 222struct ecore_fc_npiv_tbl { 223 u16 num_wwpn; 224 u16 num_wwnn; 225 u8 wwpn[ECORE_MAX_NPIV_ENTRIES][ECORE_WWN_SIZE]; 226 u8 wwnn[ECORE_MAX_NPIV_ENTRIES][ECORE_WWN_SIZE]; 227}; 228 229enum ecore_led_mode { 230 ECORE_LED_MODE_OFF, 231 ECORE_LED_MODE_ON, 232 ECORE_LED_MODE_RESTORE 233}; 234#endif 235 236struct ecore_temperature_sensor { 237 u8 sensor_location; 238 u8 threshold_high; 239 u8 critical; 240 u8 current_temp; 241}; 242 243#define ECORE_MAX_NUM_OF_SENSORS 7 244struct ecore_temperature_info { 245 u32 num_sensors; 246 struct ecore_temperature_sensor sensors[ECORE_MAX_NUM_OF_SENSORS]; 247}; 248 249enum ecore_mba_img_idx { 250 ECORE_MBA_LEGACY_IDX, 251 ECORE_MBA_PCI3CLP_IDX, 252 ECORE_MBA_PCI3_IDX, 253 ECORE_MBA_FCODE_IDX, 254 ECORE_EFI_X86_IDX, 255 ECORE_EFI_IPF_IDX, 256 ECORE_EFI_EBC_IDX, 257 ECORE_EFI_X64_IDX, 258 ECORE_MAX_NUM_OF_ROMIMG 259}; 260 261struct ecore_mba_vers { 262 u32 mba_vers[ECORE_MAX_NUM_OF_ROMIMG]; 263}; 264 265enum ecore_mfw_tlv_type { 266 ECORE_MFW_TLV_GENERIC = 0x1, /* Core driver TLVs */ 267 ECORE_MFW_TLV_ETH = 0x2, /* L2 driver TLVs */ 268 ECORE_MFW_TLV_FCOE = 0x4, /* FCoE protocol TLVs */ 269 ECORE_MFW_TLV_ISCSI = 0x8, /* SCSI protocol TLVs */ 270 ECORE_MFW_TLV_MAX = 0x16, 271}; 272 273struct ecore_mfw_tlv_generic { 274 struct { 275 u8 ipv4_csum_offload; 276 u8 lso_supported; 277 bool b_set; 278 } flags; 279 280#define ECORE_MFW_TLV_MAC_COUNT 3 281 /* First entry for primary MAC, 2 secondary MACs possible */ 282 u8 mac[ECORE_MFW_TLV_MAC_COUNT][6]; 283 bool mac_set[ECORE_MFW_TLV_MAC_COUNT]; 284 285 u64 rx_frames; 286 bool rx_frames_set; 287 u64 rx_bytes; 288 bool rx_bytes_set; 289 u64 tx_frames; 290 bool tx_frames_set; 291 u64 tx_bytes; 292 bool tx_bytes_set; 293}; 294 295#ifndef __EXTRACT__LINUX__ 296struct ecore_mfw_tlv_eth { 297 u16 lso_maxoff_size; 298 bool lso_maxoff_size_set; 299 u16 lso_minseg_size; 300 bool lso_minseg_size_set; 301 u8 prom_mode; 302 bool prom_mode_set; 303 u16 tx_descr_size; 304 bool tx_descr_size_set; 305 u16 rx_descr_size; 306 bool rx_descr_size_set; 307 u16 netq_count; 308 bool netq_count_set; 309 u32 tcp4_offloads; 310 bool tcp4_offloads_set; 311 u32 tcp6_offloads; 312 bool tcp6_offloads_set; 313 u16 tx_descr_qdepth; 314 bool tx_descr_qdepth_set; 315 u16 rx_descr_qdepth; 316 bool rx_descr_qdepth_set; 317 u8 iov_offload; 318#define ECORE_MFW_TLV_IOV_OFFLOAD_NONE (0) 319#define ECORE_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1) 320#define ECORE_MFW_TLV_IOV_OFFLOAD_VEB (2) 321#define ECORE_MFW_TLV_IOV_OFFLOAD_VEPA (3) 322 bool iov_offload_set; 323 u8 txqs_empty; 324 bool txqs_empty_set; 325 u8 rxqs_empty; 326 bool rxqs_empty_set; 327 u8 num_txqs_full; 328 bool num_txqs_full_set; 329 u8 num_rxqs_full; 330 bool num_rxqs_full_set; 331}; 332 333struct ecore_mfw_tlv_time { 334 bool b_set; 335 u8 month; 336 u8 day; 337 u8 hour; 338 u8 min; 339 u16 msec; 340 u16 usec; 341}; 342 343struct ecore_mfw_tlv_fcoe { 344 u8 scsi_timeout; 345 bool scsi_timeout_set; 346 u32 rt_tov; 347 bool rt_tov_set; 348 u32 ra_tov; 349 bool ra_tov_set; 350 u32 ed_tov; 351 bool ed_tov_set; 352 u32 cr_tov; 353 bool cr_tov_set; 354 u8 boot_type; 355 bool boot_type_set; 356 u8 npiv_state; 357 bool npiv_state_set; 358 u32 num_npiv_ids; 359 bool num_npiv_ids_set; 360 u8 switch_name[8]; 361 bool switch_name_set; 362 u16 switch_portnum; 363 bool switch_portnum_set; 364 u8 switch_portid[3]; 365 bool switch_portid_set; 366 u8 vendor_name[8]; 367 bool vendor_name_set; 368 u8 switch_model[8]; 369 bool switch_model_set; 370 u8 switch_fw_version[8]; 371 bool switch_fw_version_set; 372 u8 qos_pri; 373 bool qos_pri_set; 374 u8 port_alias[3]; 375 bool port_alias_set; 376 u8 port_state; 377#define ECORE_MFW_TLV_PORT_STATE_OFFLINE (0) 378#define ECORE_MFW_TLV_PORT_STATE_LOOP (1) 379#define ECORE_MFW_TLV_PORT_STATE_P2P (2) 380#define ECORE_MFW_TLV_PORT_STATE_FABRIC (3) 381 bool port_state_set; 382 u16 fip_tx_descr_size; 383 bool fip_tx_descr_size_set; 384 u16 fip_rx_descr_size; 385 bool fip_rx_descr_size_set; 386 u16 link_failures; 387 bool link_failures_set; 388 u8 fcoe_boot_progress; 389 bool fcoe_boot_progress_set; 390 u64 rx_bcast; 391 bool rx_bcast_set; 392 u64 tx_bcast; 393 bool tx_bcast_set; 394 u16 fcoe_txq_depth; 395 bool fcoe_txq_depth_set; 396 u16 fcoe_rxq_depth; 397 bool fcoe_rxq_depth_set; 398 u64 fcoe_rx_frames; 399 bool fcoe_rx_frames_set; 400 u64 fcoe_rx_bytes; 401 bool fcoe_rx_bytes_set; 402 u64 fcoe_tx_frames; 403 bool fcoe_tx_frames_set; 404 u64 fcoe_tx_bytes; 405 bool fcoe_tx_bytes_set; 406 u16 crc_count; 407 bool crc_count_set; 408 u32 crc_err_src_fcid[5]; 409 bool crc_err_src_fcid_set[5]; 410 struct ecore_mfw_tlv_time crc_err[5]; 411 u16 losync_err; 412 bool losync_err_set; 413 u16 losig_err; 414 bool losig_err_set; 415 u16 primtive_err; 416 bool primtive_err_set; 417 u16 disparity_err; 418 bool disparity_err_set; 419 u16 code_violation_err; 420 bool code_violation_err_set; 421 u32 flogi_param[4]; 422 bool flogi_param_set[4]; 423 struct ecore_mfw_tlv_time flogi_tstamp; 424 u32 flogi_acc_param[4]; 425 bool flogi_acc_param_set[4]; 426 struct ecore_mfw_tlv_time flogi_acc_tstamp; 427 u32 flogi_rjt; 428 bool flogi_rjt_set; 429 struct ecore_mfw_tlv_time flogi_rjt_tstamp; 430 u32 fdiscs; 431 bool fdiscs_set; 432 u8 fdisc_acc; 433 bool fdisc_acc_set; 434 u8 fdisc_rjt; 435 bool fdisc_rjt_set; 436 u8 plogi; 437 bool plogi_set; 438 u8 plogi_acc; 439 bool plogi_acc_set; 440 u8 plogi_rjt; 441 bool plogi_rjt_set; 442 u32 plogi_dst_fcid[5]; 443 bool plogi_dst_fcid_set[5]; 444 struct ecore_mfw_tlv_time plogi_tstamp[5]; 445 u32 plogi_acc_src_fcid[5]; 446 bool plogi_acc_src_fcid_set[5]; 447 struct ecore_mfw_tlv_time plogi_acc_tstamp[5]; 448 u8 tx_plogos; 449 bool tx_plogos_set; 450 u8 plogo_acc; 451 bool plogo_acc_set; 452 u8 plogo_rjt; 453 bool plogo_rjt_set; 454 u32 plogo_src_fcid[5]; 455 bool plogo_src_fcid_set[5]; 456 struct ecore_mfw_tlv_time plogo_tstamp[5]; 457 u8 rx_logos; 458 bool rx_logos_set; 459 u8 tx_accs; 460 bool tx_accs_set; 461 u8 tx_prlis; 462 bool tx_prlis_set; 463 u8 rx_accs; 464 bool rx_accs_set; 465 u8 tx_abts; 466 bool tx_abts_set; 467 u8 rx_abts_acc; 468 bool rx_abts_acc_set; 469 u8 rx_abts_rjt; 470 bool rx_abts_rjt_set; 471 u32 abts_dst_fcid[5]; 472 bool abts_dst_fcid_set[5]; 473 struct ecore_mfw_tlv_time abts_tstamp[5]; 474 u8 rx_rscn; 475 bool rx_rscn_set; 476 u32 rx_rscn_nport[4]; 477 bool rx_rscn_nport_set[4]; 478 u8 tx_lun_rst; 479 bool tx_lun_rst_set; 480 u8 abort_task_sets; 481 bool abort_task_sets_set; 482 u8 tx_tprlos; 483 bool tx_tprlos_set; 484 u8 tx_nos; 485 bool tx_nos_set; 486 u8 rx_nos; 487 bool rx_nos_set; 488 u8 ols; 489 bool ols_set; 490 u8 lr; 491 bool lr_set; 492 u8 lrr; 493 bool lrr_set; 494 u8 tx_lip; 495 bool tx_lip_set; 496 u8 rx_lip; 497 bool rx_lip_set; 498 u8 eofa; 499 bool eofa_set; 500 u8 eofni; 501 bool eofni_set; 502 u8 scsi_chks; 503 bool scsi_chks_set; 504 u8 scsi_cond_met; 505 bool scsi_cond_met_set; 506 u8 scsi_busy; 507 bool scsi_busy_set; 508 u8 scsi_inter; 509 bool scsi_inter_set; 510 u8 scsi_inter_cond_met; 511 bool scsi_inter_cond_met_set; 512 u8 scsi_rsv_conflicts; 513 bool scsi_rsv_conflicts_set; 514 u8 scsi_tsk_full; 515 bool scsi_tsk_full_set; 516 u8 scsi_aca_active; 517 bool scsi_aca_active_set; 518 u8 scsi_tsk_abort; 519 bool scsi_tsk_abort_set; 520 u32 scsi_rx_chk[5]; 521 bool scsi_rx_chk_set[5]; 522 struct ecore_mfw_tlv_time scsi_chk_tstamp[5]; 523}; 524 525struct ecore_mfw_tlv_iscsi { 526 u8 target_llmnr; 527 bool target_llmnr_set; 528 u8 header_digest; 529 bool header_digest_set; 530 u8 data_digest; 531 bool data_digest_set; 532 u8 auth_method; 533#define ECORE_MFW_TLV_AUTH_METHOD_NONE (1) 534#define ECORE_MFW_TLV_AUTH_METHOD_CHAP (2) 535#define ECORE_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP (3) 536 bool auth_method_set; 537 u16 boot_taget_portal; 538 bool boot_taget_portal_set; 539 u16 frame_size; 540 bool frame_size_set; 541 u16 tx_desc_size; 542 bool tx_desc_size_set; 543 u16 rx_desc_size; 544 bool rx_desc_size_set; 545 u8 boot_progress; 546 bool boot_progress_set; 547 u16 tx_desc_qdepth; 548 bool tx_desc_qdepth_set; 549 u16 rx_desc_qdepth; 550 bool rx_desc_qdepth_set; 551 u64 rx_frames; 552 bool rx_frames_set; 553 u64 rx_bytes; 554 bool rx_bytes_set; 555 u64 tx_frames; 556 bool tx_frames_set; 557 u64 tx_bytes; 558 bool tx_bytes_set; 559}; 560#endif 561 562union ecore_mfw_tlv_data { 563 struct ecore_mfw_tlv_generic generic; 564 struct ecore_mfw_tlv_eth eth; 565 struct ecore_mfw_tlv_fcoe fcoe; 566 struct ecore_mfw_tlv_iscsi iscsi; 567}; 568 569#ifndef __EXTRACT__LINUX__ 570enum ecore_hw_info_change { 571 ECORE_HW_INFO_CHANGE_OVLAN, 572}; 573#endif 574 575/** 576 * @brief - returns the link params of the hw function 577 * 578 * @param p_hwfn 579 * 580 * @returns pointer to link params 581 */ 582struct ecore_mcp_link_params *ecore_mcp_get_link_params(struct ecore_hwfn 583 *p_hwfn); 584 585/** 586 * @brief - return the link state of the hw function 587 * 588 * @param p_hwfn 589 * 590 * @returns pointer to link state 591 */ 592struct ecore_mcp_link_state *ecore_mcp_get_link_state(struct ecore_hwfn 593 *p_hwfn); 594 595/** 596 * @brief - return the link capabilities of the hw function 597 * 598 * @param p_hwfn 599 * 600 * @returns pointer to link capabilities 601 */ 602struct ecore_mcp_link_capabilities 603*ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn); 604 605/** 606 * @brief Request the MFW to set the the link according to 'link_input'. 607 * 608 * @param p_hwfn 609 * @param p_ptt 610 * @param b_up - raise link if `true'. Reset link if `false'. 611 * 612 * @return enum _ecore_status_t 613 */ 614enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn, 615 struct ecore_ptt *p_ptt, 616 bool b_up); 617 618/** 619 * @brief Get the management firmware version value 620 * 621 * @param p_hwfn 622 * @param p_ptt 623 * @param p_mfw_ver - mfw version value 624 * @param p_running_bundle_id - image id in nvram; Optional. 625 * 626 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 627 */ 628enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn, 629 struct ecore_ptt *p_ptt, 630 u32 *p_mfw_ver, 631 u32 *p_running_bundle_id); 632 633/** 634 * @brief Get the MBI version value 635 * 636 * @param p_hwfn 637 * @param p_ptt 638 * @param p_mbi_ver - A pointer to a variable to be filled with the MBI version. 639 * 640 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 641 */ 642enum _ecore_status_t ecore_mcp_get_mbi_ver(struct ecore_hwfn *p_hwfn, 643 struct ecore_ptt *p_ptt, 644 u32 *p_mbi_ver); 645 646/** 647 * @brief Get media type value of the port. 648 * 649 * @param p_dev - ecore dev pointer 650 * @param p_ptt 651 * @param mfw_ver - media type value 652 * 653 * @return enum _ecore_status_t - 654 * ECORE_SUCCESS - Operation was successful. 655 * ECORE_BUSY - Operation failed 656 */ 657enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn, 658 struct ecore_ptt *p_ptt, 659 u32 *media_type); 660 661/** 662 * @brief Get transciever data of the port. 663 * 664 * @param p_dev - ecore dev pointer 665 * @param p_ptt 666 * @param p_transciever_type - media type value 667 * 668 * @return enum _ecore_status_t - 669 * ECORE_SUCCESS - Operation was successful. 670 * ECORE_BUSY - Operation failed 671 */ 672enum _ecore_status_t ecore_mcp_get_transceiver_data(struct ecore_hwfn *p_hwfn, 673 struct ecore_ptt *p_ptt, 674 u32 *p_tranceiver_type); 675 676/** 677 * @brief Get transciever supported speed mask. 678 * 679 * @param p_dev - ecore dev pointer 680 * @param p_ptt 681 * @param p_speed_mask - Bit mask of all supported speeds. 682 * 683 * @return enum _ecore_status_t - 684 * ECORE_SUCCESS - Operation was successful. 685 * ECORE_BUSY - Operation failed 686 */ 687 688enum _ecore_status_t ecore_mcp_trans_speed_mask(struct ecore_hwfn *p_hwfn, 689 struct ecore_ptt *p_ptt, 690 u32 *p_speed_mask); 691 692/** 693 * @brief Get board configuration. 694 * 695 * @param p_dev - ecore dev pointer 696 * @param p_ptt 697 * @param p_board_config - Board config. 698 * 699 * @return enum _ecore_status_t - 700 * ECORE_SUCCESS - Operation was successful. 701 * ECORE_BUSY - Operation failed 702 */ 703enum _ecore_status_t ecore_mcp_get_board_config(struct ecore_hwfn *p_hwfn, 704 struct ecore_ptt *p_ptt, 705 u32 *p_board_config); 706 707/** 708 * @brief - Sends a command to the MCP mailbox. 709 * 710 * @param p_hwfn - hw function 711 * @param p_ptt - PTT required for register access 712 * @param cmd - command to be sent to the MCP 713 * @param param - Optional param 714 * @param o_mcp_resp - The MCP response code (exclude sequence) 715 * @param o_mcp_param - Optional parameter provided by the MCP response 716 * 717 * @return enum _ecore_status_t - 718 * ECORE_SUCCESS - operation was successful 719 * ECORE_BUSY - operation failed 720 */ 721enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn, 722 struct ecore_ptt *p_ptt, u32 cmd, u32 param, 723 u32 *o_mcp_resp, u32 *o_mcp_param); 724 725/** 726 * @brief - drains the nig, allowing completion to pass in case of pauses. 727 * (Should be called only from sleepable context) 728 * 729 * @param p_hwfn 730 * @param p_ptt 731 */ 732enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn, 733 struct ecore_ptt *p_ptt); 734 735#ifndef LINUX_REMOVE 736/** 737 * @brief - return the mcp function info of the hw function 738 * 739 * @param p_hwfn 740 * 741 * @returns pointer to mcp function info 742 */ 743const struct ecore_mcp_function_info 744*ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn); 745#endif 746 747#ifndef LINUX_REMOVE 748/** 749 * @brief - count number of function with a matching personality on engine. 750 * 751 * @param p_hwfn 752 * @param p_ptt 753 * @param personalities - a bitmask of ecore_pci_personality values 754 * 755 * @returns the count of all devices on engine whose personality match one of 756 * the bitsmasks. 757 */ 758int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn, 759 struct ecore_ptt *p_ptt, 760 u32 personalities); 761#endif 762 763/** 764 * @brief Get the flash size value 765 * 766 * @param p_hwfn 767 * @param p_ptt 768 * @param p_flash_size - flash size in bytes to be filled. 769 * 770 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 771 */ 772enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn, 773 struct ecore_ptt *p_ptt, 774 u32 *p_flash_size); 775 776/** 777 * @brief Send driver version to MFW 778 * 779 * @param p_hwfn 780 * @param p_ptt 781 * @param version - Version value 782 * @param name - Protocol driver name 783 * 784 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 785 */ 786enum _ecore_status_t 787ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 788 struct ecore_mcp_drv_version *p_ver); 789 790/** 791 * @brief Read the MFW process kill counter 792 * 793 * @param p_hwfn 794 * @param p_ptt 795 * 796 * @return u32 797 */ 798u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn, 799 struct ecore_ptt *p_ptt); 800 801/** 802 * @brief Trigger a recovery process 803 * 804 * @param p_hwfn 805 * @param p_ptt 806 * 807 * @return enum _ecore_status_t 808 */ 809enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn, 810 struct ecore_ptt *p_ptt); 811 812/** 813 * @brief A recovery handler must call this function as its first step. 814 * It is assumed that the handler is not run from an interrupt context. 815 * 816 * @param p_dev 817 * @param p_ptt 818 * 819 * @return enum _ecore_status_t 820 */ 821enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev); 822 823/** 824 * @brief Notify MFW about the change in base device properties 825 * 826 * @param p_hwfn 827 * @param p_ptt 828 * @param client - ecore client type 829 * 830 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 831 */ 832enum _ecore_status_t 833ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn, 834 struct ecore_ptt *p_ptt, 835 enum ecore_ov_client client); 836 837/** 838 * @brief Notify MFW about the driver state 839 * 840 * @param p_hwfn 841 * @param p_ptt 842 * @param drv_state - Driver state 843 * 844 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 845 */ 846enum _ecore_status_t 847ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn, 848 struct ecore_ptt *p_ptt, 849 enum ecore_ov_driver_state drv_state); 850 851/** 852 * @brief Read NPIV settings form the MFW 853 * 854 * @param p_hwfn 855 * @param p_ptt 856 * @param p_table - Array to hold the FC NPIV data. Client need allocate the 857 * required buffer. The field 'count' specifies number of NPIV 858 * entries. A value of 0 means the table was not populated. 859 * 860 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 861 */ 862enum _ecore_status_t 863ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 864 struct ecore_fc_npiv_tbl *p_table); 865 866/** 867 * @brief Send MTU size to MFW 868 * 869 * @param p_hwfn 870 * @param p_ptt 871 * @param mtu - MTU size 872 * 873 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 874 */ 875enum _ecore_status_t ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn, 876 struct ecore_ptt *p_ptt, u16 mtu); 877 878/** 879 * @brief Send MAC address to MFW 880 * 881 * @param p_hwfn 882 * @param p_ptt 883 * @param mac - MAC address 884 * 885 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 886 */ 887enum _ecore_status_t 888ecore_mcp_ov_update_mac(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 889 u8 *mac); 890 891/** 892 * @brief Send WOL mode to MFW 893 * 894 * @param p_hwfn 895 * @param p_ptt 896 * @param wol - WOL mode 897 * 898 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 899 */ 900enum _ecore_status_t 901ecore_mcp_ov_update_wol(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 902 enum ecore_ov_wol wol); 903 904/** 905 * @brief Set LED status 906 * 907 * @param p_hwfn 908 * @param p_ptt 909 * @param mode - LED mode 910 * 911 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 912 */ 913enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn, 914 struct ecore_ptt *p_ptt, 915 enum ecore_led_mode mode); 916 917/** 918 * @brief Set secure mode 919 * 920 * @param p_dev 921 * @param addr - nvm offset 922 * 923 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 924 */ 925enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev, 926 u32 addr); 927 928/** 929 * @brief Write to phy 930 * 931 * @param p_dev 932 * @param addr - nvm offset 933 * @param cmd - nvm command 934 * @param p_buf - nvm write buffer 935 * @param len - buffer len 936 * 937 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 938 */ 939enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd, 940 u32 addr, u8 *p_buf, u32 len); 941 942/** 943 * @brief Write to nvm 944 * 945 * @param p_dev 946 * @param addr - nvm offset 947 * @param cmd - nvm command 948 * @param p_buf - nvm write buffer 949 * @param len - buffer len 950 * 951 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 952 */ 953enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd, 954 u32 addr, u8 *p_buf, u32 len); 955 956/** 957 * @brief Put file begin 958 * 959 * @param p_dev 960 * @param addr - nvm offset 961 * 962 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 963 */ 964enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev, 965 u32 addr); 966 967/** 968 * @brief Delete file 969 * 970 * @param p_dev 971 * @param addr - nvm offset 972 * 973 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 974 */ 975enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, 976 u32 addr); 977 978/** 979 * @brief Check latest response 980 * 981 * @param p_dev 982 * @param p_buf - nvm write buffer 983 * 984 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 985 */ 986enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf); 987 988/** 989 * @brief Read from phy 990 * 991 * @param p_dev 992 * @param addr - nvm offset 993 * @param cmd - nvm command 994 * @param p_buf - nvm read buffer 995 * @param len - buffer len 996 * 997 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 998 */ 999enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd, 1000 u32 addr, u8 *p_buf, u32 len); 1001 1002/** 1003 * @brief Read from nvm 1004 * 1005 * @param p_dev 1006 * @param addr - nvm offset 1007 * @param p_buf - nvm read buffer 1008 * @param len - buffer len 1009 * 1010 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1011 */ 1012enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr, 1013 u8 *p_buf, u32 len); 1014 1015struct ecore_nvm_image_att { 1016 u32 start_addr; 1017 u32 length; 1018}; 1019 1020/** 1021 * @brief Allows reading a whole nvram image 1022 * 1023 * @param p_hwfn 1024 * @param p_ptt 1025 * @param image_id - image to get attributes for 1026 * @param p_image_att - image attributes structure into which to fill data 1027 * 1028 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1029 */ 1030enum _ecore_status_t 1031ecore_mcp_get_nvm_image_att(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1032 enum ecore_nvm_images image_id, 1033 struct ecore_nvm_image_att *p_image_att); 1034 1035/** 1036 * @brief Allows reading a whole nvram image 1037 * 1038 * @param p_hwfn 1039 * @param p_ptt 1040 * @param image_id - image requested for reading 1041 * @param p_buffer - allocated buffer into which to fill data 1042 * @param buffer_len - length of the allocated buffer. 1043 * 1044 * @return ECORE_SUCCESS iff p_buffer now contains the nvram image. 1045 */ 1046enum _ecore_status_t ecore_mcp_get_nvm_image(struct ecore_hwfn *p_hwfn, 1047 struct ecore_ptt *p_ptt, 1048 enum ecore_nvm_images image_id, 1049 u8 *p_buffer, u32 buffer_len); 1050 1051/** 1052 * @brief - Sends an NVM write command request to the MFW with 1053 * payload. 1054 * 1055 * @param p_hwfn 1056 * @param p_ptt 1057 * @param cmd - Command: Either DRV_MSG_CODE_NVM_WRITE_NVRAM or 1058 * DRV_MSG_CODE_NVM_PUT_FILE_DATA 1059 * @param param - [0:23] - Offset [24:31] - Size 1060 * @param o_mcp_resp - MCP response 1061 * @param o_mcp_param - MCP response param 1062 * @param i_txn_size - Buffer size 1063 * @param i_buf - Pointer to the buffer 1064 * 1065 * @param return ECORE_SUCCESS upon success. 1066 */ 1067enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn, 1068 struct ecore_ptt *p_ptt, 1069 u32 cmd, 1070 u32 param, 1071 u32 *o_mcp_resp, 1072 u32 *o_mcp_param, 1073 u32 i_txn_size, 1074 u32 *i_buf); 1075 1076/** 1077 * @brief - Sends an NVM read command request to the MFW to get 1078 * a buffer. 1079 * 1080 * @param p_hwfn 1081 * @param p_ptt 1082 * @param cmd - Command: DRV_MSG_CODE_NVM_GET_FILE_DATA or 1083 * DRV_MSG_CODE_NVM_READ_NVRAM commands 1084 * @param param - [0:23] - Offset [24:31] - Size 1085 * @param o_mcp_resp - MCP response 1086 * @param o_mcp_param - MCP response param 1087 * @param o_txn_size - Buffer size output 1088 * @param o_buf - Pointer to the buffer returned by the MFW. 1089 * 1090 * @param return ECORE_SUCCESS upon success. 1091 */ 1092enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn, 1093 struct ecore_ptt *p_ptt, 1094 u32 cmd, 1095 u32 param, 1096 u32 *o_mcp_resp, 1097 u32 *o_mcp_param, 1098 u32 *o_txn_size, 1099 u32 *o_buf); 1100 1101/** 1102 * @brief Read from sfp 1103 * 1104 * @param p_hwfn - hw function 1105 * @param p_ptt - PTT required for register access 1106 * @param port - transceiver port 1107 * @param addr - I2C address 1108 * @param offset - offset in sfp 1109 * @param len - buffer length 1110 * @param p_buf - buffer to read into 1111 * 1112 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1113 */ 1114enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn, 1115 struct ecore_ptt *p_ptt, 1116 u32 port, u32 addr, u32 offset, 1117 u32 len, u8 *p_buf); 1118 1119/** 1120 * @brief Write to sfp 1121 * 1122 * @param p_hwfn - hw function 1123 * @param p_ptt - PTT required for register access 1124 * @param port - transceiver port 1125 * @param addr - I2C address 1126 * @param offset - offset in sfp 1127 * @param len - buffer length 1128 * @param p_buf - buffer to write from 1129 * 1130 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1131 */ 1132enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn, 1133 struct ecore_ptt *p_ptt, 1134 u32 port, u32 addr, u32 offset, 1135 u32 len, u8 *p_buf); 1136 1137/** 1138 * @brief Gpio read 1139 * 1140 * @param p_hwfn - hw function 1141 * @param p_ptt - PTT required for register access 1142 * @param gpio - gpio number 1143 * @param gpio_val - value read from gpio 1144 * 1145 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1146 */ 1147enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn, 1148 struct ecore_ptt *p_ptt, 1149 u16 gpio, u32 *gpio_val); 1150 1151/** 1152 * @brief Gpio write 1153 * 1154 * @param p_hwfn - hw function 1155 * @param p_ptt - PTT required for register access 1156 * @param gpio - gpio number 1157 * @param gpio_val - value to write to gpio 1158 * 1159 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1160 */ 1161enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn, 1162 struct ecore_ptt *p_ptt, 1163 u16 gpio, u16 gpio_val); 1164 1165/** 1166 * @brief Gpio get information 1167 * 1168 * @param p_hwfn - hw function 1169 * @param p_ptt - PTT required for register access 1170 * @param gpio - gpio number 1171 * @param gpio_direction - gpio is output (0) or input (1) 1172 * @param gpio_ctrl - gpio control is uninitialized (0), 1173 * path 0 (1), path 1 (2) or shared(3) 1174 * 1175 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1176 */ 1177enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn, 1178 struct ecore_ptt *p_ptt, 1179 u16 gpio, u32 *gpio_direction, 1180 u32 *gpio_ctrl); 1181 1182/** 1183 * @brief Bist register test 1184 * 1185 * @param p_hwfn - hw function 1186 * @param p_ptt - PTT required for register access 1187 * 1188 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1189 */ 1190enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn, 1191 struct ecore_ptt *p_ptt); 1192 1193/** 1194 * @brief Bist clock test 1195 * 1196 * @param p_hwfn - hw function 1197 * @param p_ptt - PTT required for register access 1198 * 1199 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1200 */ 1201enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn, 1202 struct ecore_ptt *p_ptt); 1203 1204/** 1205 * @brief Bist nvm test - get number of images 1206 * 1207 * @param p_hwfn - hw function 1208 * @param p_ptt - PTT required for register access 1209 * @param num_images - number of images if operation was 1210 * successful. 0 if not. 1211 * 1212 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1213 */ 1214enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(struct ecore_hwfn *p_hwfn, 1215 struct ecore_ptt *p_ptt, 1216 u32 *num_images); 1217 1218/** 1219 * @brief Bist nvm test - get image attributes by index 1220 * 1221 * @param p_hwfn - hw function 1222 * @param p_ptt - PTT required for register access 1223 * @param p_image_att - Attributes of image 1224 * @param image_index - Index of image to get information for 1225 * 1226 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1227 */ 1228enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(struct ecore_hwfn *p_hwfn, 1229 struct ecore_ptt *p_ptt, 1230 struct bist_nvm_image_att *p_image_att, 1231 u32 image_index); 1232 1233/** 1234 * @brief ecore_mcp_get_temperature_info - get the status of the temperature 1235 * sensors 1236 * 1237 * @param p_hwfn - hw function 1238 * @param p_ptt - PTT required for register access 1239 * @param p_temp_status - A pointer to an ecore_temperature_info structure to 1240 * be filled with the temperature data 1241 * 1242 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1243 */ 1244enum _ecore_status_t 1245ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn, 1246 struct ecore_ptt *p_ptt, 1247 struct ecore_temperature_info *p_temp_info); 1248 1249/** 1250 * @brief Get MBA versions - get MBA sub images versions 1251 * 1252 * @param p_hwfn - hw function 1253 * @param p_ptt - PTT required for register access 1254 * @param p_mba_vers - MBA versions array to fill 1255 * 1256 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1257 */ 1258enum _ecore_status_t ecore_mcp_get_mba_versions( 1259 struct ecore_hwfn *p_hwfn, 1260 struct ecore_ptt *p_ptt, 1261 struct ecore_mba_vers *p_mba_vers); 1262 1263/** 1264 * @brief Count memory ecc events 1265 * 1266 * @param p_hwfn - hw function 1267 * @param p_ptt - PTT required for register access 1268 * @param num_events - number of memory ecc events 1269 * 1270 * @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful. 1271 */ 1272enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn, 1273 struct ecore_ptt *p_ptt, 1274 u64 *num_events); 1275 1276struct ecore_mdump_info { 1277 u32 reason; 1278 u32 version; 1279 u32 config; 1280 u32 epoch; 1281 u32 num_of_logs; 1282 u32 valid_logs; 1283}; 1284 1285/** 1286 * @brief - Gets the MFW crash dump configuration and logs info. 1287 * 1288 * @param p_hwfn 1289 * @param p_ptt 1290 * @param p_mdump_info 1291 * 1292 * @param return ECORE_SUCCESS upon success. 1293 */ 1294enum _ecore_status_t 1295ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1296 struct ecore_mdump_info *p_mdump_info); 1297 1298/** 1299 * @brief - Clears the MFW crash dump logs. 1300 * 1301 * @param p_hwfn 1302 * @param p_ptt 1303 * 1304 * @param return ECORE_SUCCESS upon success. 1305 */ 1306enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn, 1307 struct ecore_ptt *p_ptt); 1308 1309/** 1310 * @brief - Clear the mdump retained data. 1311 * 1312 * @param p_hwfn 1313 * @param p_ptt 1314 * 1315 * @param return ECORE_SUCCESS upon success. 1316 */ 1317enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn, 1318 struct ecore_ptt *p_ptt); 1319 1320/** 1321 * @brief - Gets the LLDP MAC address. 1322 * 1323 * @param p_hwfn 1324 * @param p_ptt 1325 * @param lldp_mac_addr - a buffer to be filled with the read LLDP MAC address. 1326 * 1327 * @param return ECORE_SUCCESS upon success. 1328 */ 1329enum _ecore_status_t ecore_mcp_get_lldp_mac(struct ecore_hwfn *p_hwfn, 1330 struct ecore_ptt *p_ptt, 1331 u8 lldp_mac_addr[ETH_ALEN]); 1332 1333/** 1334 * @brief - Sets the LLDP MAC address. 1335 * 1336 * @param p_hwfn 1337 * @param p_ptt 1338 * @param lldp_mac_addr - a buffer with the LLDP MAC address to be written. 1339 * 1340 * @param return ECORE_SUCCESS upon success. 1341 */ 1342enum _ecore_status_t ecore_mcp_set_lldp_mac(struct ecore_hwfn *p_hwfn, 1343 struct ecore_ptt *p_ptt, 1344 u8 lldp_mac_addr[ETH_ALEN]); 1345 1346/** 1347 * @brief - Processes the TLV request from MFW i.e., get the required TLV info 1348 * from the ecore client and send it to the MFW. 1349 * 1350 * @param p_hwfn 1351 * @param p_ptt 1352 * 1353 * @param return ECORE_SUCCESS upon success. 1354 */ 1355enum _ecore_status_t ecore_mfw_process_tlv_req(struct ecore_hwfn *p_hwfn, 1356 struct ecore_ptt *p_ptt); 1357 1358/** 1359 * @brief - Update fcoe vlan id value to the MFW. 1360 * 1361 * @param p_hwfn 1362 * @param p_ptt 1363 * @param vlan - fcoe vlan 1364 * 1365 * @param return ECORE_SUCCESS upon success. 1366 */ 1367enum _ecore_status_t 1368ecore_mcp_update_fcoe_cvid(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1369 u16 vlan); 1370 1371/** 1372 * @brief - Update fabric name (wwn) value to the MFW. 1373 * 1374 * @param p_hwfn 1375 * @param p_ptt 1376 * @param wwn - world wide name 1377 * 1378 * @param return ECORE_SUCCESS upon success. 1379 */ 1380enum _ecore_status_t 1381ecore_mcp_update_fcoe_fabric_name(struct ecore_hwfn *p_hwfn, 1382 struct ecore_ptt *p_ptt, u8 *wwn); 1383 1384/** 1385 * @brief - Return whether management firmware support smart AN 1386 * 1387 * @param p_hwfn 1388 * 1389 * @return bool - true if feature is supported. 1390 */ 1391bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn); 1392 1393/** 1394 * @brief - Return whether management firmware support setting of 1395 * PCI relaxed ordering. 1396 * 1397 * @param p_hwfn 1398 * 1399 * @return bool - true if feature is supported. 1400 */ 1401bool ecore_mcp_rlx_odr_supported(struct ecore_hwfn *p_hwfn); 1402#endif 1403