1/*
2 * Copyright (c) 2017-2018 Cavium, Inc.
3 * All rights reserved.
4 *
5 *  Redistribution and use in source and binary forms, with or without
6 *  modification, are permitted provided that the following conditions
7 *  are met:
8 *
9 *  1. Redistributions of source code must retain the above copyright
10 *     notice, this list of conditions and the following disclaimer.
11 *  2. Redistributions in binary form must reproduce the above copyright
12 *     notice, this list of conditions and the following disclaimer in the
13 *     documentation and/or other materials provided with the distribution.
14 *
15 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 *  POSSIBILITY OF SUCH DAMAGE.
26 *
27 */
28
29#ifndef __ECORE_HSI_RDMA__
30#define __ECORE_HSI_RDMA__
31/************************************************************************/
32/* Add include to common rdma target for both eCore and protocol rdma driver */
33/************************************************************************/
34#include "rdma_common.h"
35
36/*
37 * The rdma task context of Mstorm
38 */
39struct ystorm_rdma_task_st_ctx
40{
41	struct regpair temp[4];
42};
43
44struct e4_ystorm_rdma_task_ag_ctx
45{
46	u8 reserved /* cdu_validation */;
47	u8 byte1 /* state */;
48	__le16 msem_ctx_upd_seq /* icid */;
49	u8 flags0;
50#define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
51#define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
52#define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
53#define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
54#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
55#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT            5
56#define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK            0x1 /* bit2 */
57#define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT           6
58#define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK     0x1 /* bit3 */
59#define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT    7
60	u8 flags1;
61#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK              0x3 /* cf0 */
62#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT             0
63#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK              0x3 /* cf1 */
64#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT             2
65#define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK       0x3 /* cf2special */
66#define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT      4
67#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
68#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT           6
69#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
70#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT           7
71	u8 flags2;
72#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK             0x1 /* bit4 */
73#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT            0
74#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
75#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT         1
76#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
77#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT         2
78#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
79#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT         3
80#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
81#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT         4
82#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
83#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT         5
84#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
85#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT         6
86#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
87#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT         7
88	u8 key /* byte2 */;
89	__le32 mw_cnt /* reg0 */;
90	u8 ref_cnt_seq /* byte3 */;
91	u8 ctx_upd_seq /* byte4 */;
92	__le16 dif_flags /* word1 */;
93	__le16 tx_ref_count /* word2 */;
94	__le16 last_used_ltid /* word3 */;
95	__le16 parent_mr_lo /* word4 */;
96	__le16 parent_mr_hi /* word5 */;
97	__le32 fbo_lo /* reg1 */;
98	__le32 fbo_hi /* reg2 */;
99};
100
101struct e4_mstorm_rdma_task_ag_ctx
102{
103	u8 reserved /* cdu_validation */;
104	u8 byte1 /* state */;
105	__le16 icid /* icid */;
106	u8 flags0;
107#define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
108#define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
109#define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
110#define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
111#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
112#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT            5
113#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK             0x1 /* bit2 */
114#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT            6
115#define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK     0x1 /* bit3 */
116#define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT    7
117	u8 flags1;
118#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK              0x3 /* cf0 */
119#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT             0
120#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK              0x3 /* cf1 */
121#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT             2
122#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK              0x3 /* cf2 */
123#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT             4
124#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
125#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT           6
126#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
127#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT           7
128	u8 flags2;
129#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK            0x1 /* cf2en */
130#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT           0
131#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
132#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT         1
133#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
134#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT         2
135#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
136#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT         3
137#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
138#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT         4
139#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
140#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT         5
141#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
142#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT         6
143#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
144#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT         7
145	u8 key /* byte2 */;
146	__le32 mw_cnt /* reg0 */;
147	u8 ref_cnt_seq /* byte3 */;
148	u8 ctx_upd_seq /* byte4 */;
149	__le16 dif_flags /* word1 */;
150	__le16 tx_ref_count /* word2 */;
151	__le16 last_used_ltid /* word3 */;
152	__le16 parent_mr_lo /* word4 */;
153	__le16 parent_mr_hi /* word5 */;
154	__le32 fbo_lo /* reg1 */;
155	__le32 fbo_hi /* reg2 */;
156};
157
158/*
159 * The roce task context of Mstorm
160 */
161struct mstorm_rdma_task_st_ctx
162{
163	struct regpair temp[4];
164};
165
166/*
167 * The roce task context of Ustorm
168 */
169struct ustorm_rdma_task_st_ctx
170{
171	struct regpair temp[2];
172};
173
174struct e4_ustorm_rdma_task_ag_ctx
175{
176	u8 reserved /* cdu_validation */;
177	u8 byte1 /* state */;
178	__le16 icid /* icid */;
179	u8 flags0;
180#define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF /* connection_type */
181#define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
182#define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1 /* exist_in_qm0 */
183#define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
184#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK          0x1 /* exist_in_qm1 */
185#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT         5
186#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK     0x3 /* timer0cf */
187#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT    6
188	u8 flags1;
189#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK   0x3 /* timer1cf */
190#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT  0
191#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK           0x3 /* timer2cf */
192#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT          2
193#define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK                     0x3 /* timer_stop_all */
194#define E4_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT                    4
195#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK            0x3 /* cf4 */
196#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT           6
197	u8 flags2;
198#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK  0x1 /* cf0en */
199#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
200#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK               0x1 /* cf1en */
201#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT              1
202#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK               0x1 /* cf2en */
203#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT              2
204#define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK                   0x1 /* cf3en */
205#define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT                  3
206#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK         0x1 /* cf4en */
207#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT        4
208#define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK                 0x1 /* rule0en */
209#define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT                5
210#define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK                 0x1 /* rule1en */
211#define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT                6
212#define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK                 0x1 /* rule2en */
213#define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT                7
214	u8 flags3;
215#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK                 0x1 /* rule3en */
216#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT                0
217#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK                 0x1 /* rule4en */
218#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT                1
219#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK                 0x1 /* rule5en */
220#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT                2
221#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK                 0x1 /* rule6en */
222#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT                3
223#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK          0xF /* nibble1 */
224#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT         4
225	__le32 dif_err_intervals /* reg0 */;
226	__le32 dif_error_1st_interval /* reg1 */;
227	__le32 reg2 /* reg2 */;
228	__le32 dif_runt_value /* reg3 */;
229	__le32 reg4 /* reg4 */;
230	__le32 reg5 /* reg5 */;
231};
232
233/*
234 * RDMA task context
235 */
236struct e4_rdma_task_context
237{
238	struct ystorm_rdma_task_st_ctx ystorm_st_context /* ystorm storm context */;
239	struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */;
240	struct tdif_task_context tdif_context /* tdif context */;
241	struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */;
242	struct mstorm_rdma_task_st_ctx mstorm_st_context /* mstorm storm context */;
243	struct rdif_task_context rdif_context /* rdif context */;
244	struct ustorm_rdma_task_st_ctx ustorm_st_context /* ustorm storm context */;
245	struct regpair ustorm_st_padding[2] /* padding */;
246	struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
247};
248
249struct e5_ystorm_rdma_task_ag_ctx
250{
251	u8 reserved /* cdu_validation */;
252	u8 byte1 /* state_and_core_id */;
253	__le16 msem_ctx_upd_seq /* icid */;
254	u8 flags0;
255#define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
256#define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
257#define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
258#define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
259#define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
260#define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT            5
261#define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK            0x1 /* bit2 */
262#define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT           6
263#define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK             0x1 /* bit3 */
264#define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT            7
265	u8 flags1;
266#define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK              0x3 /* cf0 */
267#define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT             0
268#define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK              0x3 /* cf1 */
269#define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT             2
270#define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK       0x3 /* cf2special */
271#define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT      4
272#define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
273#define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT           6
274#define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
275#define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT           7
276	u8 flags2;
277#define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK             0x1 /* bit4 */
278#define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT            0
279#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
280#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT         1
281#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
282#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT         2
283#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
284#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT         3
285#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
286#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT         4
287#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
288#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT         5
289#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
290#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT         6
291#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
292#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT         7
293	u8 flags3;
294#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK     0x1 /* bit5 */
295#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT    0
296#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK     0x3 /* cf3 */
297#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT    1
298#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK     0x3 /* cf4 */
299#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT    3
300#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK     0x1 /* cf3en */
301#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT    5
302#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK     0x1 /* cf4en */
303#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT    6
304#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK     0x1 /* rule7en */
305#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT    7
306	__le32 mw_cnt /* reg0 */;
307	u8 key /* byte2 */;
308	u8 ref_cnt_seq /* byte3 */;
309	u8 ctx_upd_seq /* byte4 */;
310	u8 e4_reserved7 /* byte5 */;
311	__le16 dif_flags /* word1 */;
312	__le16 tx_ref_count /* word2 */;
313	__le16 last_used_ltid /* word3 */;
314	__le16 parent_mr_lo /* word4 */;
315	__le16 parent_mr_hi /* word5 */;
316	__le16 e4_reserved8 /* word6 */;
317	__le32 fbo_lo /* reg1 */;
318};
319
320struct e5_mstorm_rdma_task_ag_ctx
321{
322	u8 reserved /* cdu_validation */;
323	u8 byte1 /* state_and_core_id */;
324	__le16 icid /* icid */;
325	u8 flags0;
326#define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
327#define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
328#define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
329#define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
330#define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
331#define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT            5
332#define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK             0x1 /* bit2 */
333#define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT            6
334#define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK             0x1 /* bit3 */
335#define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT            7
336	u8 flags1;
337#define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK              0x3 /* cf0 */
338#define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT             0
339#define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK              0x3 /* cf1 */
340#define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT             2
341#define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK              0x3 /* cf2 */
342#define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT             4
343#define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
344#define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT           6
345#define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
346#define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT           7
347	u8 flags2;
348#define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK            0x1 /* cf2en */
349#define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT           0
350#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
351#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT         1
352#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
353#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT         2
354#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
355#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT         3
356#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
357#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT         4
358#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
359#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT         5
360#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
361#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT         6
362#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
363#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT         7
364	u8 flags3;
365#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK     0x1 /* bit4 */
366#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT    0
367#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK     0x3 /* cf3 */
368#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT    1
369#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK     0x3 /* cf4 */
370#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT    3
371#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK     0x1 /* cf3en */
372#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT    5
373#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK     0x1 /* cf4en */
374#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT    6
375#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK     0x1 /* rule7en */
376#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT    7
377	__le32 mw_cnt /* reg0 */;
378	u8 key /* byte2 */;
379	u8 ref_cnt_seq /* byte3 */;
380	u8 ctx_upd_seq /* byte4 */;
381	u8 e4_reserved7 /* byte5 */;
382	__le16 dif_flags /* regpair0 */;
383	__le16 tx_ref_count /* word2 */;
384	__le16 last_used_ltid /* word3 */;
385	__le16 parent_mr_lo /* word4 */;
386	__le16 parent_mr_hi /* regpair1 */;
387	__le16 e4_reserved8 /* word6 */;
388	__le32 fbo_lo /* reg1 */;
389};
390
391struct e5_ustorm_rdma_task_ag_ctx
392{
393	u8 reserved /* cdu_validation */;
394	u8 byte1 /* state_and_core_id */;
395	__le16 icid /* icid */;
396	u8 flags0;
397#define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF /* connection_type */
398#define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
399#define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1 /* exist_in_qm0 */
400#define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
401#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK          0x1 /* exist_in_qm1 */
402#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT         5
403#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK     0x3 /* timer0cf */
404#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT    6
405	u8 flags1;
406#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK   0x3 /* timer1cf */
407#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT  0
408#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK           0x3 /* timer2cf */
409#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT          2
410#define E5_USTORM_RDMA_TASK_AG_CTX_CF3_MASK                     0x3 /* timer_stop_all */
411#define E5_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT                    4
412#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK            0x3 /* dif_error_cf */
413#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT           6
414	u8 flags2;
415#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK  0x1 /* cf0en */
416#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
417#define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK               0x1 /* cf1en */
418#define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT              1
419#define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK               0x1 /* cf2en */
420#define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT              2
421#define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK                   0x1 /* cf3en */
422#define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT                  3
423#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK         0x1 /* cf4en */
424#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT        4
425#define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK                 0x1 /* rule0en */
426#define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT                5
427#define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK                 0x1 /* rule1en */
428#define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT                6
429#define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK                 0x1 /* rule2en */
430#define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT                7
431	u8 flags3;
432#define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK                 0x1 /* rule3en */
433#define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT                0
434#define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK                 0x1 /* rule4en */
435#define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT                1
436#define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK                 0x1 /* rule5en */
437#define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT                2
438#define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK                 0x1 /* rule6en */
439#define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT                3
440#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK            0x1 /* bit2 */
441#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT           4
442#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK            0x1 /* bit3 */
443#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT           5
444#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK            0x1 /* bit4 */
445#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT           6
446#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK            0x1 /* rule7en */
447#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT           7
448	u8 flags4;
449#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK            0x3 /* cf5 */
450#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT           0
451#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK            0x1 /* cf5en */
452#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT           2
453#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_MASK            0x1 /* rule8en */
454#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_SHIFT           3
455#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK          0xF /* dif_error_type */
456#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT         4
457	u8 byte2 /* byte2 */;
458	u8 byte3 /* byte3 */;
459	u8 e4_reserved8 /* byte4 */;
460	__le32 dif_err_intervals /* dif_err_intervals */;
461	__le32 dif_error_1st_interval /* dif_error_1st_interval */;
462	__le32 reg2 /* reg2 */;
463	__le32 dif_runt_value /* reg3 */;
464	__le32 reg4 /* reg4 */;
465};
466
467/*
468 * RDMA task context
469 */
470struct e5_rdma_task_context
471{
472	struct ystorm_rdma_task_st_ctx ystorm_st_context /* ystorm storm context */;
473	struct e5_ystorm_rdma_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */;
474	struct tdif_task_context tdif_context /* tdif context */;
475	struct e5_mstorm_rdma_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */;
476	struct mstorm_rdma_task_st_ctx mstorm_st_context /* mstorm storm context */;
477	struct rdif_task_context rdif_context /* rdif context */;
478	struct ustorm_rdma_task_st_ctx ustorm_st_context /* ustorm storm context */;
479	struct regpair ustorm_st_padding[2] /* padding */;
480	struct e5_ustorm_rdma_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
481};
482
483/*
484 * rdma function init ramrod data
485 */
486struct rdma_close_func_ramrod_data
487{
488	u8 cnq_start_offset;
489	u8 num_cnqs;
490	u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
491	u8 vf_valid;
492	u8 reserved[4];
493};
494
495/*
496 * rdma function init CNQ parameters
497 */
498struct rdma_cnq_params
499{
500	__le16 sb_num /* Status block number used by the queue */;
501	u8 sb_index /* Status block index used by the queue */;
502	u8 num_pbl_pages /* Number of pages in the PBL allocated for this queue */;
503	__le32 reserved;
504	struct regpair pbl_base_addr /* Address to the first entry of the queue PBL */;
505	__le16 queue_zone_num /* Queue Zone ID used for CNQ consumer update */;
506	u8 reserved1[6];
507};
508
509/*
510 * rdma create cq ramrod data
511 */
512struct rdma_create_cq_ramrod_data
513{
514	struct regpair cq_handle;
515	struct regpair pbl_addr;
516	__le32 max_cqes;
517	__le16 pbl_num_pages;
518	__le16 dpi;
519	u8 is_two_level_pbl;
520	u8 cnq_id;
521	u8 pbl_log_page_size;
522	u8 toggle_bit;
523	__le16 int_timeout /* Timeout used for interrupt moderation */;
524	__le16 reserved1;
525};
526
527/*
528 * rdma deregister tid ramrod data
529 */
530struct rdma_deregister_tid_ramrod_data
531{
532	__le32 itid;
533	__le32 reserved;
534};
535
536/*
537 * rdma destroy cq output params
538 */
539struct rdma_destroy_cq_output_params
540{
541	__le16 cnq_num /* Sequence number of completion notification sent for the cq on the associated CNQ */;
542	__le16 reserved0;
543	__le32 reserved1;
544};
545
546/*
547 * rdma destroy cq ramrod data
548 */
549struct rdma_destroy_cq_ramrod_data
550{
551	struct regpair output_params_addr;
552};
553
554/*
555 * RDMA slow path EQ cmd IDs
556 */
557enum rdma_event_opcode
558{
559	RDMA_EVENT_UNUSED,
560	RDMA_EVENT_FUNC_INIT,
561	RDMA_EVENT_FUNC_CLOSE,
562	RDMA_EVENT_REGISTER_MR,
563	RDMA_EVENT_DEREGISTER_MR,
564	RDMA_EVENT_CREATE_CQ,
565	RDMA_EVENT_RESIZE_CQ,
566	RDMA_EVENT_DESTROY_CQ,
567	RDMA_EVENT_CREATE_SRQ,
568	RDMA_EVENT_MODIFY_SRQ,
569	RDMA_EVENT_DESTROY_SRQ,
570	MAX_RDMA_EVENT_OPCODE
571};
572
573/*
574 * RDMA FW return code for slow path ramrods
575 */
576enum rdma_fw_return_code
577{
578	RDMA_RETURN_OK=0,
579	RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
580	RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
581	RDMA_RETURN_RESIZE_CQ_ERR,
582	RDMA_RETURN_NIG_DRAIN_REQ,
583	MAX_RDMA_FW_RETURN_CODE
584};
585
586/*
587 * rdma function init header
588 */
589struct rdma_init_func_hdr
590{
591	u8 cnq_start_offset /* First RDMA CNQ */;
592	u8 num_cnqs /* Number of CNQs */;
593	u8 cq_ring_mode /* 0 for 32 bit cq producer and consumer counters and 1 for 16 bit */;
594	u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
595	u8 vf_valid;
596	u8 relaxed_ordering /* 1 for using relaxed ordering PCI writes */;
597	__le16 first_reg_srq_id /* The SRQ ID of thr first regular (non XRC) SRQ */;
598	__le32 reg_srq_base_addr /* Logical base address of first regular (non XRC) SRQ */;
599	__le32 reserved;
600};
601
602/*
603 * rdma function init ramrod data
604 */
605struct rdma_init_func_ramrod_data
606{
607	struct rdma_init_func_hdr params_header;
608	struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
609};
610
611/*
612 * RDMA ramrod command IDs
613 */
614enum rdma_ramrod_cmd_id
615{
616	RDMA_RAMROD_UNUSED,
617	RDMA_RAMROD_FUNC_INIT,
618	RDMA_RAMROD_FUNC_CLOSE,
619	RDMA_RAMROD_REGISTER_MR,
620	RDMA_RAMROD_DEREGISTER_MR,
621	RDMA_RAMROD_CREATE_CQ,
622	RDMA_RAMROD_RESIZE_CQ,
623	RDMA_RAMROD_DESTROY_CQ,
624	RDMA_RAMROD_CREATE_SRQ,
625	RDMA_RAMROD_MODIFY_SRQ,
626	RDMA_RAMROD_DESTROY_SRQ,
627	MAX_RDMA_RAMROD_CMD_ID
628};
629
630/*
631 * rdma register tid ramrod data
632 */
633struct rdma_register_tid_ramrod_data
634{
635	__le16 flags;
636#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK      0x1F
637#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT     0
638#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK      0x1
639#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT     5
640#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK         0x1
641#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT        6
642#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK             0x1
643#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT            7
644#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK        0x1
645#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT       8
646#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK       0x1
647#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT      9
648#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK      0x1
649#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT     10
650#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK        0x1
651#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT       11
652#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK         0x1
653#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT        12
654#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK     0x1
655#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT    13
656#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK           0x3
657#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT          14
658	u8 flags1;
659#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK  0x1F
660#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
661#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK           0x7
662#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT          5
663	u8 flags2;
664#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK             0x1 /* Bit indicating that this MR is DMA_MR meaning SGEs that use it have the physical address on them */
665#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT            0
666#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK    0x1 /* Bit indicating that this MR has DIF protection enabled. */
667#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT   1
668#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK          0x3F
669#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT         2
670	u8 key;
671	u8 length_hi;
672	u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */;
673	u8 vf_valid;
674	__le16 pd;
675	__le16 reserved2;
676	__le32 length_lo /* lower 32 bits of the registered MR length. */;
677	__le32 itid;
678	__le32 reserved3;
679	struct regpair va;
680	struct regpair pbl_base;
681	struct regpair dif_error_addr /* DIF TX IO writes error information to this location when memory region is invalidated. */;
682	struct regpair dif_runt_addr /* DIF RX IO writes runt value to this location when last RDMA Read of the IO has completed. */;
683	__le32 reserved4[2];
684};
685
686/*
687 * rdma resize cq output params
688 */
689struct rdma_resize_cq_output_params
690{
691	__le32 old_cq_cons /* cq consumer value on old PBL */;
692	__le32 old_cq_prod /* cq producer value on old PBL */;
693};
694
695/*
696 * rdma resize cq ramrod data
697 */
698struct rdma_resize_cq_ramrod_data
699{
700	u8 flags;
701#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK        0x1
702#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT       0
703#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK  0x1
704#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
705#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK          0x3F
706#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT         2
707	u8 pbl_log_page_size;
708	__le16 pbl_num_pages;
709	__le32 max_cqes;
710	struct regpair pbl_addr;
711	struct regpair output_params_addr;
712};
713
714/*
715 * The rdma SRQ context
716 */
717struct rdma_srq_context
718{
719	struct regpair temp[8];
720};
721
722/*
723 * rdma create qp requester ramrod data
724 */
725struct rdma_srq_create_ramrod_data
726{
727	u8 flags;
728#define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK         0x1
729#define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT        0
730#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK  0x1 /* Only applicable when xrc_flag is set */
731#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1
732#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK        0x3F
733#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT       2
734	u8 reserved2;
735	__le16 xrc_domain /* Only applicable when xrc_flag is set */;
736	__le32 xrc_srq_cq_cid /* Only applicable when xrc_flag is set */;
737	struct regpair pbl_base_addr /* SRQ PBL base address */;
738	__le16 pages_in_srq_pbl /* Number of pages in PBL */;
739	__le16 pd_id;
740	struct rdma_srq_id srq_id /* SRQ Index */;
741	__le16 page_size /* Page size in SGEs(16 bytes) elements. Supports up to 2M bytes page size */;
742	__le16 reserved3;
743	__le32 reserved4;
744	struct regpair producers_addr /* SRQ PBL base address */;
745};
746
747/*
748 * rdma create qp requester ramrod data
749 */
750struct rdma_srq_destroy_ramrod_data
751{
752	struct rdma_srq_id srq_id /* SRQ Index */;
753	__le32 reserved;
754};
755
756/*
757 * rdma create qp requester ramrod data
758 */
759struct rdma_srq_modify_ramrod_data
760{
761	struct rdma_srq_id srq_id /* SRQ Index */;
762	__le32 wqe_limit;
763};
764
765/*
766 * RDMA Tid type enumeration (for register_tid ramrod)
767 */
768enum rdma_tid_type
769{
770	RDMA_TID_REGISTERED_MR,
771	RDMA_TID_FMR,
772	RDMA_TID_MW_TYPE1,
773	RDMA_TID_MW_TYPE2A,
774	MAX_RDMA_TID_TYPE
775};
776
777/*
778 * The rdma XRC SRQ context
779 */
780struct rdma_xrc_srq_context
781{
782	struct regpair temp[9];
783};
784
785struct E4XstormRoceConnAgCtxDqExtLdPart
786{
787	u8 reserved0 /* cdu_validation */;
788	u8 state /* state */;
789	u8 flags0;
790#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK      0x1 /* exist_in_qm0 */
791#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT     0
792#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK              0x1 /* exist_in_qm1 */
793#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT             1
794#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK              0x1 /* exist_in_qm2 */
795#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT             2
796#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK      0x1 /* exist_in_qm3 */
797#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT     3
798#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK              0x1 /* bit4 */
799#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT             4
800#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK              0x1 /* cf_array_active */
801#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT             5
802#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK              0x1 /* bit6 */
803#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT             6
804#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK              0x1 /* bit7 */
805#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT             7
806	u8 flags1;
807#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK              0x1 /* bit8 */
808#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT             0
809#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK              0x1 /* bit9 */
810#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT             1
811#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK             0x1 /* bit10 */
812#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT            2
813#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK             0x1 /* bit11 */
814#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT            3
815#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK             0x1 /* bit12 */
816#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT            4
817#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK      0x1 /* bit13 */
818#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT     5
819#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK             0x1 /* bit14 */
820#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT            6
821#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK      0x1 /* bit15 */
822#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT     7
823	u8 flags2;
824#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK               0x3 /* timer0cf */
825#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT              0
826#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK               0x3 /* timer1cf */
827#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT              2
828#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK               0x3 /* timer2cf */
829#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT              4
830#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK               0x3 /* timer_stop_all */
831#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT              6
832	u8 flags3;
833#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK               0x3 /* cf4 */
834#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT              0
835#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK               0x3 /* cf5 */
836#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT              2
837#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK               0x3 /* cf6 */
838#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT              4
839#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK       0x3 /* cf7 */
840#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT      6
841	u8 flags4;
842#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK               0x3 /* cf8 */
843#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT              0
844#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK               0x3 /* cf9 */
845#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT              2
846#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK              0x3 /* cf10 */
847#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT             4
848#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK              0x3 /* cf11 */
849#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT             6
850	u8 flags5;
851#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK              0x3 /* cf12 */
852#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT             0
853#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK              0x3 /* cf13 */
854#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT             2
855#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK              0x3 /* cf14 */
856#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT             4
857#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK              0x3 /* cf15 */
858#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT             6
859	u8 flags6;
860#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK              0x3 /* cf16 */
861#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT             0
862#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK              0x3 /* cf_array_cf */
863#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT             2
864#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK              0x3 /* cf18 */
865#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT             4
866#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK              0x3 /* cf19 */
867#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT             6
868	u8 flags7;
869#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK              0x3 /* cf20 */
870#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT             0
871#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK              0x3 /* cf21 */
872#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT             2
873#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK         0x3 /* cf22 */
874#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT        4
875#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK             0x1 /* cf0en */
876#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT            6
877#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK             0x1 /* cf1en */
878#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT            7
879	u8 flags8;
880#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK             0x1 /* cf2en */
881#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT            0
882#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK             0x1 /* cf3en */
883#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT            1
884#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK             0x1 /* cf4en */
885#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT            2
886#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK             0x1 /* cf5en */
887#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT            3
888#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK             0x1 /* cf6en */
889#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT            4
890#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK    0x1 /* cf7en */
891#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT   5
892#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK             0x1 /* cf8en */
893#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT            6
894#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK             0x1 /* cf9en */
895#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT            7
896	u8 flags9;
897#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK            0x1 /* cf10en */
898#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT           0
899#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK            0x1 /* cf11en */
900#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT           1
901#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK            0x1 /* cf12en */
902#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT           2
903#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK            0x1 /* cf13en */
904#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT           3
905#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK            0x1 /* cf14en */
906#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT           4
907#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK            0x1 /* cf15en */
908#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT           5
909#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK            0x1 /* cf16en */
910#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT           6
911#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK            0x1 /* cf_array_cf_en */
912#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT           7
913	u8 flags10;
914#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK            0x1 /* cf18en */
915#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT           0
916#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK            0x1 /* cf19en */
917#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT           1
918#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK            0x1 /* cf20en */
919#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT           2
920#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK            0x1 /* cf21en */
921#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT           3
922#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK      0x1 /* cf22en */
923#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT     4
924#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK            0x1 /* cf23en */
925#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT           5
926#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK           0x1 /* rule0en */
927#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT          6
928#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK           0x1 /* rule1en */
929#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT          7
930	u8 flags11;
931#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK           0x1 /* rule2en */
932#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT          0
933#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK           0x1 /* rule3en */
934#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT          1
935#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK           0x1 /* rule4en */
936#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT          2
937#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK           0x1 /* rule5en */
938#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT          3
939#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK           0x1 /* rule6en */
940#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT          4
941#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK           0x1 /* rule7en */
942#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT          5
943#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK      0x1 /* rule8en */
944#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT     6
945#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK           0x1 /* rule9en */
946#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT          7
947	u8 flags12;
948#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK          0x1 /* rule10en */
949#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT         0
950#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK          0x1 /* rule11en */
951#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT         1
952#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK      0x1 /* rule12en */
953#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT     2
954#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK      0x1 /* rule13en */
955#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT     3
956#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK          0x1 /* rule14en */
957#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT         4
958#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK          0x1 /* rule15en */
959#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT         5
960#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK          0x1 /* rule16en */
961#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT         6
962#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK          0x1 /* rule17en */
963#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT         7
964	u8 flags13;
965#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK          0x1 /* rule18en */
966#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT         0
967#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK          0x1 /* rule19en */
968#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT         1
969#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK      0x1 /* rule20en */
970#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT     2
971#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK      0x1 /* rule21en */
972#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT     3
973#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK      0x1 /* rule22en */
974#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT     4
975#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK      0x1 /* rule23en */
976#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT     5
977#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK      0x1 /* rule24en */
978#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT     6
979#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK      0x1 /* rule25en */
980#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT     7
981	u8 flags14;
982#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK         0x1 /* bit16 */
983#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT        0
984#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK             0x1 /* bit17 */
985#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT            1
986#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK      0x3 /* bit18 */
987#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT     2
988#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK          0x1 /* bit20 */
989#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT         4
990#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK  0x1 /* bit21 */
991#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
992#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK              0x3 /* cf23 */
993#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT             6
994	u8 byte2 /* byte2 */;
995	__le16 physical_q0 /* physical_q0 */;
996	__le16 word1 /* physical_q1 */;
997	__le16 word2 /* physical_q2 */;
998	__le16 word3 /* word3 */;
999	__le16 word4 /* word4 */;
1000	__le16 word5 /* word5 */;
1001	__le16 conn_dpi /* conn_dpi */;
1002	u8 byte3 /* byte3 */;
1003	u8 byte4 /* byte4 */;
1004	u8 byte5 /* byte5 */;
1005	u8 byte6 /* byte6 */;
1006	__le32 reg0 /* reg0 */;
1007	__le32 reg1 /* reg1 */;
1008	__le32 reg2 /* reg2 */;
1009	__le32 snd_nxt_psn /* reg3 */;
1010	__le32 reg4 /* reg4 */;
1011};
1012
1013struct e4_mstorm_rdma_conn_ag_ctx
1014{
1015	u8 byte0 /* cdu_validation */;
1016	u8 byte1 /* state */;
1017	u8 flags0;
1018#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
1019#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT    0
1020#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
1021#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT    1
1022#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
1023#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT     2
1024#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
1025#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT     4
1026#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
1027#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT     6
1028	u8 flags1;
1029#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
1030#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT   0
1031#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
1032#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT   1
1033#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
1034#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT   2
1035#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
1036#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
1037#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
1038#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
1039#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
1040#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
1041#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
1042#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
1043#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
1044#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
1045	__le16 word0 /* word0 */;
1046	__le16 word1 /* word1 */;
1047	__le32 reg0 /* reg0 */;
1048	__le32 reg1 /* reg1 */;
1049};
1050
1051struct e4_tstorm_rdma_conn_ag_ctx
1052{
1053	u8 reserved0 /* cdu_validation */;
1054	u8 byte1 /* state */;
1055	u8 flags0;
1056#define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1 /* exist_in_qm0 */
1057#define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
1058#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK                  0x1 /* exist_in_qm1 */
1059#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT                 1
1060#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK                  0x1 /* bit2 */
1061#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT                 2
1062#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK                  0x1 /* bit3 */
1063#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT                 3
1064#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK                  0x1 /* bit4 */
1065#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT                 4
1066#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK                  0x1 /* bit5 */
1067#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT                 5
1068#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK                   0x3 /* timer0cf */
1069#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT                  6
1070	u8 flags1;
1071#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK                   0x3 /* timer1cf */
1072#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT                  0
1073#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK                   0x3 /* timer2cf */
1074#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT                  2
1075#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK     0x3 /* timer_stop_all */
1076#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT    4
1077#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK           0x3 /* cf4 */
1078#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT          6
1079	u8 flags2;
1080#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK       0x3 /* cf5 */
1081#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT      0
1082#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK                   0x3 /* cf6 */
1083#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT                  2
1084#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK                   0x3 /* cf7 */
1085#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT                  4
1086#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK                   0x3 /* cf8 */
1087#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT                  6
1088	u8 flags3;
1089#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK                   0x3 /* cf9 */
1090#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT                  0
1091#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK                  0x3 /* cf10 */
1092#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT                 2
1093#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK                 0x1 /* cf0en */
1094#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT                4
1095#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK                 0x1 /* cf1en */
1096#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT                5
1097#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK                 0x1 /* cf2en */
1098#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT                6
1099#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK  0x1 /* cf3en */
1100#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
1101	u8 flags4;
1102#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK        0x1 /* cf4en */
1103#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT       0
1104#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK    0x1 /* cf5en */
1105#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT   1
1106#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK                 0x1 /* cf6en */
1107#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT                2
1108#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK                 0x1 /* cf7en */
1109#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT                3
1110#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK                 0x1 /* cf8en */
1111#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT                4
1112#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK                 0x1 /* cf9en */
1113#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT                5
1114#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK                0x1 /* cf10en */
1115#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT               6
1116#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK               0x1 /* rule0en */
1117#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT              7
1118	u8 flags5;
1119#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK               0x1 /* rule1en */
1120#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT              0
1121#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK               0x1 /* rule2en */
1122#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT              1
1123#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK               0x1 /* rule3en */
1124#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT              2
1125#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK               0x1 /* rule4en */
1126#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT              3
1127#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK               0x1 /* rule5en */
1128#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT              4
1129#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK               0x1 /* rule6en */
1130#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT              5
1131#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK               0x1 /* rule7en */
1132#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT              6
1133#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK               0x1 /* rule8en */
1134#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT              7
1135	__le32 reg0 /* reg0 */;
1136	__le32 reg1 /* reg1 */;
1137	__le32 reg2 /* reg2 */;
1138	__le32 reg3 /* reg3 */;
1139	__le32 reg4 /* reg4 */;
1140	__le32 reg5 /* reg5 */;
1141	__le32 reg6 /* reg6 */;
1142	__le32 reg7 /* reg7 */;
1143	__le32 reg8 /* reg8 */;
1144	u8 byte2 /* byte2 */;
1145	u8 byte3 /* byte3 */;
1146	__le16 word0 /* word0 */;
1147	u8 byte4 /* byte4 */;
1148	u8 byte5 /* byte5 */;
1149	__le16 word1 /* word1 */;
1150	__le16 word2 /* conn_dpi */;
1151	__le16 word3 /* word3 */;
1152	__le32 reg9 /* reg9 */;
1153	__le32 reg10 /* reg10 */;
1154};
1155
1156struct e4_tstorm_rdma_task_ag_ctx
1157{
1158	u8 byte0 /* cdu_validation */;
1159	u8 byte1 /* state */;
1160	__le16 word0 /* icid */;
1161	u8 flags0;
1162#define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK  0xF /* connection_type */
1163#define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
1164#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
1165#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT    4
1166#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
1167#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT    5
1168#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK     0x1 /* bit2 */
1169#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT    6
1170#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK     0x1 /* bit3 */
1171#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT    7
1172	u8 flags1;
1173#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK     0x1 /* bit4 */
1174#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT    0
1175#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK     0x1 /* bit5 */
1176#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT    1
1177#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK      0x3 /* timer0cf */
1178#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT     2
1179#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK      0x3 /* timer1cf */
1180#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT     4
1181#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK      0x3 /* timer2cf */
1182#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT     6
1183	u8 flags2;
1184#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK      0x3 /* timer_stop_all */
1185#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT     0
1186#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK      0x3 /* cf4 */
1187#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT     2
1188#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK      0x3 /* cf5 */
1189#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT     4
1190#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK      0x3 /* cf6 */
1191#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT     6
1192	u8 flags3;
1193#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK      0x3 /* cf7 */
1194#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT     0
1195#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
1196#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT   2
1197#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
1198#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT   3
1199#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
1200#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT   4
1201#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK    0x1 /* cf3en */
1202#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT   5
1203#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK    0x1 /* cf4en */
1204#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT   6
1205#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK    0x1 /* cf5en */
1206#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT   7
1207	u8 flags4;
1208#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK    0x1 /* cf6en */
1209#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT   0
1210#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK    0x1 /* cf7en */
1211#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT   1
1212#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
1213#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
1214#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
1215#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
1216#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
1217#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
1218#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
1219#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
1220#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
1221#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
1222#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK  0x1 /* rule5en */
1223#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
1224	u8 byte2 /* byte2 */;
1225	__le16 word1 /* word1 */;
1226	__le32 reg0 /* reg0 */;
1227	u8 byte3 /* byte3 */;
1228	u8 byte4 /* byte4 */;
1229	__le16 word2 /* word2 */;
1230	__le16 word3 /* word3 */;
1231	__le16 word4 /* word4 */;
1232	__le32 reg1 /* reg1 */;
1233	__le32 reg2 /* reg2 */;
1234};
1235
1236struct e4_ustorm_rdma_conn_ag_ctx
1237{
1238	u8 reserved /* cdu_validation */;
1239	u8 byte1 /* state */;
1240	u8 flags0;
1241#define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
1242#define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT    0
1243#define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
1244#define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT            1
1245#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK      0x3 /* timer0cf */
1246#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT     2
1247#define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK              0x3 /* timer1cf */
1248#define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT             4
1249#define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK              0x3 /* timer2cf */
1250#define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT             6
1251	u8 flags1;
1252#define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK              0x3 /* timer_stop_all */
1253#define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT             0
1254#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK     0x3 /* cf4 */
1255#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT    2
1256#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK        0x3 /* cf5 */
1257#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT       4
1258#define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK              0x3 /* cf6 */
1259#define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT             6
1260	u8 flags2;
1261#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK   0x1 /* cf0en */
1262#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT  0
1263#define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
1264#define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT           1
1265#define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK            0x1 /* cf2en */
1266#define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT           2
1267#define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK            0x1 /* cf3en */
1268#define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT           3
1269#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK  0x1 /* cf4en */
1270#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
1271#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK     0x1 /* cf5en */
1272#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT    5
1273#define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK            0x1 /* cf6en */
1274#define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT           6
1275#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK         0x1 /* rule0en */
1276#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT        7
1277	u8 flags3;
1278#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK            0x1 /* rule1en */
1279#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT           0
1280#define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
1281#define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT         1
1282#define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
1283#define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT         2
1284#define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
1285#define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT         3
1286#define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
1287#define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT         4
1288#define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
1289#define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT         5
1290#define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK          0x1 /* rule7en */
1291#define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT         6
1292#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK          0x1 /* rule8en */
1293#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT         7
1294	u8 byte2 /* byte2 */;
1295	u8 byte3 /* byte3 */;
1296	__le16 conn_dpi /* conn_dpi */;
1297	__le16 word1 /* word1 */;
1298	__le32 cq_cons /* reg0 */;
1299	__le32 cq_se_prod /* reg1 */;
1300	__le32 cq_prod /* reg2 */;
1301	__le32 reg3 /* reg3 */;
1302	__le16 int_timeout /* word2 */;
1303	__le16 word3 /* word3 */;
1304};
1305
1306struct e4_xstorm_rdma_conn_ag_ctx
1307{
1308	u8 reserved0 /* cdu_validation */;
1309	u8 state /* state */;
1310	u8 flags0;
1311#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK      0x1 /* exist_in_qm0 */
1312#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT     0
1313#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK              0x1 /* exist_in_qm1 */
1314#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT             1
1315#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK              0x1 /* exist_in_qm2 */
1316#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT             2
1317#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK      0x1 /* exist_in_qm3 */
1318#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT     3
1319#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK              0x1 /* bit4 */
1320#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT             4
1321#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK              0x1 /* cf_array_active */
1322#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT             5
1323#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK              0x1 /* bit6 */
1324#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT             6
1325#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK              0x1 /* bit7 */
1326#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT             7
1327	u8 flags1;
1328#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK              0x1 /* bit8 */
1329#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT             0
1330#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK              0x1 /* bit9 */
1331#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT             1
1332#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK             0x1 /* bit10 */
1333#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT            2
1334#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK             0x1 /* bit11 */
1335#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT            3
1336#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK             0x1 /* bit12 */
1337#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT            4
1338#define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK      0x1 /* bit13 */
1339#define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT     5
1340#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK             0x1 /* bit14 */
1341#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT            6
1342#define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK      0x1 /* bit15 */
1343#define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT     7
1344	u8 flags2;
1345#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK               0x3 /* timer0cf */
1346#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT              0
1347#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK               0x3 /* timer1cf */
1348#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT              2
1349#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK               0x3 /* timer2cf */
1350#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT              4
1351#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK               0x3 /* timer_stop_all */
1352#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT              6
1353	u8 flags3;
1354#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK               0x3 /* cf4 */
1355#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT              0
1356#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK               0x3 /* cf5 */
1357#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT              2
1358#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK               0x3 /* cf6 */
1359#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT              4
1360#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK       0x3 /* cf7 */
1361#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT      6
1362	u8 flags4;
1363#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK               0x3 /* cf8 */
1364#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT              0
1365#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK               0x3 /* cf9 */
1366#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT              2
1367#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK              0x3 /* cf10 */
1368#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT             4
1369#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK              0x3 /* cf11 */
1370#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT             6
1371	u8 flags5;
1372#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK              0x3 /* cf12 */
1373#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT             0
1374#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK              0x3 /* cf13 */
1375#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT             2
1376#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK              0x3 /* cf14 */
1377#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT             4
1378#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK              0x3 /* cf15 */
1379#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT             6
1380	u8 flags6;
1381#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK              0x3 /* cf16 */
1382#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT             0
1383#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK              0x3 /* cf_array_cf */
1384#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT             2
1385#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK              0x3 /* cf18 */
1386#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT             4
1387#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK              0x3 /* cf19 */
1388#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT             6
1389	u8 flags7;
1390#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK              0x3 /* cf20 */
1391#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT             0
1392#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK              0x3 /* cf21 */
1393#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT             2
1394#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK         0x3 /* cf22 */
1395#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT        4
1396#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK             0x1 /* cf0en */
1397#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT            6
1398#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK             0x1 /* cf1en */
1399#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT            7
1400	u8 flags8;
1401#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK             0x1 /* cf2en */
1402#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT            0
1403#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK             0x1 /* cf3en */
1404#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT            1
1405#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK             0x1 /* cf4en */
1406#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT            2
1407#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK             0x1 /* cf5en */
1408#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT            3
1409#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK             0x1 /* cf6en */
1410#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT            4
1411#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK    0x1 /* cf7en */
1412#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT   5
1413#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK             0x1 /* cf8en */
1414#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT            6
1415#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK             0x1 /* cf9en */
1416#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT            7
1417	u8 flags9;
1418#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK            0x1 /* cf10en */
1419#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT           0
1420#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK            0x1 /* cf11en */
1421#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT           1
1422#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK            0x1 /* cf12en */
1423#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT           2
1424#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK            0x1 /* cf13en */
1425#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT           3
1426#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK            0x1 /* cf14en */
1427#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT           4
1428#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK            0x1 /* cf15en */
1429#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT           5
1430#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK            0x1 /* cf16en */
1431#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT           6
1432#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK            0x1 /* cf_array_cf_en */
1433#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT           7
1434	u8 flags10;
1435#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK            0x1 /* cf18en */
1436#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT           0
1437#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK            0x1 /* cf19en */
1438#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT           1
1439#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK            0x1 /* cf20en */
1440#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT           2
1441#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK            0x1 /* cf21en */
1442#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT           3
1443#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK      0x1 /* cf22en */
1444#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT     4
1445#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK            0x1 /* cf23en */
1446#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT           5
1447#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK           0x1 /* rule0en */
1448#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT          6
1449#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK           0x1 /* rule1en */
1450#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT          7
1451	u8 flags11;
1452#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK           0x1 /* rule2en */
1453#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT          0
1454#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK           0x1 /* rule3en */
1455#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT          1
1456#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK           0x1 /* rule4en */
1457#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT          2
1458#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK           0x1 /* rule5en */
1459#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT          3
1460#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK           0x1 /* rule6en */
1461#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT          4
1462#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK           0x1 /* rule7en */
1463#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT          5
1464#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK      0x1 /* rule8en */
1465#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT     6
1466#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK           0x1 /* rule9en */
1467#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT          7
1468	u8 flags12;
1469#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK          0x1 /* rule10en */
1470#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT         0
1471#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK          0x1 /* rule11en */
1472#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT         1
1473#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK      0x1 /* rule12en */
1474#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT     2
1475#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK      0x1 /* rule13en */
1476#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT     3
1477#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK          0x1 /* rule14en */
1478#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT         4
1479#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK          0x1 /* rule15en */
1480#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT         5
1481#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK          0x1 /* rule16en */
1482#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT         6
1483#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK          0x1 /* rule17en */
1484#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT         7
1485	u8 flags13;
1486#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK          0x1 /* rule18en */
1487#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT         0
1488#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK          0x1 /* rule19en */
1489#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT         1
1490#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK      0x1 /* rule20en */
1491#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT     2
1492#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK      0x1 /* rule21en */
1493#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT     3
1494#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK      0x1 /* rule22en */
1495#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT     4
1496#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK      0x1 /* rule23en */
1497#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT     5
1498#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK      0x1 /* rule24en */
1499#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT     6
1500#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK      0x1 /* rule25en */
1501#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT     7
1502	u8 flags14;
1503#define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK         0x1 /* bit16 */
1504#define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT        0
1505#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK             0x1 /* bit17 */
1506#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT            1
1507#define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK      0x3 /* bit18 */
1508#define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT     2
1509#define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK          0x1 /* bit20 */
1510#define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT         4
1511#define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK  0x1 /* bit21 */
1512#define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
1513#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK              0x3 /* cf23 */
1514#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT             6
1515	u8 byte2 /* byte2 */;
1516	__le16 physical_q0 /* physical_q0 */;
1517	__le16 word1 /* physical_q1 */;
1518	__le16 word2 /* physical_q2 */;
1519	__le16 word3 /* word3 */;
1520	__le16 word4 /* word4 */;
1521	__le16 word5 /* word5 */;
1522	__le16 conn_dpi /* conn_dpi */;
1523	u8 byte3 /* byte3 */;
1524	u8 byte4 /* byte4 */;
1525	u8 byte5 /* byte5 */;
1526	u8 byte6 /* byte6 */;
1527	__le32 reg0 /* reg0 */;
1528	__le32 reg1 /* reg1 */;
1529	__le32 reg2 /* reg2 */;
1530	__le32 snd_nxt_psn /* reg3 */;
1531	__le32 reg4 /* reg4 */;
1532	__le32 reg5 /* cf_array0 */;
1533	__le32 reg6 /* cf_array1 */;
1534};
1535
1536struct e4_ystorm_rdma_conn_ag_ctx
1537{
1538	u8 byte0 /* cdu_validation */;
1539	u8 byte1 /* state */;
1540	u8 flags0;
1541#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
1542#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT    0
1543#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
1544#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT    1
1545#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
1546#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT     2
1547#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
1548#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT     4
1549#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
1550#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT     6
1551	u8 flags1;
1552#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
1553#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT   0
1554#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
1555#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT   1
1556#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
1557#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT   2
1558#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
1559#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
1560#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
1561#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
1562#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
1563#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
1564#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
1565#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
1566#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
1567#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
1568	u8 byte2 /* byte2 */;
1569	u8 byte3 /* byte3 */;
1570	__le16 word0 /* word0 */;
1571	__le32 reg0 /* reg0 */;
1572	__le32 reg1 /* reg1 */;
1573	__le16 word1 /* word1 */;
1574	__le16 word2 /* word2 */;
1575	__le16 word3 /* word3 */;
1576	__le16 word4 /* word4 */;
1577	__le32 reg2 /* reg2 */;
1578	__le32 reg3 /* reg3 */;
1579};
1580
1581struct e5_mstorm_rdma_conn_ag_ctx
1582{
1583	u8 byte0 /* cdu_validation */;
1584	u8 byte1 /* state_and_core_id */;
1585	u8 flags0;
1586#define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
1587#define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT    0
1588#define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
1589#define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT    1
1590#define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
1591#define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT     2
1592#define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
1593#define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT     4
1594#define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
1595#define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT     6
1596	u8 flags1;
1597#define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
1598#define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT   0
1599#define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
1600#define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT   1
1601#define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
1602#define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT   2
1603#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
1604#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
1605#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
1606#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
1607#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
1608#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
1609#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
1610#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
1611#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
1612#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
1613	__le16 word0 /* word0 */;
1614	__le16 word1 /* word1 */;
1615	__le32 reg0 /* reg0 */;
1616	__le32 reg1 /* reg1 */;
1617};
1618
1619struct e5_tstorm_rdma_conn_ag_ctx
1620{
1621	u8 reserved0 /* cdu_validation */;
1622	u8 byte1 /* state_and_core_id */;
1623	u8 flags0;
1624#define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1 /* exist_in_qm0 */
1625#define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
1626#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK                  0x1 /* exist_in_qm1 */
1627#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT                 1
1628#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK                  0x1 /* bit2 */
1629#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT                 2
1630#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK                  0x1 /* bit3 */
1631#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT                 3
1632#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK                  0x1 /* bit4 */
1633#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT                 4
1634#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK                  0x1 /* bit5 */
1635#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT                 5
1636#define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK                   0x3 /* timer0cf */
1637#define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT                  6
1638	u8 flags1;
1639#define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK                   0x3 /* timer1cf */
1640#define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT                  0
1641#define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK                   0x3 /* timer2cf */
1642#define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT                  2
1643#define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK     0x3 /* timer_stop_all */
1644#define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT    4
1645#define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK           0x3 /* cf4 */
1646#define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT          6
1647	u8 flags2;
1648#define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK       0x3 /* cf5 */
1649#define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT      0
1650#define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK                   0x3 /* cf6 */
1651#define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT                  2
1652#define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK                   0x3 /* cf7 */
1653#define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT                  4
1654#define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK                   0x3 /* cf8 */
1655#define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT                  6
1656	u8 flags3;
1657#define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK                   0x3 /* cf9 */
1658#define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT                  0
1659#define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK                  0x3 /* cf10 */
1660#define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT                 2
1661#define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK                 0x1 /* cf0en */
1662#define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT                4
1663#define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK                 0x1 /* cf1en */
1664#define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT                5
1665#define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK                 0x1 /* cf2en */
1666#define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT                6
1667#define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK  0x1 /* cf3en */
1668#define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
1669	u8 flags4;
1670#define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK        0x1 /* cf4en */
1671#define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT       0
1672#define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK    0x1 /* cf5en */
1673#define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT   1
1674#define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK                 0x1 /* cf6en */
1675#define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT                2
1676#define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK                 0x1 /* cf7en */
1677#define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT                3
1678#define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK                 0x1 /* cf8en */
1679#define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT                4
1680#define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK                 0x1 /* cf9en */
1681#define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT                5
1682#define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK                0x1 /* cf10en */
1683#define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT               6
1684#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK               0x1 /* rule0en */
1685#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT              7
1686	u8 flags5;
1687#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK               0x1 /* rule1en */
1688#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT              0
1689#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK               0x1 /* rule2en */
1690#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT              1
1691#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK               0x1 /* rule3en */
1692#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT              2
1693#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK               0x1 /* rule4en */
1694#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT              3
1695#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK               0x1 /* rule5en */
1696#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT              4
1697#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK               0x1 /* rule6en */
1698#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT              5
1699#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK               0x1 /* rule7en */
1700#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT              6
1701#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK               0x1 /* rule8en */
1702#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT              7
1703	u8 flags6;
1704#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK          0x1 /* bit6 */
1705#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT         0
1706#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK          0x1 /* bit7 */
1707#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT         1
1708#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK          0x1 /* bit8 */
1709#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT         2
1710#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK          0x3 /* cf11 */
1711#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT         3
1712#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK          0x1 /* cf11en */
1713#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT         5
1714#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK          0x1 /* rule9en */
1715#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT         6
1716#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_MASK          0x1 /* rule10en */
1717#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_SHIFT         7
1718	u8 byte2 /* byte2 */;
1719	__le16 word0 /* word0 */;
1720	__le32 reg0 /* reg0 */;
1721	__le32 reg1 /* reg1 */;
1722	__le32 reg2 /* reg2 */;
1723	__le32 reg3 /* reg3 */;
1724	__le32 reg4 /* reg4 */;
1725	__le32 reg5 /* reg5 */;
1726	__le32 reg6 /* reg6 */;
1727	__le32 reg7 /* reg7 */;
1728	__le32 reg8 /* reg8 */;
1729	u8 byte3 /* byte3 */;
1730	u8 byte4 /* byte4 */;
1731	u8 byte5 /* byte5 */;
1732	u8 e4_reserved8 /* byte6 */;
1733	__le16 word1 /* word1 */;
1734	__le16 word2 /* conn_dpi */;
1735	__le32 reg9 /* reg9 */;
1736	__le16 word3 /* word3 */;
1737	__le16 e4_reserved9 /* word4 */;
1738};
1739
1740struct e5_tstorm_rdma_task_ag_ctx
1741{
1742	u8 byte0 /* cdu_validation */;
1743	u8 byte1 /* state_and_core_id */;
1744	__le16 word0 /* icid */;
1745	u8 flags0;
1746#define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK  0xF /* connection_type */
1747#define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
1748#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
1749#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT    4
1750#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
1751#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT    5
1752#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK     0x1 /* bit2 */
1753#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT    6
1754#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK     0x1 /* bit3 */
1755#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT    7
1756	u8 flags1;
1757#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK     0x1 /* bit4 */
1758#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT    0
1759#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK     0x1 /* bit5 */
1760#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT    1
1761#define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK      0x3 /* timer0cf */
1762#define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT     2
1763#define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK      0x3 /* timer1cf */
1764#define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT     4
1765#define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK      0x3 /* timer2cf */
1766#define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT     6
1767	u8 flags2;
1768#define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK      0x3 /* timer_stop_all */
1769#define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT     0
1770#define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK      0x3 /* cf4 */
1771#define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT     2
1772#define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK      0x3 /* cf5 */
1773#define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT     4
1774#define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK      0x3 /* cf6 */
1775#define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT     6
1776	u8 flags3;
1777#define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK      0x3 /* cf7 */
1778#define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT     0
1779#define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
1780#define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT   2
1781#define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
1782#define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT   3
1783#define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
1784#define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT   4
1785#define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK    0x1 /* cf3en */
1786#define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT   5
1787#define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK    0x1 /* cf4en */
1788#define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT   6
1789#define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK    0x1 /* cf5en */
1790#define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT   7
1791	u8 flags4;
1792#define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK    0x1 /* cf6en */
1793#define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT   0
1794#define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK    0x1 /* cf7en */
1795#define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT   1
1796#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
1797#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
1798#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
1799#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
1800#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
1801#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
1802#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
1803#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
1804#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
1805#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
1806#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK  0x1 /* rule5en */
1807#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
1808	u8 byte2 /* byte2 */;
1809	__le16 word1 /* word1 */;
1810	__le32 reg0 /* reg0 */;
1811	u8 byte3 /* regpair0 */;
1812	u8 byte4 /* byte4 */;
1813	__le16 word2 /* word2 */;
1814	__le16 word3 /* word3 */;
1815	__le16 word4 /* word4 */;
1816	__le32 reg1 /* regpair1 */;
1817	__le32 reg2 /* reg2 */;
1818};
1819
1820struct e5_ustorm_rdma_conn_ag_ctx
1821{
1822	u8 reserved /* cdu_validation */;
1823	u8 byte1 /* state_and_core_id */;
1824	u8 flags0;
1825#define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
1826#define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT    0
1827#define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
1828#define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT            1
1829#define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK      0x3 /* timer0cf */
1830#define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT     2
1831#define E5_USTORM_RDMA_CONN_AG_CTX_CF1_MASK              0x3 /* timer1cf */
1832#define E5_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT             4
1833#define E5_USTORM_RDMA_CONN_AG_CTX_CF2_MASK              0x3 /* timer2cf */
1834#define E5_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT             6
1835	u8 flags1;
1836#define E5_USTORM_RDMA_CONN_AG_CTX_CF3_MASK              0x3 /* timer_stop_all */
1837#define E5_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT             0
1838#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK     0x3 /* cf4 */
1839#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT    2
1840#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK        0x3 /* cf5 */
1841#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT       4
1842#define E5_USTORM_RDMA_CONN_AG_CTX_CF6_MASK              0x3 /* cf6 */
1843#define E5_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT             6
1844	u8 flags2;
1845#define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK   0x1 /* cf0en */
1846#define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT  0
1847#define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
1848#define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT           1
1849#define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK            0x1 /* cf2en */
1850#define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT           2
1851#define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK            0x1 /* cf3en */
1852#define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT           3
1853#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK  0x1 /* cf4en */
1854#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
1855#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK     0x1 /* cf5en */
1856#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT    5
1857#define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK            0x1 /* cf6en */
1858#define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT           6
1859#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK         0x1 /* rule0en */
1860#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT        7
1861	u8 flags3;
1862#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK            0x1 /* rule1en */
1863#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT           0
1864#define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
1865#define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT         1
1866#define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
1867#define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT         2
1868#define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
1869#define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT         3
1870#define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
1871#define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT         4
1872#define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
1873#define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT         5
1874#define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK          0x1 /* rule7en */
1875#define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT         6
1876#define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK          0x1 /* rule8en */
1877#define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT         7
1878	u8 flags4;
1879#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK     0x1 /* bit2 */
1880#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT    0
1881#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK     0x1 /* bit3 */
1882#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT    1
1883#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK     0x3 /* cf7 */
1884#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT    2
1885#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK     0x3 /* cf8 */
1886#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT    4
1887#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK     0x1 /* cf7en */
1888#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT    6
1889#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK     0x1 /* cf8en */
1890#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT    7
1891	u8 byte2 /* byte2 */;
1892	__le16 conn_dpi /* conn_dpi */;
1893	__le16 word1 /* word1 */;
1894	__le32 cq_cons /* reg0 */;
1895	__le32 cq_se_prod /* reg1 */;
1896	__le32 cq_prod /* reg2 */;
1897	__le32 reg3 /* reg3 */;
1898	__le16 int_timeout /* word2 */;
1899	__le16 word3 /* word3 */;
1900};
1901
1902struct e5_xstorm_rdma_conn_ag_ctx
1903{
1904	u8 reserved0 /* cdu_validation */;
1905	u8 state_and_core_id /* state_and_core_id */;
1906	u8 flags0;
1907#define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK      0x1 /* exist_in_qm0 */
1908#define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT     0
1909#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK              0x1 /* exist_in_qm1 */
1910#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT             1
1911#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK              0x1 /* exist_in_qm2 */
1912#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT             2
1913#define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK      0x1 /* exist_in_qm3 */
1914#define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT     3
1915#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK              0x1 /* bit4 */
1916#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT             4
1917#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK              0x1 /* cf_array_active */
1918#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT             5
1919#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK              0x1 /* bit6 */
1920#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT             6
1921#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK              0x1 /* bit7 */
1922#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT             7
1923	u8 flags1;
1924#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK              0x1 /* bit8 */
1925#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT             0
1926#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK              0x1 /* bit9 */
1927#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT             1
1928#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK             0x1 /* bit10 */
1929#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT            2
1930#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK             0x1 /* bit11 */
1931#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT            3
1932#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK             0x1 /* bit12 */
1933#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT            4
1934#define E5_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK      0x1 /* bit13 */
1935#define E5_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT     5
1936#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK             0x1 /* bit14 */
1937#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT            6
1938#define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK      0x1 /* bit15 */
1939#define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT     7
1940	u8 flags2;
1941#define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK               0x3 /* timer0cf */
1942#define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT              0
1943#define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK               0x3 /* timer1cf */
1944#define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT              2
1945#define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK               0x3 /* timer2cf */
1946#define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT              4
1947#define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK               0x3 /* timer_stop_all */
1948#define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT              6
1949	u8 flags3;
1950#define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK               0x3 /* cf4 */
1951#define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT              0
1952#define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK               0x3 /* cf5 */
1953#define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT              2
1954#define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK               0x3 /* cf6 */
1955#define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT              4
1956#define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK       0x3 /* cf7 */
1957#define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT      6
1958	u8 flags4;
1959#define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK               0x3 /* cf8 */
1960#define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT              0
1961#define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK               0x3 /* cf9 */
1962#define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT              2
1963#define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK              0x3 /* cf10 */
1964#define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT             4
1965#define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK              0x3 /* cf11 */
1966#define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT             6
1967	u8 flags5;
1968#define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK              0x3 /* cf12 */
1969#define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT             0
1970#define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK              0x3 /* cf13 */
1971#define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT             2
1972#define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK              0x3 /* cf14 */
1973#define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT             4
1974#define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK              0x3 /* cf15 */
1975#define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT             6
1976	u8 flags6;
1977#define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK              0x3 /* cf16 */
1978#define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT             0
1979#define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK              0x3 /* cf_array_cf */
1980#define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT             2
1981#define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK              0x3 /* cf18 */
1982#define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT             4
1983#define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK              0x3 /* cf19 */
1984#define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT             6
1985	u8 flags7;
1986#define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK              0x3 /* cf20 */
1987#define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT             0
1988#define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK              0x3 /* cf21 */
1989#define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT             2
1990#define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK         0x3 /* cf22 */
1991#define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT        4
1992#define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK             0x1 /* cf0en */
1993#define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT            6
1994#define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK             0x1 /* cf1en */
1995#define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT            7
1996	u8 flags8;
1997#define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK             0x1 /* cf2en */
1998#define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT            0
1999#define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK             0x1 /* cf3en */
2000#define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT            1
2001#define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK             0x1 /* cf4en */
2002#define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT            2
2003#define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK             0x1 /* cf5en */
2004#define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT            3
2005#define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK             0x1 /* cf6en */
2006#define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT            4
2007#define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK    0x1 /* cf7en */
2008#define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT   5
2009#define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK             0x1 /* cf8en */
2010#define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT            6
2011#define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK             0x1 /* cf9en */
2012#define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT            7
2013	u8 flags9;
2014#define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK            0x1 /* cf10en */
2015#define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT           0
2016#define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK            0x1 /* cf11en */
2017#define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT           1
2018#define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK            0x1 /* cf12en */
2019#define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT           2
2020#define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK            0x1 /* cf13en */
2021#define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT           3
2022#define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK            0x1 /* cf14en */
2023#define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT           4
2024#define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK            0x1 /* cf15en */
2025#define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT           5
2026#define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK            0x1 /* cf16en */
2027#define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT           6
2028#define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK            0x1 /* cf_array_cf_en */
2029#define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT           7
2030	u8 flags10;
2031#define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK            0x1 /* cf18en */
2032#define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT           0
2033#define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK            0x1 /* cf19en */
2034#define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT           1
2035#define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK            0x1 /* cf20en */
2036#define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT           2
2037#define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK            0x1 /* cf21en */
2038#define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT           3
2039#define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK      0x1 /* cf22en */
2040#define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT     4
2041#define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK            0x1 /* cf23en */
2042#define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT           5
2043#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK           0x1 /* rule0en */
2044#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT          6
2045#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK           0x1 /* rule1en */
2046#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT          7
2047	u8 flags11;
2048#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK           0x1 /* rule2en */
2049#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT          0
2050#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK           0x1 /* rule3en */
2051#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT          1
2052#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK           0x1 /* rule4en */
2053#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT          2
2054#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK           0x1 /* rule5en */
2055#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT          3
2056#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK           0x1 /* rule6en */
2057#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT          4
2058#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK           0x1 /* rule7en */
2059#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT          5
2060#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK      0x1 /* rule8en */
2061#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT     6
2062#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK           0x1 /* rule9en */
2063#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT          7
2064	u8 flags12;
2065#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK          0x1 /* rule10en */
2066#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT         0
2067#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK          0x1 /* rule11en */
2068#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT         1
2069#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK      0x1 /* rule12en */
2070#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT     2
2071#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK      0x1 /* rule13en */
2072#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT     3
2073#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK          0x1 /* rule14en */
2074#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT         4
2075#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK          0x1 /* rule15en */
2076#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT         5
2077#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK          0x1 /* rule16en */
2078#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT         6
2079#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK          0x1 /* rule17en */
2080#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT         7
2081	u8 flags13;
2082#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK          0x1 /* rule18en */
2083#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT         0
2084#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK          0x1 /* rule19en */
2085#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT         1
2086#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK      0x1 /* rule20en */
2087#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT     2
2088#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK      0x1 /* rule21en */
2089#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT     3
2090#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK      0x1 /* rule22en */
2091#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT     4
2092#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK      0x1 /* rule23en */
2093#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT     5
2094#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK      0x1 /* rule24en */
2095#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT     6
2096#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK      0x1 /* rule25en */
2097#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT     7
2098	u8 flags14;
2099#define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK         0x1 /* bit16 */
2100#define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT        0
2101#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK             0x1 /* bit17 */
2102#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT            1
2103#define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK      0x3 /* bit18 */
2104#define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT     2
2105#define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK          0x1 /* bit20 */
2106#define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT         4
2107#define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK  0x1 /* bit21 */
2108#define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
2109#define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK              0x3 /* cf23 */
2110#define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT             6
2111	u8 byte2 /* byte2 */;
2112	__le16 physical_q0 /* physical_q0 */;
2113	__le16 word1 /* physical_q1 */;
2114	__le16 word2 /* physical_q2 */;
2115	__le16 word3 /* word3 */;
2116	__le16 word4 /* word4 */;
2117	__le16 word5 /* word5 */;
2118	__le16 conn_dpi /* conn_dpi */;
2119	u8 byte3 /* byte3 */;
2120	u8 byte4 /* byte4 */;
2121	u8 byte5 /* byte5 */;
2122	u8 byte6 /* byte6 */;
2123	__le32 reg0 /* reg0 */;
2124	__le32 reg1 /* reg1 */;
2125	__le32 reg2 /* reg2 */;
2126	__le32 snd_nxt_psn /* reg3 */;
2127	__le32 reg4 /* reg4 */;
2128	__le32 reg5 /* cf_array0 */;
2129	__le32 reg6 /* cf_array1 */;
2130};
2131
2132struct e5_ystorm_rdma_conn_ag_ctx
2133{
2134	u8 byte0 /* cdu_validation */;
2135	u8 byte1 /* state_and_core_id */;
2136	u8 flags0;
2137#define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
2138#define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT    0
2139#define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
2140#define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT    1
2141#define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
2142#define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT     2
2143#define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
2144#define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT     4
2145#define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
2146#define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT     6
2147	u8 flags1;
2148#define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
2149#define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT   0
2150#define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
2151#define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT   1
2152#define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
2153#define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT   2
2154#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
2155#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3
2156#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
2157#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4
2158#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
2159#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5
2160#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
2161#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6
2162#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
2163#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7
2164	u8 byte2 /* byte2 */;
2165	u8 byte3 /* byte3 */;
2166	__le16 word0 /* word0 */;
2167	__le32 reg0 /* reg0 */;
2168	__le32 reg1 /* reg1 */;
2169	__le16 word1 /* word1 */;
2170	__le16 word2 /* word2 */;
2171	__le16 word3 /* word3 */;
2172	__le16 word4 /* word4 */;
2173	__le32 reg2 /* reg2 */;
2174	__le32 reg3 /* reg3 */;
2175};
2176
2177#endif /* __ECORE_HSI_RDMA__ */
2178