1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#include <sys/param.h> 30#include <sys/systm.h> 31 32#include <sys/bus.h> 33#include <sys/interrupt.h> 34#include <sys/malloc.h> 35#include <sys/lock.h> 36#include <sys/mutex.h> 37#include <sys/kernel.h> 38#include <sys/module.h> 39#include <sys/rman.h> 40#include <sys/gpio.h> 41 42#include <vm/vm.h> 43#include <vm/pmap.h> 44#include <vm/vm_extern.h> 45 46#include <machine/bus.h> 47#include <machine/cpu.h> 48 49#include <dev/fdt/fdt_common.h> 50#include <dev/fdt/fdt_pinctrl.h> 51 52#include <dev/gpio/gpiobusvar.h> 53#include <dev/ofw/ofw_bus.h> 54#include <dev/ofw/ofw_bus_subr.h> 55 56#include <dev/clk/clk.h> 57#include <dev/hwreset/hwreset.h> 58 59#include <dev/spibus/spi.h> 60#include <dev/spibus/spibusvar.h> 61#include "spibus_if.h" 62 63#include <dev/qcom_qup/qcom_spi_var.h> 64#include <dev/qcom_qup/qcom_qup_reg.h> 65#include <dev/qcom_qup/qcom_spi_reg.h> 66#include <dev/qcom_qup/qcom_spi_debug.h> 67 68static struct ofw_compat_data compat_data[] = { 69 { "qcom,spi-qup-v1.1.1", QCOM_SPI_HW_QPI_V1_1 }, 70 { "qcom,spi-qup-v2.1.1", QCOM_SPI_HW_QPI_V2_1 }, 71 { "qcom,spi-qup-v2.2.1", QCOM_SPI_HW_QPI_V2_2 }, 72 { NULL, 0 } 73}; 74 75/* 76 * Flip the CS GPIO line either active or inactive. 77 * 78 * Actually listen to the CS polarity. 79 */ 80static void 81qcom_spi_set_chipsel(struct qcom_spi_softc *sc, int cs, bool active) 82{ 83 bool pinactive; 84 bool invert = !! (cs & SPIBUS_CS_HIGH); 85 86 cs = cs & ~SPIBUS_CS_HIGH; 87 88 if (sc->cs_pins[cs] == NULL) { 89 device_printf(sc->sc_dev, 90 "%s: cs=%u, active=%u, invert=%u, no gpio?\n", 91 __func__, cs, active, invert); 92 return; 93 } 94 95 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_CHIPSELECT, 96 "%s: cs=%u active=%u\n", __func__, cs, active); 97 98 /* 99 * Default rule here is CS is active low. 100 */ 101 if (active) 102 pinactive = false; 103 else 104 pinactive = true; 105 106 /* 107 * Invert the CS line if required. 108 */ 109 if (invert) 110 pinactive = !! pinactive; 111 112 gpio_pin_set_active(sc->cs_pins[cs], pinactive); 113 gpio_pin_is_active(sc->cs_pins[cs], &pinactive); 114} 115 116static void 117qcom_spi_intr(void *arg) 118{ 119 struct qcom_spi_softc *sc = arg; 120 int ret; 121 122 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR, "%s: called\n", __func__); 123 124 125 QCOM_SPI_LOCK(sc); 126 ret = qcom_spi_hw_interrupt_handle(sc); 127 if (ret != 0) { 128 device_printf(sc->sc_dev, 129 "ERROR: failed to read intr status\n"); 130 goto done; 131 } 132 133 /* 134 * Handle spurious interrupts outside of an actual 135 * transfer. 136 */ 137 if (sc->transfer.active == false) { 138 device_printf(sc->sc_dev, 139 "ERROR: spurious interrupt\n"); 140 qcom_spi_hw_ack_opmode(sc); 141 goto done; 142 } 143 144 /* Now, handle interrupts */ 145 if (sc->intr.error) { 146 sc->intr.error = false; 147 device_printf(sc->sc_dev, "ERROR: intr\n"); 148 } 149 150 if (sc->intr.do_rx) { 151 sc->intr.do_rx = false; 152 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR, 153 "%s: PIO_READ\n", __func__); 154 if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO) 155 ret = qcom_spi_hw_read_pio_fifo(sc); 156 else 157 ret = qcom_spi_hw_read_pio_block(sc); 158 if (ret != 0) { 159 device_printf(sc->sc_dev, 160 "ERROR: qcom_spi_hw_read failed (%u)\n", ret); 161 goto done; 162 } 163 } 164 if (sc->intr.do_tx) { 165 sc->intr.do_tx = false; 166 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR, 167 "%s: PIO_WRITE\n", __func__); 168 /* 169 * For FIFO operations we do not do a write here, we did 170 * it at the beginning of the transfer. 171 * 172 * For BLOCK operations yes, we call the routine. 173 */ 174 175 if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO) 176 ret = qcom_spi_hw_ack_write_pio_fifo(sc); 177 else 178 ret = qcom_spi_hw_write_pio_block(sc); 179 if (ret != 0) { 180 device_printf(sc->sc_dev, 181 "ERROR: qcom_spi_hw_write failed (%u)\n", ret); 182 goto done; 183 } 184 } 185 186 /* 187 * Do this last. We may actually have completed the 188 * transfer in the PIO receive path above and it will 189 * set the done flag here. 190 */ 191 if (sc->intr.done) { 192 sc->intr.done = false; 193 sc->transfer.done = true; 194 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR, 195 "%s: transfer done\n", __func__); 196 wakeup(sc); 197 } 198 199done: 200 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR, 201 "%s: done\n", __func__); 202 QCOM_SPI_UNLOCK(sc); 203} 204 205static int 206qcom_spi_probe(device_t dev) 207{ 208 209 if (!ofw_bus_status_okay(dev)) 210 return (ENXIO); 211 212 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 213 return (ENXIO); 214 215 device_set_desc(dev, "Qualcomm SPI Interface"); 216 return (BUS_PROBE_DEFAULT); 217} 218 219/* 220 * Allocate GPIOs if provided in the SPI controller block. 221 * 222 * Some devices will use GPIO lines for chip select. 223 * It's also quite annoying because some devices will want to use 224 * the hardware provided CS gating for say, the first chipselect block, 225 * and then use GPIOs for the later ones. 226 * 227 * So here we just assume for now that SPI index 0 uses the hardware 228 * lines, and >0 use GPIO lines. Revisit this if better hardware 229 * shows up. 230 * 231 * And finally, iterating over the cs-gpios list to allocate GPIOs 232 * doesn't actually tell us what the polarity is. For that we need 233 * to actually iterate over the list of child nodes and check what 234 * their properties are (and look for "spi-cs-high".) 235 */ 236static void 237qcom_spi_attach_gpios(struct qcom_spi_softc *sc) 238{ 239 phandle_t node; 240 int idx, err; 241 242 /* Allocate gpio pins for configured chip selects. */ 243 node = ofw_bus_get_node(sc->sc_dev); 244 for (idx = 0; idx < nitems(sc->cs_pins); idx++) { 245 err = gpio_pin_get_by_ofw_propidx(sc->sc_dev, node, 246 "cs-gpios", idx, &sc->cs_pins[idx]); 247 if (err == 0) { 248 err = gpio_pin_setflags(sc->cs_pins[idx], 249 GPIO_PIN_OUTPUT); 250 if (err != 0) { 251 device_printf(sc->sc_dev, 252 "error configuring gpio for" 253 " cs %u (%d)\n", idx, err); 254 } 255 /* 256 * We can't set this HIGH right now because 257 * we don't know if it needs to be set to 258 * high for inactive or low for inactive 259 * based on the child SPI device flags. 260 */ 261#if 0 262 gpio_pin_set_active(sc->cs_pins[idx], 1); 263 gpio_pin_is_active(sc->cs_pins[idx], &tmp); 264#endif 265 } else { 266 device_printf(sc->sc_dev, 267 "cannot configure gpio for chip select %u\n", idx); 268 sc->cs_pins[idx] = NULL; 269 } 270 } 271} 272 273static void 274qcom_spi_sysctl_attach(struct qcom_spi_softc *sc) 275{ 276 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 277 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 278 279 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 280 "debug", CTLFLAG_RW, &sc->sc_debug, 0, 281 "control debugging printfs"); 282} 283 284static int 285qcom_spi_attach(device_t dev) 286{ 287 struct qcom_spi_softc *sc = device_get_softc(dev); 288 int rid, ret, i, val; 289 290 sc->sc_dev = dev; 291 292 /* 293 * Hardware version is stored in the ofw_compat_data table. 294 */ 295 sc->hw_version = 296 ofw_bus_search_compatible(dev, compat_data)->ocd_data; 297 298 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 299 300 rid = 0; 301 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 302 RF_ACTIVE); 303 if (!sc->sc_mem_res) { 304 device_printf(dev, "ERROR: Could not map memory\n"); 305 ret = ENXIO; 306 goto error; 307 } 308 309 rid = 0; 310 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 311 RF_ACTIVE | RF_SHAREABLE); 312 if (!sc->sc_irq_res) { 313 device_printf(dev, "ERROR: Could not map interrupt\n"); 314 ret = ENXIO; 315 goto error; 316 } 317 318 ret = bus_setup_intr(dev, sc->sc_irq_res, 319 INTR_TYPE_MISC | INTR_MPSAFE, 320 NULL, qcom_spi_intr, sc, &sc->sc_irq_h); 321 if (ret != 0) { 322 device_printf(dev, "ERROR: could not configure interrupt " 323 "(%d)\n", 324 ret); 325 goto error; 326 } 327 328 qcom_spi_attach_gpios(sc); 329 330 ret = clk_get_by_ofw_name(dev, 0, "core", &sc->clk_core); 331 if (ret != 0) { 332 device_printf(dev, "ERROR: could not get %s clock (%d)\n", 333 "core", ret); 334 goto error; 335 } 336 ret = clk_get_by_ofw_name(dev, 0, "iface", &sc->clk_iface); 337 if (ret != 0) { 338 device_printf(dev, "ERROR: could not get %s clock (%d)\n", 339 "iface", ret); 340 goto error; 341 } 342 343 /* Bring up initial clocks if they're off */ 344 ret = clk_enable(sc->clk_core); 345 if (ret != 0) { 346 device_printf(dev, "ERROR: couldn't enable core clock (%u)\n", 347 ret); 348 goto error; 349 } 350 ret = clk_enable(sc->clk_iface); 351 if (ret != 0) { 352 device_printf(dev, "ERROR: couldn't enable iface clock (%u)\n", 353 ret); 354 goto error; 355 } 356 357 /* 358 * Read optional spi-max-frequency 359 */ 360 if (OF_getencprop(ofw_bus_get_node(dev), "spi-max-frequency", 361 &val, sizeof(val)) > 0) 362 sc->config.max_frequency = val; 363 else 364 sc->config.max_frequency = SPI_MAX_RATE; 365 366 /* 367 * Read optional cs-select 368 */ 369 if (OF_getencprop(ofw_bus_get_node(dev), "cs-select", 370 &val, sizeof(val)) > 0) 371 sc->config.cs_select = val; 372 else 373 sc->config.cs_select = 0; 374 375 /* 376 * Read optional num-cs 377 */ 378 if (OF_getencprop(ofw_bus_get_node(dev), "num-cs", 379 &val, sizeof(val)) > 0) 380 sc->config.num_cs = val; 381 else 382 sc->config.num_cs = SPI_NUM_CHIPSELECTS; 383 384 ret = fdt_pinctrl_configure_by_name(dev, "default"); 385 if (ret != 0) { 386 device_printf(dev, 387 "ERROR: could not configure default pinmux\n"); 388 goto error; 389 } 390 391 ret = qcom_spi_hw_read_controller_transfer_sizes(sc); 392 if (ret != 0) { 393 device_printf(dev, "ERROR: Could not read transfer config\n"); 394 goto error; 395 } 396 397 398 device_printf(dev, "BLOCK: input=%u bytes, output=%u bytes\n", 399 sc->config.input_block_size, 400 sc->config.output_block_size); 401 device_printf(dev, "FIFO: input=%u bytes, output=%u bytes\n", 402 sc->config.input_fifo_size, 403 sc->config.output_fifo_size); 404 405 /* QUP config */ 406 QCOM_SPI_LOCK(sc); 407 ret = qcom_spi_hw_qup_init_locked(sc); 408 if (ret != 0) { 409 device_printf(dev, "ERROR: QUP init failed (%d)\n", ret); 410 QCOM_SPI_UNLOCK(sc); 411 goto error; 412 } 413 414 /* Initial SPI config */ 415 ret = qcom_spi_hw_spi_init_locked(sc); 416 if (ret != 0) { 417 device_printf(dev, "ERROR: SPI init failed (%d)\n", ret); 418 QCOM_SPI_UNLOCK(sc); 419 goto error; 420 } 421 QCOM_SPI_UNLOCK(sc); 422 423 sc->spibus = device_add_child(dev, "spibus", -1); 424 425 /* We're done, so shut down the interface clock for now */ 426 device_printf(dev, "DONE: shutting down interface clock for now\n"); 427 clk_disable(sc->clk_iface); 428 429 /* Register for debug sysctl */ 430 qcom_spi_sysctl_attach(sc); 431 432 return (bus_generic_attach(dev)); 433error: 434 if (sc->sc_irq_h) 435 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h); 436 if (sc->sc_mem_res) 437 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 438 if (sc->sc_irq_res) 439 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 440 if (sc->clk_core) { 441 clk_disable(sc->clk_core); 442 clk_release(sc->clk_core); 443 } 444 if (sc->clk_iface) { 445 clk_disable(sc->clk_iface); 446 clk_release(sc->clk_iface); 447 } 448 for (i = 0; i < CS_MAX; i++) { 449 if (sc->cs_pins[i] != NULL) 450 gpio_pin_release(sc->cs_pins[i]); 451 } 452 mtx_destroy(&sc->sc_mtx); 453 return (ret); 454} 455 456/* 457 * Do a PIO transfer. 458 * 459 * Note that right now the TX/RX lens need to match, I'm not doing 460 * dummy reads / dummy writes as required if they're not the same 461 * size. The QUP hardware supports doing multi-phase transactions 462 * where the FIFO isn't engaged for transmit or receive, but it's 463 * not yet being done here. 464 */ 465static int 466qcom_spi_transfer_pio_block(struct qcom_spi_softc *sc, int mode, 467 char *tx_buf, int tx_len, char *rx_buf, int rx_len) 468{ 469 int ret = 0; 470 471 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER, "%s: start\n", 472 __func__); 473 474 if (rx_len != tx_len) { 475 device_printf(sc->sc_dev, 476 "ERROR: tx/rx len doesn't match (%d/%d)\n", 477 tx_len, rx_len); 478 return (ENXIO); 479 } 480 481 QCOM_SPI_ASSERT_LOCKED(sc); 482 483 /* 484 * Make initial choices for transfer configuration. 485 */ 486 ret = qcom_spi_hw_setup_transfer_selection(sc, tx_len); 487 if (ret != 0) { 488 device_printf(sc->sc_dev, 489 "ERROR: failed to setup transfer selection (%d)\n", 490 ret); 491 return (ret); 492 } 493 494 /* Now set suitable buffer/lengths */ 495 sc->transfer.tx_buf = tx_buf; 496 sc->transfer.tx_len = tx_len; 497 sc->transfer.rx_buf = rx_buf; 498 sc->transfer.rx_len = rx_len; 499 sc->transfer.done = false; 500 sc->transfer.active = false; 501 502 /* 503 * Loop until the full transfer set is done. 504 * 505 * qcom_spi_hw_setup_current_transfer() will take care of 506 * setting a maximum transfer size for the hardware and choose 507 * a suitable operating mode. 508 */ 509 while (sc->transfer.tx_offset < sc->transfer.tx_len) { 510 /* 511 * Set transfer to false early; this covers 512 * it also finishing a sub-transfer and we're 513 * about the put the block into RESET state before 514 * starting a new transfer. 515 */ 516 sc->transfer.active = false; 517 518 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER, 519 "%s: tx=%d of %d bytes, rx=%d of %d bytes\n", 520 __func__, 521 sc->transfer.tx_offset, sc->transfer.tx_len, 522 sc->transfer.rx_offset, sc->transfer.rx_len); 523 524 /* 525 * Set state to RESET before doing anything. 526 * 527 * Otherwise the second sub-transfer that we queue up 528 * will generate interrupts immediately when we start 529 * configuring it here and it'll start underflowing. 530 */ 531 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RESET); 532 if (ret != 0) { 533 device_printf(sc->sc_dev, 534 "ERROR: can't transition to RESET (%u)\n", ret); 535 goto done; 536 } 537 /* blank interrupt state; we'll do a RESET below */ 538 bzero(&sc->intr, sizeof(sc->intr)); 539 sc->transfer.done = false; 540 541 /* 542 * Configure what the transfer configuration for this 543 * sub-transfer will be. 544 */ 545 ret = qcom_spi_hw_setup_current_transfer(sc); 546 if (ret != 0) { 547 device_printf(sc->sc_dev, 548 "ERROR: failed to setup sub transfer (%d)\n", 549 ret); 550 goto done; 551 } 552 553 /* 554 * For now since we're configuring up PIO, we only setup 555 * the PIO transfer size. 556 */ 557 ret = qcom_spi_hw_setup_pio_transfer_cnt(sc); 558 if (ret != 0) { 559 device_printf(sc->sc_dev, 560 "ERROR: qcom_spi_hw_setup_pio_transfer_cnt failed" 561 " (%u)\n", ret); 562 goto done; 563 } 564 565#if 0 566 /* 567 * This is what we'd do to setup the block transfer sizes. 568 */ 569 ret = qcom_spi_hw_setup_block_transfer_cnt(sc); 570 if (ret != 0) { 571 device_printf(sc->sc_dev, 572 "ERROR: qcom_spi_hw_setup_block_transfer_cnt failed" 573 " (%u)\n", ret); 574 goto done; 575 } 576#endif 577 578 ret = qcom_spi_hw_setup_io_modes(sc); 579 if (ret != 0) { 580 device_printf(sc->sc_dev, 581 "ERROR: qcom_spi_hw_setup_io_modes failed" 582 " (%u)\n", ret); 583 goto done; 584 } 585 586 ret = qcom_spi_hw_setup_spi_io_clock_polarity(sc, 587 !! (mode & SPIBUS_MODE_CPOL)); 588 if (ret != 0) { 589 device_printf(sc->sc_dev, 590 "ERROR: qcom_spi_hw_setup_spi_io_clock_polarity" 591 " failed (%u)\n", ret); 592 goto done; 593 } 594 595 ret = qcom_spi_hw_setup_spi_config(sc, sc->state.frequency, 596 !! (mode & SPIBUS_MODE_CPHA)); 597 if (ret != 0) { 598 device_printf(sc->sc_dev, 599 "ERROR: qcom_spi_hw_setup_spi_config failed" 600 " (%u)\n", ret); 601 goto done; 602 } 603 604 ret = qcom_spi_hw_setup_qup_config(sc, !! (tx_len > 0), 605 !! (rx_len > 0)); 606 if (ret != 0) { 607 device_printf(sc->sc_dev, 608 "ERROR: qcom_spi_hw_setup_qup_config failed" 609 " (%u)\n", ret); 610 goto done; 611 } 612 613 ret = qcom_spi_hw_setup_operational_mask(sc); 614 if (ret != 0) { 615 device_printf(sc->sc_dev, 616 "ERROR: qcom_spi_hw_setup_operational_mask failed" 617 " (%u)\n", ret); 618 goto done; 619 } 620 621 /* 622 * Setup is done; reset the controller and start the PIO 623 * write. 624 */ 625 626 /* 627 * Set state to RUN; we may start getting interrupts that 628 * are valid and we need to handle. 629 */ 630 sc->transfer.active = true; 631 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RUN); 632 if (ret != 0) { 633 device_printf(sc->sc_dev, 634 "ERROR: can't transition to RUN (%u)\n", ret); 635 goto done; 636 } 637 638 /* 639 * Set state to PAUSE 640 */ 641 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_PAUSE); 642 if (ret != 0) { 643 device_printf(sc->sc_dev, 644 "ERROR: can't transition to PAUSE (%u)\n", ret); 645 goto done; 646 } 647 648 /* 649 * If FIFO mode, write data now. Else, we'll get an 650 * interrupt when it's time to populate more data 651 * in BLOCK mode. 652 */ 653 if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO) 654 ret = qcom_spi_hw_write_pio_fifo(sc); 655 else 656 ret = qcom_spi_hw_write_pio_block(sc); 657 if (ret != 0) { 658 device_printf(sc->sc_dev, 659 "ERROR: qcom_spi_hw_write failed (%u)\n", ret); 660 goto done; 661 } 662 663 /* 664 * Set state to RUN 665 */ 666 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RUN); 667 if (ret != 0) { 668 device_printf(sc->sc_dev, 669 "ERROR: can't transition to RUN (%u)\n", ret); 670 goto done; 671 } 672 673 /* 674 * Wait for an interrupt notification (which will 675 * continue to drive the state machine for this 676 * sub-transfer) or timeout. 677 */ 678 ret = 0; 679 while (ret == 0 && sc->transfer.done == false) { 680 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER, 681 "%s: waiting\n", __func__); 682 ret = msleep(sc, &sc->sc_mtx, 0, "qcom_spi", 0); 683 } 684 } 685done: 686 /* 687 * Complete; put controller into reset. 688 * 689 * Don't worry about return value here; if we errored out above then 690 * we want to communicate that value to the caller. 691 */ 692 (void) qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RESET); 693 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER, 694 "%s: completed\n", __func__); 695 696 /* 697 * Blank the transfer state so we don't use an old transfer 698 * state in a subsequent interrupt. 699 */ 700 (void) qcom_spi_hw_complete_transfer(sc); 701 sc->transfer.active = false; 702 703 return (ret); 704} 705 706static int 707qcom_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) 708{ 709 struct qcom_spi_softc *sc = device_get_softc(dev); 710 uint32_t cs_val, mode_val, clock_val; 711 uint32_t ret = 0; 712 713 spibus_get_cs(child, &cs_val); 714 spibus_get_clock(child, &clock_val); 715 spibus_get_mode(child, &mode_val); 716 717 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER, 718 "%s: called; child cs=0x%08x, clock=%u, mode=0x%08x, " 719 "cmd=%u/%u bytes; data=%u/%u bytes\n", 720 __func__, 721 cs_val, 722 clock_val, 723 mode_val, 724 cmd->tx_cmd_sz, cmd->rx_cmd_sz, 725 cmd->tx_data_sz, cmd->rx_data_sz); 726 727 QCOM_SPI_LOCK(sc); 728 729 /* 730 * wait until the controller isn't busy 731 */ 732 while (sc->sc_busy == true) 733 mtx_sleep(sc, &sc->sc_mtx, 0, "qcom_spi_wait", 0); 734 735 /* 736 * it's ours now! 737 */ 738 sc->sc_busy = true; 739 740 sc->state.cs_high = !! (cs_val & SPIBUS_CS_HIGH); 741 sc->state.frequency = clock_val; 742 743 /* 744 * We can't set the clock frequency and enable it 745 * with the driver lock held, as the SPI lock is non-sleepable 746 * and the clock framework is sleepable. 747 * 748 * No other transaction is going on right now, so we can 749 * unlock here and do the clock related work. 750 */ 751 QCOM_SPI_UNLOCK(sc); 752 753 /* 754 * Set the clock frequency 755 */ 756 ret = clk_set_freq(sc->clk_iface, sc->state.frequency, 0); 757 if (ret != 0) { 758 device_printf(sc->sc_dev, 759 "ERROR: failed to set frequency to %u\n", 760 sc->state.frequency); 761 goto done2; 762 } 763 clk_enable(sc->clk_iface); 764 765 QCOM_SPI_LOCK(sc); 766 767 /* 768 * Set state to RESET 769 */ 770 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RESET); 771 if (ret != 0) { 772 device_printf(sc->sc_dev, 773 "ERROR: can't transition to RESET (%u)\n", ret); 774 goto done; 775 } 776 777 /* Assert hardware CS if set, else GPIO */ 778 if (sc->cs_pins[cs_val & ~SPIBUS_CS_HIGH] == NULL) 779 qcom_spi_hw_spi_cs_force(sc, cs_val & SPIBUS_CS_HIGH, true); 780 else 781 qcom_spi_set_chipsel(sc, cs_val & ~SPIBUS_CS_HIGH, true); 782 783 /* 784 * cmd buffer transfer 785 */ 786 ret = qcom_spi_transfer_pio_block(sc, mode_val, cmd->tx_cmd, 787 cmd->tx_cmd_sz, cmd->rx_cmd, cmd->rx_cmd_sz); 788 if (ret != 0) { 789 device_printf(sc->sc_dev, 790 "ERROR: failed to transfer cmd payload (%u)\n", ret); 791 goto done; 792 } 793 794 /* 795 * data buffer transfer 796 */ 797 if (cmd->tx_data_sz > 0) { 798 ret = qcom_spi_transfer_pio_block(sc, mode_val, cmd->tx_data, 799 cmd->tx_data_sz, cmd->rx_data, cmd->rx_data_sz); 800 if (ret != 0) { 801 device_printf(sc->sc_dev, 802 "ERROR: failed to transfer data payload (%u)\n", 803 ret); 804 goto done; 805 } 806 } 807 808done: 809 /* De-assert GPIO/CS */ 810 if (sc->cs_pins[cs_val & ~SPIBUS_CS_HIGH] == NULL) 811 qcom_spi_hw_spi_cs_force(sc, cs_val & ~SPIBUS_CS_HIGH, false); 812 else 813 qcom_spi_set_chipsel(sc, cs_val & ~SPIBUS_CS_HIGH, false); 814 815 /* 816 * Similarly to when we enabled the clock, we can't hold it here 817 * across a clk API as that's a sleep lock and we're non-sleepable. 818 * So instead we unlock/relock here, but we still hold the busy flag. 819 */ 820 821 QCOM_SPI_UNLOCK(sc); 822 clk_disable(sc->clk_iface); 823 QCOM_SPI_LOCK(sc); 824done2: 825 /* 826 * We're done; so mark the bus as not busy and wakeup 827 * the next caller. 828 */ 829 sc->sc_busy = false; 830 wakeup_one(sc); 831 QCOM_SPI_UNLOCK(sc); 832 return (ret); 833} 834 835static int 836qcom_spi_detach(device_t dev) 837{ 838 struct qcom_spi_softc *sc = device_get_softc(dev); 839 int i; 840 841 bus_generic_detach(sc->sc_dev); 842 if (sc->spibus != NULL) 843 device_delete_child(dev, sc->spibus); 844 845 if (sc->sc_irq_h) 846 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h); 847 848 if (sc->clk_iface) { 849 clk_disable(sc->clk_iface); 850 clk_release(sc->clk_iface); 851 } 852 if (sc->clk_core) { 853 clk_disable(sc->clk_core); 854 clk_release(sc->clk_core); 855 } 856 857 for (i = 0; i < CS_MAX; i++) { 858 if (sc->cs_pins[i] != NULL) 859 gpio_pin_release(sc->cs_pins[i]); 860 } 861 862 if (sc->sc_mem_res) 863 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 864 if (sc->sc_irq_res) 865 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 866 867 mtx_destroy(&sc->sc_mtx); 868 869 return (0); 870} 871 872static phandle_t 873qcom_spi_get_node(device_t bus, device_t dev) 874{ 875 876 return ofw_bus_get_node(bus); 877} 878 879 880static device_method_t qcom_spi_methods[] = { 881 /* Device interface */ 882 DEVMETHOD(device_probe, qcom_spi_probe), 883 DEVMETHOD(device_attach, qcom_spi_attach), 884 DEVMETHOD(device_detach, qcom_spi_detach), 885 /* TODO: suspend */ 886 /* TODO: resume */ 887 888 DEVMETHOD(spibus_transfer, qcom_spi_transfer), 889 890 /* ofw_bus_if */ 891 DEVMETHOD(ofw_bus_get_node, qcom_spi_get_node), 892 893 DEVMETHOD_END 894}; 895 896static driver_t qcom_spi_driver = { 897 "qcom_spi", 898 qcom_spi_methods, 899 sizeof(struct qcom_spi_softc), 900}; 901 902DRIVER_MODULE(qcom_spi, simplebus, qcom_spi_driver, 0, 0); 903DRIVER_MODULE(ofw_spibus, qcom_spi, ofw_spibus_driver, 0, 0); 904MODULE_DEPEND(qcom_spi, ofw_spibus, 1, 1, 1); 905SIMPLEBUS_PNP_INFO(compat_data); 906