1/* SPDX-License-Identifier: BSD-3-Clause */ 2/* Copyright(c) 2007-2022 Intel Corporation */ 3#ifndef _ICP_QAT_FW_H_ 4#define _ICP_QAT_FW_H_ 5#include <sys/types.h> 6#include "icp_qat_hw.h" 7 8#define QAT_FIELD_SET(flags, val, bitpos, mask) \ 9 { \ 10 (flags) = (((flags) & (~((mask) << (bitpos)))) | \ 11 (((val) & (mask)) << (bitpos))); \ 12 } 13 14#define QAT_FIELD_GET(flags, bitpos, mask) (((flags) >> (bitpos)) & (mask)) 15 16#define ICP_QAT_FW_REQ_DEFAULT_SZ 128 17#define ICP_QAT_FW_RESP_DEFAULT_SZ 32 18#define ICP_QAT_FW_COMN_ONE_BYTE_SHIFT 8 19#define ICP_QAT_FW_COMN_SINGLE_BYTE_MASK 0xFF 20#define ICP_QAT_FW_NUM_LONGWORDS_1 1 21#define ICP_QAT_FW_NUM_LONGWORDS_2 2 22#define ICP_QAT_FW_NUM_LONGWORDS_3 3 23#define ICP_QAT_FW_NUM_LONGWORDS_4 4 24#define ICP_QAT_FW_NUM_LONGWORDS_5 5 25#define ICP_QAT_FW_NUM_LONGWORDS_6 6 26#define ICP_QAT_FW_NUM_LONGWORDS_7 7 27#define ICP_QAT_FW_NUM_LONGWORDS_10 10 28#define ICP_QAT_FW_NUM_LONGWORDS_13 13 29#define ICP_QAT_FW_NULL_REQ_SERV_ID 1 30 31enum icp_qat_fw_comn_resp_serv_id { 32 ICP_QAT_FW_COMN_RESP_SERV_NULL, 33 ICP_QAT_FW_COMN_RESP_SERV_CPM_FW, 34 ICP_QAT_FW_COMN_RESP_SERV_DELIMITER 35}; 36 37enum icp_qat_fw_comn_request_id { 38 ICP_QAT_FW_COMN_REQ_NULL = 0, 39 ICP_QAT_FW_COMN_REQ_CPM_FW_PKE = 3, 40 ICP_QAT_FW_COMN_REQ_CPM_FW_LA = 4, 41 ICP_QAT_FW_COMN_REQ_CPM_FW_DMA = 7, 42 ICP_QAT_FW_COMN_REQ_CPM_FW_COMP = 9, 43 ICP_QAT_FW_COMN_REQ_DELIMITER 44}; 45 46struct icp_qat_fw_comn_req_hdr_cd_pars { 47 union { 48 struct { 49 uint64_t content_desc_addr; 50 uint16_t content_desc_resrvd1; 51 uint8_t content_desc_params_sz; 52 uint8_t content_desc_hdr_resrvd2; 53 uint32_t content_desc_resrvd3; 54 } s; 55 struct { 56 uint32_t serv_specif_fields[4]; 57 } s1; 58 } u; 59}; 60 61struct icp_qat_fw_comn_req_mid { 62 uint64_t opaque_data; 63 uint64_t src_data_addr; 64 uint64_t dest_data_addr; 65 uint32_t src_length; 66 uint32_t dst_length; 67}; 68 69struct icp_qat_fw_comn_req_cd_ctrl { 70 uint32_t content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5]; 71}; 72 73struct icp_qat_fw_comn_req_hdr { 74 uint8_t resrvd1; 75 uint8_t service_cmd_id; 76 uint8_t service_type; 77 uint8_t hdr_flags; 78 uint16_t serv_specif_flags; 79 uint16_t comn_req_flags; 80}; 81 82struct icp_qat_fw_comn_req_rqpars { 83 uint32_t serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13]; 84}; 85 86struct icp_qat_fw_comn_req { 87 struct icp_qat_fw_comn_req_hdr comn_hdr; 88 struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars; 89 struct icp_qat_fw_comn_req_mid comn_mid; 90 struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars; 91 struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl; 92}; 93 94struct icp_qat_fw_comn_error { 95 uint8_t xlat_err_code; 96 uint8_t cmp_err_code; 97}; 98 99struct icp_qat_fw_comn_resp_hdr { 100 uint8_t resrvd1; 101 uint8_t service_id; 102 uint8_t response_type; 103 uint8_t hdr_flags; 104 struct icp_qat_fw_comn_error comn_error; 105 uint8_t comn_status; 106 uint8_t cmd_id; 107}; 108 109struct icp_qat_fw_comn_resp { 110 struct icp_qat_fw_comn_resp_hdr comn_hdr; 111 uint64_t opaque_data; 112 uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4]; 113}; 114 115#define ICP_QAT_FW_COMN_REQ_FLAG_SET 1 116#define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0 117#define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7 118#define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1 119#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F 120 121#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \ 122 icp_qat_fw_comn_req_hdr_t.service_type 123 124#define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \ 125 icp_qat_fw_comn_req_hdr_t.service_type = val 126 127#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \ 128 icp_qat_fw_comn_req_hdr_t.service_cmd_id 129 130#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \ 131 icp_qat_fw_comn_req_hdr_t.service_cmd_id = val 132 133#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \ 134 ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags) 135 136#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \ 137 ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) 138 139#define ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_flags) \ 140 QAT_FIELD_GET(hdr_flags, \ 141 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \ 142 ICP_QAT_FW_COMN_VALID_FLAG_MASK) 143 144#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags) \ 145 (hdr_flags & ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK) 146 147#define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \ 148 QAT_FIELD_SET((hdr_t.hdr_flags), \ 149 (val), \ 150 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \ 151 ICP_QAT_FW_COMN_VALID_FLAG_MASK) 152 153#define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(valid) \ 154 (((valid)&ICP_QAT_FW_COMN_VALID_FLAG_MASK) \ 155 << ICP_QAT_FW_COMN_VALID_FLAG_BITPOS) 156 157#define QAT_COMN_PTR_TYPE_BITPOS 0 158#define QAT_COMN_PTR_TYPE_MASK 0x1 159#define QAT_COMN_CD_FLD_TYPE_BITPOS 1 160#define QAT_COMN_CD_FLD_TYPE_MASK 0x1 161#define QAT_COMN_PTR_TYPE_FLAT 0x0 162#define QAT_COMN_PTR_TYPE_SGL 0x1 163#define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0 164#define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1 165 166#define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \ 167 ((((cdt)&QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) | \ 168 (((ptr)&QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS)) 169 170#define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \ 171 QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK) 172 173#define ICP_QAT_FW_COMN_CD_FLD_TYPE_GET(flags) \ 174 QAT_FIELD_GET(flags, \ 175 QAT_COMN_CD_FLD_TYPE_BITPOS, \ 176 QAT_COMN_CD_FLD_TYPE_MASK) 177 178#define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \ 179 QAT_FIELD_SET(flags, \ 180 val, \ 181 QAT_COMN_PTR_TYPE_BITPOS, \ 182 QAT_COMN_PTR_TYPE_MASK) 183 184#define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \ 185 QAT_FIELD_SET(flags, \ 186 val, \ 187 QAT_COMN_CD_FLD_TYPE_BITPOS, \ 188 QAT_COMN_CD_FLD_TYPE_MASK) 189 190#define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4 191#define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0 192#define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0 193#define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F 194 195#define ICP_QAT_FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t) \ 196 ((((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) >> \ 197 (ICP_QAT_FW_COMN_NEXT_ID_BITPOS)) 198 199#define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \ 200 { \ 201 ((cd_ctrl_hdr_t)->next_curr_id) = \ 202 ((((cd_ctrl_hdr_t)->next_curr_id) & \ 203 ICP_QAT_FW_COMN_CURR_ID_MASK) | \ 204 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) & \ 205 ICP_QAT_FW_COMN_NEXT_ID_MASK)); \ 206 } 207 208#define ICP_QAT_FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t) \ 209 (((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) 210 211#define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \ 212 { \ 213 ((cd_ctrl_hdr_t)->next_curr_id) = \ 214 ((((cd_ctrl_hdr_t)->next_curr_id) & \ 215 ICP_QAT_FW_COMN_NEXT_ID_MASK) | \ 216 ((val)&ICP_QAT_FW_COMN_CURR_ID_MASK)); \ 217 } 218 219#define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7 220#define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1 221#define QAT_COMN_RESP_PKE_STATUS_BITPOS 6 222#define QAT_COMN_RESP_PKE_STATUS_MASK 0x1 223#define QAT_COMN_RESP_CMP_STATUS_BITPOS 5 224#define QAT_COMN_RESP_CMP_STATUS_MASK 0x1 225#define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4 226#define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1 227#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3 228#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1 229 230#define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \ 231 ((((crypto)&QAT_COMN_RESP_CRYPTO_STATUS_MASK) \ 232 << QAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \ 233 (((comp)&QAT_COMN_RESP_CMP_STATUS_MASK) \ 234 << QAT_COMN_RESP_CMP_STATUS_BITPOS) | \ 235 (((xlat)&QAT_COMN_RESP_XLAT_STATUS_MASK) \ 236 << QAT_COMN_RESP_XLAT_STATUS_BITPOS) | \ 237 (((eolb)&QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) \ 238 << QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS)) 239 240#define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \ 241 QAT_FIELD_GET(status, \ 242 QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \ 243 QAT_COMN_RESP_CRYPTO_STATUS_MASK) 244 245#define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \ 246 QAT_FIELD_GET(status, \ 247 QAT_COMN_RESP_CMP_STATUS_BITPOS, \ 248 QAT_COMN_RESP_CMP_STATUS_MASK) 249 250#define ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(status) \ 251 QAT_FIELD_GET(status, \ 252 QAT_COMN_RESP_XLAT_STATUS_BITPOS, \ 253 QAT_COMN_RESP_XLAT_STATUS_MASK) 254 255#define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \ 256 QAT_FIELD_GET(status, \ 257 QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \ 258 QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) 259 260#define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0 261#define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1 262#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0 263#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1 264#define ERR_CODE_NO_ERROR 0 265#define ERR_CODE_INVALID_BLOCK_TYPE -1 266#define ERR_CODE_NO_MATCH_ONES_COMP -2 267#define ERR_CODE_TOO_MANY_LEN_OR_DIS -3 268#define ERR_CODE_INCOMPLETE_LEN -4 269#define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5 270#define ERR_CODE_RPT_GT_SPEC_LEN -6 271#define ERR_CODE_INV_LIT_LEN_CODE_LEN -7 272#define ERR_CODE_INV_DIS_CODE_LEN -8 273#define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9 274#define ERR_CODE_DIS_TOO_FAR_BACK -10 275#define ERR_CODE_OVERFLOW_ERROR -11 276#define ERR_CODE_SOFT_ERROR -12 277#define ERR_CODE_FATAL_ERROR -13 278#define ERR_CODE_SSM_ERROR -14 279#define ERR_CODE_ENDPOINT_ERROR -15 280 281enum icp_qat_fw_slice { 282 ICP_QAT_FW_SLICE_NULL = 0, 283 ICP_QAT_FW_SLICE_CIPHER = 1, 284 ICP_QAT_FW_SLICE_AUTH = 2, 285 ICP_QAT_FW_SLICE_DRAM_RD = 3, 286 ICP_QAT_FW_SLICE_DRAM_WR = 4, 287 ICP_QAT_FW_SLICE_COMP = 5, 288 ICP_QAT_FW_SLICE_XLAT = 6, 289 ICP_QAT_FW_SLICE_DELIMITER 290}; 291#endif 292