1122574Sume/* SPDX-License-Identifier: BSD-3-Clause */ 262637Skris/* Copyright(c) 2007-2022 Intel Corporation */ 355163Sshin#ifndef ADF_DEV_ERR_H_ 455163Sshin#define ADF_DEV_ERR_H_ 555163Sshin 655163Sshin#include <sys/types.h> 755163Sshin#include <dev/pci/pcivar.h> 855163Sshin#include "adf_accel_devices.h" 955163Sshin 1055163Sshin#define ADF_ERRSOU0 (0x3A000 + 0x00) 1155163Sshin#define ADF_ERRSOU1 (0x3A000 + 0x04) 1255163Sshin#define ADF_ERRSOU2 (0x3A000 + 0x08) 1355163Sshin#define ADF_ERRSOU3 (0x3A000 + 0x0C) 1455163Sshin#define ADF_ERRSOU4 (0x3A000 + 0xD0) 1555163Sshin#define ADF_ERRSOU5 (0x3A000 + 0xD8) 1655163Sshin#define ADF_ERRMSK0 (0x3A000 + 0x10) 1755163Sshin#define ADF_ERRMSK1 (0x3A000 + 0x14) 1855163Sshin#define ADF_ERRMSK2 (0x3A000 + 0x18) 1955163Sshin#define ADF_ERRMSK3 (0x3A000 + 0x1C) 2055163Sshin#define ADF_ERRMSK4 (0x3A000 + 0xD4) 2155163Sshin#define ADF_ERRMSK5 (0x3A000 + 0xDC) 2255163Sshin#define ADF_EMSK3_CPM0_MASK BIT(2) 2355163Sshin#define ADF_EMSK3_CPM1_MASK BIT(3) 2455163Sshin#define ADF_EMSK5_CPM2_MASK BIT(16) 2555163Sshin#define ADF_EMSK5_CPM3_MASK BIT(17) 2655163Sshin#define ADF_EMSK5_CPM4_MASK BIT(18) 2755163Sshin#define ADF_RICPPINTSTS (0x3A000 + 0x114) 2855163Sshin#define ADF_RIERRPUSHID (0x3A000 + 0x118) 2955163Sshin#define ADF_RIERRPULLID (0x3A000 + 0x11C) 3055163Sshin#define ADF_CPP_CFC_ERR_STATUS (0x30000 + 0xC04) 3155163Sshin#define ADF_CPP_CFC_ERR_PPID (0x30000 + 0xC08) 3255163Sshin#define ADF_TICPPINTSTS (0x3A400 + 0x13C) 3355163Sshin#define ADF_TIERRPUSHID (0x3A400 + 0x140) 3455163Sshin#define ADF_TIERRPULLID (0x3A400 + 0x144) 3555163Sshin#define ADF_SECRAMUERR (0x3AC00 + 0x04) 3655163Sshin#define ADF_SECRAMUERRAD (0x3AC00 + 0x0C) 3755163Sshin#define ADF_CPPMEMTGTERR (0x3AC00 + 0x10) 3855163Sshin#define ADF_ERRPPID (0x3AC00 + 0x14) 3955163Sshin#define ADF_INTSTATSSM(i) ((i)*0x4000 + 0x04) 4055163Sshin#define ADF_INTSTATSSM_SHANGERR BIT(13) 4155163Sshin#define ADF_PPERR(i) ((i)*0x4000 + 0x08) 4255163Sshin#define ADF_PPERRID(i) ((i)*0x4000 + 0x0C) 4355163Sshin#define ADF_CERRSSMSH(i) ((i)*0x4000 + 0x10) 4455163Sshin#define ADF_UERRSSMSH(i) ((i)*0x4000 + 0x18) 4555163Sshin#define ADF_UERRSSMSHAD(i) ((i)*0x4000 + 0x1C) 4655163Sshin#define ADF_SLICEHANGSTATUS(i) ((i)*0x4000 + 0x4C) 4755163Sshin#define ADF_SLICE_HANG_AUTH0_MASK BIT(0) 4855163Sshin#define ADF_SLICE_HANG_AUTH1_MASK BIT(1) 4955163Sshin#define ADF_SLICE_HANG_AUTH2_MASK BIT(2) 5055163Sshin#define ADF_SLICE_HANG_CPHR0_MASK BIT(4) 5155163Sshin#define ADF_SLICE_HANG_CPHR1_MASK BIT(5) 5255163Sshin#define ADF_SLICE_HANG_CPHR2_MASK BIT(6) 5355163Sshin#define ADF_SLICE_HANG_CMP0_MASK BIT(8) 5455163Sshin#define ADF_SLICE_HANG_CMP1_MASK BIT(9) 5555163Sshin#define ADF_SLICE_HANG_XLT0_MASK BIT(12) 5655163Sshin#define ADF_SLICE_HANG_XLT1_MASK BIT(13) 5755163Sshin#define ADF_SLICE_HANG_MMP0_MASK BIT(16) 5855163Sshin#define ADF_SLICE_HANG_MMP1_MASK BIT(17) 5955163Sshin#define ADF_SLICE_HANG_MMP2_MASK BIT(18) 6055163Sshin#define ADF_SLICE_HANG_MMP3_MASK BIT(19) 6155163Sshin#define ADF_SLICE_HANG_MMP4_MASK BIT(20) 6255163Sshin#define ADF_SSMWDT(i) ((i)*0x4000 + 0x54) 6355163Sshin#define ADF_SSMWDTPKE(i) ((i)*0x4000 + 0x58) 6455163Sshin#define ADF_SHINTMASKSSM(i) ((i)*0x4000 + 0x1018) 6555163Sshin#define ADF_ENABLE_SLICE_HANG 0x000000 6655163Sshin#define ADF_MAX_MMP (5) 6755163Sshin#define ADF_MMP_BASE(i) ((i)*0x1000 % 0x3800) 6855163Sshin#define ADF_CERRSSMMMP(i, n) ((i)*0x4000 + ADF_MMP_BASE(n) + 0x380) 6955163Sshin#define ADF_UERRSSMMMP(i, n) ((i)*0x4000 + ADF_MMP_BASE(n) + 0x388) 7055163Sshin#define ADF_UERRSSMMMPAD(i, n) ((i)*0x4000 + ADF_MMP_BASE(n) + 0x38C) 7155163Sshin 7255163Sshinbool adf_handle_slice_hang(struct adf_accel_dev *accel_dev, 7355163Sshin u8 accel_num, 7455163Sshin struct resource *csr, 7562637Skris u32 slice_hang_offset); 7655163Sshinbool adf_check_slice_hang(struct adf_accel_dev *accel_dev); 7762637Skrisvoid adf_print_err_registers(struct adf_accel_dev *accel_dev); 7862637Skris 7962637Skris#endif 8055163Sshin