1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
5 *
6 * This software was developed by SRI International and the University of
7 * Cambridge Computer Laboratory (Department of Computer Science and
8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
9 * DARPA SSITH research programme.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 *    notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 *    notice, this list of conditions and the following disclaimer in the
18 *    documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33#include <machine/asm.h>
34.macro arm_smccc_1_0	insn
35ENTRY(arm_smccc_\insn)
36	\insn	#0
37	ldr	x4, [sp]
38	cbz	x4, 1f
39	stp	x0, x1, [x4, #16 * 0]
40	stp	x2, x3, [x4, #16 * 1]
411:	ret
42END(arm_smccc_\insn)
43.endm
44
45/*
46 * int arm_smccc_*(register_t, register_t, register_t, register_t,
47 *     register_t, register_t, register_t, register_t,
48 *     struct arm_smccc_res *res)
49 */
50arm_smccc_1_0	hvc
51arm_smccc_1_0	smc
52
53.macro arm_smccc_1_2	insn
54ENTRY(arm_smccc_1_2_\insn)
55	stp	x1, x19, [sp, #-16]!
56	mov	x19, x0
57	ldp	x0, x1, [x19, #16 * 0]
58	ldp	x2, x3, [x19, #16 * 1]
59	ldp	x4, x5, [x19, #16 * 2]
60	ldp	x6, x7, [x19, #16 * 3]
61	ldp	x8, x9, [x19, #16 * 4]
62	ldp	x10, x11, [x19, #16 * 5]
63	ldp	x12, x13, [x19, #16 * 6]
64	ldp	x14, x15, [x19, #16 * 7]
65	ldp	x16, x17, [x19, #16 * 8]
66	\insn	#0
67	ldr	x19, [sp]
68	cbz	x19, 1f
69	stp	x0, x1, [x19, #16 * 0]
70	stp	x2, x3, [x19, #16 * 1]
71	stp	x4, x5, [x19, #16 * 2]
72	stp	x6, x7, [x19, #16 * 3]
73	stp	x8, x9, [x19, #16 * 4]
74	stp	x10, x11, [x19, #16 * 5]
75	stp	x12, x13, [x19, #16 * 6]
76	stp	x14, x15, [x19, #16 * 7]
77	stp	x16, x17, [x19, #16 * 8]
781:	ldp	xzr, x19, [sp], #16
79	ret
80END(arm_smccc_1_2_\insn)
81.endm
82/* int arm_smccc_1_2_*(const struct arm_smccc_1_2_regs *args,
83 *     struct arm_smccc_1_2_regs *res)
84 */
85arm_smccc_1_2	hvc
86arm_smccc_1_2	smc
87