1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2001 Alcove - Nicolas Souchu 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29#ifndef __PPCREG_H 30#define __PPCREG_H 31 32#include <sys/_lock.h> 33#include <sys/_mutex.h> 34 35/* 36 * Parallel Port Chipset type. 37 */ 38#define SMC_LIKE 0 39#define SMC_37C665GT 1 40#define SMC_37C666GT 2 41#define NS_PC87332 3 42#define NS_PC87306 4 43#define INTEL_820191AA 5 /* XXX not implemented */ 44#define GENERIC 6 45#define WINB_W83877F 7 46#define WINB_W83877AF 8 47#define WINB_UNKNOWN 9 48#define NS_PC87334 10 49#define SMC_37C935 11 50#define NS_PC87303 12 51 52/* 53 * Parallel Port Chipset Type. SMC versus GENERIC (others) 54 */ 55#define PPC_TYPE_SMCLIKE 0 56#define PPC_TYPE_GENERIC 1 57 58/* 59 * Generic structure to hold parallel port chipset info. 60 */ 61struct ppc_data { 62 device_t ppc_dev; 63 int ppc_model; /* chipset model if detected */ 64 int ppc_type; /* generic or smclike chipset type */ 65 66 int ppc_mode; /* chipset current mode */ 67 int ppc_avm; /* chipset available modes */ 68 int ppc_dtm; /* chipset detected modes */ 69 70#define PPC_IRQ_NONE 0x0 71#define PPC_IRQ_nACK 0x1 72#define PPC_IRQ_DMA 0x2 73#define PPC_IRQ_FIFO 0x4 74#define PPC_IRQ_nFAULT 0x8 75 int ppc_irqstat; /* remind irq settings */ 76 77#define PPC_DMA_INIT 0x01 78#define PPC_DMA_STARTED 0x02 79#define PPC_DMA_COMPLETE 0x03 80#define PPC_DMA_INTERRUPTED 0x04 81#define PPC_DMA_ERROR 0x05 82 int ppc_dmastat; /* dma state */ 83 int ppc_dmachan; /* dma channel */ 84 int ppc_dmaflags; /* dma transfer flags */ 85 caddr_t ppc_dmaddr; /* buffer address */ 86 u_int ppc_dmacnt; /* count of bytes sent with dma */ 87 void (*ppc_dmadone)(struct ppc_data*); 88 89#define PPC_PWORD_MASK 0x30 90#define PPC_PWORD_16 0x00 91#define PPC_PWORD_8 0x10 92#define PPC_PWORD_32 0x20 93 char ppc_pword; /* PWord size */ 94 short ppc_fifo; /* FIFO threshold */ 95 96 short ppc_wthr; /* writeIntrThresold */ 97 short ppc_rthr; /* readIntrThresold */ 98 99 char *ppc_ptr; /* microseq current pointer */ 100 int ppc_accum; /* microseq accumulator */ 101 int ppc_base; /* parallel port base address */ 102 int ppc_epp; /* EPP mode (1.7 or 1.9) */ 103 int ppc_irq; 104 105 unsigned char ppc_flags; 106 107 device_t ppbus; /* parallel port chipset corresponding ppbus */ 108 109 int rid_irq, rid_drq, rid_ioport; 110 struct resource *res_irq, *res_drq, *res_ioport; 111 112 void *intr_cookie; 113 114 ppc_intr_handler ppc_intr_hook; 115 void *ppc_intr_arg; 116 117 struct mtx ppc_lock; 118}; 119 120#define PPC_LOCK(data) mtx_lock(&(data)->ppc_lock) 121#define PPC_UNLOCK(data) mtx_unlock(&(data)->ppc_lock) 122#define PPC_ASSERT_LOCKED(data) mtx_assert(&(data)->ppc_lock, MA_OWNED) 123 124/* 125 * Parallel Port Chipset registers. 126 */ 127#define PPC_SPP_DTR 0 /* SPP data register */ 128#define PPC_ECP_A_FIFO 0 /* ECP Address fifo register */ 129#define PPC_SPP_STR 1 /* SPP status register */ 130#define PPC_SPP_CTR 2 /* SPP control register */ 131#define PPC_EPP_ADDR 3 /* EPP address register (8 bit) */ 132#define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */ 133#define PPC_ECP_D_FIFO 0x400 /* ECP Data fifo register */ 134#define PPC_ECP_CNFGA 0x400 /* Configuration register A */ 135#define PPC_ECP_CNFGB 0x401 /* Configuration register B */ 136#define PPC_ECP_ECR 0x402 /* ECP extended control register */ 137 138#define PPC_FIFO_EMPTY 0x1 /* ecr register - bit 0 */ 139#define PPC_FIFO_FULL 0x2 /* ecr register - bit 1 */ 140#define PPC_SERVICE_INTR 0x4 /* ecr register - bit 2 */ 141#define PPC_ENABLE_DMA 0x8 /* ecr register - bit 3 */ 142#define PPC_nFAULT_INTR 0x10 /* ecr register - bit 4 */ 143#define PPC_ECR_STD 0x0 144#define PPC_ECR_PS2 0x20 145#define PPC_ECR_FIFO 0x40 146#define PPC_ECR_ECP 0x60 147#define PPC_ECR_EPP 0x80 148 149#define PPC_DISABLE_INTR (PPC_SERVICE_INTR | PPC_nFAULT_INTR) 150#define PPC_ECR_RESET (PPC_ECR_PS2 | PPC_DISABLE_INTR) 151 152#define r_dtr(ppc) (bus_read_1((ppc)->res_ioport, PPC_SPP_DTR)) 153#define r_str(ppc) (bus_read_1((ppc)->res_ioport, PPC_SPP_STR)) 154#define r_ctr(ppc) (bus_read_1((ppc)->res_ioport, PPC_SPP_CTR)) 155 156#define r_epp_A(ppc) (bus_read_1((ppc)->res_ioport, PPC_EPP_ADDR)) 157#define r_epp_D(ppc) (bus_read_1((ppc)->res_ioport, PPC_EPP_DATA)) 158#define r_cnfgA(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_CNFGA)) 159#define r_cnfgB(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_CNFGB)) 160#define r_ecr(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_ECR)) 161#define r_fifo(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_D_FIFO)) 162 163#define w_dtr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_DTR, byte)) 164#define w_str(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_STR, byte)) 165#define w_ctr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_CTR, byte)) 166 167#define w_epp_A(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_EPP_ADDR, byte)) 168#define w_epp_D(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_EPP_DATA, byte)) 169#define w_ecr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_ECP_ECR, byte)) 170#define w_fifo(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_ECP_D_FIFO, byte)) 171 172/* 173 * Register defines for the PC873xx parts 174 */ 175 176#define PC873_FER 0x00 177#define PC873_PPENABLE (1<<0) 178#define PC873_FAR 0x01 179#define PC873_PTR 0x02 180#define PC873_CFGLOCK (1<<6) 181#define PC873_EPPRDIR (1<<7) 182#define PC873_EXTENDED (1<<7) 183#define PC873_LPTBIRQ7 (1<<3) 184#define PC873_FCR 0x03 185#define PC873_ZWS (1<<5) 186#define PC873_ZWSPWDN (1<<6) 187#define PC873_PCR 0x04 188#define PC873_EPPEN (1<<0) 189#define PC873_EPP19 (1<<1) 190#define PC873_ECPEN (1<<2) 191#define PC873_ECPCLK (1<<3) 192#define PC873_PMC 0x06 193#define PC873_TUP 0x07 194#define PC873_SID 0x08 195#define PC873_PNP0 0x1b 196#define PC873_PNP1 0x1c 197#define PC873_LPTBA 0x19 198 199/* 200 * Register defines for the SMC FDC37C66xGT parts 201 */ 202 203/* Init codes */ 204#define SMC665_iCODE 0x55 205#define SMC666_iCODE 0x44 206 207/* Base configuration ports */ 208#define SMC66x_CSR 0x3F0 209#define SMC666_CSR 0x370 /* hard-configured value for 666 */ 210 211/* Bits */ 212#define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */ 213#define SMC_CR1_MODE (1<<3) /* bit 3 */ 214#define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */ 215#define SMC_CR4_EPPTYPE (1<<6) /* bit 6 */ 216 217/* Extended modes */ 218#define SMC_SPP 0x0 /* SPP */ 219#define SMC_EPPSPP 0x1 /* EPP and SPP */ 220#define SMC_ECP 0x2 /* ECP */ 221#define SMC_ECPEPP 0x3 /* ECP and EPP */ 222 223/* 224 * Register defines for the SMC FDC37C935 parts 225 */ 226 227/* Configuration ports */ 228#define SMC935_CFG 0x370 229#define SMC935_IND 0x370 230#define SMC935_DAT 0x371 231 232/* Registers */ 233#define SMC935_LOGDEV 0x7 234#define SMC935_ID 0x20 235#define SMC935_PORTHI 0x60 236#define SMC935_PORTLO 0x61 237#define SMC935_PPMODE 0xf0 238 239/* Parallel port modes */ 240#define SMC935_SPP 0x38 + 0 241#define SMC935_EPP19SPP 0x38 + 1 242#define SMC935_ECP 0x38 + 2 243#define SMC935_ECPEPP19 0x38 + 3 244#define SMC935_CENT 0x38 + 4 245#define SMC935_EPP17SPP 0x38 + 5 246#define SMC935_UNUSED 0x38 + 6 247#define SMC935_ECPEPP17 0x38 + 7 248 249/* 250 * Register defines for the Winbond W83877F parts 251 */ 252 253#define WINB_W83877F_ID 0xa 254#define WINB_W83877AF_ID 0xb 255 256/* Configuration bits */ 257#define WINB_HEFERE (1<<5) /* CROC bit 5 */ 258#define WINB_HEFRAS (1<<0) /* CR16 bit 0 */ 259 260#define WINB_PNPCVS (1<<2) /* CR16 bit 2 */ 261#define WINB_CHIPID 0xf /* CR9 bits 0-3 */ 262 263#define WINB_PRTMODS0 (1<<2) /* CR0 bit 2 */ 264#define WINB_PRTMODS1 (1<<3) /* CR0 bit 3 */ 265#define WINB_PRTMODS2 (1<<7) /* CR9 bit 7 */ 266 267/* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */ 268#define WINB_W83757 0x0 269#define WINB_EXTFDC 0x4 270#define WINB_EXTADP 0x8 271#define WINB_EXT2FDD 0xc 272#define WINB_JOYSTICK 0x80 273 274#define WINB_PARALLEL 0x80 275#define WINB_EPP_SPP 0x4 276#define WINB_ECP 0x8 277#define WINB_ECP_EPP 0xc 278 279#endif 280