1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2000-2001 Jonathan Chen All rights reserved. 5 * Copyright (c) 2002-2004 M. Warner Losh <imp@FreeBSD.org> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30/*- 31 * Copyright (c) 1998, 1999 and 2000 32 * HAYAKAWA Koichi. All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by HAYAKAWA Koichi. 45 * 4. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60/* 61 * Driver for PCI to CardBus Bridge chips 62 * 63 * References: 64 * TI Datasheets: 65 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS 66 * 67 * Written by Jonathan Chen <jon@freebsd.org> 68 * The author would like to acknowledge: 69 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing 70 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things 71 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver 72 * * David Cross: Author of the initial ugly hack for a specific cardbus card 73 */ 74 75#include <sys/param.h> 76#include <sys/systm.h> 77#include <sys/proc.h> 78#include <sys/condvar.h> 79#include <sys/errno.h> 80#include <sys/kernel.h> 81#include <sys/lock.h> 82#include <sys/malloc.h> 83#include <sys/mutex.h> 84#include <sys/sysctl.h> 85#include <sys/kthread.h> 86#include <sys/bus.h> 87#include <machine/bus.h> 88#include <sys/rman.h> 89#include <machine/resource.h> 90#include <sys/module.h> 91 92#include <dev/pci/pcireg.h> 93#include <dev/pci/pcivar.h> 94#include <dev/pci/pcib_private.h> 95 96#include <dev/pccard/pccardreg.h> 97#include <dev/pccard/pccardvar.h> 98 99#include <dev/exca/excareg.h> 100#include <dev/exca/excavar.h> 101 102#include <dev/pccbb/pccbbreg.h> 103#include <dev/pccbb/pccbbvar.h> 104 105#include "power_if.h" 106#include "card_if.h" 107#include "pcib_if.h" 108 109#define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) 110#define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) 111 112#define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ 113 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) 114#define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ 115 pci_write_config(DEV, REG, ( \ 116 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) 117 118static void cbb_chipinit(struct cbb_softc *sc); 119static int cbb_pci_filt(void *arg); 120 121static struct yenta_chipinfo { 122 uint32_t yc_id; 123 const char *yc_name; 124 int yc_chiptype; 125} yc_chipsets[] = { 126 /* Texas Instruments chips */ 127 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, 128 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, 129 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, 130 131 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, 132 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, 133 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, 134 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, 135 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, 136 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, 137 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, 138 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, 139 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, 140 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, 141 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, 142 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, 143 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, 144 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ 145 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, 146 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, 147 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, 148 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, 149 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, 150 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, 151 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, 152 {PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX}, 153 {PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 154 {PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, 155 {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX}, 156 {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX}, 157 {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 158 {PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 159 {PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 160 {PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, 161 162 /* ENE */ 163 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, 164 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, 165 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, 166 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, 167 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, 168 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, 169 170 /* Ricoh chips */ 171 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, 172 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, 173 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, 174 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, 175 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, 176 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, 177 178 /* Toshiba products */ 179 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, 180 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, 181 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, 182 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, 183 184 /* Cirrus Logic */ 185 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, 186 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, 187 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, 188 189 /* 02Micro */ 190 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, 191 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, 192 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, 193 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, 194 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, 195 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, 196 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO}, 197 {PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO}, 198 {PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO}, 199 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO}, 200 {PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO}, 201 {PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO}, 202 203 /* SMC */ 204 {PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS}, 205 206 /* sentinel */ 207 {0 /* null id */, "unknown", CB_UNKNOWN}, 208}; 209 210/************************************************************************/ 211/* Probe/Attach */ 212/************************************************************************/ 213 214static int 215cbb_chipset(uint32_t pci_id, const char **namep) 216{ 217 struct yenta_chipinfo *ycp; 218 219 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) 220 continue; 221 if (namep != NULL) 222 *namep = ycp->yc_name; 223 return (ycp->yc_chiptype); 224} 225 226static int 227cbb_pci_probe(device_t brdev) 228{ 229 const char *name; 230 uint32_t progif; 231 uint32_t baseclass; 232 uint32_t subclass; 233 234 /* 235 * Do we know that we support the chipset? If so, then we 236 * accept the device. 237 */ 238 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { 239 device_set_desc(brdev, name); 240 return (BUS_PROBE_DEFAULT); 241 } 242 243 /* 244 * We do support generic CardBus bridges. All that we've seen 245 * to date have progif 0 (the Yenta spec, and successors mandate 246 * this). 247 */ 248 baseclass = pci_get_class(brdev); 249 subclass = pci_get_subclass(brdev); 250 progif = pci_get_progif(brdev); 251 if (baseclass == PCIC_BRIDGE && 252 subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { 253 device_set_desc(brdev, "PCI-CardBus Bridge"); 254 return (BUS_PROBE_GENERIC); 255 } 256 return (ENXIO); 257} 258 259/* 260 * Print out the config space 261 */ 262static void 263cbb_print_config(device_t dev) 264{ 265 int i; 266 267 device_printf(dev, "PCI Configuration space:"); 268 for (i = 0; i < 256; i += 4) { 269 if (i % 16 == 0) 270 printf("\n 0x%02x: ", i); 271 printf("0x%08x ", pci_read_config(dev, i, 4)); 272 } 273 printf("\n"); 274} 275 276static int 277cbb_pci_attach(device_t brdev) 278{ 279#if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 280 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ 281 uint32_t pribus; 282#endif 283 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 284 struct sysctl_ctx_list *sctx; 285 struct sysctl_oid *soid; 286 int rid; 287 device_t parent; 288 289 parent = device_get_parent(brdev); 290 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); 291 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); 292 sc->dev = brdev; 293 sc->cbdev = NULL; 294 sc->domain = pci_get_domain(brdev); 295 sc->pribus = pcib_get_bus(parent); 296#if defined(NEW_PCIB) && defined(PCI_RES_BUS) 297 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); 298 pcib_setup_secbus(brdev, &sc->bus, 1); 299#else 300 sc->bus.sec = pci_read_config(brdev, PCIR_SECBUS_2, 1); 301 sc->bus.sub = pci_read_config(brdev, PCIR_SUBBUS_2, 1); 302#endif 303 SLIST_INIT(&sc->rl); 304 305 rid = CBBR_SOCKBASE; 306 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid, 307 RF_ACTIVE); 308 if (!sc->base_res) { 309 device_printf(brdev, "Could not map register memory\n"); 310 mtx_destroy(&sc->mtx); 311 return (ENOMEM); 312 } else { 313 DEVPRINTF((brdev, "Found memory at %jx\n", 314 rman_get_start(sc->base_res))); 315 } 316 317 /* attach children */ 318 sc->cbdev = device_add_child(brdev, "cardbus", -1); 319 if (sc->cbdev == NULL) 320 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); 321 else if (device_probe_and_attach(sc->cbdev) != 0) 322 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); 323 324 sc->bst = rman_get_bustag(sc->base_res); 325 sc->bsh = rman_get_bushandle(sc->base_res); 326 exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); 327 sc->exca.flags |= EXCA_HAS_MEMREG_WIN; 328 sc->exca.chipset = EXCA_CARDBUS; 329 sc->chipinit = cbb_chipinit; 330 sc->chipinit(sc); 331 332 /*Sysctls*/ 333 sctx = device_get_sysctl_ctx(brdev); 334 soid = device_get_sysctl_tree(brdev); 335 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 336 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 337 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 338 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 339 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 340 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); 341 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 342 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); 343#if 0 344 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "memory", 345 CTLFLAG_RD, &sc->subbus, 0, "Memory window open"); 346 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "premem", 347 CTLFLAG_RD, &sc->subbus, 0, "Prefetch memory window open"); 348 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io1", 349 CTLFLAG_RD, &sc->subbus, 0, "io range 1 open"); 350 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io2", 351 CTLFLAG_RD, &sc->subbus, 0, "io range 2 open"); 352#endif 353 354#if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) 355 /* 356 * This is a gross hack. We should be scanning the entire pci 357 * tree, assigning bus numbers in a way such that we (1) can 358 * reserve 1 extra bus just in case and (2) all sub buses 359 * are in an appropriate range. 360 */ 361 DEVPRINTF((brdev, "Secondary bus is %d\n", sc->bus.sec)); 362 pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1); 363 if (sc->bus.sec == 0 || sc->pribus != pribus) { 364 if (curr_bus_number <= sc->pribus) 365 curr_bus_number = sc->pribus + 1; 366 if (pribus != sc->pribus) { 367 DEVPRINTF((brdev, "Setting primary bus to %d\n", 368 sc->pribus)); 369 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); 370 } 371 sc->bus.sec = curr_bus_number++; 372 sc->bus.sub = curr_bus_number++; 373 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", 374 sc->bus.sec, sc->bus.sub)); 375 pci_write_config(brdev, PCIR_SECBUS_2, sc->bus.sec, 1); 376 pci_write_config(brdev, PCIR_SUBBUS_2, sc->bus.sub, 1); 377 } 378#endif 379 380 /* Map and establish the interrupt. */ 381 rid = 0; 382 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid, 383 RF_SHAREABLE | RF_ACTIVE); 384 if (sc->irq_res == NULL) { 385 device_printf(brdev, "Unable to map IRQ...\n"); 386 goto err; 387 } 388 389 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, 390 cbb_pci_filt, NULL, sc, &sc->intrhand)) { 391 device_printf(brdev, "couldn't establish interrupt\n"); 392 goto err; 393 } 394 395 /* reset 16-bit pcmcia bus */ 396 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 397 398 /* turn off power */ 399 cbb_power(brdev, CARD_OFF); 400 401 /* CSC Interrupt: Card detect interrupt on */ 402 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 403 404 /* reset interrupt */ 405 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); 406 407 if (bootverbose) 408 cbb_print_config(brdev); 409 410 /* Start the thread */ 411 if (kproc_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, 412 "%s event thread", device_get_nameunit(brdev))) { 413 device_printf(brdev, "unable to create event thread.\n"); 414 panic("cbb_create_event_thread"); 415 } 416 sc->sc_root_token = root_mount_hold(device_get_nameunit(sc->dev)); 417 return (0); 418err: 419 if (sc->irq_res) 420 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); 421 if (sc->base_res) { 422 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, 423 sc->base_res); 424 } 425 mtx_destroy(&sc->mtx); 426 return (ENOMEM); 427} 428 429static int 430cbb_pci_detach(device_t brdev) 431{ 432#if defined(NEW_PCIB) && defined(PCI_RES_BUS) 433 struct cbb_softc *sc = device_get_softc(brdev); 434#endif 435 int error; 436 437 error = cbb_detach(brdev); 438#if defined(NEW_PCIB) && defined(PCI_RES_BUS) 439 if (error == 0) 440 pcib_free_secbus(brdev, &sc->bus); 441#endif 442 return (error); 443} 444 445static void 446cbb_chipinit(struct cbb_softc *sc) 447{ 448 uint32_t mux, sysctrl, reg; 449 450 /* Set CardBus latency timer */ 451 if (pci_read_config(sc->dev, PCIR_SECLAT_2, 1) < 0x20) 452 pci_write_config(sc->dev, PCIR_SECLAT_2, 0x20, 1); 453 454 /* Set PCI latency timer */ 455 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) 456 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); 457 458 /* Enable DMA, memory access for this card and I/O access for children */ 459 pci_enable_busmaster(sc->dev); 460 pci_enable_io(sc->dev, SYS_RES_IOPORT); 461 pci_enable_io(sc->dev, SYS_RES_MEMORY); 462 463 /* disable Legacy IO */ 464 switch (sc->chipset) { 465 case CB_RF5C46X: 466 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, 467 & ~(CBBM_BRIDGECTRL_RL_3E0_EN | 468 CBBM_BRIDGECTRL_RL_3E2_EN), 2); 469 break; 470 default: 471 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); 472 break; 473 } 474 475 /* Use PCI interrupt for interrupt routing */ 476 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, 477 & ~(CBBM_BRIDGECTRL_MASTER_ABORT | 478 CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN), 479 | CBBM_BRIDGECTRL_WRITE_POST_EN, 480 2); 481 482 /* 483 * XXX this should be a function table, ala OLDCARD. This means 484 * that we could more easily support ISA interrupts for pccard 485 * cards if we had to. 486 */ 487 switch (sc->chipset) { 488 case CB_TI113X: 489 /* 490 * The TI 1031, TI 1130 and TI 1131 all require another bit 491 * be set to enable PCI routing of interrupts, and then 492 * a bit for each of the CSC and Function interrupts we 493 * want routed. 494 */ 495 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, 496 | CBBM_CBCTRL_113X_PCI_INTR | 497 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 498 1); 499 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, 500 & ~(CBBM_DEVCTRL_INT_SERIAL | 501 CBBM_DEVCTRL_INT_PCI), 1); 502 break; 503 case CB_TI12XX: 504 /* 505 * Some TI 12xx (and [14][45]xx) based pci cards 506 * sometimes have issues with the MFUNC register not 507 * being initialized due to a bad EEPROM on board. 508 * Laptops that this matters on have this register 509 * properly initialized. 510 * 511 * The TI125X parts have a different register. 512 * 513 * Note: Only the lower two nibbles matter. When set 514 * to 0, the MFUNC{0,1} pins are GPIO, which isn't 515 * going to work out too well because we specifically 516 * program these parts to parallel interrupt signalling 517 * elsewhere. We preserve the upper bits of this 518 * register since changing them have subtle side effects 519 * for different variants of the card and are 520 * extremely difficult to exaustively test. 521 * 522 * Also, the TI 1510/1520 changed the default for the MFUNC 523 * register from 0x0 to 0x1000 to enable IRQSER by default. 524 * We want to be careful to avoid overriding that, and the 525 * below test will do that. Should this check prove to be 526 * too permissive, we should just check against 0 and 0x1000 527 * and not touch it otherwise. 528 */ 529 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); 530 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); 531 if ((mux & (CBBM_MFUNC_PIN0 | CBBM_MFUNC_PIN1)) == 0) { 532 mux = (mux & ~CBBM_MFUNC_PIN0) | 533 CBBM_MFUNC_PIN0_INTA; 534 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) 535 mux = (mux & ~CBBM_MFUNC_PIN1) | 536 CBBM_MFUNC_PIN1_INTB; 537 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); 538 } 539 /*FALLTHROUGH*/ 540 case CB_TI125X: 541 /* 542 * Disable zoom video. Some machines initialize this 543 * improperly and exerpience has shown that this helps 544 * prevent strange behavior. We don't support zoom 545 * video anyway, so no harm can come from this. 546 */ 547 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); 548 break; 549 case CB_O2MICRO: 550 /* 551 * Issue #1: INT# generated at the same time as 552 * selected ISA IRQ. When IREQ# or STSCHG# is active, 553 * in addition to the ISA IRQ being generated, INT# 554 * will also be generated at the same time. 555 * 556 * Some of the older controllers have an issue in 557 * which the slot's PCI INT# will be asserted whenever 558 * IREQ# or STSCGH# is asserted even if ExCA registers 559 * 03h or 05h have an ISA IRQ selected. 560 * 561 * The fix for this issue, which will work for any 562 * controller (old or new), is to set ExCA registers 563 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. 564 * These bits are undocumented. By setting this 565 * register (of each slot) to '1010xxxxb' a routing of 566 * IREQ# to INTC# and STSCHG# to INTC# is selected. 567 * Since INTC# isn't connected there will be no 568 * unexpected PCI INT when IREQ# or STSCHG# is active. 569 * However, INTA# (slot 0) or INTB# (slot 1) will 570 * still be correctly generated if NO ISA IRQ is 571 * selected (ExCA regs 03h or 05h are cleared). 572 */ 573 reg = exca_getb(&sc->exca, EXCA_O2MICRO_CTRL_C); 574 reg = (reg & 0x0f) | 575 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; 576 exca_putb(&sc->exca, EXCA_O2MICRO_CTRL_C, reg); 577 break; 578 case CB_TOPIC97: 579 /* 580 * Disable Zoom Video, ToPIC 97, 100. 581 */ 582 pci_write_config(sc->dev, TOPIC97_ZV_CONTROL, 0, 1); 583 /* 584 * ToPIC 97, 100 585 * At offset 0xa1: INTERRUPT CONTROL register 586 * 0x1: Turn on INT interrupts. 587 */ 588 PCI_MASK_CONFIG(sc->dev, TOPIC_INTCTRL, 589 | TOPIC97_INTCTRL_INTIRQSEL, 1); 590 /* 591 * ToPIC97, 100 592 * Need to assert support for low voltage cards 593 */ 594 exca_setb(&sc->exca, EXCA_TOPIC97_CTRL, 595 EXCA_TOPIC97_CTRL_LV_MASK); 596 goto topic_common; 597 case CB_TOPIC95: 598 /* 599 * SOCKETCTRL appears to be TOPIC 95/B specific 600 */ 601 PCI_MASK_CONFIG(sc->dev, TOPIC95_SOCKETCTRL, 602 | TOPIC95_SOCKETCTRL_SCR_IRQSEL, 4); 603 604 topic_common:; 605 /* 606 * At offset 0xa0: SLOT CONTROL 607 * 0x80 Enable CardBus Functionality 608 * 0x40 Enable CardBus and PC Card registers 609 * 0x20 Lock ID in exca regs 610 * 0x10 Write protect ID in config regs 611 * Clear the rest of the bits, which defaults the slot 612 * in legacy mode to 0x3e0 and offset 0. (legacy 613 * mode is determined elsewhere) 614 */ 615 pci_write_config(sc->dev, TOPIC_SLOTCTRL, 616 TOPIC_SLOTCTRL_SLOTON | 617 TOPIC_SLOTCTRL_SLOTEN | 618 TOPIC_SLOTCTRL_ID_LOCK | 619 TOPIC_SLOTCTRL_ID_WP, 1); 620 621 /* 622 * At offset 0xa3 Card Detect Control Register 623 * 0x80 CARDBUS enbale 624 * 0x01 Cleared for hardware change detect 625 */ 626 PCI_MASK2_CONFIG(sc->dev, TOPIC_CDC, 627 | TOPIC_CDC_CARDBUS, & ~TOPIC_CDC_SWDETECT, 4); 628 break; 629 } 630 631 /* 632 * Need to tell ExCA registers to CSC interrupts route via PCI 633 * interrupts. There are two ways to do this. One is to set 634 * INTR_ENABLE and the other is to set CSC to 0. Since both 635 * methods are mutually compatible, we do both. 636 */ 637 exca_putb(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE); 638 exca_putb(&sc->exca, EXCA_CSC_INTR, 0); 639 640 cbb_disable_func_intr(sc); 641 642 /* close all memory and io windows */ 643 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); 644 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); 645 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); 646 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); 647 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); 648 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); 649 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); 650 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); 651} 652 653static int 654cbb_route_interrupt(device_t pcib, device_t dev, int pin) 655{ 656 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib); 657 658 return (rman_get_start(sc->irq_res)); 659} 660 661static int 662cbb_pci_shutdown(device_t brdev) 663{ 664 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 665 666 /* 667 * We're about to pull the rug out from the card, so mark it as 668 * gone to prevent harm. 669 */ 670 sc->cardok = 0; 671 672 /* 673 * Place the cards in reset, turn off the interrupts and power 674 * down the socket. 675 */ 676 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); 677 exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); 678 cbb_set(sc, CBB_SOCKET_MASK, 0); 679 cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff); 680 cbb_power(brdev, CARD_OFF); 681 682 /* 683 * For paranoia, turn off all address decoding. Really not needed, 684 * it seems, but it can't hurt 685 */ 686 exca_putb(&sc->exca, EXCA_ADDRWIN_ENABLE, 0); 687 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); 688 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); 689 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); 690 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); 691 pci_write_config(brdev, CBBR_IOBASE0, 0, 4); 692 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); 693 pci_write_config(brdev, CBBR_IOBASE1, 0, 4); 694 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); 695 return (0); 696} 697 698static int 699cbb_pci_filt(void *arg) 700{ 701 struct cbb_softc *sc = arg; 702 uint32_t sockevent; 703 uint8_t csc; 704 int retval = FILTER_STRAY; 705 706 /* 707 * Some chips also require us to read the old ExCA registe for card 708 * status change when we route CSC vis PCI. This isn't supposed to be 709 * required, but it clears the interrupt state on some chipsets. 710 * Maybe there's a setting that would obviate its need. Maybe we 711 * should test the status bits and deal with them, but so far we've 712 * not found any machines that don't also give us the socket status 713 * indication above. 714 * 715 * This call used to be unconditional. However, further research 716 * suggests that we hit this condition when the card READY interrupt 717 * fired. So now we only read it for 16-bit cards, and we only claim 718 * the interrupt if READY is set. If this still causes problems, then 719 * the next step would be to read this if we have a 16-bit card *OR* 720 * we have no card. We treat the READY signal as if it were the power 721 * completion signal. Some bridges may double signal things here, bit 722 * signalling twice should be OK since we only sleep on the powerintr 723 * in one place and a double wakeup would be benign there. 724 */ 725 if (sc->flags & CBB_16BIT_CARD) { 726 csc = exca_getb(&sc->exca, EXCA_CSC); 727 if (csc & EXCA_CSC_READY) { 728 atomic_add_int(&sc->powerintr, 1); 729 wakeup((void *)&sc->powerintr); 730 retval = FILTER_HANDLED; 731 } 732 } 733 734 /* 735 * Read the socket event. Sometimes, the theory goes, the PCI bus is 736 * so loaded that it cannot satisfy the read request, so we get 737 * garbage back from the following read. We have to filter out the 738 * garbage so that we don't spontaneously reset the card under high 739 * load. PCI isn't supposed to act like this. No doubt this is a bug 740 * in the PCI bridge chipset (or cbb brige) that's being used in 741 * certain amd64 laptops today. Work around the issue by assuming 742 * that any bits we don't know about being set means that we got 743 * garbage. 744 */ 745 sockevent = cbb_get(sc, CBB_SOCKET_EVENT); 746 if (sockevent != 0 && (sockevent & ~CBB_SOCKET_EVENT_VALID_MASK) == 0) { 747 /* 748 * If anything has happened to the socket, we assume that the 749 * card is no longer OK, and we shouldn't call its ISR. We 750 * set cardok as soon as we've attached the card. This helps 751 * in a noisy eject, which happens all too often when users 752 * are ejecting their PC Cards. 753 * 754 * We use this method in preference to checking to see if the 755 * card is still there because the check suffers from a race 756 * condition in the bouncing case. 757 */ 758#define DELTA (CBB_SOCKET_MASK_CD) 759 if (sockevent & DELTA) { 760 cbb_clrb(sc, CBB_SOCKET_MASK, DELTA); 761 cbb_set(sc, CBB_SOCKET_EVENT, DELTA); 762 sc->cardok = 0; 763 cbb_disable_func_intr(sc); 764 wakeup(&sc->intrhand); 765 } 766#undef DELTA 767 768 /* 769 * Wakeup anybody waiting for a power interrupt. We have to 770 * use atomic_add_int for wakups on other cores. 771 */ 772 if (sockevent & CBB_SOCKET_EVENT_POWER) { 773 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_EVENT_POWER); 774 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_POWER); 775 atomic_add_int(&sc->powerintr, 1); 776 wakeup((void *)&sc->powerintr); 777 } 778 779 /* 780 * Status change interrupts aren't presently used in the 781 * rest of the driver. For now, just ACK them. 782 */ 783 if (sockevent & CBB_SOCKET_EVENT_CSTS) 784 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_CSTS); 785 retval = FILTER_HANDLED; 786 } 787 return retval; 788} 789 790#if defined(NEW_PCIB) && defined(PCI_RES_BUS) 791static struct resource * 792cbb_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 793 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 794{ 795 struct cbb_softc *sc; 796 797 sc = device_get_softc(bus); 798 if (type == PCI_RES_BUS) 799 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, 800 count, flags)); 801 return (cbb_alloc_resource(bus, child, type, rid, start, end, count, 802 flags)); 803} 804 805static int 806cbb_pci_adjust_resource(device_t bus, device_t child, 807 struct resource *r, rman_res_t start, rman_res_t end) 808{ 809 struct cbb_softc *sc; 810 811 sc = device_get_softc(bus); 812 if (rman_get_type(r) == PCI_RES_BUS) { 813 if (!rman_is_region_manager(r, &sc->bus.rman)) 814 return (EINVAL); 815 return (rman_adjust_resource(r, start, end)); 816 } 817 return (bus_generic_adjust_resource(bus, child, r, start, end)); 818} 819 820static int 821cbb_pci_release_resource(device_t bus, device_t child, struct resource *r) 822{ 823 struct cbb_softc *sc; 824 int error; 825 826 sc = device_get_softc(bus); 827 if (rman_get_type(r) == PCI_RES_BUS) { 828 if (!rman_is_region_manager(r, &sc->bus.rman)) 829 return (EINVAL); 830 if (rman_get_flags(r) & RF_ACTIVE) { 831 error = bus_deactivate_resource(child, r); 832 if (error) 833 return (error); 834 } 835 return (rman_release_resource(r)); 836 } 837 return (cbb_release_resource(bus, child, r)); 838} 839#endif 840 841/************************************************************************/ 842/* PCI compat methods */ 843/************************************************************************/ 844 845static int 846cbb_maxslots(device_t brdev) 847{ 848 return (0); 849} 850 851static uint32_t 852cbb_read_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, int width) 853{ 854 /* 855 * Pass through to the next ppb up the chain (i.e. our grandparent). 856 */ 857 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), 858 b, s, f, reg, width)); 859} 860 861static void 862cbb_write_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, 863 int width) 864{ 865 /* 866 * Pass through to the next ppb up the chain (i.e. our grandparent). 867 */ 868 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), 869 b, s, f, reg, val, width); 870} 871 872static int 873cbb_pci_suspend(device_t brdev) 874{ 875 int error = 0; 876 struct cbb_softc *sc = device_get_softc(brdev); 877 878 error = bus_generic_suspend(brdev); 879 if (error != 0) 880 return (error); 881 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ 882 sc->cardok = 0; /* Card is bogus now */ 883 return (0); 884} 885 886static int 887cbb_pci_resume(device_t brdev) 888{ 889 int error = 0; 890 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); 891 uint32_t tmp; 892 893 /* 894 * In the APM and early ACPI era, BIOSes saved the PCI config 895 * registers. As chips became more complicated, that functionality moved 896 * into the ACPI code / tables. We must therefore, restore the settings 897 * we made here to make sure the device come back. Transitions to Dx 898 * from D0 and back to D0 cause the bridge to lose its config space, so 899 * all the bus mappings and such are preserved. 900 * 901 * The PCI layer handles standard PCI registers like the 902 * command register and BARs, but cbb-specific registers are 903 * handled here. 904 */ 905 sc->chipinit(sc); 906 907 /* reset interrupt -- Do we really need to do this? */ 908 tmp = cbb_get(sc, CBB_SOCKET_EVENT); 909 cbb_set(sc, CBB_SOCKET_EVENT, tmp); 910 911 /* CSC Interrupt: Card detect interrupt on */ 912 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); 913 914 /* Signal the thread to wakeup. */ 915 wakeup(&sc->intrhand); 916 917 error = bus_generic_resume(brdev); 918 919 return (error); 920} 921 922static device_method_t cbb_methods[] = { 923 /* Device interface */ 924 DEVMETHOD(device_probe, cbb_pci_probe), 925 DEVMETHOD(device_attach, cbb_pci_attach), 926 DEVMETHOD(device_detach, cbb_pci_detach), 927 DEVMETHOD(device_shutdown, cbb_pci_shutdown), 928 DEVMETHOD(device_suspend, cbb_pci_suspend), 929 DEVMETHOD(device_resume, cbb_pci_resume), 930 931 /* bus methods */ 932 DEVMETHOD(bus_read_ivar, cbb_read_ivar), 933 DEVMETHOD(bus_write_ivar, cbb_write_ivar), 934#if defined(NEW_PCIB) && defined(PCI_RES_BUS) 935 DEVMETHOD(bus_alloc_resource, cbb_pci_alloc_resource), 936 DEVMETHOD(bus_adjust_resource, cbb_pci_adjust_resource), 937 DEVMETHOD(bus_release_resource, cbb_pci_release_resource), 938#else 939 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), 940 DEVMETHOD(bus_release_resource, cbb_release_resource), 941#endif 942 DEVMETHOD(bus_activate_resource, cbb_activate_resource), 943 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), 944 DEVMETHOD(bus_driver_added, cbb_driver_added), 945 DEVMETHOD(bus_child_detached, cbb_child_detached), 946 DEVMETHOD(bus_setup_intr, cbb_setup_intr), 947 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), 948 DEVMETHOD(bus_child_present, cbb_child_present), 949 950 /* 16-bit card interface */ 951 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), 952 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), 953 954 /* power interface */ 955 DEVMETHOD(power_enable_socket, cbb_power_enable_socket), 956 DEVMETHOD(power_disable_socket, cbb_power_disable_socket), 957 958 /* pcib compatibility interface */ 959 DEVMETHOD(pcib_maxslots, cbb_maxslots), 960 DEVMETHOD(pcib_read_config, cbb_read_config), 961 DEVMETHOD(pcib_write_config, cbb_write_config), 962 DEVMETHOD(pcib_route_interrupt, cbb_route_interrupt), 963 964 DEVMETHOD_END 965}; 966 967static driver_t cbb_driver = { 968 "cbb", 969 cbb_methods, 970 sizeof(struct cbb_softc) 971}; 972 973DRIVER_MODULE(cbb, pci, cbb_driver, 0, 0); 974MODULE_PNP_INFO("W32:vendor/device;D:#", pci, cbb, yc_chipsets, 975 nitems(yc_chipsets) - 1); 976MODULE_DEPEND(cbb, exca, 1, 1, 1); 977