1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#ifndef __NVME_PRIVATE_H__ 30#define __NVME_PRIVATE_H__ 31 32#include <sys/param.h> 33#include <sys/bio.h> 34#include <sys/bus.h> 35#include <sys/kernel.h> 36#include <sys/lock.h> 37#include <sys/malloc.h> 38#include <sys/memdesc.h> 39#include <sys/module.h> 40#include <sys/mutex.h> 41#include <sys/rman.h> 42#include <sys/systm.h> 43#include <sys/taskqueue.h> 44 45#include <vm/uma.h> 46 47#include <machine/bus.h> 48 49#include "nvme.h" 50 51#define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 52 53MALLOC_DECLARE(M_NVME); 54 55#define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 56#define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 57 58#define NVME_ADMIN_TRACKERS (16) 59#define NVME_ADMIN_ENTRIES (128) 60 61/* 62 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 63 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 64 * will allow outstanding on an I/O qpair at any time. The only advantage in 65 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 66 * the contents of the submission and completion queues, it will show a longer 67 * history of data. 68 */ 69#define NVME_IO_ENTRIES (256) 70#define NVME_IO_TRACKERS (128) 71#define NVME_MIN_IO_TRACKERS (4) 72#define NVME_MAX_IO_TRACKERS (1024) 73 74#define NVME_INT_COAL_TIME (0) /* disabled */ 75#define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 76 77#define NVME_MAX_NAMESPACES (16) 78#define NVME_MAX_CONSUMERS (2) 79#define NVME_MAX_ASYNC_EVENTS (8) 80 81#define NVME_ADMIN_TIMEOUT_PERIOD (60) /* in seconds */ 82#define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 83#define NVME_MIN_TIMEOUT_PERIOD (5) 84#define NVME_MAX_TIMEOUT_PERIOD (120) 85 86#define NVME_DEFAULT_RETRY_COUNT (4) 87 88/* Maximum log page size to fetch for AERs. */ 89#define NVME_MAX_AER_LOG_SIZE (4096) 90 91/* 92 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define 93 * it. 94 */ 95#ifndef CACHE_LINE_SIZE 96#define CACHE_LINE_SIZE (64) 97#endif 98 99#define NVME_GONE 0xfffffffful 100 101extern int32_t nvme_retry_count; 102extern bool nvme_verbose_cmd_dump; 103 104struct nvme_completion_poll_status { 105 struct nvme_completion cpl; 106 int done; 107}; 108 109struct nvme_request { 110 struct nvme_command cmd; 111 struct nvme_qpair *qpair; 112 struct memdesc payload; 113 nvme_cb_fn_t cb_fn; 114 void *cb_arg; 115 int32_t retries; 116 bool payload_valid; 117 bool timeout; 118 bool spare[2]; /* Future use */ 119 STAILQ_ENTRY(nvme_request) stailq; 120}; 121 122struct nvme_async_event_request { 123 struct nvme_controller *ctrlr; 124 struct nvme_request *req; 125 struct nvme_completion cpl; 126 uint32_t log_page_id; 127 uint32_t log_page_size; 128 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 129}; 130 131struct nvme_tracker { 132 TAILQ_ENTRY(nvme_tracker) tailq; 133 struct nvme_request *req; 134 struct nvme_qpair *qpair; 135 sbintime_t deadline; 136 bus_dmamap_t payload_dma_map; 137 uint16_t cid; 138 139 uint64_t *prp; 140 bus_addr_t prp_bus_addr; 141}; 142 143enum nvme_recovery { 144 RECOVERY_NONE = 0, /* Normal operations */ 145 RECOVERY_WAITING, /* waiting for the reset to complete */ 146}; 147struct nvme_qpair { 148 struct nvme_controller *ctrlr; 149 uint32_t id; 150 int domain; 151 int cpu; 152 153 uint16_t vector; 154 int rid; 155 struct resource *res; 156 void *tag; 157 158 struct callout timer; /* recovery lock */ 159 bool timer_armed; /* recovery lock */ 160 enum nvme_recovery recovery_state; /* recovery lock */ 161 162 uint32_t num_entries; 163 uint32_t num_trackers; 164 uint32_t sq_tdbl_off; 165 uint32_t cq_hdbl_off; 166 167 uint32_t phase; 168 uint32_t sq_head; 169 uint32_t sq_tail; 170 uint32_t cq_head; 171 172 int64_t num_cmds; 173 int64_t num_intr_handler_calls; 174 int64_t num_retries; 175 int64_t num_failures; 176 int64_t num_ignored; 177 int64_t num_recovery_nolock; 178 179 struct nvme_command *cmd; 180 struct nvme_completion *cpl; 181 182 bus_dma_tag_t dma_tag; 183 bus_dma_tag_t dma_tag_payload; 184 185 bus_dmamap_t queuemem_map; 186 uint64_t cmd_bus_addr; 187 uint64_t cpl_bus_addr; 188 189 TAILQ_HEAD(, nvme_tracker) free_tr; 190 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 191 STAILQ_HEAD(, nvme_request) queued_req; 192 193 struct nvme_tracker **act_tr; 194 195 struct mtx_padalign lock; 196 struct mtx_padalign recovery; 197} __aligned(CACHE_LINE_SIZE); 198 199struct nvme_namespace { 200 struct nvme_controller *ctrlr; 201 struct nvme_namespace_data data; 202 uint32_t id; 203 uint32_t flags; 204 struct cdev *cdev; 205 void *cons_cookie[NVME_MAX_CONSUMERS]; 206 uint32_t boundary; 207 struct mtx lock; 208}; 209 210/* 211 * One of these per allocated PCI device. 212 */ 213struct nvme_controller { 214 device_t dev; 215 216 struct mtx lock; 217 int domain; 218 uint32_t ready_timeout_in_ms; 219 uint32_t quirks; 220#define QUIRK_DELAY_B4_CHK_RDY 1 /* Can't touch MMIO on disable */ 221#define QUIRK_DISABLE_TIMEOUT 2 /* Disable broken completion timeout feature */ 222#define QUIRK_INTEL_ALIGNMENT 4 /* Pre NVMe 1.3 performance alignment */ 223#define QUIRK_AHCI 8 /* Attached via AHCI redirect */ 224 225 bus_space_tag_t bus_tag; 226 bus_space_handle_t bus_handle; 227 int resource_id; 228 struct resource *resource; 229 230 /* 231 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 232 * separate from the control registers which are in BAR 0/1. These 233 * members track the mapping of BAR 4/5 for that reason. 234 */ 235 int bar4_resource_id; 236 struct resource *bar4_resource; 237 238 int msi_count; 239 uint32_t enable_aborts; 240 241 uint32_t num_io_queues; 242 uint32_t max_hw_pend_io; 243 244 /* Fields for tracking progress during controller initialization. */ 245 struct intr_config_hook config_hook; 246 uint32_t ns_identified; 247 uint32_t queues_created; 248 249 struct task reset_task; 250 struct taskqueue *taskqueue; 251 252 /* For shared legacy interrupt. */ 253 int rid; 254 struct resource *res; 255 void *tag; 256 257 /** maximum i/o size in bytes */ 258 uint32_t max_xfer_size; 259 260 /** LO and HI capacity mask */ 261 uint32_t cap_lo; 262 uint32_t cap_hi; 263 264 /** Page size and log2(page_size) - 12 that we're currently using */ 265 uint32_t page_size; 266 uint32_t mps; 267 268 /** interrupt coalescing time period (in microseconds) */ 269 uint32_t int_coal_time; 270 271 /** interrupt coalescing threshold */ 272 uint32_t int_coal_threshold; 273 274 /** timeout period in seconds */ 275 uint32_t admin_timeout_period; 276 uint32_t timeout_period; 277 278 /** doorbell stride */ 279 uint32_t dstrd; 280 281 struct nvme_qpair adminq; 282 struct nvme_qpair *ioq; 283 284 struct nvme_registers *regs; 285 286 struct nvme_controller_data cdata; 287 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 288 289 struct cdev *cdev; 290 291 /** bit mask of event types currently enabled for async events */ 292 uint32_t async_event_config; 293 294 uint32_t num_aers; 295 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 296 297 void *cons_cookie[NVME_MAX_CONSUMERS]; 298 299 uint32_t is_resetting; 300 uint32_t is_initialized; 301 uint32_t notification_sent; 302 303 bool is_failed; 304 bool is_dying; 305 STAILQ_HEAD(, nvme_request) fail_req; 306 307 /* Host Memory Buffer */ 308 int hmb_nchunks; 309 size_t hmb_chunk; 310 bus_dma_tag_t hmb_tag; 311 struct nvme_hmb_chunk { 312 bus_dmamap_t hmbc_map; 313 void *hmbc_vaddr; 314 uint64_t hmbc_paddr; 315 } *hmb_chunks; 316 bus_dma_tag_t hmb_desc_tag; 317 bus_dmamap_t hmb_desc_map; 318 struct nvme_hmb_desc *hmb_desc_vaddr; 319 uint64_t hmb_desc_paddr; 320}; 321 322#define nvme_mmio_offsetof(reg) \ 323 offsetof(struct nvme_registers, reg) 324 325#define nvme_mmio_read_4(sc, reg) \ 326 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 327 nvme_mmio_offsetof(reg)) 328 329#define nvme_mmio_write_4(sc, reg, val) \ 330 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 331 nvme_mmio_offsetof(reg), val) 332 333#define nvme_mmio_write_8(sc, reg, val) \ 334 do { \ 335 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 336 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 337 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 338 nvme_mmio_offsetof(reg)+4, \ 339 (val & 0xFFFFFFFF00000000ULL) >> 32); \ 340 } while (0); 341 342#define nvme_printf(ctrlr, fmt, args...) \ 343 device_printf(ctrlr->dev, fmt, ##args) 344 345void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 346 347void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 348 void *payload, 349 nvme_cb_fn_t cb_fn, void *cb_arg); 350void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 351 uint32_t nsid, void *payload, 352 nvme_cb_fn_t cb_fn, void *cb_arg); 353void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 354 uint32_t microseconds, 355 uint32_t threshold, 356 nvme_cb_fn_t cb_fn, 357 void *cb_arg); 358void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 359 struct nvme_error_information_entry *payload, 360 uint32_t num_entries, /* 0 = max */ 361 nvme_cb_fn_t cb_fn, 362 void *cb_arg); 363void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 364 uint32_t nsid, 365 struct nvme_health_information_page *payload, 366 nvme_cb_fn_t cb_fn, 367 void *cb_arg); 368void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 369 struct nvme_firmware_page *payload, 370 nvme_cb_fn_t cb_fn, 371 void *cb_arg); 372void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 373 struct nvme_qpair *io_que, 374 nvme_cb_fn_t cb_fn, void *cb_arg); 375void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 376 struct nvme_qpair *io_que, 377 nvme_cb_fn_t cb_fn, void *cb_arg); 378void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 379 struct nvme_qpair *io_que, 380 nvme_cb_fn_t cb_fn, void *cb_arg); 381void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 382 struct nvme_qpair *io_que, 383 nvme_cb_fn_t cb_fn, void *cb_arg); 384void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 385 uint32_t num_queues, nvme_cb_fn_t cb_fn, 386 void *cb_arg); 387void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 388 uint32_t state, 389 nvme_cb_fn_t cb_fn, void *cb_arg); 390void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 391 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 392 393void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 394 395int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 396void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 397void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr); 398void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 399/* ctrlr defined as void * to allow use with config_intrhook. */ 400void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 401void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 402 struct nvme_request *req); 403void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 404 struct nvme_request *req); 405 406int nvme_qpair_construct(struct nvme_qpair *qpair, 407 uint32_t num_entries, uint32_t num_trackers, 408 struct nvme_controller *ctrlr); 409void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 410 struct nvme_tracker *tr); 411bool nvme_qpair_process_completions(struct nvme_qpair *qpair); 412void nvme_qpair_submit_request(struct nvme_qpair *qpair, 413 struct nvme_request *req); 414void nvme_qpair_reset(struct nvme_qpair *qpair); 415void nvme_qpair_fail(struct nvme_qpair *qpair); 416void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 417 struct nvme_request *req, 418 uint32_t sct, uint32_t sc); 419 420void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 421void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 422void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 423 424void nvme_io_qpair_enable(struct nvme_qpair *qpair); 425void nvme_io_qpair_disable(struct nvme_qpair *qpair); 426void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 427 428int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id, 429 struct nvme_controller *ctrlr); 430void nvme_ns_destruct(struct nvme_namespace *ns); 431 432void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 433 434void nvme_qpair_print_command(struct nvme_qpair *qpair, 435 struct nvme_command *cmd); 436void nvme_qpair_print_completion(struct nvme_qpair *qpair, 437 struct nvme_completion *cpl); 438 439int nvme_attach(device_t dev); 440int nvme_shutdown(device_t dev); 441int nvme_detach(device_t dev); 442 443/* 444 * Wait for a command to complete using the nvme_completion_poll_cb. Used in 445 * limited contexts where the caller knows it's OK to block briefly while the 446 * command runs. The ISR will run the callback which will set status->done to 447 * true, usually within microseconds. If not, then after one second timeout 448 * handler should reset the controller and abort all outstanding requests 449 * including this polled one. If still not after ten seconds, then something is 450 * wrong with the driver, and panic is the only way to recover. 451 * 452 * Most commands using this interface aren't actual I/O to the drive's media so 453 * complete within a few microseconds. Adaptively spin for one tick to catch the 454 * vast majority of these without waiting for a tick plus scheduling delays. Since 455 * these are on startup, this drastically reduces startup time. 456 */ 457static __inline 458void 459nvme_completion_poll(struct nvme_completion_poll_status *status) 460{ 461 int timeout = ticks + 10 * hz; 462 sbintime_t delta_t = SBT_1US; 463 464 while (!atomic_load_acq_int(&status->done)) { 465 if (timeout - ticks < 0) 466 panic("NVME polled command failed to complete within 10s."); 467 pause_sbt("nvme", delta_t, 0, C_PREL(1)); 468 delta_t = min(SBT_1MS, delta_t * 3 / 2); 469 } 470} 471 472static __inline void 473nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 474{ 475 uint64_t *bus_addr = (uint64_t *)arg; 476 477 KASSERT(nseg == 1, ("number of segments (%d) is not 1", nseg)); 478 if (error != 0) 479 printf("nvme_single_map err %d\n", error); 480 *bus_addr = seg[0].ds_addr; 481} 482 483static __inline struct nvme_request * 484_nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg) 485{ 486 struct nvme_request *req; 487 488 req = malloc(sizeof(*req), M_NVME, M_NOWAIT | M_ZERO); 489 if (req != NULL) { 490 req->cb_fn = cb_fn; 491 req->cb_arg = cb_arg; 492 req->timeout = true; 493 } 494 return (req); 495} 496 497static __inline struct nvme_request * 498nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 499 nvme_cb_fn_t cb_fn, void *cb_arg) 500{ 501 struct nvme_request *req; 502 503 req = _nvme_allocate_request(cb_fn, cb_arg); 504 if (req != NULL) { 505 req->payload = memdesc_vaddr(payload, payload_size); 506 req->payload_valid = true; 507 } 508 return (req); 509} 510 511static __inline struct nvme_request * 512nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg) 513{ 514 struct nvme_request *req; 515 516 req = _nvme_allocate_request(cb_fn, cb_arg); 517 return (req); 518} 519 520static __inline struct nvme_request * 521nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg) 522{ 523 struct nvme_request *req; 524 525 req = _nvme_allocate_request(cb_fn, cb_arg); 526 if (req != NULL) { 527 req->payload = memdesc_bio(bio); 528 req->payload_valid = true; 529 } 530 return (req); 531} 532 533static __inline struct nvme_request * 534nvme_allocate_request_ccb(union ccb *ccb, nvme_cb_fn_t cb_fn, void *cb_arg) 535{ 536 struct nvme_request *req; 537 538 req = _nvme_allocate_request(cb_fn, cb_arg); 539 if (req != NULL) { 540 req->payload = memdesc_ccb(ccb); 541 req->payload_valid = true; 542 } 543 544 return (req); 545} 546 547#define nvme_free_request(req) free(req, M_NVME) 548 549void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 550 const struct nvme_completion *async_cpl, 551 uint32_t log_page_id, void *log_page_buffer, 552 uint32_t log_page_size); 553void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 554void nvme_notify_new_controller(struct nvme_controller *ctrlr); 555void nvme_notify_ns(struct nvme_controller *ctrlr, int nsid); 556 557void nvme_ctrlr_shared_handler(void *arg); 558void nvme_ctrlr_poll(struct nvme_controller *ctrlr); 559 560int nvme_ctrlr_suspend(struct nvme_controller *ctrlr); 561int nvme_ctrlr_resume(struct nvme_controller *ctrlr); 562 563#endif /* __NVME_PRIVATE_H__ */ 564