1/* 2 * Copyright (c) 2017 Stormshield. 3 * Copyright (c) 2017 Semihalf. 4 * Copyright (c) 2015 Internet Initiative Japan Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30#ifndef _IF_MVNETAREG_H_ 31#define _IF_MVNETAREG_H_ 32 33#include "opt_mvneta.h" 34 35#if BYTE_ORDER == BIG_ENDIAN 36#error "BIG ENDIAN not supported" 37#endif 38 39#define MVNETA_SIZE 0x4000 40 41#define MVNETA_NWINDOW 6 42#define MVNETA_NREMAP 4 43 44#define MVNETA_MAX_QUEUE_SIZE 8 45#define MVNETA_RX_QNUM_MAX 1 46/* XXX: Currently multi-queue can be used on the Tx side only */ 47#ifdef MVNETA_MULTIQUEUE 48#define MVNETA_TX_QNUM_MAX 2 49#else 50#define MVNETA_TX_QNUM_MAX 1 51#endif 52 53#if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0 54#error "MVNETA_TX_QNUM_MAX Should be a power of 2" 55#endif 56#if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0 57#error "MVNETA_RX_QNUM_MAX Should be a power of 2" 58#endif 59 60#define MVNETA_QUEUE(n) (1 << (n)) 61#define MVNETA_QUEUE_ALL 0xff 62#define MVNETA_TX_QUEUE_ALL ((1<<MVNETA_TX_QNUM_MAX)-1) 63#define MVNETA_RX_QUEUE_ALL ((1<<MVNETA_RX_QNUM_MAX)-1) 64 65/* 66 * Ethernet Unit Registers 67 * GbE0 BASE 0x00007.0000 SIZE 0x4000 68 * GbE1 BASE 0x00007.4000 SIZE 0x4000 69 * 70 * TBD: reasonable bus space submapping.... 71 */ 72/* Address Decoder Registers */ 73#define MVNETA_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */ 74#define MVNETA_S(n) (0x2204 + ((n) << 3)) /* Size */ 75#define MVNETA_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */ 76#define MVNETA_BARE 0x2290 /* Base Address Enable */ 77#define MVNETA_EPAP 0x2294 /* Ethernet Port Access Protect */ 78 79/* Global Miscellaneous Registers */ 80#define MVNETA_PHYADDR 0x2000 81#define MVNETA_SMI 0x2004 82#define MVNETA_EUDA 0x2008 /* Ethernet Unit Default Address */ 83#define MVNETA_EUDID 0x200c /* Ethernet Unit Default ID */ 84#define MVNETA_MBUS_CONF 0x2010 /* MBUS configuration */ 85#define MVNETA_MBUS_RETRY_EN 0x20 /* MBUS transactions retry enable */ 86#define MVNETA_EUIC 0x2080 /* Ethernet Unit Interrupt Cause */ 87#define MVNETA_EUIM 0x2084 /* Ethernet Unit Interrupt Mask */ 88#define MVNETA_EUEA 0x2094 /* Ethernet Unit Error Address */ 89#define MVNETA_EUIAE 0x2098 /* Ethernet Unit Internal Addr Error */ 90#define MVNETA_EUC 0x20b0 /* Ethernet Unit Control */ 91 92/* Miscellaneous Registers */ 93#define MVNETA_SDC 0x241c /* SDMA Configuration */ 94 95/* Networking Controller Miscellaneous Registers */ 96#define MVNETA_PACC 0x2500 /* Port Acceleration Mode */ 97#define MVNETA_PV 0x25bc /* Port Version */ 98 99/* Rx DMA Hardware Parser Registers */ 100#define MVNETA_EVLANE 0x2410 /* VLAN EtherType */ 101#define MVNETA_MACAL 0x2414 /* MAC Address Low */ 102#define MVNETA_MACAH 0x2418 /* MAC Address High */ 103#define MVNETA_NDSCP 7 104#define MVNETA_DSCP(n) (0x2420 + ((n) << 2)) 105#define MVNETA_VPT2P 0x2440 /* VLAN Priority Tag to Priority */ 106#define MVNETA_ETP 0x24bc /* Ethernet Type Priority */ 107#define MVNETA_NDFSMT 64 108#define MVNETA_DFSMT(n) (0x3400 + ((n) << 2)) 109 /* Destination Address Filter Special Multicast Table */ 110#define MVNETA_NDFOMT 64 111#define MVNETA_DFOMT(n) (0x3500 + ((n) << 2)) 112 /* Destination Address Filter Other Multicast Table */ 113#define MVNETA_NDFUT 4 114#define MVNETA_DFUT(n) (0x3600 + ((n) << 2)) 115 /* Destination Address Filter Unicast Table */ 116 117/* Rx DMA Miscellaneous Registers */ 118#define MVNETA_PMFS 0x247c /* Port Rx Minimal Frame Size */ 119#define MVNETA_PDFC 0x2484 /* Port Rx Discard Frame Counter */ 120#define MVNETA_POFC 0x2488 /* Port Overrun Frame Counter */ 121#define MVNETA_RQC 0x2680 /* Receive Queue Command */ 122 123/* Rx DMA Networking Controller Miscellaneous Registers */ 124#define MVNETA_PRXC(q) (0x1400 + ((q) << 2)) /*Port RX queues Config*/ 125#define MVNETA_PRXSNP(q) (0x1420 + ((q) << 2)) /* Port RX queues Snoop */ 126#define MVNETA_PRXDQA(q) (0x1480 + ((q) << 2)) /*P RXqueues desc Q Addr*/ 127#define MVNETA_PRXDQS(q) (0x14a0 + ((q) << 2)) /*P RXqueues desc Q Size*/ 128#define MVNETA_PRXDQTH(q) (0x14c0 + ((q) << 2)) /*P RXqueues desc Q Thrs*/ 129#define MVNETA_PRXS(q) (0x14e0 + ((q) << 2)) /*Port RX queues Status */ 130#define MVNETA_PRXSU(q) (0x1500 + ((q) << 2)) /*P RXqueues Stat Update*/ 131#define MVNETA_PRXDI(q) (0x1520 + ((q) << 2)) /*P RXqueues Stat Update*/ 132#define MVNETA_PRXINIT 0x1cc0 /* Port RX Initialization */ 133 134/* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */ 135 136/* Tx DMA Miscellaneous Registers */ 137#define MVNETA_TQC 0x2448 /* Transmit Queue Command */ 138#define MVNETA_TQC_1 0x24e4 139#define MVNETA_PXTFTT 0x2478 /* Port Tx FIFO Threshold */ 140#define MVNETA_TXBADFCS 0x3cc0 /*Tx Bad FCS Transmitted Pckts Counter*/ 141#define MVNETA_TXDROPPED 0x3cc4 /* Tx Dropped Packets Counter */ 142 143/* Tx DMA Networking Controller Miscellaneous Registers */ 144#define MVNETA_PTXDQA(q) (0x3c00 + ((q) << 2)) /*P TXqueues desc Q Addr*/ 145#define MVNETA_PTXDQS(q) (0x3c20 + ((q) << 2)) /*P TXqueues desc Q Size*/ 146#define MVNETA_PTXS(q) (0x3c40 + ((q) << 2)) /* Port TX queues Status*/ 147#define MVNETA_PTXSU(q) (0x3c60 + ((q) << 2)) /*P TXqueues Stat Update*/ 148#define MVNETA_PTXDI(q) (0x3c80 + ((q) << 2)) /* P TXqueues Desc Index*/ 149#define MVNETA_TXTBC(q) (0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/ 150#define MVNETA_PTXINIT 0x3cf0 /* Port TX Initialization */ 151 152/* Tx DMA Packet Modification Registers */ 153#define MVNETA_NMH 15 154#define MVNETA_TXMH(n) (0x3d44 + ((n) << 2)) 155#define MVNETA_TXMTU 0x3d88 156 157/* Tx DMA Queue Arbiter Registers (Version 1) */ 158#define MVNETA_TQFPC_V1 0x24dc /* Transmit Queue Fixed Priority Cfg */ 159#define MVNETA_TQTBC_V1 0x24e0 /* Transmit Queue Token-Bucket Cfg */ 160#define MVNETA_MTU_V1 0x24e8 /* MTU */ 161#define MVNETA_PMTBS_V1 0x24ec /* Port Max Token-Bucket Size */ 162#define MVNETA_TQTBCOUNT_V1(q) (0x2700 + ((q) << 4)) 163 /* Transmit Queue Token-Bucket Counter */ 164#define MVNETA_TQTBCONFIG_V1(q) (0x2704 + ((q) << 4)) 165 /* Transmit Queue Token-Bucket Configuration */ 166#define MVNETA_PTTBC_V1 0x2740 /* Port Transmit Backet Counter */ 167 168/* Tx DMA Queue Arbiter Registers (Version 3) */ 169#define MVNETA_TQC1_V3 0x3e00 /* Transmit Queue Command1 */ 170#define MVNETA_TQFPC_V3 0x3e04 /* Transmit Queue Fixed Priority Cfg */ 171#define MVNETA_BRC_V3 0x3e08 /* Basic Refill No of Clocks */ 172#define MVNETA_MTU_V3 0x3e0c /* MTU */ 173#define MVNETA_PREFILL_V3 0x3e10 /* Port Backet Refill */ 174#define MVNETA_PMTBS_V3 0x3e14 /* Port Max Token-Bucket Size */ 175#define MVNETA_QREFILL_V3(q) (0x3e20 + ((q) << 2)) 176 /* Transmit Queue Refill */ 177#define MVNETA_QMTBS_V3(q) (0x3e40 + ((q) << 2)) 178 /* Transmit Queue Max Token-Bucket Size */ 179#define MVNETA_QTTBC_V3(q) (0x3e60 + ((q) << 2)) 180 /* Transmit Queue Token-Bucket Counter */ 181#define MVNETA_TQAC_V3(q) (0x3e80 + ((q) << 2)) 182 /* Transmit Queue Arbiter Cfg */ 183#define MVNETA_TQIPG_V3(q) (0x3ea0 + ((q) << 2)) 184 /* Transmit Queue IPG(valid q=2..3) */ 185#define MVNETA_HITKNINLOPKT_V3 0x3eb0 /* High Token in Low Packet */ 186#define MVNETA_HITKNINASYNCPKT_V3 0x3eb4 /* High Token in Async Packet */ 187#define MVNETA_LOTKNINASYNCPKT_V3 0x3eb8 /* Low Token in Async Packet */ 188#define MVNETA_TS_V3 0x3ebc /* Token Speed */ 189 190/* RX_TX DMA Registers */ 191#define MVNETA_PXC 0x2400 /* Port Configuration */ 192#define MVNETA_PXCX 0x2404 /* Port Configuration Extend */ 193#define MVNETA_MH 0x2454 /* Marvell Header */ 194 195/* Serial(SMI/MII) Registers */ 196#define MVNETA_PSC0 0x243c /* Port Serial Control0 */ 197#define MVNETA_PS0 0x2444 /* Ethernet Port Status */ 198#define MVNETA_PSERDESCFG 0x24a0 /* Serdes Configuration */ 199#define MVNETA_PSERDESSTS 0x24a4 /* Serdes Status */ 200#define MVNETA_PSOMSCD 0x24f4 /* One mS Clock Divider */ 201#define MVNETA_PSPFCCD 0x24f8 /* Periodic Flow Control Clock Divider*/ 202 203/* Gigabit Ethernet MAC Serial Parameters Configuration Registers */ 204#define MVNETA_PSPC 0x2c14 /* Port Serial Parameters Config */ 205#define MVNETA_PSP1C 0x2c94 /* Port Serial Parameters 1 Config */ 206 207/* Gigabit Ethernet Auto-Negotiation Configuration Registers */ 208#define MVNETA_PANC 0x2c0c /* Port Auto-Negotiation Configuration*/ 209 210/* Gigabit Ethernet MAC Control Registers */ 211#define MVNETA_PMACC0 0x2c00 /* Port MAC Control 0 */ 212#define MVNETA_PMACC1 0x2c04 /* Port MAC Control 1 */ 213#define MVNETA_PMACC2 0x2c08 /* Port MAC Control 2 */ 214#define MVNETA_PMACC3 0x2c48 /* Port MAC Control 3 */ 215#define MVNETA_CCFCPST(p) (0x2c58 + ((p) << 2)) /*CCFC Port Speed Timerp*/ 216#define MVNETA_PMACC4 0x2c90 /* Port MAC Control 4 */ 217 218/* Gigabit Ethernet MAC Interrupt Registers */ 219#define MVNETA_PIC 0x2c20 220#define MVNETA_PIM 0x2c24 221 222/* Gigabit Ethernet Low Power Idle Registers */ 223#define MVNETA_LPIC0 0x2cc0 /* LowPowerIdle control 0 */ 224#define MVNETA_LPIC1 0x2cc4 /* LPI control 1 */ 225#define MVNETA_LPIC2 0x2cc8 /* LPI control 2 */ 226#define MVNETA_LPIS 0x2ccc /* LPI status */ 227#define MVNETA_LPIC 0x2cd0 /* LPI counter */ 228 229/* Gigabit Ethernet MAC PRBS Check Status Registers */ 230#define MVNETA_PPRBSS 0x2c38 /* Port PRBS Status */ 231#define MVNETA_PPRBSEC 0x2c3c /* Port PRBS Error Counter */ 232 233/* Gigabit Ethernet MAC Status Registers */ 234#define MVNETA_PSR 0x2c10 /* Port Status Register0 */ 235 236/* Networking Controller Interrupt Registers */ 237#define MVNETA_PCP2Q(cpu) (0x2540 + ((cpu) << 2)) 238#define MVNETA_PRXITTH(q) (0x2580 + ((q) << 2)) 239 /* Port Rx Interrupt Threshold */ 240#define MVNETA_PRXTXTIC 0x25a0 /*Port RX_TX Threshold Interrupt Cause*/ 241#define MVNETA_PRXTXTIM 0x25a4 /*Port RX_TX Threshold Interrupt Mask */ 242#define MVNETA_PRXTXIC 0x25a8 /* Port RX_TX Interrupt Cause */ 243#define MVNETA_PRXTXIM 0x25ac /* Port RX_TX Interrupt Mask */ 244#define MVNETA_PMIC 0x25b0 /* Port Misc Interrupt Cause */ 245#define MVNETA_PMIM 0x25b4 /* Port Misc Interrupt Mask */ 246#define MVNETA_PIE 0x25b8 /* Port Interrupt Enable */ 247#define MVNETA_PSNPCFG 0x25e4 /* Port Snoop Config */ 248#define MVNETA_PSNPCFG_DESCSNP_MASK (0x3 << 4) 249#define MVNETA_PSNPCFG_BUFSNP_MASK (0x3 << 8) 250 251/* Miscellaneous Interrupt Registers */ 252#define MVNETA_PEUIAE 0x2494 /* Port Internal Address Error */ 253 254/* SGMII PHY Registers */ 255#define MVNETA_PPLLC 0x2e04 /* Power and PLL Control */ 256#define MVNETA_TESTC0 0x2e54 /* PHY Test Control 0 */ 257#define MVNETA_TESTPRBSEC0 0x2e7c /* PHY Test PRBS Error Counter 0 */ 258#define MVNETA_TESTPRBSEC1 0x2e80 /* PHY Test PRBS Error Counter 1 */ 259#define MVNETA_TESTOOB0 0x2e84 /* PHY Test OOB 0 */ 260#define MVNETA_DLE 0x2e8c /* Digital Loopback Enable */ 261#define MVNETA_RCS 0x2f18 /* Reference Clock Select */ 262#define MVNETA_COMPHYC 0x2f18 /* COMPHY Control */ 263 264/* 265 * Ethernet MAC MIB Registers 266 * GbE0 BASE 0x00007.3000 267 * GbE1 BASE 0x00007.7000 268 */ 269/* MAC MIB Counters 0x3000 - 0x307c */ 270#define MVNETA_PORTMIB_BASE 0x3000 271#define MVNETA_PORTMIB_SIZE 0x0080 272#define MVNETA_PORTMIB_NOCOUNTER 30 273 274/* Rx */ 275#define MVNETA_MIB_RX_GOOD_OCT 0x00 /* 64bit */ 276#define MVNETA_MIB_RX_BAD_OCT 0x08 277#define MVNETA_MIB_RX_GOOD_FRAME 0x10 278#define MVNETA_MIB_RX_BAD_FRAME 0x14 279#define MVNETA_MIB_RX_BCAST_FRAME 0x18 280#define MVNETA_MIB_RX_MCAST_FRAME 0x1c 281#define MVNETA_MIB_RX_FRAME64_OCT 0x20 282#define MVNETA_MIB_RX_FRAME127_OCT 0x24 283#define MVNETA_MIB_RX_FRAME255_OCT 0x28 284#define MVNETA_MIB_RX_FRAME511_OCT 0x2c 285#define MVNETA_MIB_RX_FRAME1023_OCT 0x30 286#define MVNETA_MIB_RX_FRAMEMAX_OCT 0x34 287 288/* Tx */ 289#define MVNETA_MIB_TX_MAC_TRNS_ERR 0x0c 290#define MVNETA_MIB_TX_GOOD_OCT 0x38 /* 64bit */ 291#define MVNETA_MIB_TX_GOOD_FRAME 0x40 292#define MVNETA_MIB_TX_EXCES_COL 0x44 293#define MVNETA_MIB_TX_MCAST_FRAME 0x48 294#define MVNETA_MIB_TX_BCAST_FRAME 0x4c 295#define MVNETA_MIB_TX_MAC_CTL_ERR 0x50 296 297/* Flow Control */ 298#define MVNETA_MIB_FC_SENT 0x54 299#define MVNETA_MIB_FC_GOOD 0x58 300#define MVNETA_MIB_FC_BAD 0x5c 301 302/* Packet Processing */ 303#define MVNETA_MIB_PKT_UNDERSIZE 0x60 304#define MVNETA_MIB_PKT_FRAGMENT 0x64 305#define MVNETA_MIB_PKT_OVERSIZE 0x68 306#define MVNETA_MIB_PKT_JABBER 0x6c 307 308/* MAC Layer Errors */ 309#define MVNETA_MIB_MAC_RX_ERR 0x70 310#define MVNETA_MIB_MAC_CRC_ERR 0x74 311#define MVNETA_MIB_MAC_COL 0x78 312#define MVNETA_MIB_MAC_LATE_COL 0x7c 313 314/* END OF REGISTER NUMBERS */ 315 316/* 317 * 318 * Register Formats 319 * 320 */ 321/* 322 * Address Decoder Registers 323 */ 324/* Base Address (MVNETA_BASEADDR) */ 325#define MVNETA_BASEADDR_TARGET(target) ((target) & 0xf) 326#define MVNETA_BASEADDR_ATTR(attr) (((attr) & 0xff) << 8) 327#define MVNETA_BASEADDR_BASE(base) ((base) & 0xffff0000) 328 329/* Size (MVNETA_S) */ 330#define MVNETA_S_SIZE(size) (((size) - 1) & 0xffff0000) 331 332/* Base Address Enable (MVNETA_BARE) */ 333#define MVNETA_BARE_EN_MASK ((1 << MVNETA_NWINDOW) - 1) 334#define MVNETA_BARE_EN(win) ((1 << (win)) & MVNETA_BARE_EN_MASK) 335 336/* Ethernet Port Access Protect (MVNETA_EPAP) */ 337#define MVNETA_EPAP_AC_NAC 0x0 /* No access allowed */ 338#define MVNETA_EPAP_AC_RO 0x1 /* Read Only */ 339#define MVNETA_EPAP_AC_FA 0x3 /* Full access (r/w) */ 340#define MVNETA_EPAP_EPAR(win, ac) ((ac) << ((win) * 2)) 341 342/* 343 * Global Miscellaneous Registers 344 */ 345/* PHY Address (MVNETA_PHYADDR) */ 346#define MVNETA_PHYADDR_PHYAD(phy) ((phy) & 0x1f) 347#define MVNETA_PHYADDR_GET_PHYAD(reg) ((reg) & 0x1f) 348 349/* SMI register fields (MVNETA_SMI) */ 350#define MVNETA_SMI_DATA_MASK 0x0000ffff 351#define MVNETA_SMI_PHYAD(phy) (((phy) & 0x1f) << 16) 352#define MVNETA_SMI_REGAD(reg) (((reg) & 0x1f) << 21) 353#define MVNETA_SMI_OPCODE_WRITE (0 << 26) 354#define MVNETA_SMI_OPCODE_READ (1 << 26) 355#define MVNETA_SMI_READVALID (1 << 27) 356#define MVNETA_SMI_BUSY (1 << 28) 357 358/* Ethernet Unit Default ID (MVNETA_EUDID) */ 359#define MVNETA_EUDID_DIDR_MASK 0x0000000f 360#define MVNETA_EUDID_DIDR(id) ((id) & 0x0f) 361#define MVNETA_EUDID_DATTR_MASK 0x00000ff0 362#define MVNETA_EUDID_DATTR(attr) (((attr) & 0xff) << 4) 363 364/* Ethernet Unit Interrupt Cause (MVNETA_EUIC) */ 365#define MVNETA_EUIC_ETHERINTSUM (1 << 0) 366#define MVNETA_EUIC_PARITY (1 << 1) 367#define MVNETA_EUIC_ADDRVIOL (1 << 2) 368#define MVNETA_EUIC_ADDRVNOMATCH (1 << 3) 369#define MVNETA_EUIC_SMIDONE (1 << 4) 370#define MVNETA_EUIC_COUNTWA (1 << 5) 371#define MVNETA_EUIC_INTADDRERR (1 << 7) 372#define MVNETA_EUIC_PORT0DPERR (1 << 9) 373#define MVNETA_EUIC_TOPDPERR (1 << 12) 374 375/* Ethernet Unit Internal Addr Error (MVNETA_EUIAE) */ 376#define MVNETA_EUIAE_INTADDR_MASK 0x000001ff 377#define MVNETA_EUIAE_INTADDR(addr) ((addr) & 0x1ff) 378#define MVNETA_EUIAE_GET_INTADDR(addr) ((addr) & 0x1ff) 379 380/* Ethernet Unit Control (MVNETA_EUC) */ 381#define MVNETA_EUC_POLLING (1 << 1) 382#define MVNETA_EUC_PORTRESET (1 << 24) 383#define MVNETA_EUC_RAMSINITIALIZATIONCOMPLETED (1 << 25) 384 385/* 386 * Miscellaneous Registers 387 */ 388/* SDMA Configuration (MVNETA_SDC) */ 389#define MVNETA_SDC_RXBSZ(x) ((x) << 1) 390#define MVNETA_SDC_RXBSZ_MASK MVNETA_SDC_RXBSZ(7) 391#define MVNETA_SDC_RXBSZ_1_64BITWORDS MVNETA_SDC_RXBSZ(0) 392#define MVNETA_SDC_RXBSZ_2_64BITWORDS MVNETA_SDC_RXBSZ(1) 393#define MVNETA_SDC_RXBSZ_4_64BITWORDS MVNETA_SDC_RXBSZ(2) 394#define MVNETA_SDC_RXBSZ_8_64BITWORDS MVNETA_SDC_RXBSZ(3) 395#define MVNETA_SDC_RXBSZ_16_64BITWORDS MVNETA_SDC_RXBSZ(4) 396#define MVNETA_SDC_BLMR (1 << 4) 397#define MVNETA_SDC_BLMT (1 << 5) 398#define MVNETA_SDC_SWAPMODE (1 << 6) 399#define MVNETA_SDC_TXBSZ(x) ((x) << 22) 400#define MVNETA_SDC_TXBSZ_MASK MVNETA_SDC_TXBSZ(7) 401#define MVNETA_SDC_TXBSZ_1_64BITWORDS MVNETA_SDC_TXBSZ(0) 402#define MVNETA_SDC_TXBSZ_2_64BITWORDS MVNETA_SDC_TXBSZ(1) 403#define MVNETA_SDC_TXBSZ_4_64BITWORDS MVNETA_SDC_TXBSZ(2) 404#define MVNETA_SDC_TXBSZ_8_64BITWORDS MVNETA_SDC_TXBSZ(3) 405#define MVNETA_SDC_TXBSZ_16_64BITWORDS MVNETA_SDC_TXBSZ(4) 406 407/* 408 * Networking Controller Miscellaneous Registers 409 */ 410/* Port Acceleration Mode (MVNETA_PACC) */ 411#define MVNETA_PACC_ACCELERATIONMODE_MASK 0x7 412#define MVNETA_PACC_ACCELERATIONMODE_EDM 0x1 /* Enhanced Desc Mode */ 413 414/* Port Version (MVNETA_PV) */ 415#define MVNETA_PV_VERSION_MASK 0xff 416#define MVNETA_PV_VERSION(v) ((v) & 0xff) 417#define MVNETA_PV_GET_VERSION(reg) ((reg) & 0xff) 418 419/* 420 * Rx DMA Hardware Parser Registers 421 */ 422/* Ether Type Priority (MVNETA_ETP) */ 423#define MVNETA_ETP_ETHERTYPEPRIEN (1 << 0) /* EtherType Prio Ena */ 424#define MVNETA_ETP_ETHERTYPEPRIFRSTEN (1 << 1) 425#define MVNETA_ETP_ETHERTYPEPRIQ (0x7 << 2) /*EtherType Prio Queue*/ 426#define MVNETA_ETP_ETHERTYPEPRIVAL (0xffff << 5) /*EtherType Prio Value*/ 427#define MVNETA_ETP_FORCEUNICSTHIT (1 << 21) /* Force Unicast hit */ 428 429/* Destination Address Filter Registers (MVNETA_DF{SM,OM,U}T) */ 430#define MVNETA_DF(n, x) ((x) << (8 * (n))) 431#define MVNETA_DF_PASS (1 << 0) 432#define MVNETA_DF_QUEUE(q) ((q) << 1) 433#define MVNETA_DF_QUEUE_ALL ((MVNETA_RX_QNUM_MAX-1) << 1) 434#define MVNETA_DF_QUEUE_MASK ((MVNETA_RX_QNUM_MAX-1) << 1) 435 436/* 437 * Rx DMA Miscellaneous Registers 438 */ 439/* Port Rx Minimal Frame Size (MVNETA_PMFS) */ 440#define MVNETA_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c) 441 442/* Receive Queue Command (MVNETA_RQC) */ 443#define MVNETA_RQC_EN_MASK (0xff << 0) /* Enable Q */ 444#define MVNETA_RQC_ENQ(q) (1 << (0 + (q))) 445#define MVNETA_RQC_EN(n) ((n) << 0) 446#define MVNETA_RQC_DIS_MASK (0xff << 8) /* Disable Q */ 447#define MVNETA_RQC_DISQ(q) (1 << (8 + (q))) 448#define MVNETA_RQC_DIS(n) ((n) << 8) 449 450/* 451 * Rx DMA Networking Controller Miscellaneous Registers 452 */ 453/* Port RX queues Configuration (MVNETA_PRXC) */ 454#define MVNETA_PRXC_PACKETOFFSET(o) (((o) & 0xf) << 8) 455 456/* Port RX queues Snoop (MVNETA_PRXSNP) */ 457#define MVNETA_PRXSNP_SNOOPNOOFBYTES(b) (((b) & 0x3fff) << 0) 458#define MVNETA_PRXSNP_L2DEPOSITNOOFBYTES(b) (((b) & 0x3fff) << 16) 459 460/* Port RX queues Descriptors Queue Size (MVNETA_PRXDQS) */ 461#define MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(s) (((s) & 0x3fff) << 0) 462#define MVNETA_PRXDQS_BUFFERSIZE(s) (((s) & 0x1fff) << 19) 463 464/* Port RX queues Descriptors Queue Threshold (MVNETA_PRXDQTH) */ 465 /* Occupied Descriptors Threshold */ 466#define MVNETA_PRXDQTH_ODT(x) (((x) & 0x3fff) << 0) 467 /* Non Occupied Descriptors Threshold */ 468#define MVNETA_PRXDQTH_NODT(x) (((x) & 0x3fff) << 16) 469 470/* Port RX queues Status (MVNETA_PRXS) */ 471 /* Occupied Descriptors Counter */ 472#define MVNETA_PRXS_ODC(x) (((x) & 0x3fff) << 0) 473 /* Non Occupied Descriptors Counter */ 474#define MVNETA_PRXS_NODC(x) (((x) & 0x3fff) << 16) 475#define MVNETA_PRXS_GET_ODC(reg) (((reg) >> 0) & 0x3fff) 476#define MVNETA_PRXS_GET_NODC(reg) (((reg) >> 16) & 0x3fff) 477 478/* Port RX queues Status Update (MVNETA_PRXSU) */ 479#define MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(x) (((x) & 0xff) << 0) 480#define MVNETA_PRXSU_NOOFNEWDESCRIPTORS(x) (((x) & 0xff) << 16) 481 482/* Port RX Initialization (MVNETA_PRXINIT) */ 483#define MVNETA_PRXINIT_RXDMAINIT (1 << 0) 484 485/* 486 * Tx DMA Miscellaneous Registers 487 */ 488/* Transmit Queue Command (MVNETA_TQC) */ 489#define MVNETA_TQC_EN_MASK (0xff << 0) 490#define MVNETA_TQC_ENQ(q) (1 << ((q) + 0))/* Enable Q */ 491#define MVNETA_TQC_EN(n) ((n) << 0) 492#define MVNETA_TQC_DIS_MASK (0xff << 8) 493#define MVNETA_TQC_DISQ(q) (1 << ((q) + 8))/* Disable Q */ 494#define MVNETA_TQC_DIS(n) ((n) << 8) 495 496/* 497 * Tx DMA Networking Controller Miscellaneous Registers 498 */ 499/* Port TX queues Descriptors Queue Size (MVNETA_PTXDQS) */ 500 /* Descriptors Queue Size */ 501#define MVNETA_PTXDQS_DQS_MASK (0x3fff << 0) 502#define MVNETA_PTXDQS_DQS(x) (((x) & 0x3fff) << 0) 503 /* Transmitted Buffer Threshold */ 504#define MVNETA_PTXDQS_TBT_MASK (0x3fff << 16) 505#define MVNETA_PTXDQS_TBT(x) (((x) & 0x3fff) << 16) 506 507/* Port TX queues Status (MVNETA_PTXS) */ 508 /* Transmitted Buffer Counter */ 509#define MVNETA_PTXS_TBC(x) (((x) & 0x3fff) << 16) 510 511#define MVNETA_PTXS_GET_TBC(reg) (((reg) >> 16) & 0x3fff) 512 /* Pending Descriptors Counter */ 513#define MVNETA_PTXS_PDC(x) ((x) & 0x3fff) 514#define MVNETA_PTXS_GET_PDC(x) ((x) & 0x3fff) 515 516/* Port TX queues Status Update (MVNETA_PTXSU) */ 517 /* Number Of Written Descriptors */ 518#define MVNETA_PTXSU_NOWD(x) (((x) & 0xff) << 0) 519 /* Number Of Released Buffers */ 520#define MVNETA_PTXSU_NORB(x) (((x) & 0xff) << 16) 521 522/* TX Transmitted Buffers Counter (MVNETA_TXTBC) */ 523 /* Transmitted Buffers Counter */ 524#define MVNETA_TXTBC_TBC(x) (((x) & 0x3fff) << 16) 525 526/* Port TX Initialization (MVNETA_PTXINIT) */ 527#define MVNETA_PTXINIT_TXDMAINIT (1 << 0) 528 529/* 530 * Tx DMA Queue Arbiter Registers (Version 1 ) 531 */ 532/* Transmit Queue Fixed Priority Configuration */ 533#define MVNETA_TQFPC_EN(q) (1 << (q)) 534 535/* 536 * RX_TX DMA Registers 537 */ 538/* Port Configuration (MVNETA_PXC) */ 539#define MVNETA_PXC_UPM (1 << 0) /* Uni Promisc mode */ 540#define MVNETA_PXC_RXQ(q) ((q) << 1) 541#define MVNETA_PXC_RXQ_MASK MVNETA_PXC_RXQ(7) 542#define MVNETA_PXC_RXQARP(q) ((q) << 4) 543#define MVNETA_PXC_RXQARP_MASK MVNETA_PXC_RXQARP(7) 544#define MVNETA_PXC_RB (1 << 7) /* Rej mode of MAC */ 545#define MVNETA_PXC_RBIP (1 << 8) 546#define MVNETA_PXC_RBARP (1 << 9) 547#define MVNETA_PXC_AMNOTXES (1 << 12) 548#define MVNETA_PXC_RBARPF (1 << 13) 549#define MVNETA_PXC_TCPCAPEN (1 << 14) 550#define MVNETA_PXC_UDPCAPEN (1 << 15) 551#define MVNETA_PXC_TCPQ(q) ((q) << 16) 552#define MVNETA_PXC_TCPQ_MASK MVNETA_PXC_TCPQ(7) 553#define MVNETA_PXC_UDPQ(q) ((q) << 19) 554#define MVNETA_PXC_UDPQ_MASK MVNETA_PXC_UDPQ(7) 555#define MVNETA_PXC_BPDUQ(q) ((q) << 22) 556#define MVNETA_PXC_BPDUQ_MASK MVNETA_PXC_BPDUQ(7) 557#define MVNETA_PXC_RXCS (1 << 25) 558 559/* Port Configuration Extend (MVNETA_PXCX) */ 560#define MVNETA_PXCX_SPAN (1 << 1) 561#define MVNETA_PXCX_TXCRCDIS (1 << 3) 562 563/* Marvell Header (MVNETA_MH) */ 564#define MVNETA_MH_MHEN (1 << 0) 565#define MVNETA_MH_DAPREFIX (0x3 << 1) 566#define MVNETA_MH_SPID (0xf << 4) 567#define MVNETA_MH_MHMASK (0x3 << 8) 568#define MVNETA_MH_MHMASK_8QUEUES (0x0 << 8) 569#define MVNETA_MH_MHMASK_4QUEUES (0x1 << 8) 570#define MVNETA_MH_MHMASK_2QUEUES (0x3 << 8) 571#define MVNETA_MH_DSAEN_MASK (0x3 << 10) 572#define MVNETA_MH_DSAEN_DISABLE (0x0 << 10) 573#define MVNETA_MH_DSAEN_NONEXTENDED (0x1 << 10) 574#define MVNETA_MH_DSAEN_EXTENDED (0x2 << 10) 575 576/* 577 * Serial(SMI/MII) Registers 578 */ 579#define MVNETA_PSOMSCD_ENABLE (1UL<<31) 580#define MVNETA_PSERDESCFG_QSGMII (0x0667) 581#define MVNETA_PSERDESCFG_SGMII (0x0cc7) 582/* Port Seiral Control0 (MVNETA_PSC0) */ 583#define MVNETA_PSC0_FORCE_FC_MASK (0x3 << 5) 584#define MVNETA_PSC0_FORCE_FC(fc) (((fc) & 0x3) << 5) 585#define MVNETA_PSC0_FORCE_FC_PAUSE MVNETA_PSC0_FORCE_FC(0x1) 586#define MVNETA_PSC0_FORCE_FC_NO_PAUSE MVNETA_PSC0_FORCE_FC(0x0) 587#define MVNETA_PSC0_FORCE_BP_MASK (0x3 << 7) 588#define MVNETA_PSC0_FORCE_BP(fc) (((fc) & 0x3) << 5) 589#define MVNETA_PSC0_FORCE_BP_JAM MVNETA_PSC0_FORCE_BP(0x1) 590#define MVNETA_PSC0_FORCE_BP_NO_JAM MVNETA_PSC0_FORCE_BP(0x0) 591#define MVNETA_PSC0_DTE_ADV (1 << 14) 592#define MVNETA_PSC0_IGN_RXERR (1 << 28) 593#define MVNETA_PSC0_IGN_COLLISION (1 << 29) 594#define MVNETA_PSC0_IGN_CARRIER (1 << 30) 595 596/* Ethernet Port Status0 (MVNETA_PS0) */ 597#define MVNETA_PS0_TXINPROG (1 << 0) 598#define MVNETA_PS0_TXFIFOEMP (1 << 8) 599#define MVNETA_PS0_RXFIFOEMPTY (1 << 16) 600 601/* 602 * Gigabit Ethernet MAC Serial Parameters Configuration Registers 603 */ 604#define MVNETA_PSPC_MUST_SET (1 << 3 | 1 << 4 | 1 << 5 | 0x23 << 6) 605#define MVNETA_PSP1C_MUST_SET (1 << 0 | 1 << 1 | 1 << 2) 606 607/* 608 * Gigabit Ethernet Auto-Negotiation Configuration Registers 609 */ 610/* Port Auto-Negotiation Configuration (MVNETA_PANC) */ 611#define MVNETA_PANC_FORCELINKFAIL (1 << 0) 612#define MVNETA_PANC_FORCELINKPASS (1 << 1) 613#define MVNETA_PANC_INBANDANEN (1 << 2) 614#define MVNETA_PANC_INBANDANBYPASSEN (1 << 3) 615#define MVNETA_PANC_INBANDRESTARTAN (1 << 4) 616#define MVNETA_PANC_SETMIISPEED (1 << 5) 617#define MVNETA_PANC_SETGMIISPEED (1 << 6) 618#define MVNETA_PANC_ANSPEEDEN (1 << 7) 619#define MVNETA_PANC_SETFCEN (1 << 8) 620#define MVNETA_PANC_PAUSEADV (1 << 9) 621#define MVNETA_PANC_ANFCEN (1 << 11) 622#define MVNETA_PANC_SETFULLDX (1 << 12) 623#define MVNETA_PANC_ANDUPLEXEN (1 << 13) 624#define MVNETA_PANC_MUSTSET (1 << 15) 625 626/* 627 * Gigabit Ethernet MAC Control Registers 628 */ 629/* Port MAC Control 0 (MVNETA_PMACC0) */ 630#define MVNETA_PMACC0_PORTEN (1 << 0) 631#define MVNETA_PMACC0_PORTTYPE (1 << 1) 632#define MVNETA_PMACC0_FRAMESIZELIMIT(x) ((((x) >> 1) << 2) & 0x7ffc) 633#define MVNETA_PMACC0_FRAMESIZELIMIT_MASK (0x7ffc) 634#define MVNETA_PMACC0_MUSTSET (1 << 15) 635 636/* Port MAC Control 1 (MVNETA_PMACC1) */ 637#define MVNETA_PMACC1_PCSLB (1 << 6) 638 639/* Port MAC Control 2 (MVNETA_PMACC2) */ 640#define MVNETA_PMACC2_INBANDANMODE (1 << 0) 641#define MVNETA_PMACC2_PCSEN (1 << 3) 642#define MVNETA_PMACC2_PCSEN (1 << 3) 643#define MVNETA_PMACC2_RGMIIEN (1 << 4) 644#define MVNETA_PMACC2_PADDINGDIS (1 << 5) 645#define MVNETA_PMACC2_PORTMACRESET (1 << 6) 646#define MVNETA_PMACC2_PRBSCHECKEN (1 << 10) 647#define MVNETA_PMACC2_PRBSGENEN (1 << 11) 648#define MVNETA_PMACC2_SDTT_MASK (3 << 12) /* Select Data To Transmit */ 649#define MVNETA_PMACC2_SDTT_RM (0 << 12) /* Regular Mode */ 650#define MVNETA_PMACC2_SDTT_PRBS (1 << 12) /* PRBS Mode */ 651#define MVNETA_PMACC2_SDTT_ZC (2 << 12) /* Zero Constant */ 652#define MVNETA_PMACC2_SDTT_OC (3 << 12) /* One Constant */ 653#define MVNETA_PMACC2_MUSTSET (3 << 14) 654 655/* Port MAC Control 3 (MVNETA_PMACC3) */ 656#define MVNETA_PMACC3_IPG_MASK 0x7f80 657 658/* 659 * Gigabit Ethernet MAC Interrupt Registers 660 */ 661/* Port Interrupt Cause/Mask (MVNETA_PIC/MVNETA_PIM) */ 662#define MVNETA_PI_INTSUM (1 << 0) 663#define MVNETA_PI_LSC (1 << 1) /* LinkStatus Change */ 664#define MVNETA_PI_ACOP (1 << 2) /* AnCompleted OnPort */ 665#define MVNETA_PI_AOOR (1 << 5) /* AddressOut Of Range */ 666#define MVNETA_PI_SSC (1 << 6) /* SyncStatus Change */ 667#define MVNETA_PI_PRBSEOP (1 << 7) /* QSGMII PRBS error */ 668#define MVNETA_PI_MIBCWA (1 << 15) /* MIB counter wrap around */ 669#define MVNETA_PI_QSGMIIPRBSE (1 << 10) /* QSGMII PRBS error */ 670#define MVNETA_PI_PCSRXPRLPI (1 << 11) /* PCS Rx path received LPI*/ 671#define MVNETA_PI_PCSTXPRLPI (1 << 12) /* PCS Tx path received LPI*/ 672#define MVNETA_PI_MACRXPRLPI (1 << 13) /* MAC Rx path received LPI*/ 673#define MVNETA_PI_MIBCCD (1 << 14) /* MIB counters copy done */ 674 675/* 676 * Gigabit Ethernet MAC Low Power Idle Registers 677 */ 678/* LPI Control 0 (MVNETA_LPIC0) */ 679#define MVNETA_LPIC0_LILIMIT(x) (((x) & 0xff) << 0) 680#define MVNETA_LPIC0_TSLIMIT(x) (((x) & 0xff) << 8) 681 682/* LPI Control 1 (MVNETA_LPIC1) */ 683#define MVNETA_LPIC1_LPIRE (1 << 0) /* LPI request enable */ 684#define MVNETA_LPIC1_LPIRF (1 << 1) /* LPI request force */ 685#define MVNETA_LPIC1_LPIMM (1 << 2) /* LPI manual mode */ 686#define MVNETA_LPIC1_TWLIMIT(x) (((x) & 0xfff) << 4) 687 688/* LPI Control 2 (MVNETA_LPIC2) */ 689#define MVNETA_LPIC2_MUSTSET 0x17d 690 691/* LPI Status (MVNETA_LPIS) */ 692#define MVNETA_LPIS_PCSRXPLPIS (1 << 0) /* PCS Rx path LPI status */ 693#define MVNETA_LPIS_PCSTXPLPIS (1 << 1) /* PCS Tx path LPI status */ 694#define MVNETA_LPIS_MACRXPLPIS (1 << 2)/* MAC Rx path LP idle status */ 695#define MVNETA_LPIS_MACTXPLPWS (1 << 3)/* MAC Tx path LP wait status */ 696#define MVNETA_LPIS_MACTXPLPIS (1 << 4)/* MAC Tx path LP idle status */ 697 698/* 699 * Gigabit Ethernet MAC PRBS Check Status Registers 700 */ 701/* Port PRBS Status (MVNETA_PPRBSS) */ 702#define MVNETA_PPRBSS_PRBSCHECKLOCKED (1 << 0) 703#define MVNETA_PPRBSS_PRBSCHECKRDY (1 << 1) 704 705/* 706 * Gigabit Ethernet MAC Status Registers 707 */ 708/* Port Status Register (MVNETA_PSR) */ 709#define MVNETA_PSR_LINKUP (1 << 0) 710#define MVNETA_PSR_GMIISPEED (1 << 1) 711#define MVNETA_PSR_MIISPEED (1 << 2) 712#define MVNETA_PSR_FULLDX (1 << 3) 713#define MVNETA_PSR_RXFCEN (1 << 4) 714#define MVNETA_PSR_TXFCEN (1 << 5) 715#define MVNETA_PSR_PRP (1 << 6) /* Port Rx Pause */ 716#define MVNETA_PSR_PTP (1 << 7) /* Port Tx Pause */ 717#define MVNETA_PSR_PDP (1 << 8) /*Port is Doing Back-Pressure*/ 718#define MVNETA_PSR_SYNCFAIL10MS (1 << 10) 719#define MVNETA_PSR_ANDONE (1 << 11) 720#define MVNETA_PSR_IBANBA (1 << 12) /* InBand AutoNeg BypassAct */ 721#define MVNETA_PSR_SYNCOK (1 << 14) 722 723/* 724 * Networking Controller Interrupt Registers 725 */ 726/* Port CPU to Queue */ 727#define MVNETA_MAXCPU 2 728#define MVNETA_PCP2Q_TXQEN(q) (1 << ((q) + 8)) 729#define MVNETA_PCP2Q_TXQEN_MASK (0xff << 8) 730#define MVNETA_PCP2Q_RXQEN(q) (1 << ((q) + 0)) 731#define MVNETA_PCP2Q_RXQEN_MASK (0xff << 0) 732 733/* Port RX_TX Interrupt Threshold */ 734#define MVNETA_PRXITTH_RITT(t) ((t) & 0xffffff) 735 736/* Port RX_TX Threshold Interrupt Cause/Mask (MVNETA_PRXTXTIC/MVNETA_PRXTXTIM) */ 737#define MVNETA_PRXTXTI_TBTCQ(q) (1 << ((q) + 0)) 738#define MVNETA_PRXTXTI_TBTCQ_MASK (0xff << 0) 739#define MVNETA_PRXTXTI_GET_TBTCQ(reg) (((reg) >> 0) & 0xff) 740 /* Tx Buffer Threshold Cross Queue*/ 741#define MVNETA_PRXTXTI_RBICTAPQ(q) (1 << ((q) + 8)) 742#define MVNETA_PRXTXTI_RBICTAPQ_MASK (0xff << 8) 743#define MVNETA_PRXTXTI_GET_RBICTAPQ(reg) (((reg) >> 8) & 0xff) 744 /* Rx Buffer Int. Coaleasing Th. Pri. Alrt Q */ 745#define MVNETA_PRXTXTI_RDTAQ(q) (1 << ((q) + 16)) 746#define MVNETA_PRXTXTI_RDTAQ_MASK (0xff << 16) 747#define MVNETA_PRXTXTI_GET_RDTAQ(reg) (((reg) >> 16) & 0xff) 748 /* Rx Descriptor Threshold Alert Queue*/ 749#define MVNETA_PRXTXTI_PRXTXICSUMMARY (1 << 29) /* PRXTXI summary */ 750#define MVNETA_PRXTXTI_PTXERRORSUMMARY (1 << 30) /* PTEXERROR summary */ 751#define MVNETA_PRXTXTI_PMISCICSUMMARY (1UL << 31) /* PMISCIC summary */ 752 753/* Port RX_TX Interrupt Cause/Mask (MVNETA_PRXTXIC/MVNETA_PRXTXIM) */ 754#define MVNETA_PRXTXI_TBRQ(q) (1 << ((q) + 0)) 755#define MVNETA_PRXTXI_TBRQ_MASK (0xff << 0) 756#define MVNETA_PRXTXI_GET_TBRQ(reg) (((reg) >> 0) & 0xff) 757#define MVNETA_PRXTXI_RPQ(q) (1 << ((q) + 8)) 758#define MVNETA_PRXTXI_RPQ_MASK (0xff << 8) 759#define MVNETA_PRXTXI_GET_RPQ(reg) (((reg) >> 8) & 0xff) 760#define MVNETA_PRXTXI_RREQ(q) (1 << ((q) + 16)) 761#define MVNETA_PRXTXI_RREQ_MASK (0xff << 16) 762#define MVNETA_PRXTXI_GET_RREQ(reg) (((reg) >> 16) & 0xff) 763#define MVNETA_PRXTXI_PRXTXTHICSUMMARY (1 << 29) 764#define MVNETA_PRXTXI_PTXERRORSUMMARY (1 << 30) 765#define MVNETA_PRXTXI_PMISCICSUMMARY (1UL << 31) 766 767/* Port Misc Interrupt Cause/Mask (MVNETA_PMIC/MVNETA_PMIM) */ 768#define MVNETA_PMI_PHYSTATUSCHNG (1 << 0) 769#define MVNETA_PMI_LINKCHANGE (1 << 1) 770#define MVNETA_PMI_IAE (1 << 7) /* Internal Address Error */ 771#define MVNETA_PMI_RXOVERRUN (1 << 8) 772#define MVNETA_PMI_RXCRCERROR (1 << 9) 773#define MVNETA_PMI_RXLARGEPACKET (1 << 10) 774#define MVNETA_PMI_TXUNDRN (1 << 11) 775#define MVNETA_PMI_PRBSERROR (1 << 12) 776#define MVNETA_PMI_PSCSYNCCHANGE (1 << 13) 777#define MVNETA_PMI_SRSE (1 << 14) /* SerdesRealignSyncError */ 778#define MVNETA_PMI_TREQ(q) (1 << ((q) + 24)) /* TxResourceErrorQ */ 779#define MVNETA_PMI_TREQ_MASK (0xff << 24) /* TxResourceErrorQ */ 780 781/* Port Interrupt Enable (MVNETA_PIE) */ 782#define MVNETA_PIE_RXPKTINTRPTENB(q) (1 << ((q) + 0)) 783#define MVNETA_PIE_TXPKTINTRPTENB(q) (1 << ((q) + 8)) 784#define MVNETA_PIE_RXPKTINTRPTENB_MASK (0xff << 0) 785#define MVNETA_PIE_TXPKTINTRPTENB_MASK (0xff << 8) 786 787/* 788 * Miscellaneous Interrupt Registers 789 */ 790#define MVNETA_PEUIAE_ADDR_MASK (0x3fff) 791#define MVNETA_PEUIAE_ADDR(addr) ((addr) & 0x3fff) 792#define MVNETA_PEUIAE_GET_ADDR(reg) ((reg) & 0x3fff) 793 794/* 795 * SGMII PHY Registers 796 */ 797/* Power and PLL Control (MVNETA_PPLLC) */ 798#define MVNETA_PPLLC_REF_FREF_SEL_MASK (0xf << 0) 799#define MVNETA_PPLLC_PHY_MODE_MASK (7 << 5) 800#define MVNETA_PPLLC_PHY_MODE_SATA (0 << 5) 801#define MVNETA_PPLLC_PHY_MODE_SAS (1 << 5) 802#define MVNETA_PPLLC_PLL_LOCK (1 << 8) 803#define MVNETA_PPLLC_PU_DFE (1 << 10) 804#define MVNETA_PPLLC_PU_TX_INTP (1 << 11) 805#define MVNETA_PPLLC_PU_TX (1 << 12) 806#define MVNETA_PPLLC_PU_RX (1 << 13) 807#define MVNETA_PPLLC_PU_PLL (1 << 14) 808 809/* Digital Loopback Enable (MVNETA_DLE) */ 810#define MVNETA_DLE_LOCAL_SEL_BITS_MASK (3 << 10) 811#define MVNETA_DLE_LOCAL_SEL_BITS_10BITS (0 << 10) 812#define MVNETA_DLE_LOCAL_SEL_BITS_20BITS (1 << 10) 813#define MVNETA_DLE_LOCAL_SEL_BITS_40BITS (2 << 10) 814#define MVNETA_DLE_LOCAL_RXPHER_TO_TX_EN (1 << 12) 815#define MVNETA_DLE_LOCAL_ANA_TX2RX_LPBK_EN (1 << 13) 816#define MVNETA_DLE_LOCAL_DIG_TX2RX_LPBK_EN (1 << 14) 817#define MVNETA_DLE_LOCAL_DIG_RX2TX_LPBK_EN (1 << 15) 818 819/* Reference Clock Select (MVNETA_RCS) */ 820#define MVNETA_RCS_REFCLK_SEL (1 << 10) 821 822/* 823 * DMA descriptors 824 */ 825struct mvneta_tx_desc { 826 /* LITTLE_ENDIAN */ 827 uint32_t command; /* off 0x00: commands */ 828 uint16_t l4ichk; /* initial checksum */ 829 uint16_t bytecnt; /* 0ff 0x04: buffer byte count */ 830 uint32_t bufptr_pa; /* off 0x08: buffer ptr(PA) */ 831 uint32_t flags; /* off 0x0c: flags */ 832 uint32_t reserved0; /* off 0x10 */ 833 uint32_t reserved1; /* off 0x14 */ 834 uint32_t reserved2; /* off 0x18 */ 835 uint32_t reserved3; /* off 0x1c */ 836}; 837 838struct mvneta_rx_desc { 839 /* LITTLE_ENDIAN */ 840 uint32_t status; /* status and flags */ 841 uint16_t reserved0; 842 uint16_t bytecnt; /* buffer byte count */ 843 uint32_t bufptr_pa; /* packet buffer pointer */ 844 uint32_t reserved1; 845 uint32_t bufptr_va; 846 uint16_t reserved2; 847 uint16_t l4chk; /* L4 checksum */ 848 uint32_t reserved3; 849 uint32_t reserved4; 850}; 851 852/* 853 * Received packet command header: 854 * network controller => software 855 * the controller parse the packet and set some flags. 856 */ 857#define MVNETA_RX_IPV4_FRAGMENT (1UL << 31) /* Fragment Indicator */ 858#define MVNETA_RX_L4_CHECKSUM_OK (1 << 30) /* L4 Checksum */ 859/* bit 29 reserved */ 860#define MVNETA_RX_U (1 << 28) /* Unknown Destination */ 861#define MVNETA_RX_F (1 << 27) /* First buffer */ 862#define MVNETA_RX_L (1 << 26) /* Last buffer */ 863#define MVNETA_RX_IP_HEADER_OK (1 << 25) /* IP Header is OK */ 864#define MVNETA_RX_L3_IP (1 << 24) /* IP Type 0:IP6 1:IP4 */ 865#define MVNETA_RX_L2_EV2 (1 << 23) /* Ethernet v2 frame */ 866#define MVNETA_RX_L4_MASK (3 << 21) /* L4 Type */ 867#define MVNETA_RX_L4_TCP (0x00 << 21) 868#define MVNETA_RX_L4_UDP (0x01 << 21) 869#define MVNETA_RX_L4_OTH (0x10 << 21) 870#define MVNETA_RX_BPDU (1 << 20) /* BPDU frame */ 871#define MVNETA_RX_VLAN (1 << 19) /* VLAN tag found */ 872#define MVNETA_RX_EC_MASK (3 << 17) /* Error code */ 873#define MVNETA_RX_EC_CE (0x00 << 17) /* CRC error */ 874#define MVNETA_RX_EC_OR (0x01 << 17) /* FIFO overrun */ 875#define MVNETA_RX_EC_MF (0x10 << 17) /* Max. frame len */ 876#define MVNETA_RX_EC_RE (0x11 << 17) /* Resource error */ 877#define MVNETA_RX_ES (1 << 16) /* Error summary */ 878/* bit 15:0 reserved */ 879 880/* 881 * Transmit packet command header: 882 * software => network controller 883 */ 884#define MVNETA_TX_CMD_L4_CHECKSUM_MASK (0x3 << 30) /* Do L4 Checksum */ 885#define MVNETA_TX_CMD_L4_CHECKSUM_FRAG (0x0 << 30) 886#define MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG (0x1 << 30) 887#define MVNETA_TX_CMD_L4_CHECKSUM_NONE (0x2 << 30) 888#define MVNETA_TX_CMD_PACKET_OFFSET_MASK (0x7f << 23) /* Payload offset */ 889#define MVNETA_TX_CMD_W_PACKET_OFFSET(v) (((v) & 0x7f) << 23) 890/* bit 22 reserved */ 891#define MVNETA_TX_CMD_F (1 << 21) /* First buffer */ 892#define MVNETA_TX_CMD_L (1 << 20) /* Last buffer */ 893#define MVNETA_TX_CMD_PADDING (1 << 19) /* Pad short frame */ 894#define MVNETA_TX_CMD_IP4_CHECKSUM (1 << 18) /* Do IPv4 Checksum */ 895#define MVNETA_TX_CMD_L3_IP4 (0 << 17) 896#define MVNETA_TX_CMD_L3_IP6 (1 << 17) 897#define MVNETA_TX_CMD_L4_TCP (0 << 16) 898#define MVNETA_TX_CMD_L4_UDP (1 << 16) 899/* bit 15:13 reserved */ 900#define MVNETA_TX_CMD_IP_HEADER_LEN_MASK (0x1f << 8) /* IP header len >> 2 */ 901#define MVNETA_TX_CMD_IP_HEADER_LEN(v) (((v) & 0x1f) << 8) 902/* bit 7 reserved */ 903#define MVNETA_TX_CMD_L3_OFFSET_MASK (0x7f << 0) /* offset of L3 hdr. */ 904#define MVNETA_TX_CMD_L3_OFFSET(v) (((v) & 0x7f) << 0) 905 906/* 907 * Transmit packet extra attributes 908 * and error status returned from network controller. 909 */ 910#define MVNETA_TX_F_DSA_TAG (3 << 30) /* DSA Tag */ 911/* bit 29:8 reserved */ 912#define MVNETA_TX_F_MH_SEL (0xf << 4) /* Marvell Header */ 913/* bit 3 reserved */ 914#define MVNETA_TX_F_EC_MASK (3 << 1) /* Error code */ 915#define MVNETA_TX_F_EC_LC (0x00 << 1) /* Late Collision */ 916#define MVNETA_TX_F_EC_UR (0x01 << 1) /* Underrun */ 917#define MVNETA_TX_F_EC_RL (0x10 << 1) /* Excess. Collision */ 918#define MVNETA_TX_F_EC_RESERVED (0x11 << 1) 919#define MVNETA_TX_F_ES (1 << 0) /* Error summary */ 920 921#define MVNETA_ERROR_SUMMARY (1 << 0) 922#define MVNETA_BUFFER_OWNED_MASK (1UL << 31) 923#define MVNETA_BUFFER_OWNED_BY_HOST (0UL << 31) 924#define MVNETA_BUFFER_OWNED_BY_DMA (1UL << 31) 925 926#endif /* _IF_MVNETAREG_H_ */ 927