1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/param.h> 30#include <sys/module.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/bus.h> 34#include <sys/endian.h> 35#include <sys/malloc.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/sbuf.h> 39#include <vm/uma.h> 40#include <machine/stdarg.h> 41#include <machine/resource.h> 42#include <machine/bus.h> 43#include <sys/rman.h> 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcireg.h> 46#include "mvs.h" 47 48/* local prototypes */ 49static int mvs_setup_interrupt(device_t dev); 50static void mvs_intr(void *data); 51static int mvs_suspend(device_t dev); 52static int mvs_resume(device_t dev); 53static int mvs_ctlr_setup(device_t dev); 54 55static struct { 56 uint32_t id; 57 uint8_t rev; 58 const char *name; 59 int ports; 60 int quirks; 61} mvs_ids[] = { 62 {0x504011ab, 0x00, "Marvell 88SX5040", 4, MVS_Q_GENI}, 63 {0x504111ab, 0x00, "Marvell 88SX5041", 4, MVS_Q_GENI}, 64 {0x508011ab, 0x00, "Marvell 88SX5080", 8, MVS_Q_GENI}, 65 {0x508111ab, 0x00, "Marvell 88SX5081", 8, MVS_Q_GENI}, 66 {0x604011ab, 0x00, "Marvell 88SX6040", 4, MVS_Q_GENII}, 67 {0x604111ab, 0x00, "Marvell 88SX6041", 4, MVS_Q_GENII}, 68 {0x604211ab, 0x00, "Marvell 88SX6042", 4, MVS_Q_GENIIE}, 69 {0x608011ab, 0x00, "Marvell 88SX6080", 8, MVS_Q_GENII}, 70 {0x608111ab, 0x00, "Marvell 88SX6081", 8, MVS_Q_GENII}, 71 {0x704211ab, 0x00, "Marvell 88SX7042", 4, MVS_Q_GENIIE|MVS_Q_CT}, 72 {0x02419005, 0x00, "Adaptec 1420SA", 4, MVS_Q_GENII}, 73 {0x02439005, 0x00, "Adaptec 1430SA", 4, MVS_Q_GENIIE|MVS_Q_CT}, 74 {0x00000000, 0x00, NULL, 0, 0} 75}; 76 77static int 78mvs_probe(device_t dev) 79{ 80 int i; 81 uint32_t devid = pci_get_devid(dev); 82 uint8_t revid = pci_get_revid(dev); 83 84 for (i = 0; mvs_ids[i].id != 0; i++) { 85 if (mvs_ids[i].id == devid && 86 mvs_ids[i].rev <= revid) { 87 device_set_descf(dev, "%s SATA controller", 88 mvs_ids[i].name); 89 return (BUS_PROBE_DEFAULT); 90 } 91 } 92 return (ENXIO); 93} 94 95static int 96mvs_attach(device_t dev) 97{ 98 struct mvs_controller *ctlr = device_get_softc(dev); 99 device_t child; 100 int error, unit, i; 101 uint32_t devid = pci_get_devid(dev); 102 uint8_t revid = pci_get_revid(dev); 103 104 ctlr->dev = dev; 105 i = 0; 106 while (mvs_ids[i].id != 0 && 107 (mvs_ids[i].id != devid || 108 mvs_ids[i].rev > revid)) 109 i++; 110 ctlr->channels = mvs_ids[i].ports; 111 ctlr->quirks = mvs_ids[i].quirks; 112 ctlr->ccc = 0; 113 resource_int_value(device_get_name(dev), 114 device_get_unit(dev), "ccc", &ctlr->ccc); 115 ctlr->cccc = 8; 116 resource_int_value(device_get_name(dev), 117 device_get_unit(dev), "cccc", &ctlr->cccc); 118 if (ctlr->ccc == 0 || ctlr->cccc == 0) { 119 ctlr->ccc = 0; 120 ctlr->cccc = 0; 121 } 122 if (ctlr->ccc > 100000) 123 ctlr->ccc = 100000; 124 device_printf(dev, 125 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n", 126 ((ctlr->quirks & MVS_Q_GENI) ? "I" : 127 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")), 128 ctlr->channels, 129 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"), 130 ((ctlr->quirks & MVS_Q_GENI) ? 131 "not supported" : "supported"), 132 ((ctlr->quirks & MVS_Q_GENIIE) ? 133 " with FBS" : "")); 134 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF); 135 /* We should have a memory BAR(0). */ 136 ctlr->r_rid = PCIR_BAR(0); 137 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 138 &ctlr->r_rid, RF_ACTIVE))) 139 return ENXIO; 140 /* Setup our own memory management for channels. */ 141 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 142 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 143 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 144 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 145 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 146 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 147 return (error); 148 } 149 if ((error = rman_manage_region(&ctlr->sc_iomem, 150 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 151 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 152 rman_fini(&ctlr->sc_iomem); 153 return (error); 154 } 155 pci_enable_busmaster(dev); 156 mvs_ctlr_setup(dev); 157 /* Setup interrupts. */ 158 if (mvs_setup_interrupt(dev)) { 159 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 160 rman_fini(&ctlr->sc_iomem); 161 return ENXIO; 162 } 163 /* Attach all channels on this controller */ 164 for (unit = 0; unit < ctlr->channels; unit++) { 165 child = device_add_child(dev, "mvsch", -1); 166 if (child == NULL) 167 device_printf(dev, "failed to add channel device\n"); 168 else 169 device_set_ivars(child, (void *)(intptr_t)unit); 170 } 171 bus_generic_attach(dev); 172 return 0; 173} 174 175static int 176mvs_detach(device_t dev) 177{ 178 struct mvs_controller *ctlr = device_get_softc(dev); 179 180 /* Detach & delete all children */ 181 device_delete_children(dev); 182 183 /* Free interrupt. */ 184 if (ctlr->irq.r_irq) { 185 bus_teardown_intr(dev, ctlr->irq.r_irq, 186 ctlr->irq.handle); 187 bus_release_resource(dev, SYS_RES_IRQ, 188 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 189 } 190 pci_release_msi(dev); 191 /* Free memory. */ 192 rman_fini(&ctlr->sc_iomem); 193 if (ctlr->r_mem) 194 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 195 mtx_destroy(&ctlr->mtx); 196 return (0); 197} 198 199static int 200mvs_ctlr_setup(device_t dev) 201{ 202 struct mvs_controller *ctlr = device_get_softc(dev); 203 int i, ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0; 204 205 /* Mask chip interrupts */ 206 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000); 207 /* Mask PCI interrupts */ 208 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000); 209 /* Clear PCI interrupts */ 210 ATA_OUTL(ctlr->r_mem, CHIP_PCIIC, 0x00000000); 211 if (ccc && bootverbose) { 212 device_printf(dev, 213 "CCC with %dus/%dcmd enabled\n", 214 ctlr->ccc, ctlr->cccc); 215 } 216 ccc *= 150; 217 /* Configure chip-global CCC */ 218 if (ctlr->channels > 4 && (ctlr->quirks & MVS_Q_GENI) == 0) { 219 ATA_OUTL(ctlr->r_mem, CHIP_ICT, cccc); 220 ATA_OUTL(ctlr->r_mem, CHIP_ITT, ccc); 221 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS); 222 if (ccc) 223 ccim |= IC_ALL_PORTS_COAL_DONE; 224 ccc = 0; 225 cccc = 0; 226 } 227 for (i = 0; i < ctlr->channels / 4; i++) { 228 /* Configure per-HC CCC */ 229 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ICT, cccc); 230 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ITT, ccc); 231 if (ccc) 232 ccim |= (IC_HC0_COAL_DONE << (i * IC_HC_SHIFT)); 233 /* Clear HC interrupts */ 234 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_IC, 0x00000000); 235 } 236 /* Enable chip interrupts */ 237 ctlr->gmim = (ccim ? ccim : (IC_DONE_HC0 | IC_DONE_HC1)) | 238 IC_ERR_HC0 | IC_ERR_HC1; 239 ctlr->mim = ctlr->gmim | ctlr->pmim; 240 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim); 241 /* Enable PCI interrupts */ 242 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x007fffff); 243 return (0); 244} 245 246static void 247mvs_edma(device_t dev, device_t child, int mode) 248{ 249 struct mvs_controller *ctlr = device_get_softc(dev); 250 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 251 int bit = IC_DONE_IRQ << (unit * 2 + unit / 4) ; 252 253 if (ctlr->ccc == 0) 254 return; 255 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ 256 mtx_lock(&ctlr->mtx); 257 if (mode == MVS_EDMA_OFF) 258 ctlr->pmim |= bit; 259 else 260 ctlr->pmim &= ~bit; 261 ctlr->mim = ctlr->gmim | ctlr->pmim; 262 if (!ctlr->msia) 263 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim); 264 mtx_unlock(&ctlr->mtx); 265} 266 267static int 268mvs_suspend(device_t dev) 269{ 270 struct mvs_controller *ctlr = device_get_softc(dev); 271 272 bus_generic_suspend(dev); 273 /* Mask chip interrupts */ 274 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000); 275 /* Mask PCI interrupts */ 276 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000); 277 return 0; 278} 279 280static int 281mvs_resume(device_t dev) 282{ 283 284 mvs_ctlr_setup(dev); 285 return (bus_generic_resume(dev)); 286} 287 288static int 289mvs_setup_interrupt(device_t dev) 290{ 291 struct mvs_controller *ctlr = device_get_softc(dev); 292 int msi = 0; 293 294 /* Process hints. */ 295 resource_int_value(device_get_name(dev), 296 device_get_unit(dev), "msi", &msi); 297 if (msi < 0) 298 msi = 0; 299 else if (msi > 0) 300 msi = min(1, pci_msi_count(dev)); 301 /* Allocate MSI if needed/present. */ 302 if (msi && pci_alloc_msi(dev, &msi) != 0) 303 msi = 0; 304 ctlr->msi = msi; 305 /* Allocate all IRQs. */ 306 ctlr->irq.r_irq_rid = msi ? 1 : 0; 307 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 308 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 309 device_printf(dev, "unable to map interrupt\n"); 310 return (ENXIO); 311 } 312 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL, 313 mvs_intr, ctlr, &ctlr->irq.handle))) { 314 device_printf(dev, "unable to setup interrupt\n"); 315 bus_release_resource(dev, SYS_RES_IRQ, 316 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 317 ctlr->irq.r_irq = NULL; 318 return (ENXIO); 319 } 320 return (0); 321} 322 323/* 324 * Common case interrupt handler. 325 */ 326static void 327mvs_intr(void *data) 328{ 329 struct mvs_controller *ctlr = data; 330 struct mvs_intr_arg arg; 331 void (*function)(void *); 332 int p; 333 u_int32_t ic, aic; 334 335 ic = ATA_INL(ctlr->r_mem, CHIP_MIC); 336 if (ctlr->msi) { 337 /* We have to mask MSI during processing. */ 338 mtx_lock(&ctlr->mtx); 339 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0); 340 ctlr->msia = 1; /* Deny MIM update during processing. */ 341 mtx_unlock(&ctlr->mtx); 342 } else if (ic == 0) 343 return; 344 /* Acknowledge all-ports CCC interrupt. */ 345 if (ic & IC_ALL_PORTS_COAL_DONE) 346 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS); 347 for (p = 0; p < ctlr->channels; p++) { 348 if ((p & 3) == 0) { 349 if (p != 0) 350 ic >>= 1; 351 if ((ic & IC_HC0) == 0) { 352 p += 3; 353 ic >>= 8; 354 continue; 355 } 356 /* Acknowledge interrupts of this HC. */ 357 aic = 0; 358 if (ic & (IC_DONE_IRQ << 0)) 359 aic |= HC_IC_DONE(0) | HC_IC_DEV(0); 360 if (ic & (IC_DONE_IRQ << 2)) 361 aic |= HC_IC_DONE(1) | HC_IC_DEV(1); 362 if (ic & (IC_DONE_IRQ << 4)) 363 aic |= HC_IC_DONE(2) | HC_IC_DEV(2); 364 if (ic & (IC_DONE_IRQ << 6)) 365 aic |= HC_IC_DONE(3) | HC_IC_DEV(3); 366 if (ic & IC_HC0_COAL_DONE) 367 aic |= HC_IC_COAL; 368 ATA_OUTL(ctlr->r_mem, HC_BASE(p == 4) + HC_IC, ~aic); 369 } 370 /* Call per-port interrupt handler. */ 371 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); 372 if ((arg.cause != 0) && 373 (function = ctlr->interrupt[p].function)) { 374 arg.arg = ctlr->interrupt[p].argument; 375 function(&arg); 376 } 377 ic >>= 2; 378 } 379 if (ctlr->msi) { 380 /* Unmasking MSI triggers next interrupt, if needed. */ 381 mtx_lock(&ctlr->mtx); 382 ctlr->msia = 0; /* Allow MIM update. */ 383 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim); 384 mtx_unlock(&ctlr->mtx); 385 } 386} 387 388static struct resource * 389mvs_alloc_resource(device_t dev, device_t child, int type, int *rid, 390 rman_res_t start, rman_res_t end, rman_res_t count, 391 u_int flags) 392{ 393 struct mvs_controller *ctlr = device_get_softc(dev); 394 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 395 struct resource *res = NULL; 396 int offset = HC_BASE(unit >> 2) + PORT_BASE(unit & 0x03); 397 rman_res_t st; 398 399 switch (type) { 400 case SYS_RES_MEMORY: 401 st = rman_get_start(ctlr->r_mem); 402 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 403 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child); 404 if (res) { 405 bus_space_handle_t bsh; 406 bus_space_tag_t bst; 407 bsh = rman_get_bushandle(ctlr->r_mem); 408 bst = rman_get_bustag(ctlr->r_mem); 409 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh); 410 rman_set_bushandle(res, bsh); 411 rman_set_bustag(res, bst); 412 } 413 break; 414 case SYS_RES_IRQ: 415 if (*rid == ATA_IRQ_RID) 416 res = ctlr->irq.r_irq; 417 break; 418 } 419 return (res); 420} 421 422static int 423mvs_release_resource(device_t dev, device_t child, struct resource *r) 424{ 425 426 switch (rman_get_type(r)) { 427 case SYS_RES_MEMORY: 428 rman_release_resource(r); 429 return (0); 430 case SYS_RES_IRQ: 431 if (rman_get_rid(r) != ATA_IRQ_RID) 432 return ENOENT; 433 return (0); 434 } 435 return (EINVAL); 436} 437 438static int 439mvs_setup_intr(device_t dev, device_t child, struct resource *irq, 440 int flags, driver_filter_t *filter, driver_intr_t *function, 441 void *argument, void **cookiep) 442{ 443 struct mvs_controller *ctlr = device_get_softc(dev); 444 int unit = (intptr_t)device_get_ivars(child); 445 446 if (filter != NULL) { 447 printf("mvs.c: we cannot use a filter here\n"); 448 return (EINVAL); 449 } 450 ctlr->interrupt[unit].function = function; 451 ctlr->interrupt[unit].argument = argument; 452 return (0); 453} 454 455static int 456mvs_teardown_intr(device_t dev, device_t child, struct resource *irq, 457 void *cookie) 458{ 459 struct mvs_controller *ctlr = device_get_softc(dev); 460 int unit = (intptr_t)device_get_ivars(child); 461 462 ctlr->interrupt[unit].function = NULL; 463 ctlr->interrupt[unit].argument = NULL; 464 return (0); 465} 466 467static int 468mvs_print_child(device_t dev, device_t child) 469{ 470 int retval; 471 472 retval = bus_print_child_header(dev, child); 473 retval += printf(" at channel %d", 474 (int)(intptr_t)device_get_ivars(child)); 475 retval += bus_print_child_footer(dev, child); 476 477 return (retval); 478} 479 480static int 481mvs_child_location(device_t dev, device_t child, struct sbuf *sb) 482{ 483 484 sbuf_printf(sb, "channel=%d", 485 (int)(intptr_t)device_get_ivars(child)); 486 return (0); 487} 488 489static bus_dma_tag_t 490mvs_get_dma_tag(device_t bus, device_t child) 491{ 492 493 return (bus_get_dma_tag(bus)); 494} 495 496static device_method_t mvs_methods[] = { 497 DEVMETHOD(device_probe, mvs_probe), 498 DEVMETHOD(device_attach, mvs_attach), 499 DEVMETHOD(device_detach, mvs_detach), 500 DEVMETHOD(device_suspend, mvs_suspend), 501 DEVMETHOD(device_resume, mvs_resume), 502 DEVMETHOD(bus_print_child, mvs_print_child), 503 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource), 504 DEVMETHOD(bus_release_resource, mvs_release_resource), 505 DEVMETHOD(bus_setup_intr, mvs_setup_intr), 506 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr), 507 DEVMETHOD(bus_child_location, mvs_child_location), 508 DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag), 509 DEVMETHOD(mvs_edma, mvs_edma), 510 { 0, 0 } 511}; 512static driver_t mvs_driver = { 513 "mvs", 514 mvs_methods, 515 sizeof(struct mvs_controller) 516}; 517DRIVER_MODULE(mvs, pci, mvs_driver, 0, 0); 518MODULE_PNP_INFO("W32:vendor/device", pci, mvs, mvs_ids, 519 nitems(mvs_ids) - 1); 520MODULE_VERSION(mvs, 1); 521MODULE_DEPEND(mvs, cam, 1, 1, 1); 522